Control method and electronic equipment

Abstract

The present application discloses a control method and an electronic device, the method comprising: obtaining a first signal output by a sensor; processing the first signal through a control chip to obtain multiple second signals; wherein the multiple second signals are used to provide to a processor so that the processor obtains target data according to the second signals; different second signals are used to obtain different target data.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a control method and electronic equipment. Background Art

[0002] The basis of vibration analysis is sensor data acquisition. For example, for high-frequency vibration, displacement, velocity, and acceleration data are required.

[0003] Currently, a multi-channel sampling method is used to perform differential sampling on the signals collected by the sensor through multi-channel sampling hardware to obtain multi-channel signals.

[0004] However, this solution requires the installation of multi-channel sampling hardware, resulting in high hardware wiring complexity. Summary of the Invention

[0005] In view of this, the present application provides a control method and electronic device as follows:

[0006] A control method, comprising:

[0007] obtaining a first signal output by a sensor;

[0008] Processing the first signal through a control chip to obtain a plurality of second signals;

[0009] The multiple second signals are used to be provided to a processor so that the processor obtains target data according to the second signals; and different second signals are used to obtain different target data.

[0010] The above method preferably processes the first signal by a control chip to obtain a plurality of second signals, including:

[0011] The first signal is sampled by a control chip according to a plurality of sampling frequencies to obtain a plurality of second signals, wherein the signal frequencies of the second signals are different.

[0012] The above method preferably processes the first signal by a control chip to obtain a plurality of second signals, including:

[0013] The control chip sets the first flag to a first value, where the first value is used to instruct the control chip to output the first signal to a first bus, so that the control chip processes the first signal on the first bus to obtain multiple second signals.

[0014] Preferably, the above method further includes, before setting the first flag to the first value by the control chip:

[0015] The second flag is set to a second value by the control chip, where the second value is used to instruct the control chip to convert the first signal into a target format.

[0016] In the above method, preferably, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further includes:

[0017] Resetting the first flag;

[0018] After the control chip sets the first flag to the first value, the method further includes:

[0019] monitoring whether a duration during which the first flag is set to the first value reaches a target duration;

[0020] When the duration reaches the target duration, the step of setting the first flag to the first value by the control chip is executed again.

[0021] In the above method, preferably, the second signal corresponds to a channel identifier;

[0022] After the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further includes:

[0023] The control chip saves the second signal to the register corresponding to the channel identifier according to the channel identifier, so that the second signal is read from the register corresponding to the channel identifier by the processor through a second bus, and the second bus is connected between the control chip and the processor.

[0024] The above method preferably further comprises:

[0025] The first flag and the second flag are reset by the control chip.

[0026] Preferably, the above method further comprises, before processing the first signal by the control chip to obtain a plurality of second signals:

[0027] The first AC signal is processed to obtain the first DC signal.

[0028] An electronic device, comprising:

[0029] A sensor, configured to output a first signal;

[0030] A control chip is used to obtain the first signal; process the first signal to obtain multiple second signals; wherein the multiple second signals are used to provide to a processor so that the processor obtains target data according to the second signal; different second signals are used to obtain different target data.

[0031] In the above electronic device, the control chip is a field programmable gate array FPGA (Field Programmable Gate Array).

[0032] As can be seen from the above technical solution, in a control method and electronic device disclosed in this application, a control chip is arranged between a sensor and a processor, and the control chip processes a first signal output by the sensor into multiple second signals, so that the processor can obtain different target data for each second signal. It can be seen that in this application, there is no need to set up multiple sensors to achieve multi-channel signal acquisition. Instead, the control chip is used to perform signal branching, so that the processor can process the multiple branched signals and obtain the corresponding target data. This reduces the hardware layout for obtaining target data in the electronic device, thereby reducing the hardware complexity of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 A flow chart of a control method provided in Example 1 of the present application;

[0035] Figure 2 、 Figure 3 and Figure 4 They are respectively exemplary diagrams of the embodiments of the present application;

[0036] Figure 5 Another flow chart of a control method provided in Example 1 of the present application;

[0037] Figure 6 This is another exemplary diagram of an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the structure of an electronic device provided in Example 2 of the present application;

[0039] Figure 8 This is an example diagram of a structure for signal splitting processing in the field of vibration analysis applicable to this application;

[0040] Figure 9 This is an example diagram of the waveform of multiple signal branches in the field of vibration analysis applicable to this application;

[0041] Figure 10 This is an example diagram of the identification status and processing stage of FPGA in the field of vibration analysis applicable to this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] refer to Figure 1 The figure shows a flow chart for implementing a control method provided in the first embodiment of the present application. The method can be configured in an electronic device having a control chip and a processor, such as a computer or a server. The technical solution in this embodiment is mainly used to reduce the hardware complexity of obtaining target data in the electronic device.

[0044] Specifically, the method in this embodiment may include the following steps:

[0045] Step 101: Obtain a first signal output by a sensor.

[0046] The sensor may be a sensor capable of collecting vibration data. For example, a vibration sensor disposed on a target object, such as a moving object, can collect vibration data generated by the vibration of the target object. The vibration sensor outputs the vibration data as a first signal. Therefore, in this embodiment, the first signal output by the sensor is received.

[0047] Step 102: Processing the first signal via the control chip to obtain a plurality of second signals, and providing the plurality of second signals to the processor so that the processor obtains target data according to the second signals.

[0048] Different second signals are used to obtain different target data.

[0049] Specifically, the control chip can be connected to the sensor, so that after the sensor outputs the first signal, the first signal can be transmitted to the control chip, and the control chip processes the first signal to obtain multiple second signals, thereby realizing multi-channel acquisition of vibration data. Afterwards, the control chip provides the obtained multiple second signals to the processor connected to the control chip, and the processor obtains corresponding target data based on each second signal.

[0050] For example, Figure 2 As shown in the figure, the control chip can be a field programmable gate array FPGA (Field Programmable Gate Array), and the processor is a central processing unit CPU (Central Processing Unit). The FPGA is connected to the vibration sensor and the CPU respectively. The FPGA splits the first signal output by the vibration sensor to obtain multiple second signals, and provides the multiple second signals to the CPU. The CPU processes each second signal separately to obtain corresponding target data, such as displacement data of the target object, velocity data of the target object, and acceleration data of the target object.

[0051] As can be seen from the above scheme, in a control method provided in Example 1 of the present application, a control chip is arranged between the sensor and the processor, and the control chip processes the first signal output by the sensor into multiple second signals, so that the processor can obtain different target data for each second signal. It can be seen that in this embodiment, there is no need to set up multiple sensors to achieve multi-channel signal acquisition. Instead, the control chip is used to perform signal branching, so that the processor can process the multiple branched signals and obtain the corresponding target data. This reduces the hardware layout for obtaining target data in the electronic device, thereby reducing the hardware complexity of the electronic device.

[0052] In addition, in this embodiment, the signal branching process is performed by the control chip, thereby avoiding excessive processor computing pressure caused by the processor performing signal branching and target data acquisition, and improving the processing speed of the processor.

[0053] In one implementation, in step 102, when the control chip processes the first signal to obtain multiple second signals, it can be implemented as follows:

[0054] The first signal is sampled at multiple sampling frequencies by the control chip to obtain multiple second signals, where the signal frequencies of the second signals are different.

[0055] The multiple sampling frequencies are different from each other. Therefore, after the control chip samples the first signal according to different sampling frequencies, it can obtain second signals with different signal frequencies.

[0056] For example, Figure 3 As shown in , the FPGA samples the first signal output by the vibration sensor according to the first sampling frequency, the second sampling frequency and the third sampling frequency, thereby obtaining a plurality of second signals with different signal frequencies, and provides the plurality of second signals to the CPU, which processes each second signal separately to obtain corresponding target data, such as displacement data of the target object, velocity data of the target object and acceleration data of the target object.

[0057] Among them, the first sampling frequency is a frequency greater than 0 and less than 10Hz, the second sampling frequency is a frequency greater than or equal to 10Hz and less than 1000Hz, and the third sampling frequency is a frequency greater than or equal to 1000Hz, thereby realizing signal output within the low frequency range (2-50Hz), medium frequency range (2-5KHz) and high frequency range (2-50KHz).

[0058] In one implementation, in step 102, when the control chip processes the first signal to obtain multiple second signals, it can be implemented in the following manner:

[0059] The control chip sets the first flag to a first value, where the first value is used to instruct the control chip to output the first signal to the first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals.

[0060] The first bus may be a serial bus on a control chip, which can be used for signal processing.

[0061] For example, the first identifier may be an nRD identifier, and the first value may be 1, indicating that the FPGA needs to output the first signal to the first bus, so that the FPGA samples the first signal on the first bus according to multiple different sampling frequencies to obtain multiple second signals with different signal frequencies, and the CPU processes the second signals with different signal frequencies respectively to obtain different target data.

[0062] The first flag may also be set to other values, such as 0, indicating that the FPGA does not need to perform any processing.

[0063] Furthermore, before the control chip sets the first flag to the first value in step 102, the control chip may first set the second flag to the second value, where the second value is used to instruct the control chip to convert the first signal into a target format.

[0064] Specifically, the second value is used to instruct the control chip to convert the first signal from an analog format to a digital format.

[0065] For example, the second identifier can be a CONV identifier, and the second value can be 1, indicating that the FPGA needs to convert the format of the first signal output by the vibration sensor through the analog-to-digital converter ADC (Analog-to-Digital Converter) mounted on its circuit board to obtain a first signal in a digital format, so as to facilitate subsequent FPGA signal branching and CPU signal processing.

[0066] It should be noted that after the control chip completes converting the first signal into the target format, the third flag, such as EOC, may be set to 0 to indicate that the control chip completes converting the first signal into the target format.

[0067] In addition, in this embodiment, the third identifier can be set to a third value by the control chip, and the third value is used to point to one of the ADCs on the control chip, so that after the ADC converts the first signal into the target format, the converted first signal is output to the first bus, so that the control chip processes the first signal on the first bus to obtain multiple second signals.

[0068] For example, the third identifier is the nCS identifier, and the third value can be the identifier of one of the ADCs mounted on the circuit board where the FPGA is located, such as a code, so that the ADC pointed to by the third value on the FPGA outputs the first signal after the analog-to-digital conversion to the first bus, so that the FPGA samples the first signal on the first bus according to multiple different sampling frequencies to obtain multiple second signals with different signal frequencies, and the CPU processes the second signals with different signal frequencies respectively to obtain different target data.

[0069] Based on the above implementation method, after the control chip processes the first signal on the first bus to obtain multiple second signals, in this embodiment, the control chip can reset the first flag so that the first flag is other values ​​such as 0 to indicate that the FPGA does not need to perform any processing. The first flag is set to the first value only when the control chip needs to only branch the signal.

[0070] Furthermore, in this embodiment, after the first identifier is set to the first value by the control chip in step 102, it is also possible to monitor whether the duration of the first identifier being set to the first value reaches the target duration. When the duration reaches the target duration, step 102 is re-executed to set the first identifier to the first value by the control chip.

[0071] Among them, the target duration can be the duration of a processing cycle preset in the control chip, such as a clock cycle CLK (ClockCycle). Therefore, since the first flag will be reset after the control chip obtains the second signal, in this embodiment, after setting the first flag to the first value, it is possible to monitor whether the control chip completes the branching of the first signal to obtain multiple second signals within the target duration by monitoring whether the duration of the first flag being set to the first value reaches the target duration. If the control chip does not obtain the second signal within the target duration, then in this embodiment, the first flag can be reset to the first value to re-instruct the control chip to branch the first signal until the control chip obtains multiple second signals.

[0072] In addition, in this embodiment, a loop exit condition can also be set. For example, when the number of times the first identifier is reset exceeds a threshold value, such as 10 times, but the control chip still does not obtain multiple second signals, the first identifier will no longer be reset to the first value, that is, the branch processing of the current first signal will be stopped. Furthermore, a failure signal can be output to the processor to indicate that the signal acquisition failed.

[0073] For example, the first identifier may be an nRD identifier, whose first value may be 1; the second identifier may be a CONV identifier, whose second value may be 1; and the third identifier may be an nCS identifier, whose third value may be the identifier of one of the ADCs mounted on the circuit board where the FPGA is located. This causes the ADC pointed to by the third value on the FPGA to convert the first signal into a digital format and output the converted first signal to the first bus, so that the FPGA samples the first signal on the first bus at multiple different sampling frequencies to obtain multiple second signals with different signal frequencies. After obtaining the second signals, the nRD identifier is reset to 0. During this process, the duration for which the nRD identifier is set to 1 exceeds one clock cycle. If the duration exceeds one clock cycle and the FPGA still does not obtain the second signal, the nRD identifier is reset to 1 to re-trigger the ADC pointed to by the third value on the FPGA to convert the first signal into a digital format and output the converted first signal to the first bus, until the FPGA samples the first signal on the first bus at multiple different sampling frequencies to obtain multiple second signals with different signal frequencies, or until the number of times the nRD identifier is reset to 1 exceeds a threshold.

[0074] Based on the above implementation, the second signal corresponds to a channel identifier, such as an identifier representing different signal frequencies, that is, representing different sampling frequencies, so as to uniquely characterize the second signal.

[0075] Based on this, in step 102, after the control chip processes the first signal on the first bus to obtain multiple second signals, the second signal can also be saved in the register corresponding to the channel identifier according to the channel identifier through the control chip, so that the second signal is read from the register corresponding to the channel identifier by the processor through the second bus, and the second bus is connected between the control chip and the processor.

[0076] For example, different sampling frequencies correspond to different channel identifiers, such as channel identifier 1, channel identifier 2, and channel identifier 3. Based on this, after obtaining multiple second signals with different signal frequencies, the FPGA saves each second signal to a corresponding register according to the corresponding channel identifier, such as register a, register b, and register c. As a result, the CPU can read the corresponding second signal from the corresponding register a, register b, and register c according to the channel identifier 1, channel identifier 2, and channel identifier 3 through the second bus S between the FPGA and the CPU, such as Figure 4 As shown in , the CPU processes the second signals with different signal frequencies respectively to obtain different target data, such as displacement data, velocity data and acceleration data.

[0077] Based on the above implementation method, in this embodiment, the first identifier and the second identifier can also be reset by the control chip, for example, the first identifier is reset to 0 and the second identifier is reset to 0, so as to facilitate the next signal branching processing by the control chip.

[0078] In one implementation, before the control chip processes the first signal to obtain a plurality of second signals in step 102, the following steps may also be included: Figure 5 As shown in:

[0079] Step 103: Process the first AC signal to obtain a first DC signal.

[0080] In this embodiment, a DC blocking filter can be set in front of the control chip to first perform DC filtering on the AC type first signal output by the sensor to obtain a DC type first signal, and then the DC type first signal is branched through the control chip to obtain multiple second signals.

[0081] For example, a DC blocking filter L is placed in front of the FPGA to convert the first signal in analog format output by the vibration sensor into DC, and then the ADC converts the DC first signal into digital format, and outputs the converted first signal to the first bus, so that the FPGA samples the first signal on the first bus according to multiple different sampling frequencies to obtain multiple second signals with different signal frequencies. After obtaining the second signal, each second signal is saved in a corresponding register according to the corresponding channel identifier, such as register a, register b and register c. As a result, the CPU can read the corresponding second signal from the corresponding register a, register b and register c according to channel identifier 1, channel identifier 2 and channel identifier 3 through the second bus S between the FPGA and the CPU, such as Figure 6As shown in , the CPU processes the second signals with different signal frequencies respectively to obtain different target data, such as displacement data, velocity data and acceleration data.

[0082] refer to Figure 7 , is a schematic diagram of the structure of an electronic device provided in Example 2 of the present application, and the electronic device may include the following structure:

[0083] The sensor 701 is configured to output a first signal.

[0084] The control chip 702 is configured to obtain a first signal and process the first signal to obtain a plurality of second signals. The control chip 702 is an FPGA.

[0085] The processor 703 is configured to obtain target data according to the second signal; different second signals are used to obtain different target data.

[0086] As can be seen from the above scheme, in an electronic device provided in Example 2 of the present application, a control chip is configured between the sensor and the processor, and the control chip processes the first signal output by the sensor into multiple second signals, so that the processor can obtain different target data for each second signal. It can be seen that in this embodiment, there is no need to set up multiple sensors to achieve multi-channel signal acquisition. Instead, the control chip is used to perform signal branching, so that the processor can process the multiple branched signals and obtain the corresponding target data. This reduces the hardware layout for obtaining target data in the electronic device, thereby reducing the hardware complexity of the electronic device.

[0087] Taking the field of vibration analysis as an example, the basis of vibration analysis is sensor data acquisition. The peak-to-peak value of displacement, the effective value of velocity, the peak value of acceleration, and the effective value of the high-frequency acceleration envelope are the most commonly required valid data. This is where the same signal difference sampling is used. Low-frequency vibration (<10Hz) uses displacement measurement; medium-frequency vibration (10-1000Hz) uses velocity measurement; and high-frequency vibration (>1000Hz) uses acceleration measurement. For high-frequency vibration, displacement, velocity, and acceleration data are required. There are two methods in the existing technology:

[0088] In one approach, a multi-channel sampling approach is used, where an analog signal is subjected to multi-channel differential sampling. However, this approach has the disadvantages of increased hardware cost and complex on-site wiring.

[0089] In another method, high-speed sampling is used and the software analyzes the data, but this will generate very high computing power requirements for the CPU and generate a lot of computing pressure.

[0090] To address the above issues, this application proposes an analog virtual channel acquisition solution that simulates multiple channels through hardware to achieve adjustable signal frequency. Furthermore, this application pre-processes the sampled signal through FPGA, and can select the required frequency signal according to the set frequency range. The specific solution is as follows:

[0091] First, FPGA is the core of acquisition, and triggering, acquisition, and pre-processing are all completed in FPGA. Figure 8 As shown in the figure, the sensor transmits the collected vibration data to the GAIN of the operational amplifier for proportional amplification. After calibration through CAL (CALibration), it is passed to the ADC connected to the FPGA for analog-to-digital conversion. The vibration data in digital format is then transmitted to the FPGA. The FPGA samples the vibration data at different sampling frequencies and provides the sampled multiple channels of data with different signal frequencies to the CPU through the local bus (local). The CPU then obtains the corresponding displacement data, velocity data, and acceleration data.

[0092] The FPGA simulates multiple channels based on the set sampling frequency, converting the 250 kHz sampling rate signal into multiple channels according to the set frequency value. The specific channel identifiers, frequency ranges, and corresponding signal frequencies are shown in Table 1. In addition, before sampling, the signal is converted to a DC type through a pre-DC blocking filter.

[0093] Table 1 Channels and frequencies

[0094] Channel Identification Frequency range Signal frequency 1 2-50Hz Low frequency: <10Hz 2 2-5KHz Medium frequency: 10~1000Hz 3 2-50KHz >1000Hz

[0095] The signal waveforms corresponding to the multiple channel identifiers obtained are as follows: Figure 9 As shown in .

[0096] Among them, the identification status and processing stage of FPGA are as follows Figure 10 As shown in:

[0097] Phase 0 → IDLE: Start = 0, all signals are set to invalid (waiting for Start to be set to 1);

[0098] Phase 1 → CONVS: Set CONV and reset Flag (for waiting 7 cycles).

[0099] Phase 2 → EOC: (wait for nEOC to be zero), nEOC being 0 indicates that the ADC has completed data conversion;

[0100] Phase 3 → Read_Set: Reset CONV, set nCS and nRD. And maintain one CLK;

[0101] Phase 4 → Read_Res: Reset nRD and put the ADC converted data into the corresponding registers (according to the value of the channel identifier CH-Enable, put it into multiple groups of corresponding data registers);

[0102] Phase 6 → Write_Set: Set all signals to invalid, indicating that the current data processing is completed.

[0103] Phase 7 → Write: Set nCS, nWR, BUS_CONTROL, DATA_OUT, etc. to initial values;

[0104] Phase 8 → Release: Reset nCS, nWR, and nRD to facilitate the next data processing.

[0105] It can be seen that the technical solution of this application can be adopted by sampling one channel, simplifying on-site wiring and reducing hardware costs. Moreover, in this application, data preprocessing and channel simulation are performed by hardware, which does not occupy CPU resources. In addition, the data obtained by the CPU in this application has already been processed, which lowers the entry threshold of the software in the CPU and is conducive to the popularization of the solution.

[0106] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0107] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0109] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method, comprising: obtaining a first signal output by a sensor; Processing the first signal through a control chip to obtain a plurality of second signals; The plurality of second signals are used to be provided to a processor, so that the processor obtains target data according to the second signals; different second signals are used to obtain different target data; The first signal is processed by a control chip to obtain a plurality of second signals, including: Setting a first flag to a first value by a control chip, where the first value is used to instruct the control chip to output the first signal to a first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals; Wherein, after the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further includes: Resetting the first flag; After the control chip sets the first flag to the first value, the method further includes: monitoring whether a duration during which the first flag is set to the first value reaches a target duration; When the duration reaches the target duration, the step of setting the first flag to the first value by the control chip is executed again.

2. The method according to claim 1, wherein the control chip processes the first signal to obtain a plurality of second signals, comprising: The first signal is sampled by a control chip according to a plurality of sampling frequencies to obtain a plurality of second signals, wherein the signal frequencies of the second signals are different.

3. The method according to claim 1, before setting the first flag to the first value by the control chip, the method further comprises: The second flag is set to a second value by the control chip, where the second value is used to instruct the control chip to convert the first signal into a target format.

4. The method according to claim 1, wherein the second signal corresponds to a channel identifier; in, After the control chip processes the first signal on the first bus to obtain a plurality of second signals, the method further includes: The control chip saves the second signal to the register corresponding to the channel identifier according to the channel identifier, so that the second signal is read from the register corresponding to the channel identifier by the processor through a second bus, and the second bus is connected between the control chip and the processor.

5. The method according to claim 3, further comprising: The first flag and the second flag are reset by the control chip.

6. The method according to claim 1, before processing the first signal by a control chip to obtain a plurality of second signals, the method further comprises: The first AC signal is processed to obtain the first DC signal.

7. An electronic device comprising: A sensor, configured to output a first signal; A control chip, configured to obtain the first signal; Processing the first signal to obtain a plurality of second signals; wherein the plurality of second signals are used to provide to a processor so that the processor obtains target data according to the second signals; different second signals are used to obtain different target data; The control chip is used to process the first signal to obtain multiple second signals, including: Setting a first flag to a first value by a control chip, where the first value is used to instruct the control chip to output the first signal to a first bus, so that the control chip processes the first signal on the first bus to obtain a plurality of second signals; After the control chip processes the first signal on the first bus to obtain a plurality of second signals, the control chip is further configured to: Resetting the first flag; After the control chip sets the first flag to the first value, the control chip further includes: monitoring whether a duration during which the first flag is set to the first value reaches a target duration; When the duration reaches the target duration, the step of setting the first flag to the first value by the control chip is executed again. 8 . The electronic device according to claim 7 , wherein the control chip is a field programmable gate array (FPGA).

Images