Display panel and display device

Abstract

This disclosure relates to the field of display technology, and proposes a display panel and a display device. The display area of ​​the display panel includes a fan-out area and a normal display area. The display panel further includes: a substrate, multiple data lines, multiple first signal lines, multiple second signal lines, multiple first transition portions, and a pixel electrode layer. The orthographic projection of the data lines on the substrate extends along a second direction; the orthographic projection of the first signal lines on the substrate extends along a first direction, and the first signal lines located in the normal display area form first analog lines; the orthographic projection of the second signal lines on the substrate extends along the second direction, and the second signal lines located in the normal display area form second analog lines; the first transition portions connect the intersecting first analog lines and second analog lines; the orthographic projections of the electrode portions in the pixel electrode layer on the substrate and the orthographic projections of the first transition portions on the substrate do not overlap. This display panel can improve the mura problem when the display panel is off.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In FIP (Fanout In Panel) technology, the display area of ​​the display panel includes a fan-out area and a normal display area outside the fan-out area. The fan-out area is equipped with data fan-out lines, and the normal display area is equipped with analog signal lines. The analog signal lines can simulate the data fan-out lines to make the signal line density of the fan-out area and the normal display area the same or approximately the same.

[0003] Simultaneously, the extended analog signal lines can also be connected via adapters to form a grid-structured signal line with a smaller voltage drop.

[0004] However, in the related technology, the transition part and the part of the electrode part located in the pixel electrode layer overlap, which causes the partial structure of the part of the electrode part to bulge. This bulge causes the electrode part located in the normal display area and the electrode part located in the fan-out area to have different reflective effects, resulting in the display panel mura when it is off.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] According to one aspect of this disclosure, a display panel is provided, wherein the display area of ​​the display panel includes a fan-out area and a normal display area located outside the fan-out area, and the display panel further includes: a substrate, a plurality of data lines, a plurality of first signal lines, a plurality of second signal lines, a plurality of first transition portions, and a pixel electrode layer. The plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, the first direction and the second direction intersecting; the first signal lines on the substrate extend along the first direction and are spaced apart along the second direction, the portion of the first signal lines located in the fan-out area forms a first data fan-out line, and the first signal lines located in the normal display area form a first analog line, the first data fan-out lines are correspondingly disposed with the data lines, and the first data fan-out lines are connected to their corresponding data lines; the plurality of second signal lines are located in different conductive layers from the first signal lines, and the orthographic projections of the second signal lines on the substrate are spaced apart along a first direction and extend along a second direction. The projection extends along the second direction and is distributed at intervals along the first direction. The portion of the second signal line located in the fan-out area forms a second data fan-out line, and the second signal line located in the normal display area forms a second analog line. The second data fan-out line is correspondingly arranged with the first data fan-out line, and the second data fan-out line is connected to its corresponding first data fan-out line. A plurality of first transition portions are located in the normal display area, and the first transition portions are connected between the first analog line and the second analog line whose orthographic projections intersect on the substrate. The pixel electrode layer includes a plurality of electrode portions, and the orthographic projections of the electrode portions on the substrate and the orthographic projections of the first transition portions on the substrate do not overlap.

[0007] In one exemplary embodiment of this disclosure, multiple first signal lines and the first adapter are located in the same conductive layer, and multiple second signal lines are located in the same conductive layer; the conductive layer containing the second signal lines is located on the side of the conductive layer containing the first signal lines away from the substrate; the first adapter and the first analog line are connected in the same layer, and the first adapter and the second analog line are connected through vias; the orthographic projection of the second analog line on the substrate covers the orthographic projection of the first adapter on the substrate.

[0008] In one exemplary embodiment of this disclosure, the display panel further includes: a first source / drain layer and a second source / drain layer. The first source / drain layer is located between the substrate and the pixel electrode layer, and includes the first signal line and the first transition portion. The second source / drain layer is located between the first source / drain layer and the pixel electrode layer, and includes the second signal line and the data line.

[0009] In one exemplary embodiment of this disclosure, the first analog line and the second analog line are respectively disposed at the partial intersection points of their orthogonal projections on the substrate and the first transition portion, and the first transition portion is connected between the first analog line and the second analog line corresponding to it; the number of intersection points of the orthogonal projections of the first analog line and the second analog line on the substrate is greater than the number of the first transition portions.

[0010] In one exemplary embodiment of this disclosure, the display panel includes a pixel driving circuit; in the normal display area, a portion of the pixel driving circuits are correspondingly provided with a first transition portion, and m first transition portions are correspondingly provided for n adjacent pixel driving circuits in the first direction; wherein, n is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and n is greater than m.

[0011] In an exemplary embodiment of this disclosure, n equals 4, m equals 3, the first direction is the row direction, and the second direction is the column direction; the plurality of electrode portions include a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion; among the plurality of electrode portions connected to the same row pixel driving circuit, the first electrode portion, the second electrode portion, the third electrode portion, and the fourth electrode portion are alternately distributed in the row direction; in two adjacent column pixel driving circuits, the first electrode portion and the third electrode portion are connected to the same column pixel driving circuit, and the first electrode portion and the third electrode portion connected to the same column pixel driving circuit are alternately distributed in the column direction, the second electrode portion and the fourth electrode portion are connected to another column pixel driving circuit, and the second electrode portion and the fourth electrode portion connected to the same column pixel driving circuit are alternately distributed in the column direction; in four adjacent pixel driving circuits in the first direction, the pixel driving circuit corresponding to the first electrode portion is provided with the first transition portion, the pixel driving circuit corresponding to the second electrode portion is provided with the first transition portion, and the pixel driving circuit corresponding to the third electrode portion is provided with the first transition portion.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a second transistor, and a fifth transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The first terminal of the fifth transistor is connected to a power line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor. The display panel further includes a first gate layer and a second source / drain layer. The first gate layer is located between the substrate and the pixel electrode layer. The first gate layer includes a first conductive portion and a gate line. The gate line extends along a first direction in its orthogonal projection onto the substrate. The first conductive portion forms the gate of the driving transistor, and a portion of the gate line forms the gate of the second transistor. The second source / drain layer is located between the first gate layer and the pixel electrode layer. The second source / drain layer includes the power line and the data line. The power line is connected to the first gate layer and the pixel electrode layer. The orthographic projections on the substrate and the orthographic projections on the data line extend along the second direction; the first analog line and the pixel driving circuit are correspondingly arranged, and in the corresponding pixel driving circuit and the first analog line, the orthographic projection of the first analog line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is away from the orthographic projection of the gate line on the substrate; the second analog line and the pixel driving circuit are correspondingly arranged, and in the corresponding pixel driving circuit and the second analog line, the orthographic projection of the second analog line on the substrate is located on the side where the orthographic projection of the power line on the substrate is away from the orthographic projection of the data line on the substrate; the first adapter and the first analog line and the second analog line directly connected thereto are correspondingly arranged, and the pixel driving circuit and the first adapter corresponding to the same group of first analog lines and second analog lines are correspondingly arranged.

[0013] In an exemplary embodiment of this disclosure, the conductive layer containing the first signal line further includes: a first simulated via contact and a second simulated via contact. The first simulated via contact is located in the fan-out region. The intersection of the orthographic projections of the first signal line and the second signal line in the fan-out region onto the substrate corresponds to the first simulated via contact. The first simulated via contact is insulated from the first signal line. The second signal line is connected to its corresponding first simulated via contact via a via. The second simulated via contact is located in the normal display region. Among the intersections of the orthographic projections of the first simulated line and the second simulated line onto the substrate, the intersection that does not correspond to the first transition portion corresponds to the second simulated via contact. The second simulated via contact is insulated from the first simulated line. The second simulated line is connected to its corresponding second simulated via contact via a via.

[0014] In an exemplary embodiment of this disclosure, the first adapter includes a first via contact portion, which connects to the second analog line via a via; the first analog via contact portion, the second analog via contact portion, and the first via contact portion form a via contact portion; the minimum distance between the orthographic projections of adjacent via contact portions on the substrate in the first direction is S1, and the maximum distance between the orthographic projections of adjacent via contact portions on the substrate in the first direction is S2, wherein (S2-S1) / S1 is greater than or equal to 0 and less than or equal to 0.2; the minimum distance between the orthographic projections of adjacent via contact portions on the substrate in the second direction is S3, and the maximum distance between the orthographic projections of adjacent via contact portions on the substrate in the second direction is S4, wherein (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.2.

[0015] In one exemplary embodiment of this disclosure, the orthographic projections of the first simulated via contact portion on the substrate and the orthographic projections of the electrode portion on the substrate at least partially overlap; the orthographic projections of the second simulated via contact portion on the substrate and the orthographic projections of the electrode portion on the substrate at least partially overlap.

[0016] In one exemplary embodiment of this disclosure, the display panel further includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit being connected to a first electrode of the light-emitting unit; the display panel further includes a common electrode layer, the common electrode layer being used to form a second electrode of the light-emitting unit; wherein the first analog line and the second analog line are connected to the common electrode layer.

[0017] In one exemplary embodiment of this disclosure, the display panel further includes a border area surrounding the display area, the border area including a first border area and a second border area disposed opposite to each other in the first direction, and a third border area and a fourth border area disposed opposite to each other in the second direction; the display panel further includes an electrode ring, the electrode ring being located in the border area and connected to the common electrode layer, at least a portion of the electrode ring located in the first border area being connected to the first analog line, at least a portion of the electrode ring located in the second border area being connected to the first analog line, at least a portion of the electrode ring located in the third border area being connected to the second analog line, and at least a portion of the electrode ring located in the fourth border area being connected to the second analog line.

[0018] In one exemplary embodiment of this disclosure, the minimum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S5, and the maximum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S6, wherein (S6-S5) / S5 is greater than or equal to 0 and less than or equal to 0.2; and / or, the minimum distance between the orthographic projections of two adjacent second signal lines on the substrate in the first direction is S7, and the maximum distance between the orthographic projections of two adjacent second signal lines on the substrate in the first direction is S8, wherein (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.2.

[0019] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit. The pixel driving circuit includes a driving transistor, a fourth transistor, and a seventh transistor. The first electrode of the fourth transistor is connected to the data line, the second electrode of the fourth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The display panel further includes an active layer and a first gate layer. The active layer is located between the substrate and the pixel electrode layer. The active layer includes a seventh active portion and a fourth active portion. The seventh active portion is used to form the channel region of the seventh transistor, and the fourth active portion is used to form the channel region of the fourth transistor. The first gate layer is located between the active layer and the pixel electrode layer. The first gate layer includes a second reset signal line. The orthographic projection of the second reset signal line on the substrate covers the orthographic projection of the fourth active portion on the substrate and the orthographic projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, and a portion of the structure of the second reset signal line is used to form the gate of the fourth transistor.

[0020] In one exemplary embodiment of this disclosure, the active layer further includes: a third active portion, an eighth active portion, and a ninth active portion, wherein the third active portion is used to form the channel region of the driving transistor; the eighth active portion is connected to the fourth active portion; and the ninth active portion is connected to the third active portion; the display panel further includes: a first source / drain layer, wherein the first source / drain layer is located between the first gate layer and the pixel electrode layer, and the first source / drain layer includes a first bridging portion, wherein the first bridging portion is connected to the eighth active portion and the ninth active portion respectively through vias.

[0021] In one exemplary embodiment of this disclosure, the display panel further includes a pixel driving circuit, which includes a driving transistor, a first transistor, and a second transistor. The first electrode of the first transistor is connected to a first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor. The display panel further includes an active layer and a second gate layer. The active layer is located between the substrate and the pixel electrode layer. The active layer includes a first active portion, a tenth active portion, a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion. The first active portion is used for… In the channel region forming the first transistor, the first sub-active portion and the second sub-active portion are used to form the channel region of the second transistor, and the tenth active portion is connected between the first active portion and the first sub-active portion; the second gate layer is located between the active layer and the pixel electrode layer, and the second gate layer includes the first initial signal line, the first protrusion, and the second protrusion, the first protrusion being connected to the first initial signal line, and the second protrusion being connected to the first initial signal line; wherein, the orthographic projection of the first protrusion on the substrate and the orthographic projection of the third sub-active portion on the substrate at least partially overlap, and the orthographic projection of the second protrusion on the substrate and the orthographic projection of the tenth active portion on the substrate at least partially overlap.

[0022] According to one aspect of this disclosure, a display panel is provided, wherein the display area of ​​the display panel includes a fan-out area and a normal display area located outside the fan-out area, and the display panel further includes: a substrate, a plurality of data lines, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first adapters. The plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, the first direction and the second direction intersecting; the orthographic projections of the first signal lines on the substrate extend along the first direction and are spaced apart along the second direction, the portion of the first signal lines located in the fan-out area forms a first data fan-out line, and the first signal lines located in the normal display area form a first analog line, the first data fan-out lines are correspondingly disposed with the data lines, and the first data fan-out lines are connected to their corresponding data lines; the plurality of second signal lines are located in different conductive layers from the first signal lines, and the orthographic projections of the second signal lines on the substrate extend along the second direction and are spaced apart along the first direction, the portion of the first signal lines located in the fan-out area forming a first data fan-out line, and the portion of the first signal lines located in the fan-out area forming a first data fan-out line, ... A portion of the second signal line in the normal display area forms a second data fan-out line, and the second signal line in the normal display area forms a second analog line. The second data fan-out line is correspondingly arranged with the first data fan-out line, and the second data fan-out line is connected to its corresponding first data fan-out line. A plurality of first adapters are located in the normal display area, and the first adapters are connected between the first analog line and the second analog line that intersect on the substrate by orthographic projection. The display panel further includes a pixel driving circuit. In the normal display area, a portion of the pixel driving circuit is correspondingly provided with a first adapter. And m first adapters are correspondingly provided for n adjacent pixel driving circuits in the first direction. n is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and n is greater than m.

[0023] In an exemplary embodiment of this disclosure, n equals 4, m equals 3, the first direction is the row direction, and the second direction is the column direction; the display panel further includes: a pixel electrode layer, the pixel electrode layer including a plurality of electrode portions, the plurality of electrode portions including a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion; among the plurality of electrode portions connected to the same row pixel driving circuit, the first electrode portion, the second electrode portion, the third electrode portion, and the fourth electrode portion are alternately distributed in the row direction; in two adjacent column pixel driving circuits, the first electrode portion and the third electrode portion are connected to the same column pixel driving circuit, and the first electrode portion and the third electrode portion connected to the same column pixel driving circuit are alternately distributed in the column direction, the second electrode portion and the fourth electrode portion are connected to another column pixel driving circuit, and the second electrode portion and the fourth electrode portion connected to the same column pixel driving circuit are alternately distributed in the column direction; in four adjacent pixel driving circuits in the first direction, the pixel driving circuit corresponding to the first electrode portion is provided with the first transition portion, the pixel driving circuit corresponding to the second electrode portion is provided with the first transition portion, and the pixel driving circuit corresponding to the third electrode portion is provided with the first transition portion.

[0024] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a second transistor, and a fifth transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The first terminal of the fifth transistor is connected to a power line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor. The display panel further includes a first gate layer and a second source / drain layer. The first gate layer is located on one side of the substrate and includes a first conductive portion and a gate line. The gate line extends along a first direction in its orthogonal projection onto the substrate. The first conductive portion forms the gate of the driving transistor, and a portion of the gate line forms the gate of the second transistor. The second source / drain layer is located on the side of the first gate layer opposite to the substrate and includes the power line and the data line. The power line is connected to the first source / drain layer on the substrate. The orthographic projections on the substrate and the data lines on the substrate extend along the second direction; the first analog line and the pixel driving circuit are correspondingly arranged, and in the corresponding pixel driving circuit and the first analog line, the orthographic projection of the first analog line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is away from the orthographic projection of the gate line on the substrate; the second analog line and the pixel driving circuit are correspondingly arranged, and in the corresponding pixel driving circuit and the second analog line, the orthographic projection of the second analog line on the substrate is located on the side where the orthographic projection of the power line on the substrate is away from the orthographic projection of the data line on the substrate; the first adapter and the first analog line and the second analog line directly connected thereto are correspondingly arranged, and the pixel driving circuit and the first adapter corresponding to the same group of first analog lines and second analog lines are correspondingly arranged.

[0025] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 This is a schematic diagram of the structure of a display panel in an exemplary embodiment of the related art;

[0029] Figure 2 for Figure 1 Structural layout of the normal display area in the middle;

[0030] Figure 3 for Figure 2 Structural layout of the first source / drain layer;

[0031] Figure 4 for Figure 2 Structural layout of the second source / drain layer;

[0032] Figure 5 for Figure 2 Structural layout of the middle pixel electrode layer;

[0033] Figure 6 for Figure 2 Structural layout of the first and second source / drain layers in the middle;

[0034] Figure 7 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0035] Figure 8 for Figure 7 Structural layout of the normal display area in the middle;

[0036] Figure 9 for Figure 8 Structural layout of the first source / drain layer;

[0037] Figure 10 for Figure 8 Structural layout of the second source / drain layer;

[0038] Figure 11 for Figure 8 Structural layout of the middle pixel electrode layer and pixel boundary layer;

[0039] Figure 12 for Figure 8 Structural layout of the first and second source / drain layers in the middle;

[0040] Figure 13 for Figure 7 Structural layout of part of the K1 region in the central fan-out area;

[0041] Figure 14 for Figure 13 Structural layout of the first source / drain layer;

[0042] Figure 15 for Figure 13 Structural layout of the second source / drain layer;

[0043] Figure 16 for Figure 13 Structural layout of the middle pixel electrode layer and pixel boundary layer;

[0044] Figure 17 for Figure 13 Structural layout of the first and second source / drain layers in the middle;

[0045] Figure 18 This is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel disclosed herein;

[0046] Figure 19 for Figure 18 The timing diagram of signals at each node in a driving method of the pixel circuit shown is shown.

[0047] Figure 20 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0048] Figure 21 for Figure 20 The structural layout of the active layer;

[0049] Figure 22 for Figure 20 The structural layout of the first gate layer;

[0050] Figure 23 for Figure 20 The structural layout of the second gate layer;

[0051] Figure 24 for Figure 20 Structural layout of the first source / drain layer;

[0052] Figure 25 for Figure 20 Structural layout of the second source / drain layer;

[0053] Figure 26 for Figure 20 The structural layout of the active layer and the first gate layer;

[0054] Figure 27 for Figure 20 The structural layout includes an active layer, a first gate layer, and a second gate layer;

[0055] Figure 28 for Figure 20 The structural layout includes an active layer, a first gate layer, a second gate layer, and a first source / drain layer.

[0056] Figure 29 for Figure 20 The diagram shows a partial sectional view of the display panel cut along the dashed line BB.

[0057] Figure 30 for Figure 7 Local map structure of region K3 in the middle area;

[0058] Figure 31for Figure 30 Structural layout of the first source / drain layer;

[0059] Figure 32 for Figure 30 Structural layout of the second source / drain layer;

[0060] Figure 33 for Figure 7 The local map structure of region K4 in the middle area;

[0061] Figure 34 for Figure 33 Structural layout of the first source / drain layer;

[0062] Figure 35 for Figure 33 Structural layout of the second source / drain layer;

[0063] Figure 36 for Figure 7 The local map structure of region K5 in the middle area;

[0064] Figure 37 for Figure 36 The structural layout of the first gate layer;

[0065] Figure 38 for Figure 36 The structural layout of the second gate layer;

[0066] Figure 39 for Figure 36 Structural layout of the first source / drain layer;

[0067] Figure 40 for Figure 36 Structural layout of the second source / drain layer;

[0068] Figure 41 for Figure 36 The structural layout of the first gate layer and the second gate layer;

[0069] Figure 42 for Figure 36 The structural layout of the first gate layer, the second gate layer, and the first source / drain layer. Detailed Implementation

[0070] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0071] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0072] like Figure 1 The diagram shown illustrates a structural embodiment of a display panel in the related art. The display panel may include a display area AA, which may include a fan-out area FT and a normal display area located outside the fan-out area. The display panel may also include a substrate, multiple data lines Da, multiple first signal lines L1, and multiple second signal lines L2. The multiple data lines Da are located in the display area AA. The orthographic projections of the data lines Da onto the substrate are spaced apart along a first direction X and extend along a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X may be a row direction, and the second direction Y may be a column direction. Multiple first signal lines L1, projected onto the substrate, extend along the first direction X and are spaced apart along the second direction Y. A portion of the first signal lines L1 located in the fan-out region FT forms a first data fan-out line Fa1; a portion of the first signal lines L1 located in the fan-out region FT forms a third analog line Dm3; and a portion of the first signal lines L1 located in the normal display area forms a first analog line Dm1. The first data fan-out line Fa1 is correspondingly configured with the data line Da, and the first data fan-out line Fa1 is connected to its corresponding data line Da. Multiple second signal lines L2 are connected to the first signal lines L1... 1. Located in different conductive layers, the orthographic projection of the second signal line L2 on the substrate extends along the second direction Y and is distributed at intervals along the first direction X. The portion of the second signal line L2 located in the fan-out area FT forms a second data fan-out line Fa2, the portion of the second signal line L2 located in the fan-out area FT forms a fourth analog line Dm4, and the second signal line L2 located in the normal display area forms a second analog line Dm2. The second data fan-out line Fa2 is correspondingly set with the first data fan-out line Fa1, and the second data fan-out line Fa2 is connected to its corresponding first data fan-out line Fa1.

[0073] like Figure 1 As shown, the first analog line Dm1 and the third analog line Dm3 are connected, the second analog line Dm2 and the fourth analog line Dm4 are connected, the third analog line Dm3 and the first data fan-out line Fa1 are spaced apart, and the fourth analog line Dm4 and the second data fan-out line Fa2 are spaced apart. The first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 can make the distribution density of the first signal line L1 and the second signal line L2 in the normal display area and the fan-out area FT the same, thereby improving the screen-off mura of the display panel.

[0074] like Figure 1 As shown, in the related technology, the first analog line Dm1 and the second analog line Dm2, which intersect by orthographic projection on the substrate, can be connected by a via H (black circle). The first analog line Dm1 and the second analog line Dm2 can be connected to the common electrode layer in the display panel. The grid structure of the first analog line Dm1 and the second analog line Dm2 can reduce the self-resistance of the common electrode layer, thereby reducing the voltage difference at different positions of the common electrode layer and improving the display uniformity of the display panel.

[0075] like Figure 2-6 As shown, Figure 2 for Figure 1 The structural layout of the normal display area in the display panel may include a first source / drain layer, a second source / drain layer, and a pixel electrode layer stacked in sequence. Figure 3 for Figure 2 The structural layout of the first source / drain layer in the middle. Figure 4 for Figure 2 Structural layout of the second source / drain layer in the middle. Figure 5 for Figure 2 Layout of the mid-pixel electrode layer Figure 6 for Figure 2 The structural layout of the first and second source / drain layers.

[0076] The first analog line Dm1 is located in the first source / drain layer, and the second analog line Dm2 is located in the second source / drain layer. The first source / drain layer may also include a first adapter Cnt1, which connects to the first analog line Dm1. The second analog line Dm2 connects to the first adapter Cnt1 via a via (black squares indicate the location of the via) to connect to the intersecting first analog line Dm1. However, as... Figure 2 As shown, the pixel electrode layer includes a first electrode portion R, a second electrode portion G1, a third electrode portion B, and a fourth electrode portion G2. The orthographic projection of the fourth electrode portion G2 on the substrate overlaps with the orthographic projection of the first transition portion Cnt1 on the substrate. The fourth electrode portion G2 overlapping with the first transition portion Cnt1 will locally protrude at the overlap position. At the same time, since the first transition portion is not provided in the fan-out area, the fourth electrode portion G2 in the fan-out area and the fourth electrode portion G2 in the normal display area have different reflective characteristics, resulting in a mura (screen-off mura) on the display panel.

[0077] Based on this, this exemplary embodiment provides a display panel, such as Figure 7-11 As shown, Figure 7 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein. The display panel may include a first source / drain layer, a second source / drain layer, a pixel electrode layer, and a pixel defining layer that are stacked sequentially. Figure 8 for Figure 7The structural layout of the normally displayed area in the middle. Figure 9 for Figure 8 The structural layout of the first source / drain layer in the middle. Figure 10 for Figure 8 Structural layout of the second source / drain layer in the middle. Figure 11 for Figure 8 Structural layout of the mid-pixel electrode layer and pixel boundary layer. Figure 12 for Figure 8 The structural layout of the first and second source / drain layers.

[0078] Compared to Figure 1 The display panel shown is in Figure 7 In the display panel shown, the intersection points of the orthographic projections of the first analog line Dm1 and the second analog line Dm2 onto the substrate are correspondingly arranged with the first transition portion Cnt1. The first transition portion Cnt1 connects between the corresponding first analog line and the second analog line. Specifically, the first transition portion Cnt1 and the first and second analog lines forming their corresponding intersection points are correspondingly arranged. The number of intersection points between the orthographic projections of the first analog line Dm1 and the second analog line Dm2 onto the substrate is greater than the number of first transition portions Cnt1. That is... Figure 7 The display panel shown has removed part of the first transition portion in the normal display area, so that the orthographic projections of the first transition portion and any electrode portion on the substrate do not overlap. This setting can improve the problem of mura when the display panel is off.

[0079] like Figure 8 , 11 As shown, multiple pixel openings PH can be formed on the pixel defining layer. The pixel openings PH are correspondingly arranged with electrode portions, and the orthographic projection of the pixel opening PH on the substrate lies on the orthographic projection of its corresponding electrode portion on the substrate. The orthographic projection area of ​​the electrode portion on the substrate is slightly larger than the orthographic projection area of ​​the pixel opening PH on the substrate.

[0080] It should be understood that in other exemplary embodiments, the overlap of the orthographic projections of the first adapter portion and the electrode portion on the substrate can also be avoided in other ways. For example, the overlap of the first adapter portion and the electrode portion can be avoided by changing the shape and position of the first adapter portion. Furthermore, in other exemplary embodiments, the first signal line L1 can also be located in another conductive layer, and the second signal line L2 can also be located in another conductive layer. The conductive layer containing the second signal line is located on the side of the conductive layer containing the first signal line away from the substrate. The first adapter portion and the first analog line can be connected in the same layer, and the first adapter portion and the second analog line can be connected through vias.

[0081] like Figure 8As shown, the orthographic projection of the second analog line Dm2 on the substrate can cover the orthographic projection of the first adapter Cnt1 on the substrate. This arrangement ensures that the first adapter Cnt1 does not affect the distribution density of the light-shielding structure in the normal display area, thereby allowing the fan-out area and the normal display area to have the same or approximately the same light-shielding structure distribution density, which can improve the problem of mura when the display panel is off.

[0082] like Figure 8 , 9 As shown in Figure 12, the first adapter Cnt1 may include a first via contact TH1, which connects to the second analog line Dm2 via a via. A recessed structure appears at the connection between the second analog line Dm2 and the first via contact TH1. This recessed structure alters the reflective properties of the second analog line Dm2, resulting in different reflective properties for the second analog line without the first adapter region, the second data fan-out line, and the second analog line with the first adapter region, thus causing the display panel to go out (mura).

[0083] like Figure 8 , 9 As shown in Figure 12, in this exemplary embodiment, the conductive layer where the first signal line is located may further include: a second simulated via contact portion DTH2. The second simulated via contact portion DTH2 is located in the normal display area. Among the intersections of the first simulated line Dm1 and the second simulated line Dm2 projected onto the substrate, the intersection point not corresponding to the first transition portion Cnt1 is correspondingly disposed with the second simulated via contact portion DTH2. The second simulated via contact portion DTH2 is insulated from the first simulated line Dm1. The second simulated line Dm2 is connected to its corresponding second simulated via contact portion DTH2 through a via. The second simulated line Dm2 forming the intersection point and the second simulated via contact portion DTH2 corresponding to the intersection point are correspondingly disposed. This arrangement can make the reflective characteristics of each second simulated line in the normal display area consistent, thereby improving the mutagenesis of the display panel when it is off.

[0084] Figure 13 for Figure 7 Structural map of part of the K1 region in the central fan-out area. Figure 14 for Figure 13 The structural layout of the first source / drain layer in the middle. Figure 15 for Figure 13 Structural layout of the second source / drain layer in the middle. Figure 16 for Figure 13 Structural layout of the mid-pixel electrode layer and pixel boundary layer. Figure 17 for Figure 13 The structural layout of the first and second source / drain layers.

[0085] like Figure 7 As shown, the portion of the first signal line L1 located in the fan-out region FT forms the third analog line Dm3, and the portion of the second signal line L2 located in the fan-out region FT forms the fourth analog line Dm4. The first analog line Dm1 and the third analog line Dm3 are connected, and the second analog line Dm2 and the fourth analog line Dm4 are connected.

[0086] In this exemplary embodiment, the conductive layer where the first signal line L1 is located may further include: a first analog via contact DTH1, which is located in the fan-out region FT. The intersection of the orthographic projections of the first signal line L1 (first data fan-out line Fa1) and the second signal line L2 (fourth analog line Dm4) located in the fan-out region FT onto the substrate corresponds to the first analog via contact DTH1. The first analog via contact DTH1 and the first signal line L1 are insulated from each other. The second signal line L2 is connected to its corresponding first analog via contact DTH1 via a via, and the second signal line L2 forming the intersection point corresponds to the first analog via contact DTH1 corresponding to that intersection point. This arrangement makes the reflective characteristics of the second signal line in the normal display area and the second signal line in the fan-out region FT consistent, thereby improving the mura of the display panel when it is off.

[0087] It should be understood that, in Figure 7 In the local area K2 of the fan-out area FT of the display panel shown, the intersection of the first signal line L1 (third analog line) and the second signal line L2 (second data fan-out line) projected onto the substrate can also be provided with a first analog via contact DTH1. The second signal line L2 is connected to its corresponding first analog via contact DTH1 through a via.

[0088] In this exemplary embodiment, the first simulated via contact portion DTH1, the second simulated via contact portion DTH2, and the first via contact portion TH1 form via contact portions. The minimum distance between the orthographic projections of adjacent via contact portions on the substrate in the first direction X is S1, and the maximum distance between the orthographic projections of adjacent via contact portions on the substrate in the first direction X is S2, wherein (S2-S1) / S1 is greater than or equal to 0 and less than or equal to 0.2. For example, (S2-S1) / S1 can be equal to 0, 0.1, 0.2, etc. The minimum distance between the orthographic projections of adjacent via contact portions on the substrate in the second direction Y is S3, and the maximum distance between the orthographic projections of adjacent via contact portions on the substrate in the second direction Y is S4, wherein (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.2. (S4-S3) / S3 can be equal to 0, 0.1, 0.2, etc. This arrangement allows for a uniform distribution of via contact portions, thereby further improving the mura problem when the display panel is off.

[0089] In this exemplary embodiment, the minimum distance between the orthographic projections of two adjacent first signal lines L1 on the substrate in the second direction Y is S5, and the maximum distance between the orthographic projections of two adjacent first signal lines L1 on the substrate in the second direction Y is S6, wherein (S6-S5) / S5 is greater than or equal to 0 and less than or equal to 0.2. For example, (S6-S5) / S5 can be equal to 0, 0.1, 0.2, etc. The minimum distance between the orthographic projections of two adjacent second signal lines L2 on the substrate in the first direction X is S7, and the maximum distance between the orthographic projections of two adjacent second signal lines L2 on the substrate in the first direction X is S8, wherein (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.2. For example, (S8-S7) / S7 can be equal to 0, 0.1, 0.2, etc. This arrangement allows the first signal lines L1 and the second signal lines L2 to be evenly distributed, thereby further improving the mura problem when the display panel is off.

[0090] In this exemplary embodiment, the display panel may include a pixel driving circuit, such as... Figure 18The diagram shown is a schematic representation of a pixel driving circuit in an exemplary embodiment of the display panel disclosed herein. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second reset signal terminal Re2; the first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first terminal of the second transistor T2 is connected to node N, the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3, and the gate of the second transistor T2 is connected to the gate driving signal terminal Gat. e; The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be connected to a light-emitting unit OLED, and the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors. P-type transistors have higher carrier mobility, which is beneficial for realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to the actual situation.

[0091] like Figure 19 As shown, Figure 18The diagram shows the timing of signals at each node in a driving method for a pixel circuit. Here, Gate represents the timing of signals at the gate drive signal terminal Gate, Re1 represents the timing of signals at the first reset signal terminal Re1, Re2 represents the timing of signals at the second reset signal terminal Re2, and EM represents the timing of signals at the enable signal terminal EM. The driving method for this pixel circuit may include a reset phase t1, a compensation phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to node N. In the compensation phase t2: the second reset signal terminal Re2 and the gate drive signal terminal Gate output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and simultaneously, the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs a second initial signal to the second terminal of the sixth transistor T6. During the light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. This drives the light-emitting unit to emit light under the influence of the voltage Vdata + Vth at node N. According to the formula for the output current of the driving transistor, I = (μWCox / 2L)(Vgs - Vth). 2 Where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the pixel circuit of this disclosure is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel circuit can avoid the influence of the driving transistor threshold on its output current.

[0092] In this exemplary embodiment, as Figure 7 As shown, the first analog line Dm1 and the second analog line Dm2 can be connected to the common electrode layer of the display panel, and the common electrode layer can form the second electrode of the light-emitting unit. It should be understood that in other exemplary embodiments, the first analog line and the second analog line can also transmit other signals. For example, the first analog line and the second analog line can also be used to provide a first power supply terminal, a first initial signal terminal, a second initial signal terminal, etc.

[0093] In this exemplary embodiment, the display panel may include Figure 18 The pixel driving circuit is shown. The display panel may further include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, and a second source / drain layer stacked sequentially, with insulating layers disposed between these layers. For example... Figure 20-28As shown, Figure 20 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 21 for Figure 20 The structural layout of the active layer is shown. Figure 22 for Figure 20 The structural layout of the first gate layer in the middle, Figure 23 for Figure 20 The structural layout of the second gate layer in the middle. Figure 24 for Figure 20 The structural layout of the first source / drain layer in the middle. Figure 25 for Figure 20 Structural layout of the second source / drain layer in the middle. Figure 26 for Figure 20 The structural layout includes an active layer and a first gate layer. Figure 27 for Figure 20 The structural layout includes an active layer, a first gate layer, and a second gate layer. Figure 28 for Figure 20 The diagram shows the structure layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer.

[0094] like Figure 20 , 21As shown in Figure 26, the active layer may include: a first active section 61, a third active section 63, a fourth active section 64, a fifth active section 65, a sixth active section 66, a seventh active section 67, a first sub-active section 621, a second sub-active section 622, a third sub-active section 623, an eighth active section 68, a ninth active section 69, a tenth active section 610, an eleventh active section 611, a twelfth active section 612, a thirteenth active section 613, a fourteenth active section 614, and a fifteenth active section 615. The first active portion 61 is used to form the channel region of the first transistor T1; the first sub-active portion 621 and the second sub-active portion 622 are used to form the channel region of the second transistor T2; the third sub-active portion 623 is connected between the first sub-active portion 621 and the second sub-active portion 622; the third active portion 63 is used to form the channel region of the driving transistor DT; the fourth active portion 64 is used to form the channel region of the fourth transistor T4; the fifth active portion 65 is used to form the channel region of the fifth transistor T5; the sixth active portion 66 is used to form the channel region of the sixth transistor T6; the seventh active portion 67 is used to form The channel region of the seventh transistor T7; the eighth active portion 68 and the thirteenth active portion 613 are connected to the two ends of the fourth active portion 64; the ninth active portion 69 is connected between the third active portion 63 and the fifth active portion 65; the tenth active portion 610 is connected between the first active portion 61 and the first sub-active portion 621; the eleventh active portion 611 is connected to the end of the first active portion 61 away from the first active portion 61; the twelfth active portion 612 is connected to the end of the seventh active portion 67 away from the sixth active portion 66; the fourteenth active portion 614 is connected between the seventh active portion 67 and the sixth active portion 66; and the fifteenth active portion 615 is connected to the end of the fifth active portion 65 away from the third active portion 63. The active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0095] like Figure 20 , 22As shown in Figure 26, the first gate layer may include a first reset signal line Re1, a second reset signal line Re2, a gate line Gate, an enable signal line EM, and a first conductive portion 11. The orthogonal projections of the first reset signal line Re1, the second reset signal line Re2, the gate line Gate, and the enable signal line EM on the substrate can all extend along the first direction X. The first reset signal line Re1 is used to provide a first reset signal terminal; the second reset signal line Re2 is used to provide a second reset signal terminal; the gate line Gate is used to provide a gate drive signal terminal; and the enable signal line EM is used to provide an enable signal terminal. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 61 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 67 and the fourth active portion 64 onto the substrate. A portion of the structure of the second reset signal line Re2 is used to form the gate of the seventh transistor T7, and a portion of the structure of the second reset signal line Re2 is used to form the gate of the fourth transistor T4. The orthographic projection of the gate line Gate onto the substrate covers the first sub-active portion 621. The orthographic projection of the second active portion 622 onto the substrate has a portion of the gate line structure used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 65 and the sixth active portion 66 onto the substrate. A portion of the enable signal line EM is used to form the gate of the fifth transistor T5, and a portion of the enable signal line EM is used to form the gate of the sixth transistor T6. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 63 onto the substrate. The first conductive portion 11 is used to form the gate of the driving transistor T3. The first conductive portion 11 can also be reused as the first electrode of a capacitor. In this exemplary embodiment, the orthographic projection of a certain structure onto the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure onto the substrate extending in a straight line or bending along that direction. Furthermore, the display panel can use the first gate layer as a mask to perform conductive processing on the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductive structure.

[0096] like Figure 20 , 23As shown in Figure 27, the second gate layer may include a first initial signal line Vinit1, a second initial signal line Vinit2, and a second conductive portion 22. The orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the substrate may extend along a second direction Y. The first initial signal line Vinit1 may be used to provide a first initial signal terminal, and the second initial signal line Vinit2 may be used to provide a second initial signal terminal. The orthographic projection of the second conductive portion 22 on the substrate may overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 may be used to form the first electrode of the capacitor C.

[0097] like Figure 20 , 24 As shown in Figure 28, the first source / drain layer may include a first bridging portion 31, a second bridging portion 32, a third bridging portion 33, a fourth bridging portion 34, a fifth bridging portion 35, a seventh bridging portion 37, and a first signal line L1. The first bridging portion 31 can connect to the eighth active portion 68 and the ninth active portion 69 via vias (black squares indicate via locations), connecting the second terminal of the fourth transistor T4 and the first terminal of the driving transistor T3. The second bridging portion 32 can connect to the eleventh active portion 611 and the first initial signal line Vinit1 via vias, connecting the first terminal of the first transistor T1 and the first initial signal terminal. The third bridging portion 33 can connect to the first conductive portion 11 and the tenth active portion 610 via vias, connecting the second terminal of the first transistor T1, the gate of the driving transistor T3, and the first terminal of the second transistor T2. The second conductive portion 22 has an opening 221. The orthographic projection of the via connecting the third bridging portion 33 and the first conductive portion 11 onto the substrate lies within the orthographic projection of the opening 221 onto the substrate, thus isolating it from the second conductive portion 22. The fourth bridging portion 34 can be connected to the fourteenth active portion 614 via a via, connecting the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor. The fifth bridging portion 35 can be connected to the thirteenth active portion 613 via a via, connecting the first electrode of the fourth transistor T4. The sixth bridging portion 36 can be connected to the twelfth active portion 612 and the second initial signal line Vinit2 via vias, connecting the first electrode of the seventh transistor and the second initial signal terminal. The seventh bridging portion 37 can be connected to the second conductive portion 22 and the fifteenth active portion 615 via vias, connecting the first electrode of the fifth transistor T5 and the second electrode of the capacitor C.

[0098] like Figure 20 , 25As shown, the second source / drain layer may include a power line VDD, a data line Da, a second signal line L2, and an eighth bridge portion 48. The orthogonal projections of the power line VDD, the second signal line L2, and the data line Da onto the substrate may extend along the second direction Y. The power line VDD may be used to provide a first power supply terminal, and the power line VDD may be connected to the seventh bridge portion 37 via vias to connect the first power supply terminal to the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The data line Da may be used to provide a data signal terminal, and the data line Da may be connected to the fifth bridge portion 35 via vias to connect the data signal terminal to the first electrode of the fourth transistor T4. The eighth bridge portion 48 may be connected to the fourth bridge portion 34 via vias to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighth bridge portion 48 may also be connected to an electrode portion via vias.

[0099] In this exemplary embodiment, as Figure 8 , 20 As shown, the first analog line Dm1 and the pixel driving circuit are correspondingly arranged. In the corresponding pixel driving circuit and the first analog line Dm1, the orthographic projection of the first analog line Dm1 on the substrate is located on the side of the orthographic projection of the first conductive part 11 on the substrate away from the orthographic projection of the gate line Gate on the substrate. The second analog line Dm2 and the pixel driving circuit are correspondingly arranged. In the corresponding pixel driving circuit and the second analog line Dm2, the orthographic projection of the second analog line Dm2 on the substrate is located on the side of the orthographic projection of the power line VDD on the substrate away from the orthographic projection of the data line Da on the substrate. The first adapter Cnt1 and the first analog line Dm1 and the second analog line Dm2 directly connected to it are correspondingly arranged. The pixel driving circuit and the first adapter Cnt1 corresponding to the same group of first analog lines Dm1 and second analog lines Dm2 are also correspondingly arranged.

[0100] In this exemplary embodiment, as Figure 8 , 13As shown, the plurality of electrode portions include a first electrode portion R, a second electrode portion G1, a third electrode portion B, and a fourth electrode portion G2. The first electrode portion R may be used as the first electrode for forming a red light-emitting unit, the second electrode portion G1 and the fourth electrode portion G2 may be used as the first electrode for forming a green light-emitting unit, and the third electrode portion B may be used as the first electrode for forming a blue light-emitting unit. In multiple electrode sections connected to the same row of pixel driving circuits, the first electrode section R, the second electrode section G1, the third electrode section B, and the fourth electrode section G2 are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, the first electrode section R and the third electrode section B are connected to the same column of pixel driving circuits, and the first electrode section R and the third electrode section B connected to the same column of pixel driving circuits are alternately distributed in the column direction. The second electrode section G1 and the fourth electrode section G2 are connected to another column of pixel driving circuits, and the second electrode section G1 and the fourth electrode section G2 connected to the same column of pixel driving circuits are alternately distributed in the column direction. In four adjacent pixel driving circuits in the first direction, the pixel driving circuit corresponding to the first electrode section R is provided with the first transition section, the pixel driving circuit corresponding to the second electrode section G1 is provided with the first transition section, and the pixel driving circuit corresponding to the third electrode section B is provided with the first transition section. The fourth electrode section G2 is not provided with the first transition section.

[0101] It should be understood that, in other exemplary embodiments, in the normal display area, m first transition portions are correspondingly provided for n adjacent pixel driving circuits in the first direction; where n is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and n is greater than m.

[0102] like Figure 29 As shown, Figure 20The diagram shows a partial cross-sectional view of the display panel taken along the dashed line BB. The display panel may further include a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a first dielectric layer 95, a passivation layer 96, and a planarization layer 97. The substrate 91, buffer layer 92, active layer, first insulating layer 93, first gate layer, second insulating layer 94, second gate layer, first dielectric layer 95, first source / drain layer, passivation layer 96, planarization layer 97, and second source / drain layer are sequentially stacked. The first insulating layer 93 and second insulating layer 94 may be silicon oxide layers, the first dielectric layer 95 may be a silicon nitride layer, the passivation layer 96 and buffer layer 92 may be made of silicon oxide, silicon nitride, etc., and the planarization layer 97 may be made of organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 91 may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, wherein the barrier layer may be an inorganic material. The materials of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the first source / drain layer and the second source / drain layer may include metallic materials, such as one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof, or a titanium / aluminum / titanium stack thereof. The sheet resistance of any conductive layer in the first gate layer and the second gate layer may be greater than the sheet resistance of any conductive layer in the first source / drain layer and the second source / drain layer.

[0103] like Figure 30-32 As shown, Figure 30 for Figure 7 Local map structure of region K3 in the middle area. Figure 31 for Figure 30 The structural layout of the first source / drain layer in the middle. Figure 32 for Figure 30 Structural layout of the second source / drain layer.

[0104] like Figure 7 As shown, the display panel also includes a border area CC surrounding the display area AA. The border area CC may include a first border area (left border) and a second border area (right border) disposed opposite each other in the first direction, and a third border area (top border) and a fourth border area (bottom border) disposed opposite each other in the second direction. Figure 30-32 As shown, the display panel may include an electrode ring 4HVSS located in the bezel area. The electrode ring 4HVSS can be connected to a common electrode layer via vias, and the electrode ring 4HVSS may be located in the second source / drain layer. At the upper bezel of the display panel, a second analog line Dm2 may be connected to the electrode ring 4HVSS located at the upper bezel.

[0105] like Figure 30-32As shown, the first source / drain layer may further include a first electrode line 3HVSS located on the upper frame. The orthographic projection of the first electrode line 3HVSS on the substrate extends along the first direction X. The electrode ring 4HVSS can be connected to the first electrode line 3HVSS through a via (black rectangular block). The first electrode line 3HVSS can reduce the resistance of the electrode ring 4HVSS, thereby reducing the voltage difference between different positions of the electrode ring 4HVSS.

[0106] like Figure 30-32 As shown, the display panel may also include an analog pixel driving circuit Dpix located on the upper bezel, and the sub-pixel unit where the analog pixel driving circuit Dpix is ​​located does not emit light. Figure 30 Only two rows of the analog pixel driving circuit Dpix are shown in the diagram. The first source / drain layer may also include a second electrode line 3VDD1. The orthogonal projection of the second electrode line 3VDD1 onto the substrate can extend along a first direction. The second electrode line 3VDD1 can be connected to the power line VDD in the display area.

[0107] like Figure 33-35 As shown, Figure 33 for Figure 7 Local map structure of region K4 in the middle area. Figure 34 for Figure 33 The structural layout of the first source / drain layer in the middle. Figure 35 for Figure 33 Structural layout of the second source / drain layer.

[0108] The electrode ring 4HVSS located on the left frame can be connected to the first analog line Dm1 via a via. Similarly, the electrode ring 4HVSS located on the right frame can also be connected to the first analog line Dm1 via a via.

[0109] The first source / drain layer may further include: a first initial access line 3Vinit1 and a second initial access line 3Vinit2, the orthogonal projections of the first initial access line 3Vinit1 and the second initial access line 3Vinit2 on the substrate can both extend along the second direction Y. The first initial access line 3Vinit1 can be connected to the first initial signal line Vinit1 located in the display area, and the second initial access line 3Vinit2 can be connected to the second initial signal line Vinit2 located in the display area.

[0110] The second source / drain layer may further include a first initial conductive portion 4Vinit1 and a second initial conductive portion 4Vinit2. The first initial conductive portion 4Vinit1 can be connected to the first initial access line 3Vinit1 via a via to reduce the resistance of the first initial access line 3Vinit1; the second initial conductive portion 4Vinit2 can be connected to the second initial access line 3Vinit2 via a via to reduce the resistance of the second initial access line 3Vinit2.

[0111] like Figure 36-42 As shown, Figure 36 for Figure 7 Local map structure of region K5 in the middle area. Figure 37 for Figure 36 The structural layout of the first gate layer in the middle, Figure 38 for Figure 36 The structural layout of the second gate layer in the middle. Figure 39 for Figure 36 The structural layout of the first source / drain layer in the middle. Figure 40 for Figure 36 Structural layout of the second source / drain layer in the middle. Figure 41 for Figure 36 The structural layout of the first gate layer and the second gate layer, Figure 42 for Figure 36 The structural layout of the first gate layer, the second gate layer, and the first source / drain layer.

[0112] like Figure 36-42 As shown, the first gate layer may further include a first data lead 1Da. The second gate layer may further include a second data lead 2Da. The orthographic projection of the first data lead 1Da on the substrate and the orthographic projection of the second data lead 2Da on the substrate can be alternately arranged. The data line Da and the second data fan-out line Fa2 in the display area can be connected to the first data lead 1Da through the ninth bridging part 39; the data line Da in the display area can be connected to the second data lead 2Da through the tenth bridging part 310.

[0113] like Figure 36-42 As shown, the first source / drain layer may also include a power access line 3VDD2. The orthographic projection of the power access line 3VDD2 on the substrate may extend along the first direction X. The power line VDD located in the display area may be connected to the power access line 3VDD2 through the eleventh bridging part 311.

[0114] like Figure 36-42 As shown, the second analog line Dm2 located in the display area can be connected to the electrode ring 4HVSS located on the lower bezel. The power management circuit of this display panel can provide a power signal to the electrode ring 4HVSS located on the lower bezel.

[0115] like Figure 36-42As shown, the first gate layer may further include a first initial analog line 1Vinit1, and the second gate layer may further include a second initial analog line 2Vinit1. Both the first initial analog line 1Vinit1 and the second initial analog line 2Vinit1 can be connected to a first initial signal line located in the display area. For example, the first initial analog line 1Vinit1 and the second initial analog line 2Vinit1 can be connected to a first initial access line 3Vinit1. The first initial analog line 1Vinit1 and the second initial analog line 2Vinit1 can make different areas of the display panel have a more uniform gate line distribution density, thereby improving the display uniformity of the display panel.

[0116] like Figure 36-42 As shown, the second analog line Dm2 can be connected to the first analog conductive part (not shown) located in the active layer through the first analog via DH1. The first analog conductive part can be configured in a one-to-one correspondence with the first analog via DH1. The eleventh bridging part 311 can be connected to the second analog conductive part (not shown) located in the active layer through the second analog via DH2. The second analog conductive part can be configured in a one-to-one correspondence with the second analog via DH2. The first analog conductive part and the second analog conductive part are configured independently. The first analog via DH1 and the second analog via DH2 can make the via distribution density more uniform in different areas of the display panel, thereby improving the display uniformity of the display panel.

[0117] It should be noted that, in the above embodiments, the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; the black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate. These black squares only indicate the location of the vias; different vias represented by black squares at different locations can penetrate different insulating layers.

[0118] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order or quantity meaning. A transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this exemplary embodiment, the channel region refers to the region through which the current mainly flows. In this exemplary embodiment, the first electrode can be the drain and the second electrode can be the source, or the first electrode can be the source and the second electrode can be the drain. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this exemplary embodiment, the "source" and "drain" can be interchanged. Additionally, the gate can also be referred to as the control electrode.

[0119] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0120] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0121] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel further comprises: a substrate substrate; a plurality of data lines located in the display area, a projection of the data lines on the substrate substrate is spaced apart along a first direction and extends along a second direction, the first direction and the second direction intersect; a plurality of first signal lines, a projection of the first signal lines on the substrate substrate extends along the first direction and is spaced apart along the second direction, part of the first signal lines in the fan-out area form first data fan-out lines, the first signal lines in the normal display area form first analog lines, the first data fan-out lines are arranged corresponding to the data lines, and the first data fan-out lines are connected to the data lines corresponding thereto; a plurality of second signal lines, different from the first signal lines in the same conductive layer, a projection of the second signal lines on the substrate substrate extends along the second direction and is spaced apart along the first direction, part of the second signal lines in the fan-out area form second data fan-out lines, and the second signal lines in the normal display area form second analog lines, the second data fan-out lines are arranged corresponding to the first data fan-out lines, and the second data fan-out lines are connected to the first data fan-out lines corresponding thereto; a plurality of first adapter parts located in the normal display area, the first adapter parts are connected between the first analog lines and the second analog lines which are projected on the substrate substrate and intersect; a pixel electrode layer, the pixel electrode layer comprises a plurality of electrode parts, a projection of the electrode parts on the substrate substrate and a projection of the first adapter parts on the substrate substrate do not overlap; the first analog lines and the second analog lines are arranged corresponding to part of the intersection points of the projections on the substrate substrate, and the first adapter parts are connected between the first analog lines and the second analog lines corresponding thereto; the number of intersection points of the first analog lines and the second analog lines on the substrate substrate is greater than the number of the first adapter parts; a first analog via contact part located in the fan-out area, an intersection point of the first signal lines and the second signal lines in the fan-out area on the substrate substrate and the first analog via contact part are arranged corresponding to each other, the first analog via contact part is spaced apart from the first signal lines, and the second signal lines are connected to the first analog via contact part corresponding thereto through a via; a second analog via contact part located in the normal display area, an intersection point of the first analog lines and the second analog lines on the substrate substrate which is not arranged corresponding to the first adapter part and the second analog via contact part are arranged corresponding to each other, the second analog via contact part is spaced apart from the first analog lines, and the second analog lines are connected to the second analog via contact part corresponding thereto through a via.

2. The display panel of claim 1, wherein, a plurality of the first signal lines and the first adapter parts are located in the same conductive layer, and a plurality of the second signal lines are located in the same conductive layer. The conductive layer where the second signal line is located is located on the side of the conductive layer where the first signal line is located away from the substrate. The first adapter and the first analog line are connected in the same layer, and the first adapter and the second analog line are connected through a via hole. The second analog line covers the first adapter on the substrate in orthographic projection.

3. The display panel of claim 2, wherein, The display panel further comprises: A first source-drain layer is located between the substrate and the pixel electrode layer, and the first source-drain layer comprises the first signal line and the first adapter; A second source-drain layer is located between the first source-drain layer and the pixel electrode layer, and the second source-drain layer comprises the second signal line and the data line.

4. The display panel of claim 1, wherein, The display panel comprises a pixel driving circuit; In the normal display area, part of the pixel driving circuit is provided with one first adapter, and n pixel driving circuits adjacent in the first direction are provided with m first adapters. Wherein, n is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and n is greater than m.

5. The display panel of claim 4, wherein, n is equal to 4, m is equal to 3, the first direction is the row direction, and the second direction is the column direction. The plurality of electrode parts comprises a first electrode part, a second electrode part, a third electrode part, and a fourth electrode part. In the plurality of electrode parts connected to the same row of pixel driving circuits, the first electrode part, the second electrode part, the third electrode part, and the fourth electrode part are sequentially and alternately distributed in the row direction. In the adjacent two columns of pixel driving circuits, the first electrode part and the third electrode part are connected to the same column of pixel driving circuits, and the first electrode part and the third electrode part connected to the same column of pixel driving circuits are sequentially and alternately distributed in the column direction, the second electrode part and the fourth electrode part are connected to another column of pixel driving circuits, and the second electrode part and the fourth electrode part connected to the same column of pixel driving circuits are sequentially and alternately distributed in the column direction. In the four pixel driving circuits adjacent in the first direction, the pixel driving circuit corresponding to the first electrode part is provided with the first adapter, the pixel driving circuit corresponding to the second electrode part is provided with the first adapter, and the pixel driving circuit corresponding to the third electrode part is provided with the first adapter.

6. The display panel of claim 4, wherein, The pixel driving circuit comprises a driving transistor, a second transistor, and a fifth transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the fifth transistor is connected to a power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The display panel further comprises: A first gate layer is located between the substrate and the pixel electrode layer, and the first gate layer comprises a first conductive part and a gate line, the orthographic projection of the gate line on the substrate extends along the first direction, the first conductive part is used to form the gate of the driving transistor, and part of the structure of the gate line is used to form the gate of the second transistor. A second source-drain layer is located between the first gate layer and the pixel electrode layer, and the second source-drain layer includes the power lines and the data lines, and the orthographic projection of the power lines on the substrate and the orthographic projection of the data lines on the substrate extend along the second direction; The first analog line and the pixel driving circuit are correspondingly arranged, and in the pixel driving circuit and the first analog line corresponding to each other, the orthographic projection of the first analog line on the substrate is located on the side of the orthographic projection of the first conductive part on the substrate away from the orthographic projection of the gate line on the substrate; The second analog line and the pixel driving circuit are correspondingly arranged, and in the pixel driving circuit and the second analog line corresponding to each other, the orthographic projection of the second analog line on the substrate is located on the side of the orthographic projection of the power line on the substrate away from the orthographic projection of the data line on the substrate; The first adapter and the first analog line and the second analog line directly connected thereto are correspondingly arranged, and the pixel driving circuit corresponding to the same group of the first analog line and the second analog line is correspondingly arranged with the first adapter.

7. The display panel of claim 1, wherein, The first adapter includes a first via contact part, and the first via contact part connects the second analog line through a via; The first analog via contact part, the second analog via contact part, and the first via contact part form a via contact part; The minimum distance of the orthographic projection of adjacent via contact parts on the substrate in the first direction is S1, and the maximum distance of the orthographic projection of adjacent via contact parts on the substrate in the first direction is S2, wherein (S2-S1) / S1 is greater than or equal to 0 and less than or equal to 0.2; The minimum distance of the orthographic projection of adjacent via contact parts on the substrate in the second direction is S3, and the maximum distance of the orthographic projection of adjacent via contact parts on the substrate in the second direction is S4, wherein (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.

2.

8. The display panel of claim 1, wherein, The orthographic projection of the first analog via contact part on the substrate and the orthographic projection of the electrode part on the substrate at least partially overlap; The orthographic projection of the second analog via contact part on the substrate and the orthographic projection of the electrode part on the substrate at least partially overlap.

9. The display panel of claim 1, wherein, The display panel further includes a pixel driving circuit and a light emitting unit, and the pixel driving circuit is connected to a first electrode of the light emitting unit. The display panel further includes: A common electrode layer for forming a second electrode of the light emitting unit; The first analog line and the second analog line are connected to the common electrode layer.

10. The display panel of claim 9, wherein, The display panel further includes a frame area around the display area, and the frame area includes a first frame area and a second frame area arranged opposite to each other in the first direction, and a third frame area and a fourth frame area arranged opposite to each other in the second direction; The display panel further includes: An electrode ring is located in the frame region and is connected to the common electrode layer, at least part of the structure of the electrode ring located in the first frame region is connected to the first analog line, at least part of the structure of the electrode ring located in the second frame region is connected to the first analog line, at least part of the structure of the electrode ring located in the third frame region is connected to the second analog line, and at least part of the structure of the electrode ring located in the fourth frame region is connected to the second analog line.

11. The display panel of claim 1, wherein, A minimum distance of a projection of two adjacent first signal lines on the substrate substrate in the second direction is S5, and a maximum distance of a projection of two adjacent first signal lines on the substrate substrate in the second direction is S6, wherein (S6-S5) / S5 is greater than or equal to 0 and less than or equal to 0.2; And / or, a minimum distance of a projection of two adjacent second signal lines on the substrate substrate in the first direction is S7, and a maximum distance of a projection of two adjacent second signal lines on the substrate substrate in the first direction is S8, wherein (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.

2.

12. The display panel of claim 1, wherein, The display panel further comprises a light emitting unit and a pixel driving circuit for driving the light emitting unit, the pixel driving circuit comprising a driving transistor, a fourth transistor, and a seventh transistor, a first electrode of the fourth transistor being connected to the data line, a second electrode of the fourth transistor being connected to a first electrode of the driving transistor, a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to a first electrode of the light emitting unit. The display panel further comprises: An active layer between the substrate substrate and the pixel electrode layer, the active layer comprising a seventh active part and a fourth active part, the seventh active part being used for forming a channel region of the seventh transistor, and the fourth active part being used for forming a channel region of the fourth transistor; A first gate layer between the active layer and the pixel electrode layer, the first gate layer comprising a second reset signal line, a projection of the second reset signal line on the substrate substrate covering a projection of the fourth active part on the substrate substrate and a projection of the seventh active part on the substrate substrate, part of the structure of the second reset signal line being used for forming a gate of the seventh transistor, and part of the structure of the second reset signal line being used for forming a gate of the fourth transistor.

13. The display panel of claim 12, wherein, The active layer further comprises: A third active part used for forming a channel region of the driving transistor; An eighth active part connected to the fourth active part; A ninth active part connected to the third active part; The display panel further comprises: A first source-drain layer between the first gate layer and the pixel electrode layer, the first source-drain layer comprising a first bridge part, the first bridge part being connected to the eighth active part and the ninth active part through vias, respectively.

14. The display panel of claim 1, wherein, The display panel further comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor, a first transistor and a second transistor, a first electrode of the first transistor is connected with a first initial signal line, a second electrode of the first transistor is connected with a gate electrode of the driving transistor, a first electrode of the second transistor is connected with the gate electrode of the driving transistor, and a second electrode of the second transistor is connected with a second electrode of the driving transistor. The display panel further comprises: an active layer between the substrate and the pixel electrode layer, the active layer comprises a first active part, a tenth active part, a first sub-active part, a second sub-active part, and a third sub-active part connected between the first sub-active part and the second sub-active part, the first active part is used for forming a channel region of the first transistor, the first sub-active part and the second sub-active part are used for forming a channel region of the second transistor, and the tenth active part is connected between the first active part and the first sub-active part; a second gate layer between the active layer and the pixel electrode layer, the second gate layer comprises the first initial signal line, a first protruding part and a second protruding part, the first protruding part is connected with the first initial signal line, and the second protruding part is connected with the first initial signal line; wherein a normal projection of the first protruding part on the substrate and a normal projection of the third sub-active part on the substrate at least partially overlap, and a normal projection of the second protruding part on the substrate and a normal projection of the tenth active part on the substrate at least partially overlap.

15. A display panel, wherein, The display area of the display panel comprises a fan-out area and a normal display area outside the fan-out area, and the display panel further comprises: a substrate; a plurality of data lines in the display area, normal projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, and the first direction and the second direction intersect; a plurality of first signal lines, normal projections of the first signal lines on the substrate extend along the first direction and are spaced apart along the second direction, part of the first signal lines in the fan-out area form first data fan-out lines, the first signal lines in the normal display area form first analog lines, the first data fan-out lines are arranged correspondingly to the data lines, and the first data fan-out lines are connected with the data lines corresponding thereto; a plurality of second signal lines, the second signal lines are located in different conductive layers from the first signal lines, normal projections of the second signal lines on the substrate extend along the second direction and are spaced apart along the first direction, part of the second signal lines in the fan-out area form second data fan-out lines, the second signal lines in the normal display area form second analog lines, the second data fan-out lines are arranged correspondingly to the first data fan-out lines, and the second data fan-out lines are connected with the first data fan-out lines corresponding thereto; a plurality of first switching parts in the normal display area, the first switching parts are connected between the first analog lines and the second analog lines whose normal projections on the substrate intersect. The display panel further comprises a pixel driving circuit, and in the normal display area, part of the pixel driving circuit is provided with one first adapter part in correspondence; And n pixel driving circuits adjacent in the first direction are provided with m first adapter parts in correspondence; n is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and n is greater than m; A plurality of first analog via contact parts are located in the fan-out area, and the intersection of the first signal line and the second signal line in the fan-out area is projected on the substrate substrate and the first analog via contact part is provided in correspondence, the first analog via contact part and the first signal line are spaced apart, and the second signal line is connected to the corresponding first analog via contact part through a via; A plurality of second analog via contact parts are located in the normal display area, and the intersection of the first analog line and the second analog line in the substrate substrate is not provided in correspondence with the intersection of the first adapter part, and the second analog via contact part is provided in correspondence, the second analog via contact part and the first analog line are spaced apart, and the second analog line is connected to the corresponding second analog via contact part through a via.

16. The display panel of claim 15, wherein, n is equal to 4, m is equal to 3, the first direction is the row direction, and the second direction is the column direction; The display panel further comprises: A pixel electrode layer, the pixel electrode layer comprises a plurality of electrode parts, and the plurality of electrode parts comprises a first electrode part, a second electrode part, a third electrode part and a fourth electrode part; Among the plurality of electrode parts connected to the same row of pixel driving circuits, the first electrode part, the second electrode part, the third electrode part and the fourth electrode part are alternately distributed in the row direction; Among the two adjacent columns of pixel driving circuits, the first electrode part and the third electrode part are connected to the same column of pixel driving circuits, and the first electrode part and the third electrode part connected to the same column of pixel driving circuits are alternately distributed in the column direction, the second electrode part and the fourth electrode part are connected to another column of pixel driving circuits, and the second electrode part and the fourth electrode part connected to the same column of pixel driving circuits are alternately distributed in the column direction; Among the four pixel driving circuits adjacent in the first direction, the pixel driving circuit corresponding to the first electrode part is provided with the first adapter part in correspondence, the pixel driving circuit corresponding to the second electrode part is provided with the first adapter part in correspondence, and the pixel driving circuit corresponding to the third electrode part is provided with the first adapter part in correspondence.

17. The display panel of claim 15, wherein, The pixel driving circuit comprises a driving transistor, a second transistor and a fifth transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the fifth transistor is connected to a power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor; The display panel further comprises: The first gate layer is located on one side of the substrate, and includes a first conductive part and a gate line. A projection of the gate line on the substrate extends along the first direction. The first conductive part is used to form a gate of the driving transistor. Part of the structure of the gate line is used to form a gate of the second transistor. The second source-drain layer is located on a side of the first gate layer away from the substrate, and includes the power line and the data line. A projection of the power line on the substrate and a projection of the data line on the substrate extend along the second direction. The first analog line and the pixel driving circuit are arranged correspondingly. In the corresponding pixel driving circuit and the first analog line, a projection of the first analog line on the substrate is located on a side away from a projection of the gate line on the substrate. The second analog line and the pixel driving circuit are arranged correspondingly. In the corresponding pixel driving circuit and the second analog line, a projection of the second analog line on the substrate is located on a side away from a projection of the data line on the substrate. The first transfer part, the first analog line and the second analog line directly connected to the first transfer part are arranged correspondingly. The pixel driving circuit corresponding to the same group of the first analog line and the second analog line is arranged correspondingly to the first transfer part.

18. A display device, wherein, The display device includes the display panel of any one of claims 1-17.

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