Preparation method of container isolator, container isolator and application thereof

Abstract

Embodiments of the present application relate to a preparation method of a container isolator, the container isolator and application thereof, wherein the preparation method of the container isolator comprises: forming a first electrode plate, a silicon oxide dielectric layer and a silicon nitride dielectric layer which are sequentially stacked on a substrate; forming a stress release groove in the silicon nitride dielectric layer; and forming a second electrode plate on the silicon nitride dielectric layer. According to the embodiments of the present application, the stress release groove is formed in the silicon nitride dielectric layer, so that the electric stress can be released in subsequent testing or use, the local property change at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer is avoided, the crack of the container isolator is avoided, and the working reliability of the container isolator is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a method for fabricating a capacitive isolator, the capacitive isolator itself, and its applications. Background Technology

[0002] Isolation devices in integrated circuits often employ coupling to achieve signal or power transmission, providing safety isolation and noise cancellation. Existing integrated circuit isolation methods commonly use optocoupler isolation, magnetic coupling isolation, and capacitive isolation. Among these, capacitive isolation uses capacitors to transmit signals or energy by changing charges, and can be integrated onto integrated circuits or fabricated as discrete devices. Capacitive isolation offers high immunity to electromagnetic interference, high transmission speed, and low power consumption. Based on the excellent compatibility of capacitive isolation on integrated circuits with CMOS (Complementary Metal Oxide Semiconductor) technology, its applications are more widespread, providing safety isolation and noise cancellation, and is often used in harsh environments.

[0003] A capacitive isolator consists of two opposing electrode plates and a dielectric layer between them. The dielectric layer, acting as an isolation layer, is one of the key factors determining the electrical performance of the capacitive isolator. Compared to a dielectric layer using pure silicon oxide (SiO2) film, capacitive isolators with a composite dielectric layer containing silicon nitride (SiN) exhibit higher withstand voltage characteristics and meet the requirements for higher voltage applications. Their test results in AC withstand voltage (AC BV) testing, surge testing, and dielectric breakdown (TDDB) testing are all superior to those of the former.

[0004] However, during electrical stress testing, cracks may appear in capacitive isolators with a composite dielectric layer containing silicon nitride, posing a certain risk of short circuit, reducing the reliability of the capacitive isolator, and seriously affecting its application. Summary of the Invention

[0005] In view of this, the present application provides a method for preparing a capacitive isolator, a capacitive isolator and its application in order to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a method for preparing a capacitive isolator, the method comprising:

[0007] A first electrode plate, a silicon oxide dielectric layer, and a silicon nitride dielectric layer are sequentially stacked on a substrate;

[0008] Stress relief grooves are formed in the silicon nitride dielectric layer;

[0009] A second electrode plate is formed on the silicon nitride dielectric layer.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the linewidth of the stress relief groove ranges from 5.4 μm to 12 μm; and / or, the length of the stress relief groove ranges from greater than or equal to the length of the gap between two adjacent first electrode plates or greater than or equal to the length of the gap between two adjacent second electrode plates, and in a direction perpendicular to the substrate plane, the stress relief groove is located between two adjacent first electrode plates and / or between two adjacent second electrode plates, and the length direction of the stress relief groove is consistent with the length direction of the corresponding gap.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, forming a stress-relieving groove in the silicon nitride dielectric layer includes:

[0012] A stress relief groove is formed that penetrates the silicon nitride dielectric layer; in a direction perpendicular to the substrate plane, the projection of the stress relief groove surrounds the projection of the first electrode plate and / or the projection of the second electrode plate.

[0013] In conjunction with the first aspect of this application, in an alternative embodiment,

[0014] The step of forming a second electrode plate on the silicon nitride dielectric layer includes:

[0015] A second electrode material is deposited on the silicon nitride dielectric layer, and the second electrode material fills the stress relief groove.

[0016] A portion of the second electrode plate material is removed to form the second electrode plate; wherein the second electrode plate material filling the stress relief groove is removed;

[0017] The method further includes:

[0018] A passivation layer is formed on the second electrode plate, and the passivation layer fills the stress relief groove.

[0019] Secondly, embodiments of this application provide a capacitive isolator, including: a first electrode plate, a second electrode plate, and a composite dielectric layer located between the first electrode plate and the second electrode plate;

[0020] The composite dielectric layer includes a silicon oxide dielectric layer and a silicon nitride dielectric layer stacked along the direction from the first electrode plate to the second electrode plate; wherein, stress relief grooves are formed in the silicon nitride dielectric layer.

[0021] In conjunction with the second aspect of this application, in an optional embodiment, the linewidth of the stress relief groove ranges from 5.4 μm to 12 μm; and / or, the length of the stress relief groove ranges from greater than or equal to the length of the gap between two adjacent first electrode plates or greater than or equal to the length of the gap between two adjacent second electrode plates, and in a direction perpendicular to the substrate plane, the stress relief groove is located between two adjacent first electrode plates and / or between two adjacent second electrode plates, and the length direction of the stress relief groove is consistent with the length direction of the corresponding gap.

[0022] In conjunction with a second aspect of this application, in an optional embodiment, the stress relief groove extends through the silicon nitride dielectric layer; and in a direction perpendicular to the first electrode plate and the second electrode plate, the projection of the stress relief groove surrounds the projection of the first electrode plate and / or the projection of the second electrode plate.

[0023] In conjunction with the second aspect of this application, in an optional embodiment, it further includes: a passivation layer;

[0024] The passivation layer is located on the side of the second electrode plate away from the composite dielectric layer, and the passivation layer fills the stress relief groove.

[0025] In conjunction with the second aspect of this application, in an optional embodiment, the capacitive isolator is a high-voltage capacitor, and the operating voltage of the capacitive isolator is greater than 2 kV.

[0026] Thirdly, embodiments of this application provide an application of a capacitive isolator as described in any of the second aspects in electrical stress testing.

[0027] The method for preparing the capacitive isolator, the capacitive isolator itself, and its application provided in this application, by forming a stress relief groove in the silicon nitride dielectric layer, facilitate the release of electrical stress during subsequent testing or use, avoid local characteristic changes at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer, thereby preventing cracks in the capacitive isolator and improving its operational reliability.

[0028] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0030] Figure 1 A top view of the insulator with cracks;

[0031] Figure 2 To Figure 1 Electron micrograph of a section of the medium-capacity isolator showing cracks;

[0032] Figure 3 This is a schematic diagram of the cross-sectional structure of a capacitive isolator in related technologies;

[0033] Figure 4 A schematic flowchart illustrating the fabrication method of the capacitive isolator provided in the embodiments of this application;

[0034] Figures 5 to 12 A cross-sectional structural diagram of the capacitive isolator provided in the embodiments of this application during the manufacturing process;

[0035] Figure 13 This is a planar projection view of the capacitive isolator provided in the embodiments of this application;

[0036] Figure 14 A planar projection view of a capacitive isolator including multiple capacitor units provided for embodiments of this application;

[0037] Figure 15 This is a planar projection view of another capacitive isolator provided in an embodiment of this application. Detailed Implementation

[0038] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0045] First, please refer to Figure 1 The capacitive isolator failed during electrical stress testing. Upon opening the package, numerous cracks were observed on the surface of the isolator (see reference). Figure 1 (Location indicated by the dashed box). A crack extends from one electrode of the capacitive isolator to the other, causing a short circuit between the electrodes and leading to failure.

[0046] The isolator is manufactured using the technology related to this application, and its cross-sectional structure can be referred to. Figure 3 .like Figure 3 As shown, the isolator includes: a first electrode plate 1022, a first silicon oxide dielectric layer 103, a second silicon oxide dielectric layer 106, and a silicon nitride dielectric layer 107 located on the first electrode plate 1022, a second electrode plate 1102 located on the silicon nitride dielectric layer 107, and a passivation layer 112 located on the second electrode plate 1102. The silicon oxide dielectric layers are schematically shown only through the first silicon oxide dielectric layer 103 and the second silicon oxide dielectric layer 106; in actual devices, the number of silicon oxide dielectric layers can be more than two, and of course, it is not excluded that there is only one layer. The first silicon oxide dielectric layer 103, the second silicon oxide dielectric layer 106, and the silicon nitride dielectric layer 107 form an isolation layer between the two electrode plates, which can be collectively referred to as the composite dielectric layer 1000.

[0047] The surface of the isolator is a passivation layer 112. To investigate how the cracks formed, the inventors sectioned the cracked portion of the isolator and obtained electron micrographs. Please refer to [reference needed]. Figure 2 Electron microscopy images reveal delamination at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer inside the capacitive isolator (see reference). Figure 2 (The location is indicated by the dashed box in the middle). After a series of experiments and tests, the inventors can basically determine the failure model as follows: Electrical stress causes local characteristic changes at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer, resulting in voids, defects, etc.; the local characteristic changes increase, and stress mismatch occurs at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer; delamination occurs at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer; a discharge path is generated; the stress mismatch becomes more significant; the crack becomes larger and longer, extending to the upper layer to form a passivation layer crack (PA crack).

[0048] Based on this, this application provides a method for manufacturing a capacitive isolator. Please refer to [link / reference]. Figure 4The method includes the following steps:

[0049] Step S01: A first electrode plate, a silicon oxide dielectric layer, and a silicon nitride dielectric layer are sequentially stacked on a substrate.

[0050] Step S02: Form a stress relief groove in the silicon nitride dielectric layer;

[0051] Step S03: Form a second electrode plate on the silicon nitride dielectric layer.

[0052] Understandably, the embodiments of this application form stress relief grooves in the silicon nitride dielectric layer, which helps to release electrical stress during subsequent testing or use, avoids local characteristic changes at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer, and thus avoids cracks in the capacitor isolator, improving the working reliability of the capacitor isolator.

[0053] Below, in conjunction with Figures 5 to 12 The schematic diagram of the cross-sectional structure of the capacitor isolator shown in the figure further illustrates the preparation method of the capacitor isolator provided in the embodiments of this application.

[0054] First, please refer to Figure 5 In step S01, a first electrode plate 1022, a silicon oxide dielectric layer (refer to 103 and 106 in the figure) and a silicon nitride dielectric layer 107 are formed on the substrate 100 in sequence.

[0055] Understandably, the fabrication method of the capacitive isolator provided in this application embodiment is compatible with CMOS processes. In addition to forming the capacitive isolator, other components can also be formed on the substrate 100.

[0056] The term "substrate" refers to the carrier on which subsequent material layers are deposited. The material of substrate 100 can be selected based on the actual product being fabricated, such as a polycrystalline silicon substrate, a silicon-on-insulator substrate, or other suitable substrate. Substrate 100 includes an upper surface and a lower surface that are opposite each other. The upper surface of the substrate is typically the side on which the device is formed, unless otherwise specified. Ignoring the flatness of the upper and lower surfaces, the plane containing the upper and lower surfaces of the substrate is defined as the substrate plane, and the direction parallel to the substrate plane is the direction along the substrate plane; the direction perpendicular to the substrate plane is also the stacking direction for subsequent material layers deposited on the substrate, or the thickness direction of the substrate / height direction of the device.

[0057] An intermediate dielectric layer 101 may also be included between the substrate 100 and the first electrode plate 1022. The intermediate dielectric layer 101 forms an insulating barrier between the substrate 100 and the first electrode plate 1022. The intermediate dielectric layer 101 can be a single layer or a multilayer structure, which can be set according to the actual needs of the product being manufactured.

[0058] The first electrode plate 1022 can be fabricated in the same layer as the first wiring layer 1021. Specifically, a first conductive layer 102 is formed on the substrate 100. The first conductive layer 102 includes various conductive pattern regions through an etching process. A portion of the conductive pattern regions serves as the first electrode plate 1022, and a portion of the conductive pattern regions serves as the first wiring layer 1021.

[0059] The material of the first electrode plate 1022 is, for example, a metal such as aluminum or copper, or a combination thereof.

[0060] Next, a first silicon oxide dielectric layer 103 can be formed on the first conductive layer 102. The first silicon oxide dielectric layer 103 serves not only as part of the isolation layer in the capacitor isolator but also as a dielectric layer between the first conductive layer 102 and the second conductive layer 105 to be formed. The thickness of the first silicon oxide dielectric layer 103 is approximately 6 μm. When silicon oxide material is deposited to form the first silicon oxide dielectric layer 103 using a deposition process, the silicon oxide material also fills the spaces between various conductive pattern regions of the first conductive layer 102. It is readily understood that after the deposition process, the upper surface of the first silicon oxide dielectric layer 103 is not flat; it protrudes at positions corresponding to the first electrode plate 1022 and the first wiring layer 1021, and is recessed at positions between the first electrode plate 1022 and the first wiring layer 1021. Therefore, a planarization process, such as chemical mechanical polishing (CMP), is generally required to treat the upper surface of the first silicon oxide dielectric layer 103.

[0061] Next, a first conductive via 104, electrically connected to the first conductive layer 102, can be formed within the first silicon oxide dielectric layer 103. The formation process of the first conductive via 104 can refer to existing conductive via formation processes, and will not be detailed here. The material of the first conductive via 104 includes, for example, metals such as tungsten. Furthermore, a planarization process may be further included to make the upper surface of the first conductive via 104 flush with the upper surface of the first silicon oxide dielectric layer 103.

[0062] Next, a second conductive layer 105 can be formed on the first silicon oxide dielectric layer 103. The second conductive layer 105 is etched to include various conductive pattern regions, of which a portion of the conductive pattern regions serves as the second wiring layer 1051.

[0063] Next, a second silicon oxide dielectric layer 106 can be formed on the second conductive layer 105. Similar to the first silicon oxide dielectric layer 103, the second silicon oxide dielectric layer 106 serves not only as part of the isolation layer in the capacitor isolator but also as the dielectric layer between the second conductive layer 105 and the third conductive layer 110 to be formed. The upper surface of the second silicon oxide dielectric layer 106 can also be subjected to a planarization process; please refer to the relevant description of the first silicon oxide dielectric layer 103 for details, which will not be repeated here.

[0064] Next, a silicon nitride dielectric layer 107 can be formed on the second silicon oxide dielectric layer 106. The silicon nitride dielectric layer 107 is formed only as a thin layer on the second silicon oxide dielectric layer 106. The total thickness of the silicon nitride dielectric layer 107 and the second silicon oxide dielectric layer 106 is approximately 6 μm. The thickness of the silicon nitride dielectric layer 107 can be in the range of 0.5 μm to 1.2 μm.

[0065] The first silicon oxide dielectric layer 103, the second silicon oxide dielectric layer 106, and the silicon nitride dielectric layer 107 together constitute the composite dielectric layer 1000. The composite dielectric layer 1000 can also be referred to as an isolation layer, or as part of an isolation layer. It should be noted that this explanation only uses the example of the composite dielectric layer 1000 comprising two silicon oxide dielectric layers, the first silicon oxide dielectric layer 103 and the second silicon oxide dielectric layer 106. In actual fabrication, the number of silicon oxide dielectric layers can be selected according to actual needs, and may include more than two layers, or even just one layer. Furthermore, the composite dielectric layer 1000 can obviously also include other material layers besides the silicon oxide and silicon nitride dielectric layers; this application does not specifically limit this.

[0066] In the composite dielectric layer 1000, at least one contact interface is formed between the silicon oxide dielectric layer and the silicon nitride dielectric layer.

[0067] Next, a second conductive via 108 can be formed penetrating the silicon nitride dielectric layer 107 and the second silicon oxide dielectric layer 106; the second conductive via 108 is in direct contact with the second conductive layer 105, thereby forming a conductive connection. The formation process of the second conductive via 108 can refer to the formation process of conductive vias in the prior art, and will not be described in detail here. The material of the second conductive via 108 can also include metals such as tungsten. In addition, a planarization process may be further included to make the upper surface of the second conductive via 108 flush with the upper surface of the silicon nitride dielectric layer 107.

[0068] Next, please refer to Figure 6 and Figure 7 Step S02 is performed to form a stress relief groove 1070 in the silicon nitride dielectric layer 107.

[0069] The stress relief groove 1070 is formed by photolithography. Specifically, a patterned first mask layer 109 is first formed on the silicon nitride dielectric layer 107. Then, using the first mask layer 109 as a mask, the silicon nitride dielectric layer 107 is etched to form the stress relief groove 1070 at the location where the silicon nitride dielectric layer 107 is removed.

[0070] Specifically, a stress relief groove 1070 is formed that penetrates the silicon nitride dielectric layer 107. During the etching process, the silicon oxide dielectric layer (specifically the second silicon oxide dielectric layer 106) is used as the etching stop layer.

[0071] As an optional specific implementation, the linewidth of the stress relief groove 1070 ranges from 5.4 μm to 12 μm. When the linewidth of the stress relief groove 1070 is less than 5.4 μm, the stress relief effect is not ideal, and a small amount of delamination may still occur at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer; while when the linewidth of the stress relief groove 1070 is greater than 12 μm, the stress relief groove 1070 occupies too much chip area, resulting in a large chip size. Optionally, the linewidth of the stress relief groove 1070 is, for example, 6 μm.

[0072] As an optional specific implementation, in a direction perpendicular to the substrate plane, the projection of the stress relief groove 1070 surrounds the projection of the first electrode plate 1022 (see reference). Figure 13 On the one hand, the stress relief groove 1070 has a closed annular planar shape; on the other hand, in terms of position and size, the stress relief groove 1070 is located on the periphery of the first electrode plate 1022, and the inner ring size of the stress relief groove 1070 is sufficient to accommodate the first electrode plate 1022. Thus, the stress relief groove 1070 can form isolation between the capacitor isolator and other components on the substrate; for cases where the capacitor isolator comprises multiple capacitor units consisting of multiple first electrode plates 1022 and multiple second electrode plates 1102, the stress relief groove 1070 can also form isolation between the capacitor units (see reference). Figure 14 ).

[0073] It should be understood that this application is not limited thereto. Please refer to [link / reference needed]. Figure 15 As another optional embodiment, the length of the stress relief groove 1070 is greater than or equal to the length of the gap between two adjacent first electrode plates 1022 or greater than or equal to the length of the gap between two adjacent second electrode plates 1102. Furthermore, in a direction perpendicular to the substrate plane, the stress relief groove 1070 is located between two adjacent first electrode plates 1022 and / or between two adjacent second electrode plates 1102, and the length direction of the stress relief groove 1070 is consistent with the length direction of the corresponding gap. The length of the gap is... Figure 15 It is indicated by h.

[0074] Specifically, when the stress relief groove 1070 is located between two adjacent first electrode plates 1022, the corresponding gap refers to the gap between the two adjacent first electrode plates 1022; when the stress relief groove 1070 is located between two adjacent second electrode plates 1102, the corresponding gap refers to the gap between the two adjacent second electrode plates 1102.

[0075] The gap between two adjacent first electrode plates 1022 or the gap between two adjacent second electrode plates 1102 can be referenced. Figure 15 The area indicated by the dashed box. The length direction of the gap is perpendicular to the arrangement direction between two adjacent first electrode plates 1022 or two adjacent second electrode plates 1102. Taking the case where the stress relief groove 1070 is located between two adjacent first electrode plates 1022 as an example, the length direction of the gap is perpendicular to the direction from one of the first electrode plates 1022 to the other. One side of the gap is one of the first electrode plates 1022, and the other side is the other first electrode plate 1022.

[0076] When two adjacent first electrode plates 1022 or two adjacent second electrode plates 1102 are arranged with their upper and lower edges aligned as shown in the figure, the length of the gap is equal to the length of each first electrode plate 1022 or each second electrode plate 1102. If the planar shape of the first electrode plate 1022 and / or the second electrode plate 1102 is considered to be approximately square, and two adjacent first electrode plates 1022 and / or two adjacent second electrode plates 1102 are aligned, then the length of the corresponding gap is equal to the side length of the square.

[0077] Understandably, considering that during unpacking and testing, technicians found that cracks frequently appeared between adjacent electrode plates, placing the stress relief groove between two adjacent electrode plates is more beneficial in reducing the probability of crack occurrence. Furthermore, having a stress relief groove length greater than or equal to the length of the gap between two adjacent electrode plates not only helps reduce the probability of crack occurrence but also creates a barrier between the two electrode plates, reducing the risk of short circuits and preventing crack propagation. Further, the length of the stress relief groove 1070 can be greater than or equal to 1.2h; even further, for example, greater than or equal to 1.5h.

[0078] The step of forming the stress relief groove 1070 is performed before forming the second electrode plate 1102. In the specific fabrication, the stress relief groove 1070 is etched out by adding a photomask for etching the silicon nitride dielectric layer 107 before depositing the top metal layer (hereinafter referred to as the "third conductive layer 110") to release electrical stress and prevent the capacitor isolator from cracking during high-voltage use.

[0079] It should be noted that not all trenches formed in a silicon nitride layer can be called stress-relieving trenches. A stress-relieving trench should refer to a trench that can release stress. In the capacitive isolators provided in the embodiments of this application, the stress-relieving trenches specifically release the electrical stress at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer. In fact, silicon oxide and silicon nitride stacks are frequently used in semiconductor device structures, but not all silicon oxide and silicon nitride stacks require stress release. Therefore, even if a trench is contained in the silicon nitride layer, if the trench does not play a role in releasing stress during device operation, then the trench should not be considered a stress-relieving trench.

[0080] Next, please refer to Figures 8 to 10 Step S03 is performed to form a second electrode plate 1102 on the silicon nitride dielectric layer 107.

[0081] Specifically, a second electrode material can be deposited first on the silicon nitride dielectric layer 107, and the second electrode material 1102 fills the stress relief groove 1070. Please refer to [reference needed]. Figure 8 In actual fabrication, the second electrode plate 1102 can be fabricated in the same layer as the third wiring layer 1101. Specifically, the third conductive layer 110 is formed on the silicon nitride dielectric layer 107. Next, please refer to... Figure 9 A patterned second mask layer 111 is formed on the third conductive layer 110. The second mask layer 111 defines the second electrode plate 1102, the third wiring layer 1101, and other conductive patterned areas. Next, please refer to... Figure 10 A portion of the material of the second electrode plate 1102 is removed to form the second electrode plate 1102; wherein the material of the second electrode plate 1102 filling the stress relief groove 1070 is removed. Specifically, the removal of a portion of the material of the second electrode plate 1102 is performed by an etching process, using a patterned second mask layer 111 as a mask, so that the third conductive layer 110 is formed to include various conductive pattern regions, wherein a portion of the conductive pattern regions serves as the second electrode plate 1102, and a portion of the conductive pattern regions serves as the third wiring layer 1101.

[0082] By removing the material of the second electrode plate within the stress relief groove 1070, new interface defects caused by the second electrode plate material are avoided. The step of removing the material of the second electrode plate within the stress relief groove 1070 can be completed simultaneously with the step of etching to form the second electrode plate 1102, avoiding the need for additional processes.

[0083] As an optional specific implementation, in a direction perpendicular to the substrate plane, the projection of the stress relief groove 1070 surrounds the projection of the second electrode plate 1102 (see reference). Figure 13Thus, the stress relief groove 1070 can form an isolation between the capacitor isolator and other components on the substrate; for cases where the capacitor isolator comprises multiple capacitor units consisting of multiple first electrode plates 1022 and multiple second electrode plates 1102, the stress relief groove 1070 can also form an isolation between the capacitor units (see reference). Figure 14 ).

[0084] Furthermore, in a direction perpendicular to the substrate plane, the projection of the stress relief groove 1070 can surround both the projection of the second electrode plate 1102 and the projection of the first electrode plate 1022.

[0085] It should be noted that the third wiring layer simply refers to a wiring layer different from the first wiring layer, and does not refer to the third wiring layer counting upwards from the first wiring layer where the first electrode plate 1022 is located. The material of the second electrode plate 1102, that is, the material of the third wiring layer 1101, can also be aluminum, copper, or other metal materials or combinations thereof.

[0086] Understandably, the method for fabricating the capacitive isolator provided in this application embodiment also forms an interconnect structure disposed on the same substrate 100 as the capacitive isolator. The interconnect structure includes wiring layers (such as the first wiring layer 1021, the second wiring layer 1051, and the third wiring layer 1101) and conductive vias (such as the first conductive via 104 and the second conductive via 108). At least one wiring layer is fabricated in the same layer as the first electrode plate 1022 of the capacitive isolator, and at least another wiring layer is fabricated in the same layer as the second electrode plate 1102 of the capacitive isolator. The conductive vias form conductive connections between the wiring layers.

[0087] Next, please refer to Figure 11 and Figure 12 The method may further include: forming a passivation layer 112 on the second electrode plate 1102, the passivation layer 112 filling the stress relief groove 1070.

[0088] Specifically, the passivation layer 112 can be made of silicon oxide. Thus, the stress relief groove 1070 is filled with silicon oxide, and the upper surface of the second silicon oxide dielectric layer 106 is in contact with the silicon oxide material at the location of the stress relief groove 1070.

[0089] No additional steps are required by filling the stress relief groove 1070 in the step of forming the passivation layer 112.

[0090] Understandably, in order to achieve conductive connections, the passivation layer 112 may expose the third wiring layer 1101 and the second electrode plate 1102 (see reference). Figure 12 Furthermore, this step can also be achieved through photolithography.

[0091] As an optional specific implementation, the third wiring layer 1101 is used to electrically lead out the first electrode plate 1022 of the capacitive isolator; in other words, the third wiring layer 1101 is electrically connected to the first electrode plate 1022 of the capacitive isolator. Thus, the third wiring layer 1101 and the second electrode plate 1102 can serve as the two voltage input terminals of the capacitive isolator in the electrical stress test.

[0092] Specifically, the first electrode plate 1022 and the first wiring layer 1021 can be connected through a certain conductive pattern area (not shown in the figure) in the third conductive layer 110, so that the first electrode plate 1022 is electrically connected to the third wiring layer 1101 through the first wiring layer 1021.

[0093] For a capacitive isolator, the number of first electrode plates 1022 and / or second electrode plates 1102 may be more than one; for example, two second electrode plates 1102 together constitute the upper electrode plate of a capacitive isolator. When the projection of the stress relief groove 1070 surrounds the projection of the second electrode plate 1102 and a capacitive isolator includes multiple second electrode plates 1102, the projection of the stress relief groove 1070 surrounds at least one projection of the second electrode plate 1102; of course, the projection of the stress relief groove 1070 may surround the projection of each second electrode plate 1102.

[0094] Based on this, the embodiments of this application also provide a capacitive isolator. Please continue to refer to... Figure 12 The capacitor isolator includes: a first electrode plate 1022, a second electrode plate 1102, and a composite dielectric layer 1000 located between the first electrode plate 1022 and the second electrode plate 1102; the composite dielectric layer 1000 includes a silicon oxide dielectric layer (refer to 103 and 106 in the figure) and a silicon nitride dielectric layer 107 stacked along the direction from the first electrode plate 1022 to the second electrode plate 1102; wherein, a stress relief groove 1070 is formed in the silicon nitride dielectric layer 107.

[0095] The capacitive isolator provided in this application embodiment has a stress relief groove 1070 formed in the silicon nitride dielectric layer 107, which helps to release electrical stress in subsequent testing or use, avoids local characteristic changes at the interface between the silicon oxide dielectric layer and the silicon nitride dielectric layer, and thus avoids cracks in the capacitive isolator, improving the working reliability of the capacitive isolator.

[0096] The capacitive isolator provided in this application embodiment is applied in integrated circuits.

[0097] As an optional specific implementation, the linewidth of the stress relief groove 1070 ranges from 5.4 μm to 12 μm.

[0098] As an optional specific implementation, the length of the stress relief groove 1070 is greater than or equal to the length of the gap between two adjacent first electrode plates or greater than or equal to the length of the gap between two adjacent second electrode plates, and in the direction perpendicular to the substrate plane, the stress relief groove 1070 is located between two adjacent first electrode plates and / or between two adjacent second electrode plates, and the length direction of the stress relief groove 1070 is consistent with the length direction of the corresponding gap.

[0099] As an optional specific implementation, the capacitor insulator further includes: a passivation layer 112; the passivation layer 112 is located on the side of the second electrode plate 1102 away from the composite dielectric layer, and the passivation layer 112 fills the stress relief groove 1070.

[0100] As an optional specific implementation, the capacitive isolator is a high-voltage capacitor with an operating voltage greater than 2 kV. Furthermore, the voltage applied to the capacitive isolator can be greater than 6 kV.

[0101] As an optional specific implementation, the stress relief groove 1070 penetrates the silicon nitride dielectric layer 107; in a direction perpendicular to the first electrode plate 1022 and the second electrode plate 1102, the projection of the stress relief groove 1070 surrounds the projection of the first electrode plate 1022 and / or the projection of the second electrode plate 1102.

[0102] Figure 13 This is a planar projection view of the capacitive isolator provided in an embodiment of this application, which mainly shows the projections of the silicon nitride dielectric layer 107, the stress relief groove 1070, and the first electrode plate 1022 and / or the second electrode plate 1102. As shown, the projection of the stress relief groove 1070 surrounds the projections of the first electrode plate 1022 and / or the second electrode plate 1102, so as to isolate the capacitor formed by the first electrode plate 1022 and the second electrode plate 1102 from other components on the substrate 100.

[0103] Furthermore, the capacitive isolator provided in this application embodiment may include multiple capacitor units composed of multiple first electrode plates 1022 and multiple second electrode plates 1102. Please refer to... Figure 14 The stress relief groove 1070 can also form isolation between capacitor cells. Furthermore, the portion of the stress relief groove 1070 located between two adjacent capacitor cells can be shared by the two capacitor cells (see the area shown in the dashed box in the figure), thus reducing the area occupied by the chip.

[0104] Based on this, the present application also provides an application of the capacitive isolator as described in any of the foregoing embodiments in electrical stress testing.

[0105] Specifically, the voltage applied to the capacitive isolator during the electrical stress test can be greater than 6 kV.

[0106] Practice has shown that conventional testing methods for capacitive isolators often require approximately three years for electrical stress testing, making it impossible to bring them to market and generate revenue in the short term. Shortening the testing time often requires increasing the test voltage; however, traditional capacitive isolators or those provided in related technologies cannot withstand excessively high voltages. The capacitive isolator provided in this application, by incorporating a stress relief groove 1070 to release electrical stress, can achieve electrical stress testing using a 6000V high-voltage stress, thereby significantly shortening the RE verification time.

[0107] While meeting the high-voltage testing requirements, this capacitive isolator can also be applied to even higher-voltage scenarios.

[0108] It should be noted that the embodiments of the preparation method of the capacitive isolator, the embodiments of the capacitive isolator, and the embodiments of the application of the capacitive isolator in electrical stress testing provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0109] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for preparing a capacitive isolator, characterized in that, The method comprises: forming a first electrode plate, a silicon oxide dielectric layer and a silicon nitride dielectric layer which are sequentially stacked on a substrate; forming a stress release groove in the silicon nitride dielectric layer; forming a second electrode plate on the silicon nitride dielectric layer; wherein the forming of the stress release groove in the silicon nitride dielectric layer comprises: forming a stress release groove penetrating through the silicon nitride dielectric layer; in a direction perpendicular to the substrate plane, a projection of the stress release groove encloses a projection of the first electrode plate and / or a projection of the second electrode plate.

2. The preparation method of the container isolator according to claim 1, wherein: a line width of the stress release groove ranges from 5.4 μm to 12 μm; and / or a length of the stress release groove is greater than or equal to a length of a gap between two adjacent first electrode plates or greater than or equal to a length of a gap between two adjacent second electrode plates, and in a direction perpendicular to the substrate plane, the stress release groove is located between the two adjacent first electrode plates and / or between the two adjacent second electrode plates, and a length direction of the stress release groove is consistent with a length direction of the corresponding gap.

3. The preparation method of the container isolator according to claim 1, wherein: the forming of the second electrode plate on the silicon nitride dielectric layer comprises: depositing a second electrode plate material on the silicon nitride dielectric layer, the second electrode plate material filling the stress release groove; removing part of the second electrode plate material to form the second electrode plate; wherein the second electrode plate material filled in the stress release groove is removed. The method further comprises: forming a passivation layer on the second electrode plate, the passivation layer filling the stress release groove. comprises:

4. A container isolator characterized by, a first electrode plate, a second electrode plate, and a composite dielectric layer located between the first electrode plate and the second electrode plate; the composite dielectric layer comprises a silicon oxide dielectric layer and a silicon nitride dielectric layer which are sequentially stacked in a direction from the first electrode plate to the second electrode plate; wherein a stress release groove is formed in the silicon nitride dielectric layer; the stress release groove penetrates through the silicon nitride dielectric layer; in a direction perpendicular to the first electrode plate and the second electrode plate, a projection of the stress release groove encloses a projection of the first electrode plate and / or a projection of the second electrode plate.

5. The container isolator according to claim 4, wherein: a line width of the stress release groove ranges from 5.4 μm to 12 μm; and / or a length of the stress release groove is greater than or equal to a length of a gap between two adjacent first electrode plates or greater than or equal to a length of a gap between two adjacent second electrode plates, and in a direction perpendicular to the substrate plane, the stress release groove is located between the two adjacent first electrode plates and / or between the two adjacent second electrode plates, and a length direction of the stress release groove is consistent with a length direction of the corresponding gap. further comprises: a passivation layer; 6. The container isolator of claim 4, wherein, the passivation layer is located on a side of the second electrode plate away from the composite dielectric layer, and the passivation layer fills the stress release groove. The container isolator is a high-voltage capacitor, and a working voltage of the container isolator is greater than 2 kilovolts. ​ 7. The container isolator of claim 4, wherein, ​ 8. Use of a container isolator as claimed in any one of claims 4 to 7 in electrical stress testing.

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