Quantum processing system and method

Abstract

Disclosed are quantum processing apparatuses and methods for shuttling a qubit between a pair of processing elements. In particular, a disclosed method for shuttling a qubit from a first processing element to a second processing element in a quantum processing apparatus comprising a plurality of processing elements includes applying an optimal bias configuration between the first processing element and the second processing element to shuttle the qubit from the first processing element to the second processing element in a manner that minimizes the time the qubit spends in one or more state transition points between the first processing element and the second processing element.

Description

Technical Field

[0001] Various aspects of this disclosure relate to an advanced processing device comprising an array of quantum processing elements, and particularly, but not exclusively, to an architecture for performing quantum processing and for transmitting quantum information along the array of quantum processing elements. Background Technology

[0002] Development is underway to implement novel, advanced processing devices that can perform powerful computations using methods different from current processors. These advanced devices promise to offer computational capabilities far exceeding those of current devices. For example, quantum processors capable of performing computations according to the rules of quantum mechanics are being developed. Methods for implementing devices that house qubits (qubits), the basic computational units of quantum processors, and quantum architectures have been explored and have achieved varying degrees of success.

[0003] The most promising approach to large-scale general-purpose quantum computing requires quantum error correction, a technique that enables the processing of quantum information using real-world noisy qubits, provided the noise is below the fault tolerance threshold.

[0004] For example, some quantum error correction methods for "surface codes" allow error thresholds as high as 1%. This error level can be achieved using multiple qubit platforms. However, to perform any meaningful operation with surface codes, a large number of qubits are required, thus scalability to a large number of qubits is necessary (e.g., 10^6 qubits). 8 Platforms with a large number of qubits (in kilobytes) present challenges in the field of quantum computing, even for the most promising platforms.

[0005] To build an "error-correcting quantum computer," a scalable architecture is needed. Ideally, such an architecture would incorporate a large number of qubits that are relatively close to each other and work together to perform error-correcting quantum computation. Furthermore, the architecture should be feasible to manufacture. Summary of the Invention

[0006] According to a first aspect of this disclosure, a method is provided for shuttles of qubits from a first processing element to a second processing element in a quantum processing device, the quantum processing device including a plurality of processing elements, the method comprising: applying an optimal bias configuration between the first processing element and the second processing element to shuttle the qubits from the first processing element to the second processing element by minimizing the time spent by the qubits at one or more state transition points between the first processing element and the second processing element.

[0007] The quantum processing device may further include one or more transmission elements located between the first processing element and the second processing element, and the method may further include applying an optimal bias configuration between pairs of one or more transmission elements to minimize the time spent by the qubit at one or more state transition points between one or more transmission elements and / or between the processing element and the transmission element.

[0008] In some embodiments, each of one or more transmission elements has a dwell bias point with the highest coherence time for the qubit, and shuttles the qubit from a first processing element to a second processing element by applying an optimal bias configuration such that the qubit dwells at the dwell bias point in each of the one or more transmission elements.

[0009] In some embodiments, the dwell bias point is obtained by tuning the interaction between qubit spin orbitals and qubit tunneling effects.

[0010] The method may further include: determining the cumulative phase rotation introduced into the qubit as the qubit shuttles from the first processing element to the second processing element, and correcting the cumulative phase rotation introduced into the qubit once the qubit shuttles into the second processing element.

[0011] In yet another embodiment, the method further includes correcting phase errors or phase rotations in the qubits by performing dynamic decoupling as the qubits shuttle to the second processing element and / or once the qubits shuttle to the second processing element.

[0012] Additionally, the quantum processing device may include one or more exchange-coupled gates disposed between a pair of processing elements or a pair of transmitting elements, the exchange-coupled gates being configured to control the time taken for a qubit to transition from one element to another.

[0013] In another aspect of this disclosure, a quantum processing device is provided, comprising: a plurality of quantum processing elements configured to operate as qubits; a plurality of quantum processing elements configured to transmit quantum information between qubits by shuttle electrons or holes; wherein the quantum processing elements are arranged in a predetermined geometry.

[0014] Each quantum processing element can be associated with a corresponding electrode; and in order to allow electrons or holes to shuttle between adjacent processing element pairs, an optimal bias voltage is applied between the corresponding electrode pairs to allow qubits to shuttle between adjacent processing element pairs in a manner that minimizes the time spent by electrons or holes at the state transition points between processing element pairs.

[0015] In some embodiments, one or more exchange-coupled gates may be located between pairs of quantum processing elements, and the one or more exchange-coupled gates are configured to reduce the potential barrier between adjacent pairs of processing elements during shuttle to minimize the time spent by electrons or holes at state transition points.

[0016] When a qubit is idle (i.e. not shuttling), the voltage applied to the electrodes of the corresponding processing element is at the dwell bias point where the coherence time of the qubit is highest (typically just below the voltage bias required to switch the qubit from one processing element to another).

[0017] Enabling qubits to shuttle between neighboring processing elements involves applying an optimal bias voltage such that an electron or hole remains at a dwell bias point in each of the pair of quantum processing elements.

[0018] In some embodiments, the dwell bias point is obtained by tuning the interaction between the qubit spin orbit and the qubit tunneling effect.

[0019] In some embodiments, the quantum processing device may be a silicon-based device, and in certain instances, a silicon MOS device. In such systems, multiple processing elements are quantum dots having electrons or holes encoded as qubits. Furthermore, multiple processing elements and / or transmission elements may form an N×M matrix, where N and M are integer values.

[0020] In a third aspect of this disclosure, a method is provided for shuttles of qubits from a first processing element to a second processing element in a quantum processing device, the quantum processing device comprising a plurality of processing elements, each of the processing elements having a dwell bias point with the highest coherence time for the qubits, and for shuttles of qubits from the first processing element to the second processing element, the method comprising applying an optimal bias configuration between the first and second processing elements such that the qubits remain at the dwell bias point in each of one or more transport elements.

[0021] In some embodiments, the optimal bias configuration enables the qubit to shuttle between the first processing element and the second processing element in less than 60 nanoseconds. Attached Figure Description

[0022] Figure 1A It is a schematic representation of a large-scale quantum computing device.

[0023] Figure 1B This is a schematic top view representation of a scalable quantum processing device according to some embodiments of the present disclosure.

[0024] Figure 2A and 2B A schematic diagram of a pair of quantum dots is shown according to some embodiments of the present disclosure.

[0025] Figure 3 This is a flowchart illustrating an example method for calibrating a scalable quantum processing device according to some embodiments of the present disclosure.

[0026] Figure 4 This is a stability diagram illustrating the detuned axis according to an embodiment of the present disclosure.

[0027] Figure 5 It is a graph illustrating the frequency of qubits as it changes with the detuning axis.

[0028] Figure 6 It is a graph illustrating the coherence time as it varies with the deharmonic axis.

[0029] Figure 7 This is a flowchart illustrating an example method for performing a 2-qubit operation using qubits located in spaced-apart processing elements.

[0030] Figure 8 This is a pulse diagram illustrating the ramp rate experiment.

[0031] Figure 9 It is a graph illustrating the coherence of qubits as a function of ramp time.

[0032] Figure 10 It is a graph illustrating the qubit fidelity as a function of ramp time.

[0033] Figure 11 This is a pulse diagram illustrating the corresponding states of the ESR pulse and detuning axis, and the states of the qubits, applied over time.

[0034] Figure 12 This is a pulse diagram illustrating a spectral experiment according to some embodiments of the present disclosure.

[0035] Figure 13 It is a schematic representation of a quantum state tomography experiment.

[0036] Figure 14 It is the Bloch sphere representation of the reconstructed spin state.

[0037] Figure 15 This is a schematic diagram illustrating a pulse sequence with dynamic decoupling for fidelity characterization.

[0038] Figure 16 This is a graph showing the echo fringes and the fitting results.

[0039] Figure 17 It is a graph showing the normalized echo amplitude as a function of the number of slope transitions.

[0040] Figure 18 This is a schematic diagram illustrating a pulse used to measure ramp time dependence.

[0041] Figure 19 This is a graph showing the pure transfer error as a function of ramp time.

[0042] While the invention may take various modifications and alternatives, specific embodiments are illustrated and described in detail in the accompanying drawings by way of example. However, it should be understood that the drawings and detailed description are not intended to limit the invention to the specific forms disclosed. They are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the invention as defined by the appended claims. Detailed Implementation

[0043] There are many engineering challenges associated with scalable quantum computing architectures. One challenge is related to maintaining the coherence of static or idle qubits (i.e., the qubits containing stored information). The coherence of qubits typically decreases over time due to various factors such as charge and electrical noise.

[0044] Another problem with scalable quantum computing architectures is the design constraint associated with nearest-neighbor interactions in the encoding of quantum information processing. Typically, a qubit can only interact with its nearest neighbor. The greater the distance between qubits, the lower the coupling between them. For this reason, most scalable silicon-based quantum computing architectures require densely packed qubits (typically less than 50 nanometers apart). This densely packed qubits often leads to other problems. Because each qubit requires control electrodes and charge sensing elements (which are also densely packaged), crosstalk between qubits often occurs. That is, a signal provided to control one qubit may unintentionally affect neighboring qubits.

[0045] Another problem associated with scalable quantum computing architectures involves the transport of qubits. For quantum processing, it is often necessary for a qubit to interact with another qubit that is not its nearest neighbor. In this case, the qubit needs to be transported to a location close to the other qubit (so that they can interact), and then the qubit needs to be transported back to its original location. It should be broadly understood that this transport or shuttle of qubits over longer distances also introduces undesirable decoherence within the qubit.

[0046] Various aspects of this disclosure attempt to address one or more of these problems. In some embodiments, the systems and methods described herein extend the coherence of a single qubit by storing it in a configuration least affected by charge and electrical noise. To this end, the inventors of this disclosure have identified an optimal bias configuration for the processing element that makes the precession frequency of the qubit insensitive to small changes in the bias voltage and minimizes the effects of charge and electrical noise on the decoherence of the qubit state, thereby producing high fidelity. In particular, the optimal bias configuration for the qubit to remain in a particular position is determined to be adjacent to and exactly before the bias voltage required to transfer the qubit from one position to another. This optimal bias configuration is referred to herein as the "dwelling bias point," and the bias voltage for the qubit to shuttle from one position to another is referred to herein as the "transition bias" and "state transition point."

[0047] In other aspects of this disclosure, the methods and systems described herein achieve long-distance communication between qubits by transmitting / shuttling qubits from one location to another with minimal coherence loss. Specifically, the inventors of this disclosure have determined that decoherence during the transmission / shuttling of qubits from one location to another can be minimized by ensuring that the time spent by the qubit in the configuration of the transition bias or state transition point is kept to a minimum. In particular, the inventors have identified that reducing the detuning ramp time for transitioning a qubit from one point to another minimizes decoherence and enables high-fidelity qubit shuttle. By ensuring that the qubit remains at a point of residence at a bias point and transitions from one point to another within a short detuning ramp time, aspects of this disclosure achieve long-distance transmission of qubits with minimal coherence loss.

[0048] In other aspects of this disclosure, the described systems and methods help relax the design constraints associated with nearest-neighbor interactions in quantum information processing codes and allow qubits to be further spaced apart while still allowing them to interact with each other. Because qubits can be coherently shuttled from one site to another using the techniques described above, it is possible to sparsely space processing elements in scalable quantum processing devices using interleaved transport elements. Transport elements can be used to transfer qubits from one processing element to another. This sparse spacing of processing elements helps reduce crosstalk in the system while still enabling interactions between spaced qubits.

[0049] It should be understood that dwell bias points and state transition points can differ for different qubits within the same scalable quantum processing architecture, and are most likely to differ from dwell bias points and state transition points in other scalable quantum processing architectures. However, these bias values ​​do not change over time. Therefore, scalable quantum processing devices can be calibrated incidentally or periodically to determine the dwell bias points and state transition points for each pair of sites within the scalable quantum processing device. These determined points can then be used whenever the scalable quantum processing device is required to perform computation.

[0050] In addition to the above, the inventors of this disclosure have also determined that the phase error introduced by transferring / shuttling a qubit from one point to another not only remains the same when the qubit is transferred / shuttling from the first point to the second point, but is also correctable.

[0051] These and other aspects of this disclosure will be described in detail in the following sections.

[0052] Instance-based scalable quantum processing devices

[0053] In some embodiments, aspects of this disclosure may, for example... Figure 1A The modular quantum processing device shown in the figure is implemented in a modular quantum processing device. In particular, Figure 1A Multiple qubit arrays or quantum processing modules 102 (each containing multiple processing elements or qubits 104) coupled to each other via long-distance qubit couplers 106 are shown. Furthermore, local electronics 108 intersperse these quantum processing modules 102. Figure 1A In this approach, local / classical electronic devices are placed within the qubit plane. Alternatively, these electronic device modules 108 may reside on a separate chip and be connected to the qubit module 102 via flip-chip or other similar techniques. The classical electronic devices may include analog-to-digital converters, digital-to-analog converters, and vector modulation, requiring a minimum number of control lines to interface with external systems. (Reference) Figure 4 An example of this architecture is described in “Interfacing spin qubits in quantum dots and donors-hot, dense, and coherent” by LMK Vandersypen et al. in the NPI Quantum Information article, which is incorporated herein by reference.

[0054] Furthermore, in some embodiments, the quantum processing device that performs the currently disclosed method (which may be) Figure 1AOne of the modules 102 shown includes a plurality of processing elements interspersed with a plurality of transmission elements. In some embodiments, the processing elements and transmission elements may be arranged in an N×M matrix (where N and M are integer values).

[0055] Figure 1B A simplified top view illustrating this quantum processing device 102. Processing element 110 is located in... Figure 1B The processing element 110 is depicted as a solid dot, and the transmission element 112 is depicted as an unfilled dot. The placement of the processing element 110 and the transmission element 112 is such that the distance between the processing element 110 and the other element is sufficient to prevent crosstalk (crosstalk often occurs in previously known architectures of quantum processing devices that include processing elements but not transmission elements).

[0056] In some embodiments, processing element 110 includes a silicon / dielectric interface and an electrode arrangement suitable for confining one or more electrons or holes in the silicon near the interface to form one or more quantum dots that can operate as one or more qubits. Transport elements 112 are similarly constructed as quantum dots, the only difference being that they do not operate as qubits. Alternatively, qubits are stationary in transport elements 112 by tunneling from adjacent processing or transport elements.

[0057] The quantum processing device 102 also includes a plurality of control components (not shown) disposed around the processing elements. Each control component includes a switch that interacts with electrodes to enable quantum operations. Multiple control lines are connected to the control components to enable simultaneous operation of the multiple processing elements.

[0058] Figure 2 illustrates as follows: Figure 1B A simplified view of the quantum processing device / module 200 shown (including processing element 110 and transmission element 112). Figure 2A It is a top view and Figure 2B This is a side cross-sectional view. In the described embodiment, the quantum processing device 200 includes a silicon substrate 202 and a dielectric layer 204, which in this example is silicon dioxide. Isotope-enriched silicon can be used. 28 Si. This can be an epitaxial layer grown on a conventional silicon substrate.

[0059] Quantum processing device 200 may include spin qubits, i.e., qubits encoded in the spin of electrons or holes. Because the hyperfine coupling between the qubits and the nuclear spins in the host crystal is reduced, implementations of spin qubits in silicon / silicon dioxide systems offer increased spin coherence compared to most compound semiconductors. Typically, to generate qubits, an electrostatic field is used to confine a small number of electrons within a quantum dot.

[0060] To do this, the quantum processing device 200 includes a first electrode 206 operable to form quantum dots 210 near an interface 205 between a silicon substrate 202 and a dielectric layer 204. Figure 2B Region 210 is shown that can confine electrons or holes. Specifically, a sufficient positive voltage applied to electrode 206 will cause electrons to be confined in region 210 and attached to dielectric layer 204, while a sufficient negative voltage applied to electrode 206 will cause holes to be confined in region 210 and adjacent to dielectric layer 204.

[0061] For example, a single electron can be confined in region 210, thus forming a confined quantum dot. A single qubit can be encoded in the spin of an isolated electron. Alternatively, the spin of an electron or hole within a single quantum dot can be used to encode the qubit. Additional electrode structures can also be used to assist in the confinement of the quantum dot. In an alternative embodiment, a single qubit can be encoded in the spin of one or more electrons or holes within one or more corresponding quantum dots. Other elements, such as doped regions or dielectric regions, can also be introduced at the interface to facilitate electron confinement. Additionally, global isolation electrodes above or below the interface can be used to modify the total electron concentration at the interface.

[0062] A second electrode 207 associated with transmission element 112 is operable to enable processing element qubits to be transported (typically via tunneling) from region 210 to region 211. The potential difference (or voltage bias) between the first electrode 206 and the second electrode 207 determines whether the qubit remains in region 210 or moves to region 211. As previously described, the voltage bias required for a qubit to shuttle from processing element 110 to transmission element 112 and vice versa is called a transition bias or “state transition point.” If the potential difference applied between electrodes 206 and 207 is positive and sufficient to cause tunneling of the qubit, the qubit formed under electrode 206 will shuttle to region 211 under electrode 207. Alternatively, if the potential difference applied between electrodes 206 and 207 is negative and sufficient to cause tunneling of the qubit, the qubit under region 211 will shuttle back to region 210. The value of the transition bias required for a qubit to tunnel from one quantum dot to another depends on the potential barrier between the two quantum dots, the distance between the two quantum dots, and so on.

[0063] In addition to processing element 110 and transport element 112, quantum processing device 200 may also include a charge sensing element to read the state of the qubit formed under electrode 206 when the qubit is under electrode 206, tunneling into region 211, or under electrode 207. In the example portion of the quantum processing device shown in FIG2, this charge sensing element is depicted as a single electronic transistor (SET) 208 adjacent to processing element 110 and transport element 112. In other embodiments, without departing from the scope of this disclosure, different charge sensing elements may be employed in the same plane as the processing element and transport element or in a different plane, such as quantum dot contact (QPC) sensors, tunnel junction sensors, or gate-based dispersion sensors.

[0064] Additionally, the quantum processing device 200 may also include a control element (not shown) for controlling the spin of the qubits. The control element transmits a magnetic microwave signal, also known as an electron spin resonance signal, and an ESR signal and an RF signal, also known as a nuclear magnetic resonance signal or NMR signal, to control the spin of the qubits. In the example system, the control element may be a transmission line, part of the architecture shown in Figures 1 and / or 2, or a global control element on a different plane or on a different part of a chip than the processing / transmission element.

[0065] In some embodiments, the quantum processing device 200 may also include an exchange-coupled gate (not shown) between a pair of processing elements, a pair of transmitting elements, or a pair of processing elements and a pair of transmitting elements, which is also referred to as a J-gate. The exchange-coupled gate is typically configured to tune the exchange coupling between two qubit sites, and in particular to reduce or increase the potential barrier between adjacent qubit sites to reduce or increase the time it takes for an electron or hole to transition from one qubit site to another.

[0066] In the scalable quantum computing architecture described in this paper, based on the above discussion and Figure 1B The principle configuration illustrated in Figure 2, or as an example Figure 1A The modular interconnect structure shown allows a large number of qubit devices to operate together to perform error-corrected quantum computing.

[0067] Methods for calibrating quantum processing devices

[0068] As previously discussed, in order to achieve coherent dwell and shuttle, the systems and methods of this disclosure calibrate quantum processing devices to identify the parameters required for storing and shuttle qubits with minimal coherence loss.

[0069] Figure 3An example method 300 for doing this is described, namely, a method for identifying parameters for storing and shuttling qubits between two locations with minimal coherence. Method 300 will be described relative to a pair of quantum dots, such as the quantum dot of processing element 110 and the quantum dot of transmission element 112. However, it should be understood that this method can be repeated for all other pairs of nearest-neighbor quantum dots in a quantum processing device, including between other adjacent processing elements 110 and transmission elements 112, between adjacent transmission elements 112, and between adjacent processing elements 110.

[0070] The method begins at step 302, where a dwell point is determined between a pair of adjacent quantum dots, for example, between quantum dot 210 of processing element 110 and quantum dot 212 of transmission element 112. In some embodiments, this is determined by first determining a transition point between the two quantum dots.

[0071] As previously described, in order to transfer electrons or holes from one quantum dot to another, for example from region 210 to region 211, a voltage difference is applied to two electrodes 206 and 207, causing electrons or holes confined under one electrode to tunnel to a region under the other electrode. In this disclosure, region 210 and region 211 will be referred to as quantum dot site A and quantum dot site B, respectively.

[0072] In one example, the difference between the gate voltage of electrode 207 and the inter-point transition voltage is defined as detuning ε. When the detuning value changes (i.e., as the gate voltage of electrode 207 changes), it alters the energy difference between the spin states located at individual sites. In another example, the detuning axis can be defined as a combination of the gate voltages (or even the J-gate, if used) of electrodes 206 and 207 and can be scanned by this combination of gate voltages.

[0073] Figure 4 The illustration shows a stability diagram 400 illustrating an example of this detuning. The x-axis represents the gate voltage applied at site B, and the y-axis represents the gate voltages applied at sites A 207 and 206, respectively. Line 402 defines the detuning axis for qubit transfer. A charge sensing element (e.g., SET 208) can be used to: a) sense the charge at sites A and B, b) determine whether the qubit remains at site A or site B, c) determine when the qubit shuttles between the two sites, and d) determine the transition point. For example, when the qubit tunnels from site A to site B, a spot of light is observed in the SET current as the charge state at site A changes from full to empty. This spot of light is interpreted as the qubit shuttling from site A to site B.

[0074] In one instance, to determine the transition point, a detuning value ε is increased and the corresponding charge at point A is sensed. The point on the detuning axis where a spot of light is observed in the sensed charge is determined as the transition point. This is defined as ε = 0 and at... Figure 4 The middle is marked by point 404.

[0075] Once the transition point is determined, the dwell point can be determined. As previously explained, the dwell point is the point where the influence of charge and electrical noise on the detuning axis on the qubit is minimal. In one embodiment, this dwell point can be determined based on the determination of the qubit precession frequency and ESR frequency, which vary with the detuning axis 402. For example, the detuning axis value can be increased and the qubit frequency can be detected.

[0076] Figure 5 Graph 500 illustrates the qubit precession frequency (along the y-axis) and ESR frequency as a function of the detuning axis (x-axis). As seen in graph 500, the qubit precession frequency and ESR frequency increase steadily as the detuning value increases toward ε = 0 (i.e., the transition point), and then suddenly decrease when the detuning axis is at ε = 0, i.e., when the qubit shuttles to site B. The detuning value at which the sudden change in precession frequency and ESR frequency is detected is identified as the transition point. Furthermore, due to the competition between Stark shift and tunneling hybridization, the detuning value at which the qubit frequency becomes insensitive to detuning fluctuations caused by charge noise is identified as the dwell point of said site.

[0077] In another instance, the dwell point can be determined (e.g., using the Hahn echo experiment) by measuring the coherence time of the qubits at different locations along the detuning axis. The point where the coherence time of the qubits along the detuning axis is highest is determined as the dwell point of said site. Figure 6 Figure 600 illustrates this situation. As can be seen from the figure, based on specific experiments and specific sites, the coherence time of the qubit at said site is determined to be highest at a detuning value of approximately -0.5 mV (about 300 microseconds), which determines the dwell point of said site.

[0078] Returning to method 300, once a stop point is determined for each of the two sites, the phase rotation that occurs when the qubit shuttles between site A and site B is determined at step 304.

[0079] Generally, when qubits shuttle, the transmitted electrons or holes experience electrical and magnetic interference, which affects the spin and phase of the electrons / holes, resulting in decoherence in the corresponding qubits.

[0080] Furthermore, because electrons or holes are confined below the dielectric layer 204, and the dielectric layer 204 can have microscopic variations in its structure, qubits in one quantum dot can behave differently from qubits in another quantum dot.

[0081] Due to these known problems, it is widely believed that transferring a qubit from one quantum dot to another will cause severe spin and phase decoherence in the qubit. However, the inventors of this disclosure have investigated the effects of such errors on the movement of a qubit from one site (e.g., processing element 110 quantum dot) to another (e.g., transport element 112 quantum dot) and have determined that the errors introduced by such movement of the qubit (if performed rapidly between dwell points) not only remain the same over time but are also correctable. In particular, it has been determined that if the determined dwell points are used and the qubit is transported using a short ramp time, the qubit experiences only small polarization errors, but may experience phase errors in some cases.

[0082] In one embodiment, quantum state tomography of the transferred qubit spin can be used to determine the effects on the qubit (e.g., rotation, decoherence, depolarization, and leakage) caused by shuttle between the two sites. The effects on the qubit's phase (e.g., phase rotation and dephase) introduced by shuttle between the two sites can also be determined by measuring the Ramsey fringes used for the transferred qubit spin. The potentially smaller effects of the shuttle process can be amplified by repeating the process. In an example, the qubit can be initialized with a specific spin at site A (and preferably at a determined dwell point), and then the qubit can shuttle to site B and back multiple times. Each time the qubit shuttles to site B and back, its spin phase can be determined by projecting along multiple axes. Alternatively, the phase of the qubit spin can be determined after a predetermined dwell time without the qubit shuttles back and forth. Using this, the phase rotation introduced by shuttle between the qubit and the site pair A and B can be determined.

[0083] Once the dwell point of each site is determined, and the transition point and phase rotation introduced by making the qubit shuttle between the two sites are determined, method 300 ends.

[0084] Subsequently, when the quantum processing device 100 is used for quantum computing and two qubit operations need to be performed between qubits located in two spaced-apart processing elements, one of the qubits can shuttle from its original site to the site of the other qubit and then shuttle back after performing the two qubit operations.

[0085] Figure 7 An example method 700 for performing a 2-qubit operation using qubits is described, wherein the qubits are located at two processing elements 110 spaced apart from each other. In the example method described herein, it is assumed that the two processing elements 110 are separated by five transmission elements 112 quantum dots. However, it should be understood that this is merely an example, and in implementations, the number of transmission elements 112 that the qubits must traverse can vary.

[0086] The method begins at step 702, wherein the qubit spin is held in the first processing element 110 at a dwell point. The dwell point can be calculated using method 300.

[0087] At step 704, the voltage bias between the first processing element 110 and its adjacent transmission element 112 ramps up to the dwell point of the adjacent transmission element, causing the qubit to tunnel from the first processing element 110 to the adjacent transmission element 112. In some embodiments, the ramp time for performing this operation is sufficiently small (e.g., approximately 50 ns) to minimize the time spent by the qubit at the state transition point. In other embodiments, the ramp time may be further reduced to a few nanoseconds or possibly to the sub-nanosecond level to further minimize the time spent by the qubit at the state transition point.

[0088] At step 706, it is determined whether further shuttle is needed. For example, because there are one or more transport elements 112 between the current transport element 112 and the second processing element 110. If it is determined that further shuttle is needed, method step 704 is repeated.

[0089] However, by repeating each subsequent time step 704, the voltage bias between the current transmission element 112 and the next transmission element 112 is ramped up to the dwell point of the next transmission element, so that the qubit tunnels from the current transmission element to the next transmission element.

[0090] This process is repeated until it is determined at step 706 that no further shuttles are needed. Thereafter, the method proceeds to step 708, where a given two-bit operation is performed between the shuttled qubit and the qubit residing in the second processing element. In some embodiments, if any phase rotation occurs during the shuttle from the first processing element to the second processing element, a cumulative phase rotation is calculated (e.g., based on a known phase rotation for each intermediate shuttle), and the cumulative phase rotation is corrected before performing the qubit operation.

[0091] Once the operation is complete, the shuttle qubit can be returned to the first processing element using a process similar to that described with reference to steps 704 and 706. When the qubit returns to the first processing unit, the accumulated phase rotation determined during the return shuttle is corrected.

[0092] Experimental results

[0093] Experiments were conducted on a system similar to the one shown in Figure 2.

[0094] Experiment 1: Dependence on ramp rate

[0095] Ramp time is the time required to detune the bias voltage between sites A and B so that the dwell bias point in site A is switched to the dwell bias point in site B.

[0096] The inventors of this disclosure have determined that a faster ramp rate exhibits the highest qubit coherence and qubit fidelity when shuttling between sites A and B.

[0097] Figure 8 The pulse diagram 800 illustrates this experiment. Specifically, the qubit superposition state is prepared by applying a half-π ESR pulse to the qubit. This is followed by multiple ramps and projected ESR pulses used to shuttle the qubit from site A to site B.

[0098] This operation was performed multiple times at different ramp times. Then, the coherence and fidelity of the qubits were measured for each ramp time. Figure 9 The diagram 900 illustrates the measured coherence (y-axis) as a function of ramp time (x-axis) over a single return journey. (See Figure 900.) Figure 9 As observed, coherence is negatively correlated with ramp time; that is, as ramp time increases, the coherence of qubits decreases.

[0099] Figure 10 The illustration shows graph 1000, which shows the qubit fidelity as a function of ramp time. From... Figure 10 As can be seen, the fidelity is highest for shorter ramp times (between approximately 0 and 80 ns) or faster ramp rates, and decreases as ramp time increases (e.g., above 100 ns in this example).

[0100] Experiment 2: To confirm that the polarization of qubits can be transmitted between sites with high fidelity.

[0101] In any experiment used to confirm whether the polarization of a qubit can be transmitted between sites with high fidelity, a major problem is that when the deharmonic axis value ε becomes equal to the Zeeman split, the energy levels of the relative spins in sites A and B will eventually match, thus contributing to the spin-flipping tunneling process from site A to site B due to a small site difference in the spin orbital field or spin quantization axis generated by electron movement. To avoid the formation of these degenerate points, tunneling coupling can be enhanced, for example, by using a J-gate above the Zeeman energy. Another advantage of large tunneling coupling is that it also suppresses state leakage due to non-adiabatic tunneling and allows for faster ramp rates.

[0102] During the experiment, to amplify the polarization error to a measurable level, spins were repeatedly transferred between sites (initialized in down or up states). See also Figure 11This diagram illustrates the pulses used in the polarization transfer fidelity experiment. A 368 ns long π pulse is applied (X) and deactivated (I) to prepare for both spin-up and spin-down initial states and to measure the probability of finding each state. The total time in the detuning ramp pulse segment increases by 56 ns for each detuning ramp, moving from one point to another. Detuning ramps are applied at 56 ns intervals to ensure spin transfer to the other point.

[0103] In one instance, from n consecutive transfer ramps F_pol ↑,n (or 1-F_pol) ↑,n ) and F_pol ↓,n (or 1-F_pol) ↓,n Then, the probability of finding a spin state that is the same as (or opposite to) the input state is used to obtain the spin-related polarization transfer fidelity F_pol. ↑ and F_pol ↓ These probabilities can be modeled as follows, treating the spin flip caused by the transfer as a memoryless process.

[0104]

[0105] Once the value F_pol is calculated ↑ and F_pol ↓ The polarization transfer fidelity for the spin-up and spin-down cases is determined to be respectively... and The spin scheme fidelity was determined to be high enough to justify neglecting the depolarization effect in the following experiments.

[0106] Experiment 3: Determining whether qubit coherence is maintained after the shuttle.

[0107] Furthermore, Ramsey-type spectroscopy was used to determine whether qubit coherence was maintained after qubits moved across sites. Figure 12 This diagram illustrates the pulses used in the spectral experiment. The spin prepared in the downward state at point A first rotates by half, and then accumulates the phase dwell time t during the inter-point deharmonic pulse. dwell This continues until the second half-π pulse projects the phase onto the polarization (up or down).

[0108] In this technique, a half-πESR pulse (at resonance with the Larmor frequency at site A) is used to initially prepare the qubit spin in an equal superposition of up and down states. Then, the detuning ε decreases on a nanosecond time scale from ε1 (at site A) to ε2 (at site A or B), for a duration of t. dwell The phase acquired during the detour to the deharmonic axis value ε2 is then projected onto the spin polarization via a second half-πESR pulse.

[0109] Based on this experiment, the time t spent at the deharmonic value ε2 is determined. dwell The final spin-up probability (p) changes up The oscillation of ) is visible, and is related to the dwell time t. dwell This is irrelevant, indicating that the entire process is phase-coherent. Importantly, the frequency for ε2>0 qubits begins to change rapidly and at approximately 30 MHz (compared to...). Figure 5 The saturation of the qubit resonance frequency difference between the observed sites indicates that electrons have actually completely transferred to sites in the saturation region (ε2>5mV). This leads to the conclusion that spins can be transferred to different sites while maintaining phase coherence.

[0110] The Ramsey-type spectroscopy technique described above allows for accurate measurement of voltage-dependent parameters (see above). Figure 5 This allows for the determination of the qubit precession frequency and the establishment of an understanding of qubit dispersion in tunnel-coupled quantum dot arrays.

[0111] Because of the energy splitting between instantaneous eigenstates in Ramsey-type spectroscopy measurements, the contribution from the smaller spin-flip tunneling term can be neglected, and a simple four-layer model can be used to predict the qubit precession frequency f as follows. Q -

[0112]

[0113] Where f A(B) It is the frequency of the bare qubit at site A(B). Here, α indicates the lever arm of the gate B voltage change along the ε axis over the energy difference between local states, t c Indicates tunnel coupling and t s Indicates its spin dependence (if the spin-up is larger, it is positively dependent). f A(B) Further parameterization to f A(B) =f Z +η A(B) ε+(-)Δf AB / 2, where f Z η is the average frequency of the bare qubit at ε = 0. A(B) Explain the Stark displacement constant, and Δf AB This gives the qubit frequency difference between sites at ε = 0. This explains the qubit frequency f measured along the ε axis at 200 mV. Q This modeling can also be used to determine the starting point of the deharmonic axis ε. Using the lever arm extracted from a separate experiment (0.21 eV / V), t is obtained. c =104GHz, t s =-3.4MHz, η A(B) =39(-7.1)MHz / V and Δf ABThe best fit is 33.4 MHz. Furthermore, in this example, the voltage at electrode 207 at the inter-point transition point is calculated to be 968.85 ± 0.04 mV, which experimentally defines the point where ε = 0. This model also allows for precise calculation of wavefunction hybridization for a given gate voltage condition. It should be noted that the qubit frequency exhibits very small spin dependence in inter-point tunneling coupling due to spin-orbit interactions. Furthermore, a dwell point (approximately ε = 7 mV) is found where the qubit frequency is first-order insensitive to detuning fluctuations caused by charge noise due to competition between Stark shift and tunneling hybridization. Notably, qubit shuttle can be performed within nanometers, several orders of magnitude faster than qubit dephase time.

[0114] Experiment 4: The effect of tunneling on qubits

[0115] Quantum state tomography experiments are performed to determine the effect of tunneling on qubits. In particular, quantum state tomography is performed with respect to spin states, both with and without site-to-site transfer.

[0116] As in Figure 13 The diagram schematically illustrates that, after initialization to the down state, a pre-transfer electron spin state |+y> is prepared at site A (ε = 10 mV) via a half-πESR pulse. The spin is then transferred to site B (ε = 10 mV), or idled at site A for the same amount of time as the transfer would take.

[0117] Ten types of predictive quantity control – eight half-p rotations with phase variation (controlled by microwave phase f) and identification (I) and π rotation (X) operations – for effectively altering the measurement fundamental state |ψ after spin-up readout. v > and helps reduce measurement bias error.

[0118] Furthermore, state preparation and measurement fidelity F are obtained by interleaving measurements of the spin-up probability of the spin prepared in the down or up state. M,↑(↓) F M,↑(↓) The measurement was 80.4% (87.9%), thus allowing for measurement visibility correction.

[0119] After 4,000 repetitions for each of the ten measurement base states, the corrected spin-up probability p was then estimated using maximum likelihood estimation. v Reconstruct the density matrix ρ of the spin state before or after the transfer. Figure 14 The Bloch sphere representation 1400 shows the reconstructed spin states before and after the inter-site transfer process. Projections onto the xy, yz, and zx planes are also shown. The main net effect of the transfer process is a phase shift. The root cause lies in the site dependence of qubit frequencies. Figure 14The illustrations show the magnitude (height) and phase (color) of the density matrix elements for individual states. For example, without transitions, states 1402 and 1404 have zero-phase rotation, while state 1406 has a phase between -π / 2 and -π, and state 1408 has a phase between π / 2 and π. With transitions, states 1410 and 1412 have zero phase, while state 1414 has a phase between 0 and -π / 2, and state 1416 has a phase between 0 and π / 2.

[0120] The density matrix ρ of the spin state before or after the transfer is restricted to non-negative Hermitian and is expressed by a complex matrix L:

[0121]

[0122] L is a 2×2 lower triangular matrix with real diagonal elements and three independent parameters, indicated by l = (l1, l2, l3). To obtain the closest physical ρ, the following cost function C is minimized:

[0123]

[0124] The state fidelity of the obtained ρ is determined by Define, where ρ ideal This represents the density matrix closest to the pure state at the mid-latitude of the Bloch sphere at 1400. That is, the ideal transfer process is considered to be one that does not alter the phase gate of the spin polarization. It should be noted that this definition of state fidelity implicitly ignores any coherent phase error. To estimate the statistical error, Monte Carlo simulations are performed to produce a distribution of the estimated state fidelity, from which a sigma (68.27%) confidence interval is calculated around its median.

[0125] This further verifies that site-to-site qubit transfer can be viewed as a phase-rotating gate. Its rotation angle... This can be related to the ε-dependent qubit frequency (dominated by the site-dependent Zeeman energy). The estimation is performed by comparing the reconstructed spin state after the transfer with the ideal case—that is, the pure state obtained after applying an ideal phase gate to the accurate |+y> state—assuming no errors in state preparation and measurement (SPAM). The state fidelity. Alternatively, after correcting for SPAM errors, the spin-free state has The fidelity is high. The results indicate that the transfer process is highly coherent, and another quantification method can be used to assess the associated errors.

[0126] To address phase errors in a single transmission from SPAM errors, a sequence of ramp pulses is employed, in which the transmission is repeated multiple times between state preparation and measurement. Residual spin coherence can be assessed using Ramsey interference techniques. This protocol amplifies the phase error, causing the phase oscillation amplitude to decay with the number of transfer cycles, *n*. When the error probabilities of consecutive transfers are uncorrelated, the amplitude decay will be exponential.

[0127] Furthermore, to improve transfer fidelity and study the noise spectrum, a dynamic decoupling step is introduced into the ramp sequence. Figure 15 The protocol shown involves applying a decoupling π-pulse between two identical series of transfer ramps. Echo fringes (see...) Figure 16 The measurement is performed by scanning the angle φ of the projection axis, thus demonstrating that the fringe phase does not change with the transfer cycle, as expected. This is achieved with n ramp transfers (see...). Figure 17 The amplitude attenuation of the changing echo fringes produces a phase error for each transition. This means that the dominant portion of the phase error induced during the transfer process cannot be refocused.

[0128] This inefficiency of dynamic decoupling pulses indicates that the underlying error mechanism is not caused by residual... 29 The slow, spontaneous flipping of the Si nucleus spin or the dominance of conventional charge noise with a 1 / f-type spectrum (e.g., fluctuations in the quantum dot hierarchy).

[0129] In addition, by changing such Figure 18 The experiment was conducted using the ramp rate shown. Specifically, the ramp time was varied, while the dwell time at a particular qubit site was kept constant. This technique was used to investigate the effect of the detuning ramp rate, verifying that a slower ramp rate reduces transfer fidelity (see [link to study]). Figure 19 This excludes any adiabatic effects—the detuned ramp rate employed is adiabatic relative to the tunneling band gap and valley split. The theoretical framework based on the adiabatic effect caused by 1 / f detuned noise correctly captures the qualitative ramp time dependence—the slower the ramp, the more time is spent in the unfavorable inter-point transition region, thus causing noise-induced excitation. The experimental data are best described by showing that the overall displacement of the disfiguring is approximately 1.5%, independent of the ramp rate. This indicates that there are some sources of error at each transition that are not caused by the time spent in the inter-point transition region.

[0130] The observed approximately 2% coherence loss per transfer corresponds to a spin transfer across approximately 50 sites before the phase coherence decays to 1 / e, or a distance of approximately 2 mm (assuming a 40 nm site spacing). In cases where only spin polarization is required (e.g., for qubit readout), electrons can be transferred across 2500 sites, or approximately 100 mm, before the polarization decays to 1 / e in the spin-up case. While this accuracy in spin transfer suggests that coherent coupling between long-range spins is achievable, fault-tolerant quantum computing architectures relying on qubit movement will require device setups adapted to enhance transfer fidelity. Based on the above experiments, the following desirable features can be identified: the ability to electrostatically control the inter-site tunneling rate to guarantee adiabatic channels; a reduction in the Larmor frequency difference between adjacent sites achievable by controlling spin-orbit coupling or operating under lower magnetic fields; and improvements in fabrication processes to generate less charge noise.

[0131] It should be understood that although the systems and methods described above describe silicon metal oxide semiconductor (MOS) quantum dots, the currently disclosed systems and methods can also be applied to silicon germanium systems.

[0132] Furthermore, the architectures illustrated in Figures 1 and 2 are merely examples of suitable scalable quantum computing architectures for implementing various aspects of the present invention. It should be understood that the disclosed embodiments can be implemented in any other suitable architecture.

[0133] The term “include” (and its grammatical variations) as used herein is used in the inclusive sense of “having” or “containing” rather than in the sense of “consisting of only”.

[0134] Those skilled in the art will understand that many variations and / or modifications can be made to the invention as illustrated in the specific embodiments without departing from the spirit or scope of the invention as generally described. Therefore, the embodiments of the invention should be considered illustrative rather than restrictive in all respects.

Claims

1. A method for shuttles qubits from a first processing element to a second processing element in a quantum processing device, the quantum processing device comprising a plurality of processing elements, the method comprising: An optimal bias configuration is applied between the first processing element and the second processing element to allow the qubit to shuttle from the first processing element to the second processing element in a manner that minimizes the time spent by the qubit at one or more state transition points between the first processing element and the second processing element.

2. The method of claim 1, wherein the quantum processing device further comprises one or more transmission elements located between the first processing element and the second processing element, and the method further comprises applying the optimal bias configuration between pairs of the one or more transmission elements such that the time spent by the qubit at one or more state transition points between the one or more transmission elements and / or between the processing element and the transmission element is minimized.

3. The method of claim 2, wherein each of the one or more transmission elements has a dwell bias point, the dwell bias point being a voltage bias at which the qubit dwells at a specific location and the coherence time of the qubit is highest, and causing the qubit to shuttle from the first processing element to the second processing element includes applying the optimal bias configuration such that the qubit dwells at the dwell bias point in each of the one or more transmission elements.

4. The method of claim 1, further comprising: Determine the cumulative phase rotation introduced into the qubit when the qubit shuttles from the first processing element to the second processing element; as well as Once the qubit shuttles to the second processing element, the accumulated phase rotation introduced into the qubit is corrected.

5. The method of claim 3, wherein the dwell bias point is obtained by tuning the interaction between the qubit spin orbit and the qubit tunneling effect.

6. The method of claim 1, wherein the quantum processing device is a silicon-based system.

7. The method of claim 6, wherein the quantum processing device is a silicon MOS system.

8. The method of claim 7, wherein the plurality of processing elements are quantum dots having electrons or holes that encode the qubits.

9. The method of claim 1, further comprising correcting phase error or phase rotation in the qubit by performing dynamic decoupling as the qubit shuttles to the second processing element and / or once the qubit shuttles to the second processing element.

10. The method of claim 1, wherein the plurality of processing elements form an N×M matrix, wherein N and M are integer values.

11. The method of claim 1, wherein the quantum processing device further comprises one or more exchange-coupled gates disposed between a pair of processing elements or a pair of transmitting elements, the exchange-coupled gates being configurable to control the time taken for the qubit to transition from one element to another.

12. The method of claim 1, wherein the time spent by the qubit at one or more state transition points between the first processing element and the second processing element is faster than the qubit dephase time.

13. A quantum processing device, comprising: Multiple quantum processing elements configured as qubit operations; Multiple quantum processing elements configured to transmit quantum information between qubits via shuttle electrons or holes; The quantum processing elements are arranged in a predetermined geometry, wherein: Each quantum processing element is associated with a corresponding electrode; and In order for the electrons or holes to shuttle between a pair of adjacent processing elements, an optimal bias voltage is applied between the corresponding electrode pairs to allow the qubits to shuttle between the adjacent processing element pairs in a manner that minimizes the time spent by the electrons or holes at the state transition points between the processing element pairs.

14. The quantum processing device according to claim 13, further comprising: One or more exchange-coupled gates are located between pairs of quantum processing elements, and the one or more exchange-coupled gates are configured to reduce the potential barrier between the adjacent processing element pairs during shuttle, so as to minimize the time spent by the electrons or holes at the state transition point.

15. The quantum processing apparatus of claim 13, wherein when the qubit is in an idle state, a voltage applied to the corresponding processing element maintains the qubit at a dwell bias point, the dwell bias point being a voltage bias at which the qubit remains at a specific position and the coherence time of the qubit is highest.

16. The quantum processing apparatus of claim 15, wherein causing the qubits to shuttle between adjacent processing elements comprises applying the optimal bias voltage such that the electrons or holes remain at the dwell bias point in each of the pair of quantum processing elements.

17. The quantum processing apparatus of claim 15, wherein the dwell bias point is obtained by tuning the interaction between the qubit spin orbit and the qubit tunneling effect.

18. The quantum processing device of claim 13, wherein the quantum processing device is a silicon-based system.

19. The quantum processing device of claim 18, wherein the quantum processing device is a silicon MOS system.

20. The quantum processing device of claim 19, wherein the plurality of qubits are quantum dots.

21. The quantum processing apparatus of claim 13, wherein the plurality of processing elements form an N×M matrix, wherein N and M are integer values.

22. The quantum processing apparatus of claim 13, wherein the time spent by the qubit at one or more state transition points between the first processing element and the second processing element is faster than the qubit dephase time.

23. A method for shuttle a qubit from a first processing element to a second processing element in a quantum processing device, the quantum processing device comprising a plurality of processing elements, each of said processing elements having a dwell bias point, said dwell bias point being a voltage bias at which the qubit dwells and the coherence time of the qubit is highest, and shuttles the qubit from the first processing element to the second processing element comprising applying an optimal bias configuration between the first processing element and the second processing element such that the qubit dwells at said dwell bias point in each of the one or more transport elements.

24. The method of claim 23, wherein the optimal bias configuration causes the qubit to shuttle between the first processing element and the second processing element in less than 60 nanoseconds.

25. The method of claim 23, wherein the time spent by the qubit at one or more state transition points between the first processing element and the second processing element is faster than the qubit dephase time.

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