Display device

Abstract

The display device includes: a first data signal line (DLg1) connected to one of two sub-pixels (SPg1, SPg2) emitting light of the same color; a second data signal line (DLg2) connected to the other; and a correction circuit (HC) electrically connected to the first data signal line and the second data signal line, the correction circuit (HC) correcting the floating potential by making the first data signal line (DLg1) and the second data signal line (DLg2) conduct.

Description

Technical Field

[0001] This invention relates to a display device. Background Technology

[0002] Patent Document 1 discloses a method for setting up a protection circuit between adjacent data signal lines to prevent electrostatic damage to the internal circuitry of a liquid crystal panel.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Publication No. 2005-156703 Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] If the data signal line of the display panel is disconnected, there is a problem that grayscale control of sub-pixels connected to the electrically floating data signal line cannot be performed.

[0008] Solution for solving the problem

[0009] One aspect of the present invention relates to a display device comprising: a first data signal line connected to one of two sub-pixels emitting light of the same color; a second data signal line connected to the other; and a correction circuit electrically connected to the first data signal line and the second data signal line, the correction circuit correcting the floating potential by making the first data signal line and the second data signal line conduct between them.

[0010] Invention Effects

[0011] According to one aspect of the present invention, when the second data signal line becomes a floating potential, the second data signal line is charged from the first data signal line via the correction circuit. This enables grayscale control of the sub-pixels connected to the second data signal line. Attached Figure Description

[0012] Figure 1 (a) is a schematic top view showing the configuration of the display device according to this embodiment.

[0013] Figure 1 (b) is a cross-sectional view showing the configuration of the display device.

[0014] Figure 2 This is a circuit diagram showing an example of the configuration of a pixel circuit.

[0015] Figure 3 This is a timing diagram showing the operation of the pixel circuit.

[0016] Figure 4 This is a schematic diagram showing an example of the structure of a non-display area (without broken lines).

[0017] Figure 5 This is a schematic diagram showing an example of the structure of a non-display area (with broken lines).

[0018] Figure 6 This is a circuit diagram showing an example of the configuration of a correction circuit.

[0019] Figure 7 It is shown Figure 4 The timing diagram shows the operation of the correction circuit under the following conditions.

[0020] Figure 8 It is shown Figure 5 The timing diagram shows the operation of the correction circuit under the following conditions.

[0021] Figure 9 This is a cross-sectional view showing an example of the configuration of the correction circuit. Detailed Implementation

[0022] Figure 1 (a) is a schematic top view showing the configuration of the display device according to this embodiment. Figure 1 (b) is a cross-sectional view showing the configuration of the display device.

[0023] like Figure 1 As shown, the display device 10 includes a substrate 2, a barrier layer (base coat) 3, a TFT layer (thin film transistor layer) 4, a top-emitting (emitting light to the upper side) type light-emitting element layer 5, and a sealing layer 6, and forms a light-emitting element ED and a pixel circuit PC for controlling the light-emitting element for each sub-pixel SP.

[0024] The display device 10 has a display area DA including multiple sub-pixels SP and a non-display area NA surrounding the display area DA. The display area DA includes a data signal line DL, a scan signal line Gn, an initialization signal line IL, a light emission control line EM, a discharge control line Fn, and a power supply line (high-potential side power supply line) PL.

[0025] The non-display area NA includes a terminal area TA where an electronic circuit chip is mounted, a bending area QA, and a correction circuit area HA. ​​The correction circuit area HA is formed between the bending area QA and the display area DA. By bending the end BS after the bending area QA by 180 degrees, the display device 10 can arrange the terminal area TA on the back side.

[0026] The substrate 2 is a flexible substrate with polyimide or other resins as the main component. For example, the substrate 2 can also be composed of two polyimide films and an inorganic film sandwiched between them. The barrier layer 3 is an inorganic insulating layer that prevents the intrusion of foreign substances such as water and oxygen. For example, it can be made of silicon nitride, silicon oxide, etc.

[0027] like Figure 1 As shown, the TFT layer 4 includes: a crystalline silicon semiconductor film SC formed on the base coating film 3, a first gate insulating film 14 covering the crystalline silicon semiconductor film SC, a first metal layer (including the lower gate electrode 15g) formed above the first gate insulating film 14, a first interlayer insulating film 16 covering the first metal layer, a second metal layer (not shown) formed above the first interlayer insulating film 16, an oxide semiconductor film SZ formed above the second metal layer, a second gate insulating film 18 formed above the oxide semiconductor film SZ, a third metal layer (including the upper gate electrode 19g) formed above the second gate insulating film 18, a second interlayer insulating film 20 formed above the third metal layer, a fourth metal layer (including the SE source electrode) formed above the second interlayer insulating film 20, and a planarization film 21 formed above the fourth metal layer.

[0028] A transistor Tr is formed on TFT layer 4, comprising a crystalline silicon semiconductor film SC and a lower gate electrode 15g, and a transistor TR is formed, comprising an oxide semiconductor film SZ and an upper gate electrode 19g. Furthermore, in the crystalline silicon semiconductor film SC, the portion overlapping with the lower gate electrode 15g functions as a semiconductor (channel), while the non-overlapping portion is made conductive through impurity doping or the like.

[0029] Crystalline silicon semiconductor films (SC) are, for example, composed of low-temperature formed polycrystalline silicon (LTPS). Oxide semiconductor films (SZ) are, for example, composed of at least one element selected from indium (In), gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr), and zinc (Zn) and oxygen. Specifically, oxide semiconductors containing indium (In), gallium (Ga), zinc (Zn), and oxygen (InGaZnO), and oxide semiconductors containing indium (In), tin (Sn), zinc (Zn), and oxygen (InSnZnO), etc., can be used.

[0030] The first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are, for example, composed of a single metal film or a multilayer metal film containing at least one of molybdenum, aluminum, titanium, tungsten, tantalum, chromium, and copper.

[0031] The first gate insulating film 14 may be made of, for example, a silicon oxide (SiOx) film. The first interlayer insulating film 16 may be made of, for example, a laminated film of silicon oxide (SiOx) and silicon nitride (SiNx). The second gate insulating film 18 may be made of, for example, a silicon oxide (SiOx) film. The second interlayer insulating film 20 may be made of a single layer of silicon oxide (SiOx) or a laminated film of silicon oxide (SiOx) and silicon nitride (SiNx). The planarization film 21 may be made of a coatable organic material such as polyimide or acrylic resin.

[0032] The light-emitting element layer 5 includes a lower electrode 22, an insulating edge cover film 23 covering the edge of the lower electrode 22, an EL (electroluminescent) layer 24 above the edge cover film 23, and an upper electrode 25 above the EL layer 24. The edge cover film 23 is formed, for example, by coating an organic material such as polyimide or acrylic resin and then patterning it by photolithography.

[0033] Multiple light-emitting elements (EDs) with different emitting colors are formed on the light-emitting element layer 5. Each light-emitting element includes an island-shaped lower electrode 22, an EL layer 24 (including the light-emitting layer EK), and an upper electrode 25. The upper electrode 25 is a shared, flat electrode used by the multiple light-emitting elements (EDs).

[0034] The light-emitting element (ED) can be, for example, an OLED (organic light-emitting diode) that includes an organic layer as the light-emitting layer, or a QLED (quantum dot light-emitting diode) that includes a quantum dot layer as the light-emitting layer.

[0035] The EL layer 24 is configured, for example, to sequentially stack a hole injection layer, a hole transport layer, an emissive layer (EK), an electron transport layer, and an electron injection layer from the lower layer side. The emissive layer is formed into an island shape at the opening (each sub-pixel) of the edge cover film 23 using evaporation, inkjet printing, or photolithography. Other layers are formed into island shapes or entire surfaces (shared layers). Alternatively, a configuration may be adopted where one or more of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer are not formed.

[0036] The lower electrode 22 (anode) is, for example, a light-reflecting electrode constructed by laminating ITO (Indium Tin Oxide) and an alloy containing Ag (silver) or Ag. The upper electrode 25 (cathode) is made of a thin metal film, such as a magnesium-silver alloy, and is transparent to light.

[0037] When the light-emitting element (ED) is an OLED, holes and electrons recombine within the light-emitting layer EK via a driving current between the lower electrode 22 and the upper electrode 25. The resulting excitons then emit light as they migrate to the substrate state. When the ED is a QLED, holes and electrons recombine within the light-emitting layer EK via a driving current between the lower electrode 22 and the upper electrode 25. The resulting excitons then emit light as they migrate from the quantum dot's conduction band level to the valence band level.

[0038] The sealing layer 6 covering the light-emitting element layer 5 is a layer that prevents foreign matter such as water and oxygen from penetrating into the light-emitting element layer 5. For example, it can be composed of two inorganic sealing films 26 and 28 and an organic film 27 formed between them.

[0039] Figure 2 This is a circuit diagram illustrating an example of a pixel circuit. The pixel circuit PC includes a capacitor element Cp, a reset transistor T1 connected to the control terminal (gate terminal) and the scan signal line Gn-1 of the front segment (n-1 segment), a threshold control transistor T2 connected to the control terminal and the scan signal line Gn of the self segment (n segment), a write control transistor T3 connected to the control terminal and the scan signal line Gn of the self segment (n segment), a drive transistor T4 controlling the current of the light-emitting element ED, a power supply transistor T5 connected to the control terminal and the light-emitting control line EM (n segment), a light-emitting control transistor T6 connected to the control terminal and the light-emitting control line EM (n segment), and an initialization transistor T7 connected to the control terminal and the discharge control line Fn of the self segment (n).

[0040] Additionally, the write control transistor T3, drive transistor T4, power supply transistor T5, and light-emitting control transistor T6 can be derived from... Figure 1 (b) is composed of a transistor Tr (with a crystalline silicon semiconductor film SC), and the reset transistor T1, threshold control transistor T2, and initialization transistor T7 can also be made of Figure 1 (b) is composed of a transistor TR (with an oxide semiconductor film SZ).

[0041] The control terminal of the driving transistor T4 is connected to the power supply line PL via capacitor Cp, and to the initialization signal line IL via reset transistor T1. The power supply line PL is supplied with a high-voltage side power supply ELVDD.

[0042] The source region of the driving transistor T4 is connected to the data signal line DL via the write control transistor T3, and to the power supply line PL via the power supply transistor T5. The drain region of the driving transistor T4 is connected to the control terminal of the driving transistor T4 via the threshold control transistor T2, and to the anode (lower electrode 22) of the light-emitting element ED via the light-emitting control transistor T6.

[0043] The anode of the light-emitting element ED is connected to the initialization signal line IL via the initialization transistor T7. A low-voltage side power supply (ELVSS) is supplied to the cathode (upper electrode 25) of the light-emitting element ED.

[0044] Figure 3 This is a timing diagram illustrating the operation of the pixel circuit. During period A, power supply transistor T5 and light-emitting control transistor T6 are off, and the light-emitting element ED is in a non-emitting state. During period B, reset transistor T1 and initialization transistor T7 are on, the potential of capacitor Cp is reset (initialized), and the anode of the light-emitting element ED is discharged. During period C, threshold control transistor T2 and write control transistor T3 are on, and data signals (corresponding to the potential of the input grayscale) are written, and threshold control (internal compensation) of drive transistor T4 is performed. During period D, power supply transistor T5 and light-emitting control transistor T6 are on, and the light-emitting element ED is in an emitting state.

[0045] Figure 4 This is a schematic diagram showing an example of the structure of a non-display area (without broken lines). Figure 5 This is a schematic diagram showing an example of the structure of a non-display area (with broken lines). Figure 6 This is a circuit diagram showing an example of the configuration of a correction circuit.

[0046] like Figure 4 As shown, the display device 10 includes a first data signal line DLg1 connected to one of two sub-pixels SPg1 and SPg2 that emit light of the same color (e.g., green light), a second data signal line DLg2 connected to the other, and a correction circuit HC electrically connected to the first data signal line DLg1 and the second data signal line DLg2. The correction circuit HC is formed in the TFT layer 4 of the correction circuit region HA (see reference). Figure 1 ).

[0047] Two sub-pixels, SPg1 and SPg2, are arranged adjacent to each other in a group of sub-pixels (a green sub-pixel group) that emit light of the same color as them. The first data signal line DLg1 and the second data signal line DLg2 extend from the display area DA, through the correction circuit area HA and the bending area QA, to the terminal area TA where the electronic circuit chip (including the source driver) is mounted. The first data signal line DLg1 and the second data signal line DLg2 are electrically connected to the source driver via multiple terminals in the terminal area TA.

[0048] For each data signal line, the forming layers in the display area DA, the correction circuit area HA, and the bending area QA can also be different. For example, a fourth metal layer can be formed in the display area DA, while a first or second metal layer can be formed in the correction circuit area HA and the bending area QA.

[0049] The correction circuit HC operates when the second data signal line DLg2 is at a floating potential (e.g., as shown in the example). Figure 5 As shown, in the case where the second data signal line DLg2 is broken in the bending area QA, the floating potential of the second data signal line DLg2 is corrected by making the first data signal line DLg1 and the second data signal line DLg2 conduct.

[0050] like Figure 6 As shown, the correction circuit HC includes N-type first diodes d1 and d4, P-type second diodes d2 and d3, P-channel transistors Ta, Tb, Td, Te, Tf, and N-channel transistor Tc, and nodes na, nb, nc, nd, ng, and nh. The N-type diodes are designed to short-circuit the gate and drain terminals of the N-channel transistor, making them the anode. The P-type diodes are designed to short-circuit the gate and drain terminals of the P-channel transistor, making them the cathode.

[0051] In the calibration circuit region HA, there is a clock line CKL, a first potential supply line VL1, and a second potential supply line VL2 connected to the calibration circuit HC. The clock line CKL supplies the calibration circuit HC with a clock signal that makes HT active (e.g., -8V) during each horizontal scan. The first potential supply line VL1 supplies the calibration circuit HC with a first potential (e.g., 2.5V), and the second potential supply line VL2 supplies the calibration circuit HC with a second potential (e.g., 7V). The gate terminals of transistors Ta, Td, Te, and Tf are connected to the clock line CKL.

[0052] The correction circuit HC includes a first path K1 that allows positive charge to flow from the first data signal line DLg1 to the second data signal line DLg2 and a second path K2 that allows positive charge to flow from the second data signal line DLg2 to the first data signal line DLg1.

[0053] The first path K1 includes a first diode d1, a transistor Tb, and a second diode d2. A first data signal line DLg1 and the source terminal (node ​​nc) of transistor Tb are connected via the first diode d1, and a second data signal line DLg2 and the drain terminal (node ​​na) of transistor Tb are connected via the second diode d2. Furthermore, the gate terminal (node ​​ng) and drain terminal (node ​​na) of transistor Tb are connected via a first capacitor C1. The drain terminal (node ​​na) of transistor Tb is connected to the first potential supply line VL1 via transistor Ta. The gate terminal (node ​​ng) of transistor Tb is connected to the second potential supply line VL2 via transistor Tf, and the source terminal (node ​​nc) of transistor Tb is connected to the second potential supply line VL2 via transistor Td. Node nc is also the cathode of the first diode d1, and node na is also the anode of the second diode d2.

[0054] The second path K2 includes a third diode d3, a transistor Tc, and a fourth diode d4. The first data signal line DLg1 and the source terminal (node ​​nd) of transistor Tc are connected via the third diode d3, and the second data signal line DLg2 and the drain terminal (node ​​nb) of transistor Tc are connected via the fourth diode d4. Additionally, the gate terminal (node ​​nh) and drain terminal (node ​​nb) of transistor Tc are connected via the second capacitor C2. The drain terminal (node ​​nb) of transistor Tc is connected to the second potential supply line VL2 via transistor Td, the gate terminal (node ​​nh) of transistor Tc is connected to the first potential supply line VL1 via transistor Te, and the source terminal (node ​​nd) of transistor Tc is connected to the first potential supply line VL1 via transistor Ta. Node nd is also the anode of the third diode d3, and node nb is also the cathode of the fourth diode d4.

[0055] Figure 7 It is shown Figure 4 The timing diagram shows the operation of the correction circuit under certain conditions. For example... Figure 4 As shown, under the condition that the second data signal line DLg2 is not disconnected (normal state), the correction circuit HC is as follows: Figure 7 It operates as shown. Furthermore, the data signal range is 2.5V (white) to 7V (black), with the first potential (2.5V) below the minimum value of the range and the second potential (7V) above the maximum value of the range.

[0056] For example, during a horizontal scan where the data signal on the first data signal line DLg1 is 7V and the data signal on the second data signal line DLg2 is 2.5V, when the clock signal on the clock line CKL becomes active (-8V), the second data signal line DLg2, node na (anode of d2), node nd (anode of d3), and node nh become 2.5V, while the first data signal line DLg1, node nb (cathode of d4), node nc (cathode of d1), and node ng become 7V. That is, the gate potential of transistor Tc is initialized to 2.5V (first potential), the gate potential of the channel transistor Tb is initialized to 7V (second potential), the cathode potentials of diodes d1 and d4 are initialized to 7V (second potential), and the anode potentials of diodes d2 and d3 are initialized to 2.5V (first potential). Therefore, diodes d1, d2, d3, d4, Tb, and Tc are cut off, and paths K1 and K2 are not conducting. The same applies during horizontal scans where the data signal on the first data line DLg1 is 2.5V and the data signal on the second data line DLg2 is 7V; paths K1 and K2 are not conducting. The same applies during horizontal scans where the data signal is greater than 2.5V but less than 7V.

[0057] Figure 8 It is shown Figure 5 The timing diagram shows the operation of the correction circuit under certain conditions. For example... Figure 5 As shown, when the second data signal line DLg2 is disconnected, the correction circuit HC... Figure 8 That's how it works. For example, during a horizontal scan when the first data signal line DLg1 is 7V, when the clock signal of the clock line CKL becomes active (-8V), nodes na, nd, and nh become 2.5V, and the first data signal line DLg1, node nb, node nc, and node ng become 7V.

[0058] Here, when the disconnected second data signal line DLg2 becomes a floating potential (e.g., 0V), the P-type second diode d2 conducts. As the potential of node na decreases, the potential of node ng (the gate terminal of the P-channel transistor Tb), which is connected to node na via the first capacitor C1, is introduced, and transistor Tb conducts. Consequently, the first diode d1 conducts, the first path K1 conducts, and the second data signal line DLg2 is charged to approximately 7V (floating potential correction). When the floating potential is 0V, the second path K2 does not conduct because the fourth diode d4 is not conducting.

[0059] Furthermore, if the floating potential of the disconnected second data signal line DLg2 is 10V, then as the N-type fourth diode d4 turns on and the potential of node nb rises, the potential of node nh (the gate terminal of the N-channel transistor Tc), which is connected to node nb via the second capacitor C2, also rises, and transistor Tc turns on. Consequently, the third diode d3 turns on, the second path K2 turns on, and the second data signal line DLg2 is charged to approximately 7V (for floating potential correction). When the floating potential is 10V, since the second diode d2 does not turn on, the first path K1 does not turn on.

[0060] Additionally, during the horizontal scan when the data signal of the first data signal line DLg1 is 2.5V, when the clock signal of the clock line CKL becomes active (-8V), the first data signal line DLg1, node na, node nd, and node nh become 2.5V, and nodes nb, node nc, and node ng become 7V.

[0061] Here, when the disconnected second data signal line DLg2 becomes a floating potential (e.g., 0V), the P-type second diode d2 conducts. As the potential of node na decreases, the potential of node ng (the gate terminal of the P-channel transistor Tb), which is connected to node na via the first capacitor C1, is introduced, and transistor Tb conducts. Consequently, the first diode d1 conducts, the first path K1 conducts, and the second data signal line DLg2 is charged to approximately 2.5V (for floating potential correction). When the floating potential is 0V, the second path K2 does not conduct because the fourth diode d4 is not conducting.

[0062] Furthermore, if the floating potential of the disconnected second data signal line DLg2 is 10V, then as the N-type fourth diode d4 turns on and the potential of node nb rises, the potential of node nh (the gate terminal of the N-channel transistor Tc), which is connected to node nb via the second capacitor C2, rises, and transistor Tc turns on. Consequently, the third diode d3 turns on, the second path K2 turns on, and the second data signal line DLg2 is charged to approximately 2.5V (floating potential correction). When the floating potential is 10V, since the second diode d2 does not turn on, the first path K1 does not turn on. The same applies during the horizontal scan period when the data signal is greater than 2.5V and less than 7V.

[0063] As described above, when the second data signal line DLg2 is disconnected and becomes a floating potential, the second data signal line DLg2 is charged from the first data signal line DLg1 via the correction circuit HC. This enables grayscale control of the sub-pixel SPg2 connected to the second data signal line DLg2. Furthermore, since the sub-pixel SPg2 is adjacent to the sub-pixel SPg1 (connected to the first data signal line DLg1) in the arrangement of sub-pixels of the same color, there are almost no display problems.

[0064] Figure 9 This is a cross-sectional view showing the correction circuit area. (Example) Figure 9 As shown, in the correction circuit region HA and the bending region QA, the first data signal line DLg1 and the second data signal line DLg2 are formed on the first metal layer, and the third data signal line DLb1 is formed on the second metal layer.

[0065] The first diode d1 includes an oxide semiconductor film SZ that overlaps with the lower electrode 15e (first metal layer) via a first gate insulating film 14, with the lower electrode 15e serving as the anode and the middle electrode 17e (second metal layer) serving as the cathode. The lower electrode 15e is electrically connected to the first data signal line DLg1 via a circuitous wiring (not shown) (e.g., wiring that conducts the crystalline silicon semiconductor film).

[0066] The crystalline silicon semiconductor film SC includes semiconductor regions X2 and X4 that function as semiconductors and conductor regions X1 and X3 that function as conductors. Conductor region X3 is formed between semiconductor regions X2 and X4, and semiconductor region X2 is formed between conductor regions X1 and X3. Conductor region X1 is in contact with the middle layer electrode 17e, and semiconductor region X4 is in contact with the second data signal line DLg2 (first metal layer).

[0067] The second diode d2 includes a semiconductor region X4, with the second data signal line DLg2 serving as the cathode and the conductor region X3 serving as the anode. The transistor Tb includes a semiconductor region X2 functioning as a channel and a gate terminal 15c (node ​​ng) of a first metal layer, with the conductor region X1 serving as the source terminal (node ​​nc) and the conductor region X3 serving as the drain terminal (node ​​na). A capacitor electrode 17c (second metal layer) is in contact with the gate terminal 15c, and a first capacitor C1 is formed between the capacitor electrode 17c and the conductor region X3.

[0068] The embodiments described above are for illustrative purposes only and are not intended to be limiting. Based on these illustratives and descriptions, those skilled in the art will understand that many variations are possible.

[0069] 〔Summarize〕

[0070] [Method 1]

[0071] The display device includes: a first data signal line connected to one of two sub-pixels emitting light of the same color; a second data signal line connected to the other; and a correction circuit electrically connected to the first data signal line and the second data signal line.

[0072] When the second data signal line is at a floating potential, the correction circuit makes the first data signal line and the second data signal line conduct to correct the floating potential.

[0073] [Method 2]

[0074] For example, the display device described in method 1 includes a display area containing the two sub-pixels and a non-display area surrounding the display area.

[0075] The non-display area includes a bendable area and a terminal area where electronic circuit chips are mounted.

[0076] The first data signal line and the second data signal line extend from the display area, through the bending area, and to the terminal area, respectively.

[0077] The correction circuit is contained in the correction circuit region located between the display area and the bending area.

[0078] [Method 3]

[0079] For example, in the display device of embodiment 1, the correction circuit includes a first path for causing charge to flow from the first data signal line to the second data signal line and a second path for causing charge to flow from the second data signal line to the first data signal line.

[0080] [Method 4]

[0081] For example, in the display device described in method 3, when the second data signal line is normal, the first path and the second path are not connected; when the second data signal line is disconnected, the first path or the second path is connected.

[0082] [Method 5]

[0083] For example, in the display device described in embodiment 3, the first path includes an N-type first diode, a P-channel transistor, and a P-type second diode.

[0084] The first data signal line and the source terminal of the P-channel transistor are connected via a first diode, and the second data signal line and the drain terminal of the P-channel transistor are connected via a second diode.

[0085] [Method 6]

[0086] For example, in the display device described in embodiment 5, the second path includes a P-type third diode, an N-channel transistor, and an N-type fourth diode, wherein the first data signal line and the source terminal of the N-channel transistor are connected via the third diode, and the second data signal line and the drain terminal of the N-channel transistor are connected via the fourth diode.

[0087] [Method 7]

[0088] For example, in the display device described in embodiment 6, the gate terminal and drain terminal of the P-channel transistor are connected via a first capacitor.

[0089] The gate and drain terminals of the N-channel transistor are connected via a second capacitor.

[0090] [Method 8]

[0091] For example, in the display device described in embodiment 6, the drain terminal of the P-channel transistor is supplied with a first potential during each horizontal scan, and the gate terminal and source terminal of the P-channel transistor are supplied with a second potential greater than the first potential during each horizontal scan.

[0092] [Method 9]

[0093] For example, in the display device described in embodiment 8, the drain terminal of the N-channel transistor is supplied with the second potential during each horizontal scan.

[0094] The gate and source terminals of the N-channel transistor are supplied with the first potential during each horizontal scan.

[0095] [Method 10]

[0096] For example, in the display device described in embodiment 9, the first potential is below the minimum value of the range of data signals supplied to the first data signal line and the second data signal line.

[0097] The second potential is greater than or equal to the maximum value of the range of data signals supplied to the first data signal line and the second data signal line.

[0098] [Method 11]

[0099] For example, in the display device described in embodiment 10, during each horizontal scan, the gate potential of the N-channel transistor is initialized to the first potential, and the gate potential of the P-channel transistor is initialized to the second potential. When the second data signal line is normal, the P-channel transistor and the N-channel transistor become cut off.

[0100] [Method 12]

[0101] For example, in the display device described in embodiment 10, during each horizontal scan, the cathode potentials of the first diode and the fourth diode are initialized to the second potential, and the anode potentials of the second diode and the third diode are initialized to the first potential. When the second data signal line is normal, the first diode, the second diode, the third diode, and the fourth diode are in a cut-off state.

[0102] [Method 13]

[0103] For example, in the display device described in embodiment 5, the first diode comprises an oxide semiconductor film, and the second diode comprises a crystalline silicon semiconductor film.

[0104] [Method 14]

[0105] For example, in the display device described in methods 1 to 13, the two sub-pixels are adjacent in an arrangement of a plurality of sub-pixels that emit light of the same color as them.

[0106] [Method 15]

[0107] For example, the display device described in method 2 connects to a third data signal line of a sub-pixel that is different from the two sub-pixels.

[0108] In the correction circuit region and the bending region, the metal layer on which the first data signal line and the second data signal line are formed is different from the metal layer on which the third data signal line is formed.

[0109] [Method 16]

[0110] For example, in the display device described in embodiment 13, the second diode and the P-channel transistor share the crystalline silicon semiconductor film.

[0111] Explanation of reference numerals in the attached figures

[0112] 2 substrate

[0113] 4. TFT layer (Thin Film Transistor layer)

[0114] 5. Light-emitting element layer

[0115] 6. Sealing layer

[0116] 10 Display devices

[0117] HC correction circuit

[0118] QA Bending Area

[0119] HA correction circuit area

[0120] TA terminal area

[0121] K1 First Path

[0122] K2 Second Path

[0123] d1 First diode

[0124] d2 second diode

[0125] d3 third diode

[0126] d4 fourth diode

[0127] Ta, Tb, Td, Te, Tf P-channel transistors

[0128] Tc N-channel transistor

[0129] C1 is the first capacitor.

[0130] C2 is the second capacitor.

[0131] LED light source

[0132] SC crystalline silicon semiconductor film

[0133] SZ oxide semiconductor film

Claims

1. A display device, characterized in that, include: The first data signal line is connected to one of the two sub-pixels that emit light of the same color. Connect to the second data signal line of another; And a correction circuit electrically connected to the first data signal line and the second data signal line. When the second data signal line has a floating potential, the correction circuit corrects the floating potential by making the first data signal line and the second data signal line conductive. The correction circuit includes a first path for charge to flow from the first data signal line to the second data signal line and a second path for charge to flow from the second data signal line to the first data signal line. The first path includes an N-type first diode, a P-channel transistor, and a P-type second diode. The first data signal line is connected to the source terminal of the P-channel transistor via the first diode, and the second data signal line is connected to the drain terminal of the P-channel transistor via the second diode. The second path includes a P-type third diode, an N-channel transistor, and an N-type fourth diode. The first data signal line is connected to the source terminal of the N-channel transistor via the third diode, and the second data signal line is connected to the drain terminal of the N-channel transistor via the fourth diode.

2. The display device according to claim 1, characterized in that, This includes a display area containing the two sub-pixels and a non-display area surrounding the display area. The non-display area includes a bendable area and a terminal area where electronic circuit chips are mounted. The first data signal line and the second data signal line extend from the display area through the bending area to the terminal area, respectively, and the correction circuit is included in the correction circuit area located between the display area and the bending area.

3. The display device according to claim 1, characterized in that, When the second data signal line is functioning normally, neither the first path nor the second path is conductive. If the second data signal line is disconnected, either the first path or the second path will be connected.

4. The display device according to claim 1, characterized in that, The gate and drain terminals of the P-channel transistor are connected via a first capacitor. The gate and drain terminals of the N-channel transistor are connected via a second capacitor.

5. The display device according to claim 1, characterized in that, The drain terminal of the P-channel transistor is supplied with a first potential during each horizontal scan. The gate and source terminals of the P-channel transistor are supplied with a second potential that is greater than the first potential during each horizontal scan.

6. The display device according to claim 5, characterized in that, The drain terminal of the N-channel transistor is supplied with the second potential during each horizontal scan. The gate and source terminals of the N-channel transistor are supplied with the first potential during each horizontal scan.

7. The display device according to claim 6, characterized in that, The first potential is below the minimum value of the range of data signals supplied to the first data signal line and the second data signal line. The second potential is greater than or equal to the maximum value of the range of data signals supplied to the first data signal line and the second data signal line.

8. The display device according to claim 7, characterized in that, During each horizontal scan, the gate potential of the N-channel transistor is initialized to the first potential, and the gate potential of the P-channel transistor is initialized to the second potential. When the second data signal line is normal, the P-channel transistor and the N-channel transistor become off.

9. The display device according to claim 7, characterized in that, During each horizontal scan, the cathode potentials of the first diode and the fourth diode are initialized to the second potential, and the anode potentials of the second diode and the third diode are initialized to the first potential. When the second data signal line is normal, the first diode, the second diode, the third diode, and the fourth diode are in the off state.

10. The display device according to claim 1, characterized in that, The first diode includes an oxide semiconductor film. The second diode comprises a crystalline silicon semiconductor film.

11. The display device according to any one of claims 1 to 10, characterized in that, The two sub-pixels are adjacent in an arrangement of multiple sub-pixels that emit light of the same color as them.

12. The display device according to claim 2, characterized in that, It includes a third data signal line connected to a sub-pixel different from the two sub-pixels. In the correction circuit region and the bending region, the metal layer on which the first data signal line and the second data signal line are formed is different from the metal layer on which the third data signal line is formed.

13. The display device according to claim 10, characterized in that, The second diode and the P-channel transistor share the crystalline silicon semiconductor film.

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