Method and apparatus for field programmable system (FPS) switching

Abstract

The present disclosure relates to methods and apparatuses for display processing, including an apparatus, e.g., a display processor. In some aspects, the apparatus can store one or more pixel conversion factors for at least one display panel. The apparatus can also determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel. Additionally, the apparatus can identify, upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, a pixel conversion factor of the one or more pixel conversion factors associated with the updated frame refresh rate. The apparatus can also refresh the at least one display panel based on the updated frame refresh rate associated with the pixel conversion factor.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically utilize a graphics processing unit (GPU) to accelerate the rendering of graphics data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles. The GPU executes a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. A central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize a GPU during execution. Devices that provide content for visual presentation on a display typically include a GPU.

[0003] Typically, a device's GPU is configured to execute processes in a graphics processing pipeline. However, with the advent of wireless communications and smaller handheld devices, there is an increasing demand for improved graphics processing. Summary of the Invention

[0004] The following is a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects and is intended to neither identify key elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In one aspect of the present disclosure, a method, computer-readable medium, and apparatus are provided. The apparatus may be a display processor, a display processing unit (DPU), an application processor (AP), a display controller, a display driver integrated circuit (DDIC), a display panel, and / or any other apparatus capable of performing display processing. The apparatus may store one or more pixel conversion factors for at least one display panel. The apparatus may also determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel. The apparatus may also switch the at least one display panel to the updated frame refresh rate after determining to switch from the previous frame refresh rate to the updated frame refresh rate. Additionally, the apparatus may identify a pixel conversion factor associated with the updated frame refresh rate from one or more pixel conversion factors after determining to switch from the previous frame refresh rate to the updated frame refresh rate. The apparatus may also refresh the at least one display panel based on the updated frame refresh rate associated with the pixel conversion factor. The apparatus may also transmit the pixel conversion factor associated with the updated frame refresh rate from the one or more pixel conversion factors. Additionally, the apparatus may enable at least one adaptive variable rate (AVR) component after transmitting the pixel conversion factor. The apparatus may also stop refreshing the at least one display panel internally after enabling the at least one AVR component. The device may also apply the pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor. In addition, the device may transmit pixel data of a next frame based on the updated frame refresh rate. The device may also disable at least one adaptive variable rate (AVR) component after transmitting the pixel data of the next frame.

[0006] The details of one or more examples of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0008] Figure 2 An example GPU is shown in accordance with one or more techniques of this disclosure.

[0009] Figure 3 An example flow diagram of a display process in accordance with one or more techniques of this disclosure is shown.

[0010] Figure 4 An example timing diagram of a display process in accordance with one or more techniques of this disclosure is shown.

[0011] Figure 5 An example diagram of display processing components is shown, in accordance with one or more techniques of this disclosure.

[0012] Figure 6 An example flow chart illustrating an example method in accordance with one or more techniques of this disclosure is shown. DETAILED DESCRIPTION

[0013] In some types of smartphones, certain types of display panels can support a variety of different frame refresh rates or FPS to achieve panel flexibility. For example, in certain types of display panels (e.g., 144Hz OLED panels), the panel can support certain types of frame refresh rates or FPS, such as 144Hz, 120Hz, 90Hz, 60Hz, 50Hz and / or 30Hz FPS, to achieve high panel flexibility. However, considering the high cost of certain display panels (e.g., OLED panels) and the memory size limitations (e.g., DDIC or flash memory size limitations) within the display processor, this may be difficult to achieve. In addition to the cost limitations of certain types of display panels (e.g., OLED panels), the display processor size (e.g., DDIC or flash memory size) may be another factor that can limit the memory capacity (e.g., DDIC flash memory capacity) of the smartphone. In addition, some display panels (e.g., OLED display panels) can utilize large displays to achieve a high display visible range, such as a 100% display visible range. Accordingly, since some types of display panels may utilize large displays to achieve a high display visible range, there may be a small storage space for the display controller, such as a DDIC or flash memory chip. In some aspects, in order to support the increased frame refresh rate or FPS, the DDIC or flash chip size can be increased. However, based on the limited size of the DDIC or flash chip, doing so may be challenging for display panel or smartphone manufacturers. Aspects of the present disclosure can support increased frame refresh rate or FPS configurations for display panels (e.g., OLED panels). For example, aspects of the present disclosure can support increased frame refresh rates or FPS without increasing panel cost or increasing DDIC size or flash memory size. Aspects of the present disclosure can also provide OLED panels with different FPS specifications having large DDIC flash memory capacity. The DDIC flash memory capacity of the present disclosure can store different pixel conversion factors or gamma tables for the display brightness value (DBV) range for each individual frame refresh rate or FPS.

[0014] The following describes various aspects of the system, device, computer program product and method in more detail with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects described herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that uses other structures, functions, or structures and functions in addition to or different from the various aspects disclosed herein to practice. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0015] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential advantages and strengths of various aspects of this disclosure have been mentioned, the scope of this disclosure is not intended to be limited to specific advantages, uses, or objectives. On the contrary, various aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0016] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the detailed description below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively, "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0017] For example, an element or any part of an element or any combination of elements can be implemented as a "processing system" including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gating logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Software can be broadly interpreted as instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc., whether referring to software, firmware, middleware, microcode, hardware description languages, or other. The term "application" can refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such an example, the application may be stored on a memory, such as an on-chip memory of a processor, a system memory, or any other memory. The hardware described herein (e.g., a processor) may be configured to execute an application. For example, an application may be described as including code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such an example, a component may be hardware, software, or a combination thereof. A component may be a separate component or a subcomponent of a single component.

[0018] Therefore, in one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented in software, these functions can be stored on a computer-readable medium or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media. Storage media can be any available medium that can be accessed by a computer. As an example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage devices, magnetic disk storage devices, other magnetic storage devices, a combination of the above-mentioned types of computer-readable media, or any other medium that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0019] In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on a processing unit (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a GPU). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example advantages are described throughout this disclosure.

[0020] As used herein, instances of the term "content" may refer to "graphics content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphics content" may refer to content generated by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" may refer to content generated by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" may refer to content generated by a graphics processing unit.

[0021] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content, such as a frame, to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content, such as one or more frames, from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform composition on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to compose, blend, or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on a frame, for example, scaling up or down. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form a frame, i.e., a frame includes two or more layers, and the frame including two or more layers may then be blended.

[0022] Figure 1is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of this disclosure. Content generation system 100 includes a device 104. Device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a system-on-chip (SoC). Device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some aspects, device 104 may include multiple optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to displays 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, while the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation. In other examples, the first display and the second display may receive the same frame for rendering thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for rendering thereon. Instead, the frames or graphics processing results may be transmitted to the other device. In some aspects, this may be referred to as split rendering.

[0023] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, for example, in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (e.g., display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before presentation by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0024] Memory external to the processing unit 120 and the content encoder / decoder 122 (e.g., system memory 124) can be accessed by the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 can be configured to read from and / or write to the external memory (e.g., system memory 124). The processing unit 120 and the content encoder / decoder 122 can be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 can be communicatively coupled to each other via a bus or a different connection.

[0025] The content encoder / decoder 122 can be configured to receive graphics content from any source (e.g., system memory 124 and / or communication interface 126). The system memory 124 can be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 can be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or communication interface 126. The content encoder / decoder 122 can be configured to encode or decode any graphics content.

[0026] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0027] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be interpreted as meaning that internal memory 121 or system memory 124 is non-removable or that its contents are static. As one example, system memory 124 may be removable from device 104 and moved to another device. As another example, system memory 124 may not be removable from device 104.

[0028] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are partially implemented in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute these instructions in hardware to perform the techniques of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0029] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the mainboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are partially implemented in software, the content encoder / decoder 122 can store instructions for the software in an appropriate, non-transitory computer-readable storage medium (e.g., internal memory 123), and can use one or more processors to execute these instructions in hardware to perform the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered to be one or more processors.

[0030] In some aspects, the content generation system 100 may include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or position information. The transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which information may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In these examples, the transceiver 132 may be configured to perform any of the receiving functions and / or transmitting functions described herein with respect to the device 104.

[0031] Reference again Figure 1 In certain aspects, the graphics processing pipeline 107 may include a determination component 198 configured to store one or more pixel conversion factors for at least one display panel. The determination component 198 may also be configured to determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel. The determination component 198 may also be configured to switch the at least one display panel to the updated frame refresh rate after determining to switch from the previous frame refresh rate to the updated frame refresh rate. The determination component 198 may also be configured to identify a pixel conversion factor associated with the updated frame refresh rate from the one or more pixel conversion factors after determining to switch from the previous frame refresh rate to the updated frame refresh rate. The determination component 198 may also be configured to refresh the at least one display panel based on the updated frame refresh rate associated with the pixel conversion factor. The determination component 198 may also be configured to transmit the pixel conversion factor associated with the updated frame refresh rate from the one or more pixel conversion factors. The determination component 198 may also be configured to enable at least one adaptive variable rate (AVR) component after transmitting the pixel conversion factor. The determining component 198 may also be configured to stop refreshing the internal refresh of at least one display panel after turning on at least one AVR component. The determining component 198 may also be configured to apply the pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor. The determining component 198 may also be configured to transmit pixel data for the next frame based on the updated frame refresh rate. The determining component 198 may also be configured to turn off at least one adaptive variable rate (AVR) component after transmitting the pixel data for the next frame.

[0032] As described herein, a device (e.g., device 104) may refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, a device may be a server, a base station, a user device, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), a terminal product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smartwatch), an augmented reality device or a virtual reality device, a non-wearable device, a display or a display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but, in another embodiment, other components (e.g., a CPU) may be used to perform according to the disclosed embodiments.

[0033] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a collection of global state information, such as information about global registers, shader programs, or constant data, which can regulate how the graphics context is processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, a bit can be used to indicate which workload belongs to the context register. In addition, multiple functions or programs can be run simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0034] Context states can be used to determine how a single processing unit operates, such as a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and / or in which mode a processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline based on context register definitions of modes or states, such as vertex or pixel workloads. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states can change, the GPU may change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changed mode or state.

[0035] Figure 2 An example GPU 200 is shown in accordance with one or more techniques of this disclosure. Figure 2 As shown, the GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache memory (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a renderer back end (RB) 236, an L2 cache memory (UCHE) 238, and a system memory 240. Although Figure 2 The GPU 200 is shown to include processing units 220-238, but the GPU 200 may include multiple additional processing units. In addition, the processing units 220-238 are only examples, and a GPU according to the present disclosure may use any combination or order of processing units. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0036] like Figure 2 As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to parse a command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then send context register packet 260 or draw call data packet 212 to processing units or blocks in the GPU via separate paths. Furthermore, command buffer 250 can alternate between different states of context registers and draw calls. For example, a command buffer can be structured as follows: context registers for context N, draw calls for context N, context registers for context N+1, and draw calls for context N+1.

[0037] The GPU can render images in a variety of different ways. In some cases, the GPU can use rendering or tile rendering to render images. In a tile rendering GPU, the image can be divided or separated into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during a binning pass, the image can be divided into different blocks (bins) or tiles. In some aspects, during a binning pass, a visible stream can be constructed in which visible primitives or draw calls can be identified.

[0038] In some aspects, the GPU can apply the drawing or rendering process to different blocks or tiles. For example, the GPU can render to a block and perform all drawing for the primitives or pixels in the block. During the rendering process to a block, the render target can be located in GMEM. In some cases, after rendering to a block, the contents of the render target can be moved to system memory, and GMEM can be freed to render the next block. In addition, the GPU can render into another block and perform drawing for the primitives or pixels in that block. Therefore, in some aspects, there may be a smaller number of blocks, for example, four blocks, which cover all drawing within a surface. In addition, the GPU can loop through all drawing within a block, but only perform drawing for visible draw calls (i.e., draw calls that include visible geometry). In some aspects, for example, a visibility stream can be generated in a tiled pass to determine visibility information for each primitive in an image or scene. For example, the visibility stream can identify whether a primitive is visible. In some aspects, this information can be used to remove primitives that are not visible, for example, in a rendering pass. Furthermore, at least some of the primitives identified as visible can be rendered in the rendering pass.

[0039] In some aspects of tiled rendering, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, such as a visibility or block-visibility pass and a rendering or block-rendering pass. During the visibility pass, the GPU can input the rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which block or region. In some aspects of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pass, the GPU can input the visibility stream and process one block or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or vertices of primitives are visible or invisible. Therefore, visible primitives or vertices of primitives can be processed. By doing so, the GPU can reduce unnecessary workload of processing or rendering invisible primitives or triangles.

[0040] In some aspects, during the visibility pass, certain types of primitive geometry may be processed, for example, positional geometry only. Additionally, primitives may be sorted into different blocks or regions depending on their position or location. In some cases, sorting primitives or triangles into different blocks may be performed by determining visibility information for these primitives or triangles. For example, the GPU may determine or write visibility information for each primitive in each block or region, for example, in system memory. This visibility information may be used to determine or generate a visibility stream. In a rendering pass, primitives in each block may be rendered separately. In these cases, the visibility stream may be retrieved from memory for discarding primitives that are not visible to the block.

[0041] Some aspects of the GPU or GPU architecture can provide many different rendering options, such as software rendering and hardware rendering. In software rendering, the driver or CPU can copy the entire frame geometry by processing each view at a time. In addition, depending on the view, some different states can be changed. Therefore, in software rendering, the software can copy the entire workload by changing some states that can be used to render each viewpoint in the image. In some aspects, there may be an increased amount of overhead because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for copying or processing the geometry for each viewpoint in the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0042] As indicated herein, in some aspects, such as in a block or tile rendering architecture, a frame buffer may repeatedly store or write data thereto, such as when rendering from different types of memory. This may be referred to as parsing and unparsing a frame buffer or system memory. For example, when storing or writing to one frame buffer and then switching to another frame buffer, data or information on the frame buffer may be parsed from GPU internal memory (GMEM) at the GPU to system memory, i.e., memory in double data rate (DDR) RAM or dynamic RAM (DRAM).

[0043] In some aspects, system memory can also be system-on-chip (SOC) memory or another chip-based memory to store data or information, for example, on a device or smartphone. System memory can also be a physical data storage device shared by the CPU and / or GPU. In some aspects, system memory can be, for example, a DRAM chip on a device or smartphone. Thus, SoC memory can store data in a chip-based manner.

[0044] In some aspects, GMEM can be on-chip memory at the GPU, which can be implemented by static RAM (SRAM). In addition, GMEM can be stored on a device, such as a smartphone. As shown herein, data or information can be transferred between system memory or DRAM and GMEM (e.g., at the device). In some aspects, system memory or DRAM can be at the CPU or GPU. In addition, data can be stored in DDR or DRAM. In some aspects, for example, in block or tile rendering, a small portion of the memory can be stored at the GPU, for example, at GMEM. In some cases, storing data at GMEM can utilize a larger processing workload and / or consume less power than storing data at the frame buffer or system memory.

[0045] In some types of smartphones, for example, advanced smartphones or smartphones with organic light emitting diode (OLED) display panels, a display with a high frame refresh rate or high frames per second (FPS) may correspond to a standard configuration, for example, displaying at an FPS of 120 Hz or higher. In order to save power and align with the different preferences of each application of the smartphone, the display panel (e.g., an OLED display panel) may support multiple types of frame refresh rates or FPS. For example, the more types of frame refresh rates or FPS supported by the display panel (e.g., an OLED display panel), the more capacity or memory may be used at the display processor (e.g., a display controller or a display driver integrated circuit (DDIC)). For each separate frame refresh rate or FPS, the display panel may store different gamma tables for different panel display brightness value (DBV) ranges.

[0046] In some aspects, certain types of display panels may support multiple different frame refresh rates or FPS to enable panel flexibility. For example, in certain types of display panels (e.g., 144Hz OLED panels), the panel may support certain types of frame refresh rates or FPS, such as 144Hz, 120Hz, 90Hz, 60Hz, 50Hz, and / or 30Hz FPS, to enable a high degree of panel flexibility. However, this may be difficult to achieve given the high cost of certain display panels (e.g., OLED panels) and memory size limitations within the display processor (e.g., DDIC or flash memory size limitations).

[0047] As indicated herein, in addition to cost limitations of certain types of display panels (e.g., OLED panels), display processor size (e.g., DDIC or flash memory size) may be another factor that can limit the memory capacity (e.g., DDIC flash memory capacity) of a smartphone. Furthermore, some display panels (e.g., OLED display panels) can utilize large displays to achieve a high display visibility range, such as a 100% display visibility range. Therefore, because some types of display panels can utilize large displays to achieve a high display visibility range, there may be little storage space for the display controller, such as a DDIC or flash memory chip.

[0048] In some aspects, to support increased frame refresh rates or FPS, the DDIC or flash chip size can be increased. However, doing so can be challenging for display panel or smartphone manufacturers based on the limited size of the DDIC or flash chip. Based on the above, it may be beneficial to support increased frame refresh rate or FPS configurations for display panels (e.g., OLED panels) without increasing panel cost and / or without increasing DDIC or flash memory size. For example, it may be beneficial to provide an OLED panel that includes different FPS specifications with large DDIC flash memory capacity to store different pixel conversion factors or gamma tables for the DBV range for each FPS.

[0049] Aspects of the present disclosure can support increased frame refresh rate or FPS configurations for display panels (e.g., OLED panels). For example, aspects of the present disclosure can support increased frame refresh rates or FPS without increasing panel cost or increasing DDIC size or flash memory size. Aspects of the present disclosure can also provide OLED panels with different FPS specifications including large DDIC flash memory capacity. The DDIC flash memory capacity of the present disclosure can store different pixel conversion factors or gamma tables for each separate DBV range of frame refresh rate or FPS.

[0050] Figure 3 300 is a flow chart illustrating a display process according to one or more techniques of this disclosure. Figure 3 As shown, flowchart 300 includes multiple steps or processes for display processing. At 302, aspects of the present disclosure can store a gamma table including multiple pixel conversion factors to an AP. At 304, aspects of the present disclosure can switch one or more OLED panels to an updated frame refresh rate or FPS.

[0051] At 306, aspects of the present disclosure may determine a corresponding gamma table for the updated frame refresh rate or FPS at the AP. At 308, aspects of the present disclosure may dynamically turn on an AVR component and / or send multiple commands to a display panel or DDIC. At 310, aspects of the present disclosure may stop self-refresh at the display panel and / or wait for the next frame pixel grouping via a display serial interface (DSI). At 312, aspects of the present disclosure may send a gamma table including multiple pixel conversion factors for the updated frame refresh rate or FPS to the DDIC at the host device via a DSI link.

[0052] At 314, aspects of the present disclosure may send the updated frame refresh rate or other FPS configuration to the DDIC via the DSI link at the host device. At 316, aspects of the present disclosure may sleep for a specific period of time, e.g., 1 ms, per DSI link at the AP. At 318, aspects of the present disclosure may apply a gamma table including multiple pixel conversion factors at the DDIC. At 320, aspects of the present disclosure may transmit frame data for the next frame at the host device. At 322, aspects of the present disclosure may dynamically shut down the AVR component.

[0053] In some aspects of the present disclosure, such as Figure 3 As shown, at least one gamma table or multiple pixel conversion factors can be stored at an application processor (AP). In addition, at least one display panel (e.g., at least one OLED panel) can be switched or adjusted to a new frame refresh rate or FPS. In addition, a corresponding gamma table or pixel conversion factor can be determined for the updated frame refresh rate or updated FPS.

[0054] In some cases, at least one display panel can be refreshed based on an updated frame refresh rate or FPS associated with a pixel conversion factor. In addition, the panel can stop self-refresh and wait for the next frame pixel grouping via a display serial interface (DSI) link. Thus, a command mode OLED panel can stop its own internal refresh in order to wait for a new frame transmission. An adaptive variable rate (AVR) component can also be dynamically turned on to provide a longer vertical blanking interval (VBI) or Vblank time, such as to transmit a new FPS gamma table and other parameters via a DSI link.

[0055] In some aspects, the host device may send one or more pixel conversion factors or gamma tables and / or parameters for the new FPS to the DDIC via the DSI link. The host device may then send the updated frame refresh rate or other configuration of the FPS to the DDIC via the DSI link. The AP may then sleep for a period of time, e.g., 1 ms or another predefined delay time. Additionally, the DDIC may apply the gamma tables or pixel conversion factors. The AP may then begin transmitting new frame pixel data via the DSI link. Finally, the AP may dynamically shut down the AVR component.

[0056] Figure 4 4 shows a timing diagram 400 of a display process according to one or more techniques of this disclosure. More specifically, Figure 4 The timing diagram of FPS switching is shown in FIG. Figure 4 As shown, graph 400 includes a plurality of frames, for example, frame 410 and frame 411 . Figure 4It also includes a plurality of steps or processes, such as opening the AVR component 420, gamma table transfer 430, gamma table transfer 431, gamma table transfer n, control start 440, new FPS 450 and closing the AVR component 460. In addition, Figure 4 A Vblank time period is shown, for example, 6 ms.

[0057] Various aspects of the present disclosure can include many benefits or advantages. For example, various aspects of the present disclosure can help reduce the cost of display panels (e.g., OLED panels or DDICs) and provide different native support for frame refresh rates or FPS. Various aspects of the present disclosure can also help reduce the size of DDICs or flash memory sizes, e.g., OLED panel DDICs or flash memory sizes. In addition, various aspects of the present disclosure can help provide improved OLED visual quality, for example, by supporting longer or larger gamma tables with increased pixel conversion factors at DDICs (e.g., OLED panel DDICs).

[0058] Figure 5 Diagram 500 illustrates display processing components according to one or more techniques of this disclosure. Figure 5 As shown, diagram 500 includes an application processor (AP) 510 , a display processor or DPU 520 including a DDIC 522 , and a display panel 530 . Figure 5 Depicts display processing components that can be used at a smartphone or host device. Aspects of the present disclosure can utilize Figure 5 components in order to reduce the size of DDIC or flash memory chips and / or improve OLED visual quality.

[0059] Figure 3-5 An example of the above method and process for display processing is shown. Figure 3-5 As shown, various aspects of the present disclosure (e.g., the AP, display processor, DPU, display controller, DDIC, or display panel herein) can perform multiple different steps or processes for display processing in order to reduce the size of the DDIC or flash memory and / or improve the visual quality of the display panel or OLED.

[0060] like Figure 3-5 As shown, an AP or display processor (e.g., AP 510) herein can store one or more pixel conversion factors for at least one display panel. In some aspects, the one or more pixel conversion factors can correspond to at least one gamma table. Furthermore, the one or more pixel conversion factors can be associated with conversion from digital pixel values ​​to analog pixel luminance values ​​and / or conversion from digital sub-pixel values ​​to analog sub-pixel luminance values.

[0061] The AP or display processor herein (eg, AP 510 ) may also determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at at least one display panel (eg, display panel 530 ).

[0062] The AP or display processor herein (e.g., AP 510 or display processor 520) may also switch at least one display panel (e.g., display panel 530) to the updated frame refresh rate after determining to switch from the previous frame refresh rate to the updated frame refresh rate. Furthermore, the at least one display panel (e.g., display panel 530) may be switched to the updated frame refresh rate by the AP (e.g., AP 510).

[0063] In addition, the AP or display processor herein (e.g., AP 510 or display processor 520) may, upon determining to switch from a previous frame refresh rate to an updated frame refresh rate, identify a pixel conversion factor associated with the updated frame refresh rate from among the one or more pixel conversion factors. The one or more pixel conversion factors may be associated with at least one of a brightness level or a frame refresh rate of at least one display panel (e.g., display panel 530).

[0064] The AP or display processor herein (e.g., AP 510 or display processor 520) may also refresh at least one display panel (e.g., display panel 530) based on the updated frame refresh rate associated with the pixel conversion factor. In some cases, the updated frame refresh rate may correspond to at least one of a frame refresh time or a frames per second (FPS) value of the at least one display panel (e.g., display panel 530).

[0065] The AP or display processor (e.g., AP 510 or display processor 520) herein may also send a pixel conversion factor associated with the updated frame refresh rate among the one or more pixel conversion factors. In some cases, the AP (e.g., AP 510) may sleep for a period of time after the pixel conversion factor is sent. In addition, the pixel conversion factor may be sent to the display processor (e.g., display processor 520) or display driver integrated circuit (DDIC) (e.g., DDIC 522) via a display serial interface (DSI) link.

[0066] In addition, the AP or display processor herein (e.g., AP 510 or display processor 520) can turn on at least one adaptive variable rate (AVR) component after sending the pixel conversion factor. In some aspects, the at least one AVR component can be turned on based on a command from the AP (e.g., AP 510) to a display driver integrated circuit (DDIC) (e.g., DDIC 522).

[0067] The AP or display processor herein (eg, AP 510 or display processor 520 ) may also stop internal refresh of at least one display panel (eg, display panel 530 ) after turning on at least one AVR component.

[0068] The AP or display processor herein (eg, AP 510 or display processor 520) may also apply the pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor.

[0069] Furthermore, the AP or display processor herein (eg, AP 510 or display processor 520 ) may transmit pixel data of a next frame (eg, frame 411 ) based on the updated frame refresh rate.

[0070] The AP or display processor herein (e.g., AP 510 or display processor 520) may also turn off at least one adaptive variable rate (AVR) component after transmitting pixel data for the next frame (e.g., frame 411). In some aspects, turning off at least one AVR component may be based on a command from the AP (e.g., AP 510) to a display driver integrated circuit (DDIC) (e.g., DDIC 522).

[0071] Figure 6 Flowchart 600 shows an example method according to one or more techniques of this disclosure. The method may be performed by a device such as an AP, a display processor, a DPU, a display controller, a DDIC, a display panel, or a device for display processing.

[0072] At 602, the apparatus may store one or more pixel conversion factors for at least one display panel, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In some aspects, one or more pixel conversion factors may correspond to at least one gamma table, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 Furthermore, one or more pixel conversion factors may be associated with the conversion from digital pixel values ​​to analog pixel brightness values ​​and / or the conversion from digital sub-pixel values ​​to analog sub-pixel brightness values, as described in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0073] At 604, the apparatus may determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at at least one display panel, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0074] At 606, the apparatus may switch at least one display panel to the updated frame refresh rate after determining to switch from the previous frame refresh rate to the updated frame refresh rate, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In addition, at least one display panel may be switched to an updated frame refresh rate by the AP, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0075] At 608, the device may, upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, identify a pixel conversion factor of the one or more pixel conversion factors that is associated with the updated frame refresh rate, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 One or more pixel conversion factors may be associated with at least one of a brightness level or a frame refresh rate of at least one display panel, such as in combination with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0076] At 610, the apparatus may refresh at least one display panel based on an updated frame refresh rate associated with the pixel conversion factor, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In some cases, the updated frame refresh rate may correspond to at least one of a frame refresh time or a frames per second (FPS) value of at least one display panel, as described in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0077] At 612, the device may send a pixel conversion factor associated with an updated frame refresh rate from among the one or more pixel conversion factors, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In some cases, the AP may sleep for a period of time after the pixel conversion factor is sent, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 Additionally, the pixel conversion factors may be sent to a display processor or display driver integrated circuit (DDIC) via a display serial interface (DSI) link, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0078] At 614, the device may turn on at least one adaptive variable rate (AVR) component after sending the pixel conversion factor, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In some aspects, at least one AVR component may be turned on based on a command from an application processor (AP) to a display driver integrated circuit (DDIC), such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0079] At 616, the device may stop refreshing the internal refresh of at least one display panel after turning on at least one AVR component, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0080] At 618, the device may apply the pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0081] At 620, the device may transmit pixel data for the next frame based on the updated frame refresh rate, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0082] At 622, the device may shut down at least one adaptive variable rate (AVR) component after transmitting the pixel data of the next frame, such as in conjunction with Figure 3 、 Figure 4 and Figure 5 In some aspects, at least one AVR component can be shut down based on a command from an application processor (AP) to a display driver integrated circuit (DDIC), such as in conjunction with Figure 3 、 Figure 4 and Figure 5 As described in the examples.

[0083] In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be an AP, a display processor, a DPU, a display controller, a DDIC, a display panel, or an apparatus for display processing. In one aspect, the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus may include means for storing one or more pixel conversion factors for at least one display panel. The apparatus may also include means for determining whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel. The apparatus may also include means for, upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, identifying a pixel conversion factor associated with the updated frame refresh rate from the one or more pixel conversion factors. The apparatus may also include means for refreshing the at least one display panel based on the updated frame refresh rate associated with the pixel conversion factor. The apparatus may also include means for sending the pixel conversion factor associated with the updated frame refresh rate from the one or more pixel conversion factors. The apparatus may also include means for turning on at least one adaptive variable rate (AVR) component after sending the pixel conversion factor. The apparatus may further include means for stopping internal refresh of at least one display panel after turning on at least one AVR component. The apparatus may further include means for applying a pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor. The apparatus may further include means for transmitting pixel data for a next frame based on the updated frame refresh rate. The apparatus may further include means for turning off at least one adaptive variable rate (AVR) component after transmitting the pixel data for the next frame. The apparatus may further include means for switching at least one display panel to the updated frame refresh rate after determining to switch from the previous frame refresh rate to the updated frame refresh rate.

[0084] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing technology described can be used by an AP, a display processor, a DPU, a display controller, a DDIC, a display panel, a device for display processing, or some other processor that can perform display processing to implement the FPS switching technology described herein. Compared to other display processing technologies, this can also be implemented at a low cost. In addition, the display processing technology herein can improve or speed up display processing or execution. In addition, the display processing technology herein can improve resource or data utilization and / or resource efficiency. In addition, various aspects of the present disclosure can utilize FPS switching technology to save power, improve processing time, reduce latency and / or reduce performance overhead.

[0085] According to the present disclosure, the term "or" can be interpreted as "and / or" unless the context dictates otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used with respect to some features disclosed herein and not others, features that do not use such language can be interpreted as having such a meaning implied unless the context indicates otherwise.

[0086] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, the functionality, processing unit, technique, or other module described herein may be stored on or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media may include computer data storage media or communication media, including any media that facilitates the transfer of a computer program from one place to another. In this manner, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is non-transitory, or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures to implement the techniques described in this disclosure. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of protection of computer-readable media. A computer program product may include a computer-readable medium.

[0087] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor," as used herein, may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Furthermore, the techniques may be fully implemented in one or more circuits or logic elements.

[0088] The techniques of this disclosure can be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or collections of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units including one or more processors as described above, in combination with appropriate software and / or firmware.

[0089] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A display processing method executed by an application processor, comprising: storing a plurality of pixel conversion factors for at least one display panel; determining whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel; upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, identifying a pixel conversion factor of the plurality of pixel conversion factors associated with the updated frame refresh rate; Open at least one Adaptive Variable Rate AVR component; stopping the at least one display panel from performing internal refresh after turning on the at least one AVR component; as well as The pixel conversion factor associated with the updated frame refresh rate is sent to the at least one display panel during a vertical blanking interval of the at least one AVR component.

2. The method according to claim 1, wherein Each of the plurality of pixel conversion factors corresponds to a gamma table.

3. The method according to claim 1, wherein Each of the plurality of pixel conversion factors is associated with a conversion from a digital pixel value to an analog pixel luminance value or a conversion from a digital sub-pixel value to an analog sub-pixel luminance value.

4. The method of claim 1 , wherein the AVR component provides the vertical blanking interval of 6 ms for transmitting the pixel conversion factor associated with the updated frame refresh rate.

5. The method according to claim 1, wherein Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is turned on.

6. The method according to claim 1, further comprising: The pixel conversion factor associated with the updated frame refresh rate is applied after sending the pixel conversion factor.

7. The method according to claim 1, further comprising: Sleeping for a period of time after sending the pixel conversion factor associated with the updated frame refresh rate.

8. The method according to claim 1, wherein The pixel conversion factor associated with the updated frame refresh rate is sent to a display processor or display driver integrated circuit (DDIC) via a display serial interface (DSI) link.

9. The method according to claim 1, further comprising: Pixel data for a next frame is transmitted based on the updated frame refresh rate.

10. The method according to claim 9, further comprising: The at least one AVR component is turned off after transmitting the pixel data of the next frame.

11. The method according to claim 10, wherein: Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is shut down.

12. The method according to claim 1, further comprising: After determining to switch from the previous frame refresh rate to the updated frame refresh rate, the at least one display panel is switched to the updated frame refresh rate.

13. The method according to claim 1, wherein The updated frame refresh rate corresponds to at least one of a frame refresh time or a frames per second (FPS) value of the at least one display panel.

14. The method according to claim 1, wherein Each of the plurality of pixel conversion factors is associated with at least one of a brightness level or a frame refresh rate of the at least one display panel.

15. An apparatus for display processing, comprising: Memory; as well as an application processor coupled to the memory and configured to: storing a plurality of pixel conversion factors for at least one display panel; determining whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel; upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, identifying a pixel conversion factor of the plurality of pixel conversion factors associated with the updated frame refresh rate; Open at least one Adaptive Variable Rate AVR component; stopping the at least one display panel from performing internal refresh after turning on the at least one AVR component; as well as The pixel conversion factor associated with the updated frame refresh rate is sent to the at least one display panel during a vertical blanking interval of the at least one AVR component.

16. The device according to claim 15, wherein Each of the plurality of pixel conversion factors corresponds to a gamma table.

17. The device according to claim 15, wherein Each of the plurality of pixel conversion factors is associated with a conversion from a digital pixel value to an analog pixel luminance value or a conversion from a digital sub-pixel value to an analog sub-pixel luminance value.

18. The apparatus of claim 15, wherein the AVR component provides the vertical blanking interval of 6 ms for transmitting the pixel conversion factor associated with the updated frame refresh rate.

19. The device according to claim 15, wherein Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is turned on.

20. The apparatus according to claim 15, wherein The application processor is further configured to: The pixel conversion factor associated with the updated frame refresh rate is applied after sending the pixel conversion factor.

21. The apparatus according to claim 15, wherein The application processor is further configured to sleep for a period of time after sending the pixel conversion factor associated with the updated frame refresh rate.

22. The apparatus according to claim 15, wherein The application processor is configured to send the pixel conversion factor associated with the updated frame refresh rate to a display processor or a display driver integrated circuit (DDIC) via a display serial interface (DSI) link.

23. The apparatus according to claim 15, wherein The application processor is further configured to: Pixel data for a next frame is transmitted based on the updated frame refresh rate.

24. The device according to claim 23, wherein The application processor is further configured to: The at least one AVR component is turned off after transmitting the pixel data of the next frame.

25. The apparatus according to claim 24, wherein Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is shut down.

26. The apparatus according to claim 15, wherein The application processor is further configured to: After determining to switch from the previous frame refresh rate to the updated frame refresh rate, the at least one display panel is switched to the updated frame refresh rate.

27. The apparatus according to claim 15, wherein The updated frame refresh rate corresponds to at least one of a frame refresh time or a frames per second (FPS) value of the at least one display panel.

28. The apparatus according to claim 15, wherein Each of the plurality of pixel conversion factors is associated with at least one of a brightness level or a frame refresh rate of the at least one display panel.

29. An apparatus for display processing performed by an application processor, comprising: a unit for storing a plurality of pixel conversion factors for at least one display panel; means for determining whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel; means for identifying a pixel conversion factor of the plurality of pixel conversion factors associated with the updated frame refresh rate upon determining to switch from the previous frame refresh rate to the updated frame refresh rate; means for turning on at least one adaptive variable rate (AVR) component; means for stopping said at least one display panel from performing an internal refresh after turning on said at least one AVR component; as well as means for sending the pixel conversion factor associated with the updated frame refresh rate to the at least one display panel during a vertical blanking interval of the at least one AVR component.

30. The apparatus according to claim 29, wherein Each of the plurality of pixel conversion factors corresponds to a gamma table.

31. The apparatus according to claim 29, wherein Each of the plurality of pixel conversion factors is associated with a conversion from a digital pixel value to an analog pixel luminance value or a conversion from a digital sub-pixel value to an analog sub-pixel luminance value.

32. The apparatus of claim 29, wherein the AVR component provides the vertical blanking interval of 6 ms for transmitting the pixel conversion factor associated with the updated frame refresh rate.

33. The apparatus of claim 29, wherein: Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is turned on.

34. The apparatus of claim 29, further comprising: means for applying the pixel conversion factor associated with the updated frame refresh rate after sending the pixel conversion factor.

35. The apparatus of claim 29, further comprising: Means for sleeping for a period of time after sending the pixel conversion factor associated with the updated frame refresh rate.

36. The apparatus of claim 29, wherein: The pixel conversion factor associated with the updated frame refresh rate is sent to a display processor or display driver integrated circuit (DDIC) via a display serial interface (DSI) link.

37. The apparatus of claim 29, further comprising: Means for transmitting pixel data for a next frame based on the updated frame refresh rate.

38. The apparatus of claim 37, further comprising: for shutting down the at least one AVR after transmitting the pixel data of the next frame Unit of component.

39. The apparatus according to claim 38, wherein Based on a command from the application processor to a display driver integrated circuit (DDIC), the at least one AVR component is shut down.

40. The apparatus of claim 29, further comprising: means for switching the at least one display panel to the updated frame refresh rate upon determining to switch from the previous frame refresh rate to the updated frame refresh rate.

41. The apparatus of claim 29, wherein The updated frame refresh rate corresponds to at least one of a frame refresh time or a frames per second (FPS) value of the at least one display panel.

42. The apparatus of claim 29, wherein Each of the plurality of pixel conversion factors is associated with at least one of a brightness level or a frame refresh rate of the at least one display panel.

43. A computer-readable medium storing computer-executable code for display processing performed by an application processor, the code, when executed by the application processor, causing the application processor to: storing a plurality of pixel conversion factors for at least one display panel; determining whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel; upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, identifying a pixel conversion factor of the plurality of pixel conversion factors associated with the updated frame refresh rate; Open at least one Adaptive Variable Rate AVR component; stopping the at least one display panel from performing internal refresh after turning on the at least one AVR component; and sending the pixel conversion factor associated with the updated frame refresh rate to the at least one display panel during a vertical blanking interval of the at least one AVR component.

44. The computer-readable medium of claim 43, wherein: Each of the plurality of pixel conversion factors corresponds to a gamma table.

45. The computer-readable medium of claim 43, wherein the AVR component provides the vertical blanking interval of 6 ms for transmitting the pixel conversion factor associated with the updated frame refresh rate.

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