Device comprising a tunable resistive element

Abstract

An apparatus comprising at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer disposed between the first terminal and the second terminal. The apparatus is configured to apply at least one electrical set pulse to the resistive element to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The apparatus is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first portion adapted to increase a temperature of the conductive filament and to increase a mobility of the oxygen vacancies of the conductive filament, and a second portion configured to displace the subset of the oxygen vacancies of the conductive filament.

Description

Background Technology

[0001] This disclosure particularly relates to devices comprising one or more tunable resistive elements. This disclosure also relates to methods for programming tunable resistive elements, neuromorphic networks, and computer program products for operating devices comprising one or more tunable resistive elements.

[0002] Nanoscale memory devices (whose resistance depends on the history of the applied electrical signal) have the potential to become key components in new computing paradigms such as brain-inspired computing and memcomputing. One leading solution is resistive RAM (RRAM). It involves creating filaments, such as oxygen vacancies, in a dielectric such as HfO2 using a process called soft breakdown. The filaments then close (set) or open (reset) during operation. Strongly reducing metals (such as titanium) can be used as one of the electrodes to enhance filament formation. Summary of the Invention

[0003] Embodiments of this disclosure include methods for programming tunable resistive elements, neuromorphic networks, and computer program products for operating devices comprising one or more tunable resistive elements.

[0004] According to some embodiments of this disclosure, an apparatus includes one or more tunable resistive elements. The tunable resistive element includes a first terminal, a second terminal, and a dielectric layer disposed between the first and second terminals. The apparatus is configured to apply one or more electrical set pulses to the one or more resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer, and to apply one or more electrical reset pulses to displace a subset of the oxygen vacancies in the conductive filament. The electrical reset pulse includes a first portion and a second portion, the first portion being adapted to increase the temperature of the conductive filament and the mobility of the oxygen vacancies in the conductive filament, and the second portion being configured to displace a subset of the oxygen vacancies in the conductive filament.

[0005] According to another embodiment of this disclosure, a method is used for programming a tunable resistive element. The tunable resistive element includes a first terminal, a second terminal, and a dielectric layer between the first and second terminals. The method includes: applying one or more electrical set pulses to one or more resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer; and applying one or more electrical reset pulses to displace a subset of the oxygen vacancies in the conductive filament. The electrical reset pulse includes a first portion adapted to increase the temperature of the conductive filament and the mobility of the oxygen vacancies in the conductive filament. The electrical reset pulse also includes a second portion configured to displace a subset of the oxygen vacancies in the conductive filament.

[0006] According to another embodiment of this disclosure, a computer program product is used to operate a device including one or more tunable resistive elements. The tunable resistive element includes a first terminal, a second terminal, and a dielectric layer disposed between the first and second terminals. The computer program product includes a computer-readable storage medium having program instructions embodied therein. The program instructions are executable by a control unit of the device to cause the control unit to perform a method comprising the steps of: applying one or more electrical set pulses to one or more resistive elements to form a conductive filament including a plurality of oxygen vacancies in the dielectric layer; and applying one or more electrical reset pulses to displace a subset of the oxygen vacancies of the conductive filament. The electrical reset pulse includes a first portion and a second portion, the first portion being adapted to increase the temperature of the conductive filament and the mobility of the oxygen vacancies in the conductive filament, and the second portion being configured to displace a subset of the oxygen vacancies of the conductive filament.

[0007] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings, by way of exemplary and non-limiting examples. Attached Figure Description

[0008] Figure 1 A block diagram of an apparatus according to some embodiments of the present disclosure is shown.

[0009] Figure 2 A schematic cross-sectional view of a tunable resistor element according to some embodiments of the present disclosure is shown.

[0010] Figure 3A A schematic cross-sectional view of a tunable resistor element in a first reset resistor state according to some embodiments of the present disclosure is depicted.

[0011] Figure 3B A schematic cross-sectional view of a tunable resistor element in a first set resistor state according to some embodiments of the present disclosure is depicted.

[0012] Figure 3C A schematic cross-sectional view of a tunable resistor element in a second set resistor state according to some embodiments of the present disclosure is depicted.

[0013] Figure 3D A schematic cross-sectional view of a tunable resistor element in a third set resistor state according to some embodiments of the present disclosure is depicted.

[0014] Figure 3E A schematic cross-sectional view of a tunable resistor element in a second reset resistor state according to some embodiments of the present disclosure is depicted.

[0015] Figure 3F A schematic cross-sectional view of a tunable resistor element in a third reset resistor state according to some embodiments of the present disclosure is depicted.

[0016] Figure 3G A tunable resistor element in a first reset resistor state is depicted according to some embodiments of the present disclosure.

[0017] Figure 4 The current-voltage characteristics of a tunable resistive element according to some embodiments of the present disclosure are shown.

[0018] Figure 5 Illustrative examples of resistance curves of resistive elements according to some embodiments of the present disclosure are depicted.

[0019] Figure 6 An illustrative reset pulse according to some embodiments of the present invention is described.

[0020] Figure 7 Another illustrative reset pulse according to some embodiments of the present invention is described.

[0021] Figure 8 Examples of set pulses according to some embodiments of the present invention are depicted.

[0022] Figure 9 Neuromorphic networks according to some embodiments of the present disclosure are depicted.

[0023] Figure 10 An illustrative flowchart of a method for programming a tunable resistive element according to some embodiments of the present disclosure is shown.

[0024] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements.

[0025] While the embodiments described herein may have different modifications and alternatives, their details have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the specific embodiments described are not intended to be limiting. Rather, it is intended to cover all modifications, equivalents, and substitutions that fall within the scope of this disclosure. Detailed Implementation

[0026] The various aspects of this disclosure generally relate to the field of computing, and more particularly to devices comprising one or more tunable resistive elements. While this disclosure is not necessarily limited to such applications, various aspects of this disclosure can be understood through the discussion of different examples using this context.

[0027] While it has been shown that setting a low-resistance state can be well controlled using the current compliance of the set signal, resetting the cell to a higher resistance is far less flexible. More specifically, it is typically feasible to simply reset to a high-resistance state (HRS). Therefore, further improvements to the resistive element and related devices are needed.

[0028] refer to Figure 1-10 This describes some general aspects and terminology of embodiments of this disclosure.

[0029] According to some embodiments of this disclosure, a resistive material can be defined as a material having a resistance that can be changed by applying an electrical signal to it. The electrical signal can be, for example, a current flowing through the device or a voltage applied to the resistive material. The current and / or voltage can be applied to the resistive element, for example, in the form of pulses. Therefore, the resistance of the resistive element depends on the history of the electrical signals that have been applied to the resistive memory element.

[0030] Resistive materials are particularly well-suited for use as memory elements. Therefore, resistive memory elements are based on the physical phenomenon that occurs in materials whose resistance changes when a current or electric field is applied. This change is typically non-volatile and reversible. Several classes of resistive memory elements are known, ranging from metal oxides to chalcogenides. A typical resistive memory element is a metal / insulator / metal structure, where the metal components act as electrodes and the insulator is the resistance-switching material. These resistive memory elements exhibit good performance in terms of power consumption, integration density potential, retention, and durability.

[0031] A particularly promising example of a resistive memory device is resistive random access memory (RRAM). This is a non-volatile memory technology in which basic memory cells (“cells”) comprise RRAM material situated between a pair of electrodes. The RRAM material in these cells is an electrically insulating matrix that typically exhibits high resistance to current. However, due to the nature of the RRAM matrix or a combination of the matrix and electrode materials, a specific property of an RRAM cell is that a conductive path can be formed within the high-resistivity matrix by applying a suitable electrical signal (specifically, a voltage) to the electrodes. This conductive path extends through the matrix in the direction between the electrodes. The conductive path can be broken or eliminated by applying another “RESET” signal to the electrodes, which returns the cell to a high-resistivity reset state. Thus, by appropriately applying set and reset pulses during one or more data write operations, individual cells can be programmed to states with measurably different resistance values. The programmed cell state can be determined during a read operation using the cell resistance as a metric for the cell state. When a read voltage is applied to the electrodes, the current flowing through the cell depends on the cell's resistance, thereby allowing the cell current to be measured to determine the cell state. The read voltage is typically significantly lower than the write voltage used for programming, so that the read operation does not interfere with the state of the cell being programmed.

[0032] While conductive paths can typically be formed by any of a number of different mechanisms in an RRAM cell, embodiments of this disclosure specifically use conductive paths formed by oxygen vacancies caused by the migration of oxygen ions in the insulating matrix.

[0033] The term "set pulse" generally refers to a pulse, or more commonly an electrical signal, that reduces the resistance of a resistive element, particularly by creating oxygen vacancies between the electrodes / terminals of the resistive element.

[0034] The term "reset pulse" should generally refer to a pulse, or more generally an electrical signal, that increases the resistance of a resistive element, particularly by reducing the size or resistivity of the conductive wire.

[0035] The term "reset resistance state of a resistive element" typically refers to the resistance state after one or more reset pulses have been applied. The reset resistance state can also be broadly described as a high resistance state (HRS).

[0036] The term "resistance state of a resistive element" typically refers to the resistance state after one or more set pulses have been applied. The resistance state is generally represented as a low resistance state (LRS).

[0037] According to an embodiment of the present invention, the reset pulse has a different polarity than the set pulse.

[0038] Figure 1 A simplified schematic block diagram of the resistive device 10 is shown. In at least some embodiments of this disclosure, the resistive device 10 may be a resistive memory device 10. The memory device 10 includes a multi-level resistive memory 11 for storing data in one or more integrated arrays of resistive memory elements described below. Data reading and writing to the memory 11 are performed by a control unit 12. The control unit 12 includes circuitry of generally known form for programming the resistive memory elements during data write operations and for performing read measurements for detecting the state of the elements during data read operations. During these operations, the control unit 12 can address individual resistive memory elements by applying appropriate control signals to the word lines and bit lines array in the resistive memory 11. User data input to the device 10 may undergo some form of write processing, such as encoding for error correction purposes, before being provided to the resistive memory 11 as a write signal (particularly as a write voltage). Similarly, read signals received from the resistive memory 11 may be processed by a read processing module of the control unit 12, for example for codeword detection and / or error correction, to recover the original input user data.

[0039] Figure 2 A simplified cross-sectional view of a tunable resistive element 20 according to at least one embodiment of the present disclosure is depicted. The tunable resistive element 20 includes a first terminal 21, a second terminal 22, and a dielectric layer 23. The dielectric layer 23 may comprise a metal oxide material. The metal oxide material may, in particular, be a transition metal oxide. According to at least one embodiment, the transition metal oxide may be ABO. 3-δPerovskite, where A is an alkaline earth metal, a rare earth metal, or a combination thereof, and B is a transition metal. An example is lanthanum and / or strontium titanium oxide (La, Sr)TiO. 3-δ Yttrium and / or calcium titanium oxide (Y, Ca)TiO 3-δ Lanthanum and / or strontium manganese oxides (La, Sr)MnO 3-δ , or praseodymium and / or calcium manganese oxides (Pr, Ca)MnO 3-δ Other transition metal oxides that can be advantageously used in embodiments of this disclosure include corundum, such as vanadium oxide and / or chromium oxide (V,Cr)₂O. 3-δ Other materials that can be advantageously used include binary transition metal oxides, such as nickel oxide (NiO). 1-δ Titanium oxide (TiO) 2-δ Hafnium oxide and / or zirconium oxide (Hf, Zr)O 2-δ and cerium oxide (CeO) 2-δ Preferably, the metal oxide material has a relatively high oxygen vacancy mobility (e.g., 10⁻⁶) at room temperature. -9 cm 2 Materials ( / Vs or higher).

[0040] The first terminal 21 and the second terminal 22 may comprise or be composed of metal, metal oxide, conductive or amorphous carbon, or the like. The metal of the first terminal 21 and the second terminal 22 may comprise Ti, TiN, Ta, TaN, W, Cu, Pt, any metal oxide (such as WO3, RuO2, and ITO), or amorphous C, or may be composed of Ti, TiN, Ta, TaN, W, Cu, Pt, any metal oxide (such as WO3, RuO2, and ITO), or amorphous C. The dielectric layer 23 may preferably be implemented having a thickness in the z-direction between 1 nm and 50 nm.

[0041] The dielectric layer 23 is configured to form conductive filaments with oxygen vacancies when an electrical programming signal (e.g., current or voltage) is applied.

[0042] According to some embodiments of the present invention, a plurality of resistive elements 20 may be implemented in the resistive memory 11, and the control unit 12 of the memory device 10 may be configured to apply one or more write signals (specifically write voltages) to the first terminal 21 and the second terminal 22 in write mode for writing the resistance state. Furthermore, the control unit 12 may apply read signals, particularly read voltages, to the first terminal 21 and the second terminal 22 in read mode for reading the resistance state.

[0043] The write signal can be implemented, in particular, as an electrically set pulse and an electrically reset pulse. By applying an electrically set pulse to the resistive element, one or more conductive filaments with oxygen vacancies can be formed in the dielectric layer 23. This results in a decrease in the resistance of the resistive element 20. Furthermore, by applying one or more electrically reset pulses to the resistive element 20, a subset of the oxygen vacancies in the conductive filaments can be moved, or in other words, shifted, to reduce the size or resistivity of the conductive filaments, thereby increasing the resistivity of the resistive element 20.

[0044] According to at least some embodiments of this disclosure, the control unit 12 can program the resistance state of the resistive element 20, particularly through an iterative programming and verification process.

[0045] See Figure 3A-3G The programming of the resistance state of resistor element 20 is explained in more detail.

[0046] Figure 3A A schematic cross-sectional view of the tunable resistor element 20 in the first reset resistor state RESET1 is depicted. In the first reset resistor state RESET1, there is no conductive wire with an oxygen vacancy between the first terminal 21 and the second terminal 22, or the previous conductive wire is at least interrupted (e.g., Figure 3G (as shown in the image).

[0047] The first reset resistor state RESET1 can be considered the initial state of the resistor element 20, meaning the state before any electric field or any electrical programming pulse has been applied to the resistor element 20. Furthermore, the first reset resistor state RESET1 can be achieved by applying one or more electrical reset pulses to the resistor element 20. These electrical reset pulses return the resistor element 20 to its original state.

[0048] The first reset resistor state can also refer to a full or complete reset state, indicating that there is no oxygen vacancy wire / path between the first terminal 21 and the second terminal 22.

[0049] Figure 3B A schematic cross-sectional view of the tunable resistor element 20 in the first set resistor state SET1 is shown. The first set resistor SET1 can be achieved by applying one or more set pulses. One or more set pulses generate filaments 30b of oxygen vacancies in the dielectric layer 23 between the first terminal 21 and the second terminal 22. The corresponding process for generating the conductive filaments 30b is referred to as soft breakdown.

[0050] Despite Figures 3B to 3G Only a single conductive wire 30b-30g (generally referred to as conductive wire 30) is shown in the figure, but it should be noted that, depending on the geometry of the corresponding device / unit, the placement pulse can also create multiple parallel conductive wires for oxygen vacancies.

[0051] like Figure 3B The filament 30b shown is relatively small, as illustrated by its exemplary width w1.

[0052] Figure 3C A schematic cross-sectional view of the tunable resistor element in the second set resistor state SET2 is shown. The second set resistor state SET2 can be reached from the first set resistor state SET1 by applying one or more set pulses to the first terminal 21 and the second terminal 22. The conductive wire 30b in the first set resistor state SET1 (in...) Figure 3B Compared to the state shown in the diagram, the conductive filament 30c in the second set-resistance state SET2 is larger. More specifically, the conductive filament 30c in the second set-resistance state includes a higher number of oxygen vacancies than the conductive filament 30b in the first set-resistance state. This can in particular result in the conductive filament 30c having a larger width and a larger cross-section in the second set-resistance state. This is shown with an exemplary width w2.

[0053] Figure 3D A schematic cross-sectional view of the tunable resistor element in the third set resistor state SET3 is shown. The third set resistor state SET3 can be reached from the second set resistor state SET2 by applying one or more set pulses to the first terminal 21 and the second terminal 22. The conductive wire 30c (in the second set resistor state SET2)... Figure 3C Compared to (as shown in the diagram), conductive wire 30d is larger. More specifically, conductive wire 30d in the third resistance state includes a greater number of oxygen vacancies than conductive wire 30c in the second resistance state. This can in particular result in a larger width and a larger cross-section for conductive wire 30d in the third resistance state. This is illustrated by the exemplary width w3.

[0054] See now Figure 3E The diagram illustrates a second reset resistor state, RESET2. The second reset resistor state, RESET2, can be reached from a third set resistor state, SET3, by applying one or more reset pulses. The reset pulses typically shift a subset of oxygen vacancies in the conductive wire 30e. This shift of oxygen vacancies typically reduces the size of the wire 30e. In other words, the shift of oxygen vacancies makes the wire 30e smaller and / or less conductive. Specifically, according to embodiments of this disclosure, the reset pulse is configured to trigger oxygen vacancies to drift away from the first terminal 21. In other words, the reset pulse shifts or moves oxygen vacancies closer to the first terminal 21. More generally, according to embodiments of this disclosure, the reset pulse is configured to trigger oxygen vacancies to drift away from the electrode acting as the anode.

[0055] Therefore, the displacement of oxygen vacancies caused by the reset pulse reduces the size of wire 30e, particularly near the first terminal 21. This is in Figure 3EThe wire 30e is shown in a simplified and exemplary manner, having a smaller segment 32a near the first terminal 21 and a larger segment 32b near the second terminal 22. According to an embodiment, segment 32a of wire 30e may have a width w2 in the second reset resistor state RESET2 corresponding to the width w2 of wire 30c in the second set resistor state SET2, and segment 32b of wire may have a width w3 in the second reset resistor state RESET2 corresponding to the width w3 of wire 30d in the third set resistor state SET3. Of course, as mentioned above, segments 32a and 32b are shown in a simplified manner to explain the general operation of the tunable resistive element according to embodiments of the present disclosure.

[0056] The nominal resistance value of the second reset resistor state RESET2 may correspond to or be close to the nominal resistance value of the second set resistor state SET2.

[0057] See now Figure 3F The diagram illustrates the third reset resistor state, RESET3. The third reset resistor state, RESET3, can be reached by applying one or more reset pulses, starting from the second reset resistor state, RESET2. According to embodiments of this disclosure, the reset pulses are configured to trigger further oxygen vacancies to drift from the first terminal 21. Therefore, the reset pulses further reduce the size of the filament 30f near the first terminal 21.

[0058] This is Figure 3F The wire 30f is shown in a simplified and exemplary manner. In the third reset resistor state RESET3, the wire 30f has segments 32a and 32b, segment 32a having a width w1 corresponding to the width w1 of the wire 30b in the first set resistor state SET1, and segment 32b having a width w3 corresponding to the width w3 of the wire 30d in the third set resistor state SET3. Therefore, the nominal resistance value of the third reset resistor state RESET3 can correspond to or be close to the nominal resistance value of the first set resistor state SET1.

[0059] Now for reference Figure 3GThis illustrates a tunable resistive element that is again in the first (full) reset resistor state RESET1. The first reset resistor state RESET1 can be reached from the third reset resistor state RESET3 by applying one or more reset pulses. The reset pulses, according to embodiments of this disclosure, are configured to trigger further oxygen vacancies to drift from the first terminal 21. Thus, the reset pulses further reduce the size of the filament near the first terminal 21. More specifically, the additional reset pulses have already opened, or in other words interrupted, the filament 30g in the region adjacent to or near the first terminal 21. Therefore, there is no longer a complete conductive filament between the first terminal 21 and the second terminal 22. Although the segment 32b of the filament 30g can remain in the region adjacent to or near the second terminal 22, the breakage of the filament 30g can correspond to a significant increase in the nominal resistance of the resistive element 20. Therefore, Figure 3A The resistor element 20 shown in the figure and Figure 3G The nominal resistance states of the resistor elements 20 shown in the figure are substantially similar to each other, and therefore both are collectively referred to as the first reset resistance state RESET1.

[0060] According to embodiments of this disclosure, the reset resistor states RESET1, RESET2 and RESET3 can also be referred to as high resistance states HRS1, HRS2 and HRS3, respectively.

[0061] According to embodiments of the present invention, the set resistor states SET1, SET2, and SET3 may also be referred to as low resistance states LRS1, LRS2, and LRS3, respectively. In this regard, the term "high resistance state" should indicate that the state has been reached after the application of a reset signal / reset pulse, while the term "low resistance state" should indicate that the state has been reached after the application of a set signal / set pulse.

[0062] Figure 4 The current-voltage characteristics of a tunable resistive element according to an embodiment of the present disclosure are shown. Specifically, Figure 4 This demonstrates the feasibility of obtaining multiple high-resistance states. Using a reset signal / reset pulse, three different reset resistance states / high-resistance states HRS1, HRS2, and HRS3 can be programmed. Furthermore, a single type of set pulse (where current compliance is...) has been used. Figure 4 The unit is adjusted to 1), resulting in the set resistor state / low resistance state LRS3. As mentioned above, the nominal value of the reset resistor state can partially correspond to the nominal value of the set resistor state.

[0063] Figure 5An example of a resistance curve for a resistive element according to an embodiment of the present disclosure is depicted. The y-axis represents the resistance, and the x-axis represents the number of set or reset pulses applied to the resistive element. The resistance of the resistive element can vary between the lowest RSETL among a plurality of set resistor states and the highest RRESETH among a plurality of reset resistor states. Reference Figures 3A to 3G In the example shown, the corresponding tunable resistor element can be changed between RSET3 as the lowest set resistor state and RRESET1 as the highest reset resistor state.

[0064] Resistance can be increased by applying a reset pulse. Conversely, resistance can be decreased by applying a set pulse. In this respect, embodiments of the present disclosure can provide non-hysteretic behavior of the resistive element, which facilitates bidirectional programming of the resistance value of the resistive element. In other words, according to embodiments of the present disclosure, the resistive element provides a substantially symmetrical bidirectional resistance profile when a set pulse and a reset pulse are applied. Therefore, embodiments of the present disclosure can provide a continuously tunable resistor as a two-terminal device.

[0065] Figure 6 An example reset pulse 600 according to at least one embodiment of the present disclosure is depicted. The horizontal axis represents time t in arbitrary units, and the vertical axis represents the voltage V of the reset pulse 600 in arbitrary units. The reset pulse 600 is shaped to decouple the effects of temperature rise and electric field-induced ion drift. The reset pulse 600 includes a first portion 601 (or in other words, a first signal segment 601) extending over a first duration T1 and a second portion 602 (or in other words, a second signal segment 602) extending over a second duration T2.

[0066] Part 601 is adapted to increase the temperature of the conductive wire 30 (such as... Figure 3B-3G (As shown in the diagram) and increases the mobility of oxygen vacancies in conductive wire 30. The second portion 602 is configured to shift a subset of oxygen vacancies in conductive wire 30. More specifically, the second portion 602 is configured to remove oxygen vacancies from the terminal acting as the anode. The reset pulse 600 is shaped such that multiple reset resistor states can be programmed, and a gradual increase in resistance can be achieved directly without a complete reset.

[0067] The first part 601 of the electrical reset pulse 600 has a first peak amplitude Vpeak1, and the second part 602 of the electrical reset pulse 600 has a second peak amplitude Vpeak2. The first peak amplitude Vpeak1 is greater than the second peak amplitude Vpeak2, and the first duration T1 is less than the second duration T2.

[0068] The first segment 601 typically comprises a signal with a large amplitude and a short duration. This signal segment causes a temperature rise within / around the conductive filament 30. This results in an increase in the mobility of oxygen vacancies in this region. However, the duration of this first signal segment 601 is chosen to be so short that the oxygen vacancies have virtually no time to drift and are therefore essentially kept in place.

[0069] Part 602 includes a signal with a smaller amplitude and a longer duration. This signal segment causes the oxygen vacancy to drift.

[0070] The resistive element according to embodiments of this disclosure utilizes the increased temperature within / around the conductive filament 30 caused by the first signal segment 601 to maintain this temperature for a certain duration through the first signal segment. This is achieved, in particular, through the low thermal conductivity of the resistive element material. Consequently, during the second signal segment 602, the temperature within / around the conductive filament 30, along with the associated oxygen vacancy mobility, remains high.

[0071] The smaller amplitude of the second signal segment 602, along with the accompanying slower oxygen vacancy drift rate and longer duration, allows for well-controlled shifting of oxygen vacancies. As a result, the resistance state of the resistive element can be gradually decreased by a set pulse and gradually increased by a reset pulse. In other words, the resistance state of the resistive element can be modified in a well-controlled manner.

[0072] The resistive elements according to embodiments of this disclosure can provide greater durability than conventional RRAM, which requires a full reset to achieve a gradual increase in the resistance of the RRAM cell.

[0073] According to at least one embodiment of the present disclosure, the first peak amplitude Vpeak1 is at least twice the second peak amplitude Vpeak2. According to at least one embodiment of the present disclosure, the first peak amplitude Vpeak1 is at least three times the second peak amplitude Vpeak2. According to at least one embodiment of the present disclosure, the first peak amplitude Vpeak1 is at least four times the second peak amplitude Vpeak2. According to at least one embodiment of the present disclosure, the first peak amplitude Vpeak1 is at least five times the second peak amplitude Vpeak2.

[0074] According to at least one embodiment of the present invention, the second duration T2 is at least five times longer than the first duration T1. According to at least one embodiment of the present invention, the second duration T2 is at least ten times longer than the first duration T1.

[0075] According to at least one embodiment of this disclosure, the first peak amplitude is in the range of 0.1 volts to 2 volts.

[0076] According to at least one embodiment of this disclosure, the second peak amplitude is in the range of 0.02 volts to 1 volt.

[0077] According to at least one embodiment of the present invention, the first duration is in the range of 1 nanosecond to 100 nanoseconds.

[0078] According to at least one embodiment of the present invention, the second duration is in the range of 5-1000 nanoseconds.

[0079] Figure 7 An exemplary reset pulse 700 according to at least one embodiment of the present disclosure is depicted. The horizontal axis represents time t in arbitrary units, and the vertical axis represents the voltage V of the reset pulse 700 in arbitrary units.

[0080] The reset pulse 700 includes a first portion 701 (or in other words, a first signal segment 701) extending over a first duration T1 and a second portion 702 (or in other words, a second signal segment 702) extending over a second duration T2. ​​The first portion 701 is adapted to increase the temperature of the conductive wire 30 and increase the mobility of oxygen vacancies in the conductive wire 30. The second portion 702 is configured to displace a subset of oxygen vacancies in the conductive wire 30. More specifically, the second portion 702 is configured to move oxygen vacancies away from the terminal acting as the anode.

[0081] The first portion 701 of the electrical reset pulse 700 has a first peak amplitude Vpeak1, which remains constant for a short period of time. The second portion 702 of the electrical reset pulse 700 has a second peak amplitude Vpeak2, which is lower than that of the reset signal 600. Figure 6 The second peak amplitude Vpeak2 (shown in the diagram) is lower. The lower second peak amplitude Vpeak2 is compensated by the second duration T2 of the reset signal 700, which is longer than the second duration T2 of the reset signal 600.

[0082] It should be noted that, such as Figure 6 and 7 The shapes of the reset pulses 600 and 700 shown are merely illustrative examples, and the shapes can be adapted to the needs of the respective application. Various other shapes can be used to achieve the desired decoupling of temperature rise and oxygen vacancy drift according to other embodiments of this disclosure.

[0083] Figure 8 An illustrative example of a set pulse signal 800 according to an embodiment of the present disclosure is depicted. The set pulse of signal 800 has a basic rectangular shape with a constant peak amplitude Vpeak. According to at least one embodiment of the present disclosure, programming a desired set resistor state may include applying a plurality of consecutive set pulses, such as applying two set pulses in this example.

[0084] It should be noted that Figure 6 , Figure 7 and Figure 8 An illustrative example of the absolute voltage levels of the reset pulse and set pulse according to embodiments of the present disclosure is described. As mentioned above, the set pulse and reset pulse have different polarities.

[0085] According to at least one embodiment of the present disclosure, the absolute value of the peak amplitude Vpeak of the set pulse can be between the absolute value of the first peak amplitude Vpeak1 and the absolute value of the second peak amplitude Vpeak2 of the reset pulse.

[0086] Figure 9 A neuromorphic network 900 according to at least one embodiment of the present disclosure is depicted. The neuromorphic network 900 includes an input layer 910, a hidden layer 920, and an output layer 930. The input layer 910 includes a plurality of input nodes 911, and the output layer 930 includes a plurality of output nodes 931. The hidden layer 920 includes a plurality of neurons 940 and a plurality of synapses 950. Each synapse 950 can be implemented as a resistive element, such as the resistive element 20 described above. Given bidirectional programming enabled by a specific reset pulse, tunable resistive elements according to embodiments of the present disclosure are particularly suitable for use as synapses. Therefore, in this simulated neuromorphic network, the synaptic array can be implemented with a single resistive element instead of the two resistive elements in the prior art. Thus, the present disclosure facilitates higher density arrays.

[0087] Figure 10 An exemplary flowchart of a method 1000 for programming a tunable resistive element is shown.

[0088] In operation 1010, method 1000 includes applying one or more electrical set pulses to one or more resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in a dielectric layer, thereby reducing resistance.

[0089] In operation 1020, the method includes applying one or more electrical reset pulses to shift a subset of oxygen vacancies in the conductive wire, thereby increasing the resistance.

[0090] This invention can be a system, method, and / or computer program product with any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0091] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0092] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0093] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by personalizing the electronic circuitry with state information utilizing the computer-readable program instructions in order to perform aspects of this invention.

[0094] The present invention is described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0095] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that instructs a computer, programmable data processing apparatus, and / or other means to operate in a particular manner, wherein the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0096] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other apparatus to produce a computer-implemented process, such that the instructions that execute on the computer, other programmable apparatus, or other apparatus perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, two consecutively shown blocks may actually be completed as a single step, executed simultaneously, substantially simultaneously, or with partial or complete temporal overlap, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0098] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0099] Generally, modifications described for one embodiment can be appropriately applied to another embodiment.

[0100] In addition to the embodiments described above, other embodiments with fewer, more, or different operation steps are contemplated. Furthermore, some embodiments may perform some or all of the above operation steps in a different order. Moreover, multiple operations may occur simultaneously or as part of a larger process. Modules are illustratively listed and described according to some embodiments and do not imply the necessity of a particular module or the exclusivity of other potential modules (or functions / purposes applied to a particular module).

[0101] In the foregoing, reference has been made to various embodiments. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the features and elements described is contemplated for implementation and practice of this disclosure, regardless of whether they are associated with the various embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit this disclosure. Therefore, the described aspects, features, embodiments, and advantages are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0102] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. In the preceding detailed description of exemplary embodiments of the various embodiments, reference has been made to the accompanying drawings (in which like numbers denote like elements), which form part of the description, and specific exemplary embodiments in which the various embodiments can be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, but other embodiments may be used and logical, mechanical, electrical, and other changes may be made without departing from the scope of the various embodiments. In the preceding description, numerous specific details have been set forth to provide a thorough understanding of the various embodiments. However, the various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the embodiments.

[0103] As used in this article, when referring to a project as “multiple,” it means one or more projects. For example, “multiple different types of networks” means one or more different types of networks.

[0104] When different reference numbers include common numbers followed by different letters (e.g., 100a, 100b, 100c) or punctuation followed by different numbers (e.g., 100-1, 100-2, or 100.1, 100.2), the reference character without letters or following numbers (e.g., 100) may refer to the group of elements as a whole, any subset of that group, or an example sample of that group.

[0105] Furthermore, when used with a series of items, the phrase "at least one" indicates that different combinations of one or more of the listed items can be used, and only one item from each of the listed items may be required. In other words, "at least one" means that any combination of items and multiple items from the list can be used, but not all items from the list. Items can be specific objects, things, or categories.

[0106] For example, but not limited to, "at least one of Item A, Item B, or Item C" can include Item A, Item A and Item B, or Item B. The example could also include Item A, Item B, and Item C, or Item B and Item C. Of course, any combination of these items can exist. In some illustrative examples, "at least one" can be, for example, but not limited to, two Item A; one Item B; and ten Item C; four Item B and seven Item C; or other suitable combinations.

[0107] Different instances of the term "implementation method" as used in this specification do not necessarily refer to the same implementation method, but they may refer to the same implementation method. Any data and data structures shown or described herein are merely examples, and in other embodiments, different amounts of data, data types, fields, the number and type of fields, field names, rows, records, entries, or the number and type of data organization may be used. Furthermore, any data may be logically combined such that a separate data structure may not be necessary. Therefore, the foregoing detailed description should not be considered limiting.

[0108] While this disclosure has been described with reference to specific embodiments, variations and modifications thereof are expected to become apparent to those skilled in the art. Therefore, the following claims are intended to be construed as covering all such changes and modifications that fall within the true scope of this disclosure.

Claims

1. An apparatus comprising a tunable resistive element, comprising: At least one tunable resistor element, each tunable resistor element comprising: First terminal; Second terminal; and A dielectric layer is disposed between the first terminal and the second terminal, wherein the device is configured to: At least one electrical set pulse is applied to the at least one resistive element to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer; and Applying at least one electrical reset pulse to the at least one resistive element to shift a subset of oxygen vacancies in the conductive wire, wherein the at least one electrical reset pulse comprises: A first portion, adapted to increase the temperature of the conductive wire, increase the mobility of oxygen vacancies in the conductive wire, and without displacing the subset of oxygen vacancies; and The second part is a subset of the oxygen vacancies configured to shift the conductive wire.

2. The apparatus according to claim 1, wherein: The first portion of the at least one electrical reset pulse has a first peak amplitude and a first duration; The second portion of the at least one electrical reset pulse has a second peak amplitude and a second duration; as well as The first peak amplitude is greater than the second peak amplitude, and the first duration is shorter than the second duration.

3. The apparatus according to claim 2, wherein: The first peak amplitude is at least twice the size of the second peak amplitude.

4. The apparatus according to claim 2, wherein: The second duration is at least five times longer than the first duration.

5. The apparatus according to claim 2, wherein: The first peak amplitude is in the range of 0.1 volts to 2 volts; The second peak amplitude is in the range of 0.02 volts to 1 volt; The first duration is in the range of 1 nanosecond to 100 nanoseconds; and The second duration is in the range of 5 nanoseconds to 1000 nanoseconds.

6. The apparatus according to claim 1, wherein, The at least one tunable resistive element is configured as follows: Multiple set resistor states are provided in response to the application of at least one electrical set pulse; as well as Multiple reset resistor states are provided in response to the application of at least one electrical reset pulse.

7. The apparatus according to claim 1, wherein, The dielectric layer comprises a metal oxide material.

8. The apparatus according to claim 7, wherein, The metal oxide material is a transition metal oxide.

9. The apparatus according to claim 8, wherein, The metal oxide material is a perovskite transition metal oxide.

10. The apparatus according to claim 7, wherein, The metal oxide material is selected from the group consisting of: ABO 3-δ Perovskite, where A is an alkaline earth metal, a rare earth element, or a combination thereof, and B is a transition metal element; Corundum; and Binary transition metal oxides.

11. The apparatus according to claim 10, wherein, The metal oxide material is selected from the group consisting of: Lanthanum and / or strontium titanium oxide (La, Sr)TiO 3-δ ; Yttrium and / or perovskite (Y, Ca)TiO 3-δ ; Lanthanum and / or strontium manganese oxides (La, Sr)MnO 3-δ ; Praseodymium and / or calcium manganese oxides (Pr, Ca)MnO 3-δ ; Vanadium and / or chromium oxides (V, Cr)₂O 3-δ .

12. The apparatus according to claim 10, wherein, The metal oxide material is selected from the group consisting of: Nickel oxide NiO 1-δ ; Titanium oxide (TiO) 2-δ ; Hafnium and / or zirconium oxide (Hf, Zr)O 2-δ ;as well as Cerium oxide (CeO) 2-δ .

13. The apparatus according to claim 1, wherein, At least one of the first terminal and the second terminal comprises one of a metal, a metal oxide, conductive carbon, and amorphous carbon.

14. The apparatus according to claim 13, wherein, At least one of the first terminal and the second terminal comprises a material selected from the group consisting of: Ti, TiN, Ta, TaN, W, Cu, Pt, and metal oxides.

15. The apparatus of claim 14, wherein the metal oxide comprises: WO3, RuO2 and ITO.

16. The apparatus according to claim 1, wherein, The dielectric layer has a thickness between 1 nanometer and 50 nanometers.

17. The apparatus according to claim 1, wherein, The device is configured to provide a bidirectional resistance profile when a set pulse and a reset pulse are applied.

18. The apparatus according to claim 1, wherein, The device includes a control unit, which is configured to apply the electrical set pulse and the electrical reset pulse as electrical programming pulses to at least one of the first terminal and the second terminal.

19. The apparatus according to claim 18, wherein, The control unit is configured to program the resistance state of the resistive element through an iterative programming and verification process.

20. The apparatus according to claim 18, wherein, The control unit is configured to: In read mode, a read voltage is applied to the first terminal and the second terminal to read the resistance state of the one or more resistive elements.

21. The apparatus of claim 1, wherein, The device is configured as a synapse of a neuronal morphological network.

22. A method for programming a tunable resistive element, the tunable resistive element comprising a first terminal, a second terminal, and a dielectric layer between the first terminal and the second terminal, the method comprising: At least one electrical set pulse is applied to the tunable resistor element to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer; as well as Apply at least one electrical reset pulse to shift a subset of oxygen vacancies in the conductive wire, said at least one electrical reset pulse comprising: The first part is adapted to increase the temperature of the conductive wire, increase the mobility of oxygen vacancies in the conductive wire, and not shift the subset of oxygen vacancies. as well as The second part is a subset of the oxygen vacancies configured to shift the conductive wire.

23. A computer program product for operating a device comprising at least one tunable resistive element, wherein, Each tunable resistive element includes a first terminal, a second terminal, and a dielectric layer disposed between the first terminal and the second terminal. The computer program product includes a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a control unit to cause the control unit to perform a method comprising: At least one electrical set pulse is applied to the at least one resistive element to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer; and Apply at least one electrical reset pulse to shift a subset of oxygen vacancies in the conductive wire, said at least one electrical reset pulse comprising: A first portion, adapted to increase the temperature of the conductive wire, increase the mobility of oxygen vacancies in the conductive wire, and without displacing the subset of oxygen vacancies; and The second part is a subset of the oxygen vacancies configured to shift the conductive wire.

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