Timing detection circuit, method and electronic device

Abstract

Embodiments of the present application provide a timing detection circuit, method and electronic device, and relate to the technical field of electronic devices. The circuit comprises an oscillator, a path simulator, a delay detector and a pre-warning device. The oscillator generates an oscillation signal based on the rising edge jump of a clock signal, the path simulator simulates the propagation process of the oscillation signal in the critical path of the chip, the delay detector determines the propagation time of the oscillation signal in the path simulator based on the clock signal, and the pre-warning device generates a timing pre-warning signal representing timing anomalies when the propagation time does not meet the preset conditions. By generating an oscillation signal based on the rising edge jump of the clock signal and simulating the propagation process of the oscillation signal in the critical path, the propagation time of the oscillation signal can be detected based on the clock signal, the propagation time of the oscillation signal can be quickly determined, and the propagation time of the signal in the critical path in the chip can be determined, and it is determined whether the timing margin of the chip is sufficient.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to a timing detection circuit, method, and electronic equipment. Background Technology

[0002] During the operation of integrated circuits, phenomena such as increased dynamic power consumption and uneven heat dissipation will lead to dynamic voltage drops. Dynamic voltage drops slow down the propagation delay of the integrated circuit, resulting in insufficient timing margin. Therefore, during chip operation, it is necessary to monitor the chip's timing margin in real time to quickly adjust the chip's operating state and avoid insufficient timing margin affecting the normal operation of the chip.

[0003] In prior art, due to the long detection time of timing margin, it is impossible to determine in a timely manner whether the timing margin of the chip is sufficient. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a timing detection circuit, timing detection method and electronic device that overcomes or at least partially solves the above problems, so as to solve the problem of not being able to determine in a timely manner whether the timing margin of the chip is sufficient.

[0005] Accordingly, embodiments of the present invention also provide a timing detection method and an electronic device to ensure the implementation and application of the above method.

[0006] To address the aforementioned problems, this invention discloses a timing detection circuit applied to a chip capable of generating clock signals, comprising:

[0007] An oscillator for generating an oscillating signal based on the rising edge of the clock signal;

[0008] A path simulator, connected to the oscillator, is used to receive the oscillation signal and simulate the propagation process of the oscillation signal in the critical path of the chip, thereby transmitting the oscillation signal.

[0009] A delay detector, connected to the path simulator, is used to detect the oscillation signal transmitted by the path simulator based on the clock signal, so as to determine the propagation time of the oscillation signal in the path simulator;

[0010] An early warning device, connected to the delay detector, is used to generate a timing warning signal characterizing a timing anomaly when the propagation time does not meet preset conditions.

[0011] Optionally, it further includes: a clock delay unit, which is used to perform at least one delay processing on the clock signal to generate at least one delayed signal; the clock delay unit includes at least one clock output terminal, and each clock output terminal outputs one of the delayed signals respectively;

[0012] The input terminal of the oscillator is connected to the target clock output terminal of the at least one clock output terminal; the oscillator is used to generate the oscillation signal that jumps with the rising edge of the target delay signal; the target delay signal is output by the target clock output terminal.

[0013] Optionally, the delay detector includes at least one first detection trigger, and the clock input of each first detection trigger is connected to a clock output of the clock delayer for acquiring a delay signal.

[0014] The data input terminal of the first detection trigger is connected to the output terminal of the path simulator so that when the corresponding delay signal is acquired at the clock input terminal of the first detection trigger, the detection of the oscillation signal output by the path simulator is initiated.

[0015] Optionally, the delay detector further includes a second detection trigger corresponding to the clock signal. The data input terminal of the second detection trigger is connected to the output terminal of the path simulator to initiate the detection of the oscillation signal output by the path simulator when the clock signal is received at the clock input terminal of the second detection trigger.

[0016] Optionally, the warning device includes a comparator;

[0017] The comparator is used to acquire and combine the output values ​​of the first detection trigger to obtain a detection value; or, to acquire and combine the output values ​​of the first detection trigger and the second detection trigger to obtain a detection value.

[0018] The comparator is also used to generate the timing warning signal when the detected value does not meet the preset condition.

[0019] Optionally, the warning device is further configured to receive a delay setting signal and determine the preset condition based on the delay setting signal.

[0020] Optionally, the clock delay includes at least one group of inverters connected in sequence, each group of inverters including an even number of inverters connected in sequence;

[0021] The input terminal of the clock delayer is used to receive the clock signal, and the at least one inverter group is used to sequentially delay the clock signal to generate a delay signal corresponding to each inverter group.

[0022] Optionally, the oscillator includes: an oscillation trigger, an inverter, and an AND gate circuit;

[0023] The data input terminal of the oscillation trigger is connected to the output terminal of the AND gate circuit, and the clock input terminal of the oscillation trigger is used to acquire the clock signal; the output terminal of the oscillation trigger is connected to the input terminal of the inverter and the input terminal of the path simulator respectively.

[0024] One input terminal of the AND gate circuit is connected to the output terminal of the inverter, and is used to cause the oscillator to generate the oscillation signal when the other input terminal of the AND gate circuit receives a start signal.

[0025] This invention also discloses a timing detection method, applied to a chip capable of generating clock signals, comprising:

[0026] An oscillation signal is generated, the oscillation signal being based on the rising edge of the clock signal;

[0027] The oscillation signal is transmitted by simulating the propagation process of the oscillation signal in the critical path of the chip using a path simulator.

[0028] Based on the clock signal, the oscillation signal during the propagation process is detected to determine the propagation time of the oscillation signal in the path simulator;

[0029] When the propagation time does not meet the preset conditions, a timing warning signal representing a timing anomaly is generated.

[0030] Optionally, before generating the oscillation signal, the method further includes:

[0031] The clock signal is subjected to at least one delay processing to generate at least one delayed signal;

[0032] The generation of the oscillation signal includes:

[0033] The oscillating signal is generated that changes with the rising edge of the target delay signal.

[0034] Optionally, detecting the oscillation signal during propagation based on the clock signal to determine the propagation time of the oscillation signal in the path simulator includes:

[0035] When each of the delay signals is acquired, the oscillation signal is detected to determine the propagation time of the oscillation signal in the path simulator.

[0036] Optionally, it further includes: detecting the oscillation signal when the clock signal is acquired, in order to determine the propagation time of the oscillation signal in the path simulator.

[0037] Optionally, it further includes: receiving a delay setting signal and determining the preset condition based on the delay setting signal.

[0038] This invention also discloses an electronic device, including the timing detection circuit described above.

[0039] The embodiments of the present invention have the following advantages:

[0040] In this embodiment of the invention, the timing detection circuit includes an oscillator, a path simulator, a delay detector, and an early warning unit. The oscillator generates an oscillation signal. The path simulator, connected to the oscillator, receives the oscillation signal and simulates its propagation in the critical path of the chip. The delay detector, also connected to the path simulator, detects the oscillation signal transmitted by the path simulator based on a clock signal to determine its propagation time within the simulator. The early warning unit, connected to the delay detector, generates a timing warning signal indicating a timing anomaly when the propagation time does not meet preset conditions. By generating an oscillation signal based on the rising edge of a clock signal and simulating its propagation in the critical path using the path simulator, the propagation time of the oscillation signal in the path simulator can be detected based on the clock signal, quickly determining the propagation time and thus the propagation time of the signal in the critical path within the chip, thereby determining whether the chip's timing margin is sufficient. Attached Figure Description

[0041] Figure 1 A schematic diagram of a timing detection circuit according to the present invention is shown;

[0042] Figure 2 A schematic diagram of the circuit structure of a timing detection circuit according to the present invention is shown;

[0043] Figure 3 for Figure 2 The timing diagram of the timing detection circuit shown is shown.

[0044] Figure 4 A schematic diagram of the circuit structure of another timing detection circuit of the present invention is shown;

[0045] Figure 5 for Figure 4 The timing diagram of the timing detection circuit shown is shown.

[0046] Figure 6 A schematic diagram of the circuit structure of another timing detection circuit of the present invention is shown;

[0047] Figure 7 A flowchart of the steps of a timing detection method according to the present invention is shown;

[0048] Figure 8 This is a structural block diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Before providing a detailed description of the embodiments of the present invention, the current timing detection circuit will be introduced first.

[0051] In prior art, to test the timing margin of a chip, the central processing unit (CPU) is typically operated at a preset frequency and corresponding preset voltage. A ring oscillator is installed internally within the CPU, with its frequency corresponding to the voltage across the CPU terminals. By detecting the ring oscillator frequency, the CPU's operating voltage can be detected, further determining the CPU's operating frequency and whether the chip's timing margin is sufficient. However, detecting the CPU's operating frequency using a ring oscillator requires accumulating the ring oscillation signal count over a certain period as a reference, resulting in a lengthy detection time and making it difficult to promptly determine whether the chip's timing margin is adequate.

[0052] One of the core concepts of this invention is that an oscillation signal based on the rising edge of a clock signal is generated by an oscillator. The oscillation signal is used to simulate the propagation process of a signal in the chip in the critical path. The propagation time in the propagation process is detected based on the clock signal. The propagation time of the oscillation signal in the critical path can be quickly determined. Thus, the timing margin of the chip can be quickly determined based on the propagation time.

[0053] Reference Figure 1 The diagram shows a schematic of a timing detection circuit according to the present invention. The timing detection circuit is applied to a chip that can generate clock signals and includes: an oscillator, a path simulator, a delay detector, and an early warning device.

[0054] An oscillator is used to generate an oscillating signal, which is based on the rising edge of a clock signal.

[0055] In this embodiment, the oscillator is used to generate an oscillation signal based on the rising edge of the clock signal. When the oscillation signal changes based on the rising edge of the clock signal, the propagation process of the oscillation signal can be detected based on the clock signal to determine the propagation time of the oscillation signal during the propagation process.

[0056] Optionally, the oscillator may include an oscillation trigger, an inverter, and an AND gate. The data input of the oscillation trigger is connected to the output of the AND gate, and the clock input of the oscillation trigger is used to acquire a clock signal. The output of the oscillation trigger is connected to the input of the inverter and the input of the path simulator, respectively. One input of the AND gate is connected to the output of the inverter, and is used to cause the oscillator to generate an oscillation signal when a start signal is received at the other input of the AND gate.

[0057] For example, such as Figure 2 As shown, Figure 2 A schematic diagram of a timing detection circuit according to the present invention is shown. The oscillator 101 may include an oscillation trigger 1011, an inverter 1012, and an AND gate circuit 1013. A start signal is used to start the timing detection circuit. Figure 2 The "Run" signal indicates a start signal. A start signal can be, for example, a set signal output by the CPU within the chip, or a set signal generated by a set switch after the user manually operates it. The clock signal within the chip can be, for example, a pulse signal generated by the chip's clock circuit to control the operation of various electronic components within the chip. Figure 2 The "CLK" signal represents the clock signal. The specific methods for generating the start signal and clock signal can be set according to requirements, and this embodiment does not impose any restrictions on this.

[0058] In this embodiment, AND gate 1013 is a two-input AND gate. One input of AND gate 1013 can be connected to a set switch or CPU to receive a start signal, and the other input of AND gate 1013 is connected to the output of inverter 1012. Oscillator 1011 is a storage cell circuit that operates when triggered by a clock signal. The clock input of oscillator 1011 can be connected to the output of a clock circuit to receive the clock signal generated by the clock circuit. The data input of oscillator 1011 is connected to the output of AND gate 1013 to receive the data output by AND gate 1013.

[0059] like Figure 3 As shown, Figure 3 for Figure 2The timing diagram of the timing detection circuit shown illustrates that when the start signal Run is received at one input of AND gate 1013, that input is set to 1. When the first rising edge 301 of the clock signal CLK arrives, the output of AND gate 1013 is 1, and the data 1 output by AND gate 1013 is fed into oscillator flip-flop 1011 under the action of the first rising edge 301, causing the output of oscillator flip-flop 1011 to be 1. At this time, the output of inverter 1012 is 0, and the output of AND gate 1013 jumps to 0. When the second rising edge 302 of the clock signal arrives, the data 0 output by AND gate 1013 is fed into oscillator flip-flop 1011, causing the output of oscillator flip-flop 1011 to jump to 0. This process continues, with each rising edge of the clock signal CLK, the output of oscillator flip-flop 1011 is inverted once, causing a jump, generating an oscillation signal OS that jumps with the rising edge of the clock signal CLK.

[0060] In practical applications, an oscillation signal is generated by an oscillation trigger, which maintains the oscillation signal's transition based on the rising edge of the clock signal. Therefore, the oscillation signal can be detected based on the rising edge of the clock signal, accurately determining the propagation time of the oscillation signal. The oscillator can also be an oscillator with other circuit structures; this embodiment does not limit the specific structure of the oscillator.

[0061] It should be noted that, Figure 2 The oscillation trigger in the system can directly acquire the clock signal, causing the oscillation signal to change when the rising edge of the clock signal arrives. It can also acquire the delayed clock signal, causing the oscillation signal to change when the rising edge of the delayed signal arrives.

[0062] In this embodiment, the path simulator is connected to the oscillator to receive the oscillation signal and simulate the propagation process of the oscillation signal in the critical path of the chip, thereby transmitting the oscillation signal.

[0063] The critical path is the longest logic path in the chip from input to output. The path simulator is used to simulate the critical path in the chip. Therefore, the propagation process of the oscillating signal in the path simulator is the same as the propagation process of the signal in the chip in the critical path. The propagation time of the oscillating signal in the path simulator is the same as the propagation time of the signal in the chip in the critical path.

[0064] In one embodiment, the path simulator 102 can be a replication circuit for the critical path. Specifically, all electronic components in the critical path can be replicated according to the circuit logic of the critical path and placed between the oscillator 101 and the delay detector 103, while maintaining the power supply voltage of the path simulator consistent with that of the critical path. Figure 2As shown, the input terminal of the path simulator 102 is connected to the output terminal of the oscillation trigger 1011 to receive the oscillation signal. The output terminal of the path simulator 102 is connected to the delay detector 103. The oscillation signal propagates from the path simulator 102 to the delay detector 103 to simulate the propagation process of the signal in the chip in the critical path. It should be noted that the simulation method of the critical path may include, but is not limited to, the method of replicating the critical path. Existing or future simulation methods in the art can be applied to this embodiment.

[0065] The delay detector, connected to the path simulator, is used to detect the oscillation signal transmitted by the path simulator based on a clock signal, in order to determine the propagation time of the oscillation signal in the path simulator.

[0066] In this embodiment, the delay detector 103 can detect the oscillation signal propagating in the path simulator 102 based on the rising edge of the clock signal to determine the reception time of the oscillation signal received by the delay detector 103. Based on the reception time of the oscillation signal and the clock signal, the propagation time of the oscillation signal in the path simulator 102 can be determined, which is also the propagation time of the signal in the chip in the critical path.

[0067] Optionally, the delay detector includes a second detection trigger 1031 corresponding to the clock signal. The data input terminal of the second detection trigger 1031 is connected to the output terminal of the path simulator 102 so that when the clock signal is received at the clock input terminal of the second detection trigger 1031, the detection of the oscillation signal output by the path simulator 102 is initiated.

[0068] like Figure 2 As shown, the delay detector 103 includes a second detection trigger 1031, which is a storage cell circuit that operates when triggered by a clock signal. The data input terminal of the second detection trigger 1031 is connected to the output terminal of the path simulator 102 to receive the oscillation signal propagated by the path simulator 102. The clock input terminal of the second detection trigger 1031 can be connected to the output terminal of a clock circuit to detect the data at the output terminal of the path simulator 102 when the rising edge of the clock signal is received, and to determine whether the oscillation signal has propagated to the output terminal of the path simulator 102.

[0069] Combination Figure 2 and Figure 3When the first rising edge 301 of the clock signal CLK arrives, the oscillator 101 begins to oscillate, generating a periodically varying oscillation signal OS. At the first rising edge 301, the path simulator 102 receives the oscillation signal OS (at this time, the value of the oscillation signal is 1) and begins to propagate the oscillation signal OS towards the delay detector 103. At this time, due to the delay effect of the path simulator 102 on the oscillation signal OS, when the first rising edge 301 reaches the clock input of the second detection trigger 1031, although the second detection trigger 1031 activates, it cannot detect the oscillation signal. When the second rising edge 302 of the clock signal CLK arrives, the second detection trigger 1031 activates under the action of the second rising edge, receiving the data output by the path simulator 102 to determine whether the oscillation signal has propagated to the output of the path simulator 102. At this time, if the output of the second detection trigger 1031 is 1, that is, the oscillation signal OS propagated from the path simulator 102 has been received, it can be determined that the oscillation signal OS has been transmitted to the input terminal of the second detection trigger 1031 (i.e., the output terminal of the path simulator 102) when the second rising edge 302 arrives or before the second rising edge 302 arrives. Therefore, it can be determined that the propagation time of the oscillation signal OS in the path simulator 102 is less than or equal to the interval T between the first rising edge 301 and the second rising edge 302 of the clock signal CLK. The interval T also represents the length of one clock cycle in the clock signal. Conversely, if the second detection trigger 1031 does not receive the oscillation signal OS when the second rising edge 302 arrives, it means that the oscillation signal OS has not been transmitted to the input terminal of the second detection trigger 1031, and the propagation time of the oscillation signal OS in the path simulator 102 is greater than one clock cycle T.

[0070] Similarly, at the second rising edge 302 of the clock signal CLK, the oscillation signal OS jumps to 0 and propagates through the path simulator 102 to the delay detector 103. When the third rising edge 303 of the clock signal CLK arrives, the delay detector 103 activates, initiating the detection of the oscillation signal propagating through the path simulator 102. This process continues, checking at each rising edge after the first rising edge 301 of the clock signal CLK whether the propagation time of the oscillation signal OS in the path simulator 102 is greater than one clock cycle.

[0071] In one embodiment, when the propagation time of the signal in the chip along the critical path is greater than one clock cycle, it indicates that the propagation delay of the critical path is slowed down, and the chip's timing margin is insufficient. Therefore, when the propagation time of the oscillation signal in the path simulator is greater than one clock cycle, it indicates that the propagation time of the signal in the chip along the critical path is greater than one clock cycle, and the chip's timing margin is insufficient. Conversely, when the propagation time of the oscillation signal in the path simulator is less than or equal to one clock cycle, it indicates that the propagation time of the signal in the chip along the critical path is less than or equal to one clock cycle, and the chip's timing margin is sufficient.

[0072] In practical applications, when the delay detector includes a second detection trigger, it can detect whether the propagation time of the signal in the critical path of the chip is greater than one clock cycle, thereby determining whether the timing margin of the chip is sufficient.

[0073] The early warning device is connected to a delay detector and is used to generate a timing warning signal that characterizes timing anomalies when the propagation time does not meet preset conditions.

[0074] In this embodiment, the early warning device 104 is used to determine whether the propagation time meets the preset conditions based on the output of the delay detector 103. Optionally, the early warning device 104 includes a comparator, which is used to collect the output value of the second detection trigger to obtain the detection value, and compare the detection value with the preset conditions, so as to generate a timing early warning signal when the detection value does not meet the preset conditions.

[0075] In one embodiment, the warning device 104 may further include a counter 1042, which counts the clock signal to determine whether the current clock signal has an even or odd period. The preset condition for an even period of the clock signal is 1, where 1 represents a high level, and the preset condition for an odd period is 0, where 0 represents a low level. The comparator 1041 receives the output value of the second detection trigger 1031 during an even period of the clock signal, obtains a detection value, and determines whether the detection value is 1; and receives the output value of the second detection trigger 1031 during an odd period of the clock signal, obtains a detection value, and determines whether the detection value is 0.

[0076] like Figure 2As shown, the input of counter 1042 can be connected to the output of a clock circuit to receive the clock signal CLK. The count value of counter 1042 is initially 0, and it increments by 1 with each rising edge of the received clock signal. One input of comparator 1041 is connected to counter 1042 to determine whether the clock period of the clock signal is even or odd based on the count value of counter 1042. The other input of comparator 1041 is connected to the output of the second detection flip-flop 1031 to receive its output value and obtain the detected value. Figure 3 As shown, when the first rising edge 301 of the clock signal CLK arrives, the first clock cycle (odd-numbered cycle) of the clock signal begins, the value of the oscillation signal is 1, and the count value of the counter 1042 is 1. At this time, since the second detection trigger 1031 cannot receive the oscillation signal, the comparator 1041 can remain inactive. When the second rising edge 302 of the clock signal arrives, the second clock cycle (even-numbered cycle) of the clock signal begins, the value of the oscillation signal jumps to 0, and the count value of the counter 1042 is 2. At this time, the second detection trigger 1031 starts detecting the oscillation signal. The comparator 1041 receives the output value of the second detection trigger 1031, obtains the detection value, and compares the detection value with the count value 2 to determine whether the detection value is 1. If the detection value is 1, it is determined that the second detection trigger 1031 has received the oscillation signal, and the detection value meets the preset condition; otherwise, it is determined that the second detection trigger 1031 has not received the oscillation signal, and the detection value does not meet the preset condition.

[0077] Similarly, when the third rising edge 303 of the clock signal CLK arrives, the third clock cycle (odd cycle) of the clock signal begins, the value of the oscillation signal jumps to 1, and the count value of the counter 1042 is 3. At this time, the second detection trigger 1031 starts detecting the oscillation signal. The comparator 1041 receives the output value of the second detection trigger 1031, obtains the detection value, and compares the detection value with 0 based on the count value 3 to determine whether the detection value is 0. If the detection value is 0, it is determined that the second detection trigger 1031 has received the oscillation signal, and the detection value meets the preset condition; otherwise, it is determined that the second detection trigger 1031 has not received the oscillation signal, and the detection value does not meet the preset condition.

[0078] In this embodiment, the comparator 1041 can directly output a timing warning signal. When the comparator 1041 determines that the detected value does not meet the preset conditions, it can determine that the chip's timing margin is insufficient, and at this time, it can output a timing warning signal, such as a set signal. Conversely, when the detected value meets the preset conditions, it can determine that the chip's timing margin is sufficient, and no timing warning signal is output. The specific circuit structure of the warning device and the specific form of the timing warning signal can be set according to requirements, and this embodiment does not impose any restrictions on them.

[0079] In practical applications, comparators have a simple structure. When an early warning device is composed of a comparator, the structure of the early warning device can be simplified, and the circuit structure of the timing detection circuit can be further simplified.

[0080] In one embodiment, when the chip's timing margin is insufficient, the clock circuit can be controlled to delay the clock signal, for example, by shielding the rising edge of the next clock signal, allowing the signal in the chip sufficient time to propagate in the critical path. Figure 2 As shown, the output of comparator 1041 is connected to clock circuit 105. If comparator 1041 determines that the detected value does not meet the preset condition when the second rising edge of the clock signal arrives, it outputs a timing warning signal. Clock circuit 105 receives the timing warning signal output by comparator 1041 and can then mask the third rising edge 303 in the clock signal CLK to obtain an adjusted clock signal CLK. 1 Clock signal CLK 1 The second clock cycle is extended to allow sufficient time for signals in the chip to propagate in the critical path, thus avoiding timing errors.

[0081] When the warning device outputs a timing warning signal, it can also control the power supply voltage in the chip. Increasing the chip's power supply voltage can shorten the signal propagation time and prevent timing errors. The specific method for controlling the chip based on the timing warning signal can be set according to requirements, and this embodiment does not impose any limitations on it.

[0082] In summary, in this embodiment, the timing detection circuit includes an oscillator, a path simulator, a delay detector, and an early warning unit. The oscillator generates an oscillation signal. The path simulator, connected to the oscillator, receives the oscillation signal and simulates its propagation in the critical path of the chip, transmitting the oscillation signal. The delay detector, connected to the path simulator, detects the oscillation signal transmitted by the path simulator based on a clock signal to determine the propagation time of the oscillation signal in the path simulator. The early warning unit, connected to the delay detector, generates a timing warning signal indicating a timing anomaly when the propagation time does not meet preset conditions. By generating an oscillation signal based on the rising edge of a clock signal and simulating its propagation in the critical path using the path simulator, the propagation time of the oscillation signal in the path simulator can be detected based on the clock signal, quickly determining the propagation time of the oscillation signal in the path simulator. This allows for the determination of the signal propagation time in the critical path within the chip, thus determining whether the chip's timing margin is sufficient.

[0083] Reference Figure 4 The diagram shows a schematic of another timing detection circuit of the present invention. The timing detection circuit may include: an oscillator 101, a path simulator 102, a delay detector 103, an early warning device 104, and a clock delay device 106.

[0084] The clock delay unit 106 is used to perform at least one delay processing on the clock signal to generate at least one delayed signal. The clock delay unit includes at least one clock output terminal, and each clock output terminal outputs a delayed signal. The input terminal of the oscillator is connected to the target clock output terminal among the at least one clock output terminal. The oscillator is used to generate an oscillation signal that jumps with the rising edge of the target delayed signal. The target delayed signal is output by the target clock output terminal.

[0085] Optionally, the clock delay unit 106 includes at least one inverter group connected in sequence, each inverter group including an even number of inverters connected in sequence; the input of the clock delay unit is used to receive a clock signal, and the at least one inverter group is used to sequentially delay the clock signal to generate a delay signal corresponding to each inverter group.

[0086] like Figure 4 As shown, each inverter group in the clock delay unit 106 includes two inverters connected in series. The output of one inverter is connected to the input of another inverter, forming an inverter group. Multiple inverter groups are connected sequentially to form the clock delay unit 106. The output of each inverter group constitutes a clock output of the clock delay unit 106. Figure 5 As shown, Figure 5 for Figure 4The timing diagram of the timing detection circuit shown illustrates that the clock signal CLK is input from the input of the first inverter group. After the first delay of the first inverter group, the first delayed signal CLK1 is output from the output of the first inverter group. After the second delay of the second inverter group, the second delayed signal CLK2 is output from the output of the second inverter group. After the third delay of the third inverter group, the third delayed signal CLK3 is output from the output of the third inverter group. After the fourth delay of the fourth inverter group, the fourth delayed signal CLK4 is output from the output of the fourth inverter group. In each inverter group, each inverter delays the clock signal once and inverts it once. The delay times of two inverters constitute the delay time of one inverter group. Each inverter group contains an even number of inverters, so the delayed signal obtained from each inverter group has the same frequency as the clock signal, and the rising edge of each delayed signal is separated from the rising edge of the clock signal by a certain time difference. The rising edges of two adjacent delayed signals are separated by the delay time of one inverter group. For example, if the delay time of each inverter is t, then the delay time of each inverter group is 2t, and the interval between the rising edges of two adjacent delayed signals is 2t. Figure 5 As shown by the dashed line, if t = 0.05 seconds, that is, the delay time of each inverter is 0.05 seconds, then the delay time of each inverter group is 0.1 seconds, the time difference between the rising edge of the clock signal CLK and the rising edge of the first delay signal CLK1 is 0.1 seconds, and the time difference between the rising edges of two adjacent delay signals is 0.1 seconds.

[0087] Specifically, when the clock delay unit 106 generates at least one delayed signal, the oscillator 101 can generate an oscillation signal that jumps with the rising edge of one of the delayed signals, namely the target delayed signal. Combined with... Figure 4 and Figure 5 The target clock output of the clock delay 106 is the output of the fourth inverter group. The clock input of the oscillator 1011 can be connected to the output of the fourth inverter group, so that the oscillator 101 can generate an oscillation signal OS that jumps with the rising edge of the fourth delay signal CLK4.

[0088] In practical applications, when the oscillator generates an oscillation signal that jumps with the rising edge of the target delay signal, a certain time difference can be created between the oscillation signal and the clock signal, thus adjusting the timing margin for detection. Referring to the example above, if the first rising edge of the oscillation signal OS is 0.1 seconds away from the first rising edge of the clock signal CLK, the oscillation signal OS begins to propagate in the path simulator 0.1 seconds after the arrival of the first rising edge of the clock signal CLK. The second detection trigger starts detecting the oscillation signal when the second rising edge of the clock signal CLK arrives. If the oscillation signal OS is detected, it indicates that the propagation time of the oscillation signal in the path simulator is less than or equal to (T-0.1 seconds); otherwise, it indicates that the propagation time of the oscillation signal in the path simulator is greater than (T-0.1 seconds), and the delay signal changes the timing margin of the time detection circuit.

[0089] In this embodiment, the clock delay unit can delay the clock signal to generate a delayed signal, and the oscillator can generate an oscillation signal that jumps with the delayed signal. When detecting timing margin by detecting the oscillation signal, the clock delay unit can adjust the time difference between the rising edge of the oscillation signal and the rising edge of the clock signal, thereby adjusting the detected timing margin. When the clock delay unit is composed of an inverter group consisting of an even number of inverters connected sequentially, adjusting the number of inverters in the inverter group can adjust the delay time of the inverter group, thereby flexibly adjusting the time difference between the rising edge of the delayed signal and the rising edge of the clock signal. Furthermore, the circuit structure of the inverter group is simple, avoiding an increase in chip size.

[0090] Optionally, the delay detector may include at least one first detection trigger, the clock input of each first detection trigger being connected to a clock output of a clock delayer for acquiring a delay signal; the data input of the first detection trigger is connected to the output of the path simulator so that when the corresponding delay signal is acquired at the clock input of the first detection trigger, the detection of the oscillation signal output by the path simulator is initiated.

[0091] In one embodiment, the delay detector 103 may consist of one or more parallel first detection triggers. For example... Figure 4As shown, the clock input of the first detection trigger 1032 is connected to the output of the first inverter group to receive the delayed signal CLK1; the clock input of the first detection trigger 1033 is connected to the output of the second inverter group to receive the delayed signal CLK2; the clock input of the first detection trigger 1034 is connected to the output of the third inverter group to receive the delayed signal CLK3; and the clock input of the first detection trigger 1035 is connected to the output of the fourth inverter group to receive the delayed signal CLK4. The data inputs of the first detection triggers 1032, 1033, 1034, and 1035 are all connected to the output of the path simulator 102 to receive the oscillation signal OS transmitted by the path simulator 102.

[0092] like Figure 5 As shown, the oscillation signal OS changes once on each rising edge of the delay signal CLK4. The time difference between the first rising edge of the delay signal CLK1 and the first rising edge of the clock signal CLK is 0.1 seconds; the time difference between the first rising edge of the delay signal CLK2 and the first rising edge of the clock signal CLK is 0.2 seconds; the time difference between the first rising edge of the delay signal CLK3 and the first rising edge of the clock signal CLK is 0.3 seconds; and the time difference between the first rising edge of the delay signal CLK4 and the first rising edge of the clock signal CLK is 0.4 seconds. 0.4 seconds after the arrival of the first rising edge of the clock signal CLK, i.e., at the first rising edge of the delay signal CLK4, the value of the oscillation signal changes to 1 and begins to propagate in the path simulator 102. 0.1 seconds after the second rising edge of the clock signal CLK arrives, i.e., at the second rising edge of the delay signal CLK1, the first detection trigger 1032 starts detecting the oscillation signal. If the data output by the first detection trigger 1032 is 1, it means that the oscillation signal OS has propagated to the output of the path simulator 102 before or at the arrival of the second rising edge of the delay signal CLK1, and the propagation time of the oscillation signal OS is less than or equal to (T-0.3 seconds). Conversely, it means that the oscillation signal OS has not propagated to the output of the path simulator 102 before (T-0.3 seconds). At this time, the clock inputs of the first detection triggers 1033, 1034, and 1035 do not receive the corresponding delay signal, and the detection of the oscillation signal is not started.

[0093] Similarly, if the first detection trigger 1033 does not receive the oscillation signal at the second rising edge of the delay signal CLK2, it means that the propagation time of the oscillation signal OS in the path simulator 102 is greater than (T-0.2 seconds). At this time, the clock input terminals of the first detection trigger 1034 and the first detection trigger 1035 do not receive the corresponding delay signal, and the detection of the oscillation signal is not started.

[0094] Similarly, if the first detection trigger 1034 does not receive the oscillation signal at the second rising edge of the delay signal CLK3, it means that the propagation time of the oscillation signal OS in the path simulator 102 is greater than (T-0.1 seconds). At this time, the clock input of the first detection trigger 1035 does not receive the corresponding delay signal, and the detection of the oscillation signal is not started.

[0095] Similarly, if the first detection trigger 1035 does not receive the oscillation signal at the second rising edge of the delay signal CLK4, it means that the propagation time of the oscillation signal OS in the path simulator 102 is greater than T.

[0096] Accordingly, the comparator in the warning device 104 is used to collect and combine the output values ​​of multiple first detection triggers to obtain a detection value, and to compare the detection value with a preset condition, so as to generate a timing warning signal when the detection value does not meet the preset condition. Figure 4 As shown, the input of comparator 1041 is simultaneously connected to the output of each first detection flip-flop to receive and combine the output values ​​of all the first detection flip-flops to obtain the detection value. At this time, the output values ​​of multiple first detection flip-flops are combined into a single binary data value. For example... Figure 5 As shown, DCFF1 is the detection value 507 corresponding to the data output by the path simulator 102 when the timing margin is sufficient, and DCFF2 is the detection value 508 corresponding to the data output by the path simulator 102 when the timing margin is insufficient. Detection values ​​507 and 508 are the output values ​​of multiple first detection triggers collected by the delay detector 103 after the second rising edge of the delay signal CLK1 arrives. From left to right, detection values ​​507 and 508 are the output values ​​of first detection trigger 1032, first detection trigger 1033, first detection trigger 1034, and first detection trigger 1035, respectively.

[0097] In one embodiment, the timing margin of the chip can be determined to be insufficient if the propagation time of the signal in the critical path is greater than (T-0.3 seconds), and sufficient if it is less than 0.3 seconds. That is, when the oscillation signal OS propagates to the output of the path simulator 102 before or at the arrival of the second rising edge of the delay signal CLK1, and the output data of the first detection trigger 1032 is 1, the timing margin of the chip is sufficient. At this time, the preset condition can be set to binary number "1111" for even-numbered periods of the clock signal and binary number "0000" for odd-numbered periods. As can be seen from the detection value 508, the oscillation signal OS has not propagated to the output of the path simulator 102 before the arrival of the second rising edge of the delay signal CLK1, and the detection value "0111" does not meet the preset condition "1111", indicating insufficient timing margin of the chip. Correspondingly, the warning device 104 can output a timing warning signal, and the clock circuit can shield the third rising edge of the clock signal to obtain the adjusted clock signal CLK. 1 Similarly, if the detected value is any of "0011", "0001", or "0000", it indicates that the timing margin does not meet the preset conditions. Conversely, when the data output by multiple first detection triggers is the detected value 507, it means that the propagation time of the oscillation signal in the path simulator is less than (T-0.3 seconds), and the timing margin of the chip is sufficient.

[0098] In this embodiment, the delay detector can detect the oscillation signal at four time points: (T-0.3 seconds), (T-0.2 seconds), (T-0.1 seconds), and T seconds after the rising edge of the clock signal. When the delay detector includes multiple first detection triggers, the clock delayer can delay to obtain multiple delayed signals, allowing detection of the oscillation signal at multiple time points, thus enabling the detection of different timing margins. In practical applications, the number of first detection triggers and inverter groups can be set according to the number of time points. For example, if it is necessary to detect the oscillation signal at the four time points mentioned above, four first detection triggers can be set, and a corresponding inverter group can be set for each first detection trigger; if it is necessary to reduce the number of time points, the number of first detection triggers and inverter groups can be reduced; if it is necessary to increase the number of time points, the number of first detection triggers and inverter groups can be increased.

[0099] In practical applications, setting multiple first detection triggers in the delay detector allows for the detection of oscillation signals at multiple time points, thereby enabling the detection of timing margins of different lengths. Furthermore, by selecting the number of first detection triggers, the timing margin to be detected can be chosen.

[0100] Optionally, the warning device is also used to receive a delay setting signal 107 and determine preset conditions based on the delay setting signal 107. The delay setting signal can be sent to the warning device by the CPU or by the user through other electronic devices. Figure 4 As shown, one input of comparator 1041 can be connected to the CPU and receive the delay setting signal 107 sent by the CPU.

[0101] In one embodiment, the delay setting signal 107 can be a binary mask, such as... Figure 5 As shown, if the propagation time of the signal in the critical path of the chip is greater than (T-0.2 seconds), it is determined that the timing margin of the chip is insufficient. In this case, it is only necessary to detect the oscillation signal when the second rising edge of the delay signal CLK2 arrives, that is, to detect the oscillation signal through the first detection trigger 1033. The first detection trigger 1032 has no practical effect on the detection of the oscillation signal. At this time, it can be set to the binary number "11" for even-numbered periods of the clock signal and the binary number "00" for odd-numbered periods of the clock signal. The first and second bits of the detection value (i.e., ...) can be masked. Figure 5 The first and second bits (shaded in detection values ​​507 and 508) are compared only with the third and fourth bits and the preset conditions. That is, only the detection value obtained by combining the output values ​​of the first detection trigger 1034 and the first detection trigger 1035 is compared with the preset conditions "11" and "00". The delay setting signal can also be other forms of signal. This embodiment does not limit the specific form of the delay setting signal.

[0102] In practical applications, the delay setting signal can be received by the early warning device, and the preset conditions can be determined based on the delay setting signal. This allows for convenient adjustment of the preset conditions, thereby enabling flexible setting of the detection length of the timing margin.

[0103] In one embodiment, the delay detector 103 may simultaneously include a second detection trigger and multiple first detection triggers. Correspondingly, the comparator in the warning device 104 is used to acquire and combine the output values ​​of the first and second detection triggers to obtain a detection value; and compare the detection value with a preset condition to generate a timing warning signal when the detection value does not meet the preset condition. Figure 6 As shown, Figure 6A schematic diagram of another timing detection circuit of the present invention is shown. Multiple first and second detection flip-flops are arranged in parallel. In this case, comparator 1041 can simultaneously acquire the output values ​​of multiple first and second detection flip-flops and combine them to obtain the detected value. When the delay detector includes both first and second detection flip-flops, the delay detector can detect the oscillation signal at the rising edge of the clock signal or at the rising edge of the delay signal, thereby enabling timing margin detection at multiple time points and allowing users to flexibly set the chip's timing margin.

[0104] Reference Figure 7 The diagram illustrates a flowchart of a timing detection method according to the present invention. The timing detection method is applied to a chip capable of generating clock signals and includes:

[0105] Step 701: Generate an oscillation signal.

[0106] The oscillation signal is based on the rising edge of the clock signal.

[0107] In this embodiment, the timing detection method can be applied to a chip with a clock signal. The chip can generate an oscillation signal based on the rising edge of the clock signal. When the oscillation signal changes based on the rising edge of the clock signal, the propagation process of the oscillation signal can be detected based on the rising edge of the clock signal to determine the propagation time of the oscillation signal.

[0108] Based on the examples above, the oscillation signal can change when the rising edge of the clock signal arrives, or it can change a certain time after the rising edge of the clock signal arrives.

[0109] Step 702: Simulate the propagation process of the oscillation signal in the critical path of the chip using a path simulator to transmit the oscillation signal.

[0110] In this embodiment, the path simulator can be a replica circuit of the critical path in the chip. The critical path is the logic path with the longest delay from input to output in the chip. The path simulator is used to simulate the critical path in the chip. Therefore, the propagation process of the oscillating signal in the path simulator is equivalent to the propagation process of the signal in the critical path in the chip, and the propagation time of the oscillating signal in the path simulator is the same as the propagation time of the signal in the critical path in the chip.

[0111] Step 703: Based on the clock signal, detect the oscillation signal during the propagation process to determine the propagation time of the oscillation signal in the path simulator.

[0112] In this embodiment, the oscillation signal propagating in the path simulator can be detected based on the rising edge of the clock signal to determine the propagation time of the oscillation signal in the path simulator, that is, the propagation time of the signal in the chip in the critical path.

[0113] Step 704: When the propagation time does not meet the preset conditions, generate a timing warning signal that represents the timing anomaly.

[0114] In this embodiment, preset conditions can be set in advance. When the propagation time is greater than the preset conditions, it is determined that the timing margin of the chip is insufficient and a timing warning signal is generated; otherwise, a timing warning signal is not generated.

[0115] In this embodiment, an oscillation signal based on the rising edge transition of a clock signal is generated. The propagation process of this oscillation signal along the critical path of the chip is simulated using a path simulator. Based on the clock signal, the oscillation signal during propagation is detected to determine its propagation time in the path simulator. If the propagation time does not meet preset conditions, a timing warning signal indicating a timing anomaly is generated. Generating an oscillation signal based on the rising edge transition of a clock signal and simulating its propagation along the critical path using a path simulator allows for the detection of the oscillation signal's propagation time based on the clock signal, quickly determining the propagation time of the oscillation signal in the path simulator. This enables the determination of the signal propagation time within the chip along the critical path, thus determining whether the chip's timing margin is sufficient.

[0116] Optionally, before generating the oscillation signal, the method may further include:

[0117] Perform at least one delay processing on the clock signal to generate at least one delayed signal.

[0118] Accordingly, step 701 can be achieved by generating an oscillating signal that jumps with the rising edge of the target delay signal.

[0119] In this embodiment, the clock signal can be delayed to generate at least one delayed signal. Based on a target delayed signal among the at least one delayed signal, an oscillation signal that jumps with the rising edge of the target delayed signal can be generated. The rising edge of the delayed signal is spaced apart from the rising edge of the clock signal by a certain time difference. The oscillation signal generated based on the delayed signal can conditionally detect the length of the timing margin.

[0120] Alternatively, step 703 can be implemented in the following way:

[0121] Each time a delayed signal is acquired, the oscillation signal is detected to determine the propagation time of the oscillation signal in the path simulator.

[0122] In this embodiment, multiple delayed signals can be generated, and the oscillation signal is detected upon receiving each delayed signal to determine the propagation time of the oscillation signal in the path simulator. Detecting the oscillation signal upon receiving each delayed signal allows for detection at multiple time points, enabling users to flexibly set the timing margin for detection.

[0123] Optionally, the method may further include:

[0124] When the clock signal is acquired, the oscillation signal is detected to determine the propagation time of the oscillation signal in the path simulator.

[0125] In this embodiment, the oscillation signal can also be detected based on the clock signal to determine the propagation time of the oscillation signal, which facilitates the adjustment of the timing margin.

[0126] Optionally, the method may further include:

[0127] Receive the delay setting signal and determine the preset conditions based on the delay setting signal.

[0128] In this embodiment, the timing margin of the chip can be adjusted by setting the preset conditions based on the delay setting signal, which facilitates the adjustment of the timing margin of the detection.

[0129] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0130] Figure 8 This is a structural block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0131] Reference Figure 8 The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0132] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0133] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0134] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0135] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0136] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured not to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. Received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0137] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0138] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0139] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0140] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0141] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0142] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0143] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0144] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0146] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0147] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0148] The timing detection circuit, timing detection method, and electronic device provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A timing detection circuit, characterized in that, Applications include chips that can generate clock signals, including: An oscillator for generating an oscillating signal based on the rising edge of the clock signal; A path simulator, connected to the oscillator, is used to receive the oscillation signal and simulate the propagation process of the oscillation signal in the critical path of the chip, thereby transmitting the oscillation signal. A delay detector, connected to the path simulator, is used to detect the oscillation signal transmitted by the path simulator based on the clock signal, so as to determine the propagation time of the oscillation signal in the path simulator; An early warning device, connected to the delay detector, is used to generate a timing warning signal characterizing a timing anomaly when the propagation time does not meet a preset condition; the early warning device is also used to receive a delay setting signal and determine the preset condition based on the delay setting signal.

2. The timing detection circuit according to claim 1, characterized in that, Also includes: A clock delay unit, wherein the clock delay unit is used to perform at least one delay processing on the clock signal to generate at least one delayed signal; The clock delay device includes at least one clock output terminal, and each clock output terminal outputs a delay signal respectively. The input terminal of the oscillator is connected to the target clock output terminal of the at least one clock output terminal; The oscillator is used to generate the oscillation signal that jumps with the rising edge of the target delay signal; The target delay signal is output from the target clock output terminal.

3. The timing detection circuit according to claim 2, characterized in that, The delay detector includes at least one first detection trigger, and the clock input terminal of each first detection trigger is connected to a clock output terminal of the clock delayer, respectively, for acquiring a delay signal; The data input terminal of the first detection trigger is connected to the output terminal of the path simulator so that when the corresponding delay signal is acquired at the clock input terminal of the first detection trigger, the detection of the oscillation signal output by the path simulator is initiated.

4. The timing detection circuit according to claim 3, characterized in that, The delay detector further includes a second detection trigger corresponding to the clock signal. The data input terminal of the second detection trigger is connected to the output terminal of the path simulator so as to start the detection of the oscillation signal output by the path simulator when the clock signal is received at the clock input terminal of the second detection trigger.

5. The timing detection circuit according to claim 4, characterized in that, The warning device includes a comparator; The comparator is used to acquire and combine the output values ​​of the first detection trigger to obtain a detection value; or, to acquire and combine the output values ​​of the first detection trigger and the second detection trigger to obtain a detection value. The comparator is also used to generate the timing warning signal when the detected value does not meet the preset condition.

6. The timing detection circuit according to claim 2, characterized in that, The clock delay includes at least one group of inverters connected in sequence, and each group of inverters includes an even number of inverters connected in sequence. The input terminal of the clock delayer is used to receive the clock signal, and the at least one inverter group is used to sequentially delay the clock signal to generate a delay signal corresponding to each inverter group.

7. The timing detection circuit according to any one of claims 1-6, characterized in that, The oscillator includes: an oscillator trigger, an inverter, and an AND gate circuit; The data input terminal of the oscillation trigger is connected to the output terminal of the AND gate circuit, and the clock input terminal of the oscillation trigger is used to acquire the clock signal; the output terminal of the oscillation trigger is connected to the input terminal of the inverter and the input terminal of the path simulator respectively. One input terminal of the AND gate circuit is connected to the output terminal of the inverter, and is used to cause the oscillator to generate the oscillation signal when the other input terminal of the AND gate circuit receives a start signal.

8. A timing detection method, characterized in that, Applications include chips that can generate clock signals, including: An oscillation signal is generated, the oscillation signal being based on the rising edge of the clock signal; The oscillation signal is transmitted by simulating the propagation process of the oscillation signal in the critical path of the chip using a path simulator. Based on the clock signal, the oscillation signal during the propagation process is detected to determine the propagation time of the oscillation signal in the path simulator; When the propagation time does not meet the preset conditions, a timing warning signal representing a timing anomaly is generated; Receive a delay setting signal and determine the preset condition based on the delay setting signal.

9. The method according to claim 8, characterized in that, Before generating the oscillation signal, the following is also included: The clock signal is subjected to at least one delay processing to generate at least one delayed signal; The generation of the oscillation signal includes: The oscillating signal is generated that changes with the rising edge of the target delay signal.

10. The method according to claim 9, characterized in that, The step of detecting the oscillation signal during propagation based on the clock signal to determine the propagation time of the oscillation signal in the path simulator includes: When each of the delay signals is acquired, the oscillation signal is detected to determine the propagation time of the oscillation signal in the path simulator.

11. The method according to claim 10, characterized in that, Also includes: When the clock signal is acquired, the oscillation signal is detected to determine the propagation time of the oscillation signal in the path simulator.

12. An electronic device, characterized in that, Includes the timing detection circuit as described in any one of claims 1 to 7.

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