A test method, device and equipment for accessing a table entry and a storage medium

Abstract

Embodiments of the present application provide a table entry access test method, device, equipment and storage medium, the method comprises: obtaining the table entry access mode of target table entry, the table entry access mode at least includes direct table entry mode and indirect table entry mode, the direct table entry mode is accessed through table entry address, and the indirect table entry mode is accessed through register to table entry;Set address access mode, and construct the test flow of the table entry access mode according to the address access mode, the address access mode at least includes: the sole heat access mode, the sole heat access mode tests each sole heat address, minimum address and maximum address of target table entry;According to the table entry access mode and the test flow, target table entry is tested.The technical scheme of the present application covers more CPU table entry access scenarios, and the test speed is fast, improves the correctness verification effect of direct table entry and indirect table entry in EDA simulation.

Description

Technical Field

[0001] This invention relates to the field of testing technology for chip EDA, and more particularly to a test method, apparatus, device, and storage medium for table access. Background Technology

[0002] With the development of chip EDA simulation testing technology, current verification methods for table entries mainly focus on verifying direct table entries, and these methods are relatively simple, primarily using simple full-address-space CPU read / write verification. However, in addition to direct table entries, table entries also include indirect table entries, but existing technologies lack verification methods for indirect table entries.

[0003] Therefore, there is an urgent need to provide a technical solution to address the aforementioned technical problems. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, apparatus, device, and storage medium for testing table entry access. The method includes: obtaining a table entry access mode of a target table entry, wherein the table entry access mode includes at least a direct table entry mode and an indirect table entry mode, wherein the direct table entry mode accesses the table entry via a table entry address, and the indirect table entry mode accesses the table entry via a register; setting an address access mode and constructing a test flow for the table entry access mode based on the address access mode, wherein the address access mode includes at least a one-hot access mode, wherein the one-hot access mode tests each one-hot address, minimum address, and maximum address of the target table entry; and testing the target table entry according to the table entry access mode and the test flow. The technical solution of the present invention covers more CPU table entry access scenarios and has a fast testing speed, improving the correctness verification effect of direct and indirect table entries in EDA simulation.

[0005] In a first aspect, embodiments of the present invention provide a method for testing table entry access, comprising: obtaining a table entry access mode of a target table entry, wherein the table entry access mode includes at least a direct table entry mode and an indirect table entry mode, wherein the direct table entry mode is accessed through a table entry address, and the indirect table entry mode is accessed through a register; setting an address access mode, and constructing a test process for the table entry access mode according to the address access mode, wherein the address access mode includes at least a one-hot access mode, wherein the one-hot access mode tests each one-hot address, the minimum address, and the maximum address of the target table entry, wherein one corresponding bit in each one-hot address is 1, and the other bits are 0; and testing the target table entry according to the table entry access mode and the test process.

[0006] As described above, by testing the one-hot access mode addresses of direct and indirect table entries, compared to the traditional method of testing direct table entries only through the full space table entry addresses, this invention covers more CPU table entry access scenarios, and the testing speed is faster, thus improving the correctness verification effect of direct and indirect table entries in EDA simulation.

[0007] In one possible implementation of the first aspect, it further includes: setting a write data sample, the write data sample including one of the following: all 0s, all 5s, all as, and all fs; constructing a test process for the table entry access mode based on the address access mode, including: constructing the test process based on the address access mode and the write data sample.

[0008] As shown above, by using write data samples of all 0s, all 5s, all as, and all fs, not only are the scenarios of 0s and 1s for each bit of the target table entry covered, but also the scenarios of mutually exclusive and non-mutually exclusive adjacent bits are covered.

[0009] In one possible implementation of the first aspect, the written data sample further includes a random value.

[0010] Based on the above, using write data samples with all 0s, all 5s, all as, and all fs, we further simulated the actual scenario by using write data samples with random values.

[0011] In one possible implementation of the first aspect, it further includes: setting an address order mode, the address order mode including at least one of the following modes: ascending order mode, descending order mode, and random order mode; constructing a test process for the table entry access mode based on the address access mode, including: constructing the test process based on the address access mode and the address order mode, the test process covering at least the ascending order mode, descending order mode, and random order mode.

[0012] As shown above, the influence of adjacent addresses can be detected through forward and reverse order modes. Based on the forward and reverse order modes, the random order mode was used to more realistically simulate and test the actual scenario.

[0013] In one possible implementation of the first aspect, when the access mode is the indirect entry mode, constructing a test process for the entry access mode based on the address access mode includes: constructing the test process based on the address access mode, a written data sample, and a write mask sample, wherein the write mask sample includes at least one of the following: all 5s, all a's, and all f's. In some embodiments, the test process is constructed based on the address access mode, the current value of the entry, the written data sample, and the write mask sample.

[0014] As shown above, by using write mask samples with all 5s, all as, and all fs, we can cover tests for various write mask scenarios.

[0015] In one possible implementation of the first aspect, the write mask sample further includes a random value.

[0016] Based on the above, the actual scenario was simulated and tested more realistically using write mask samples with all 5s, all as, and all fs, and then with write mask samples with random values.

[0017] In one possible implementation of the first aspect, the address access mode further includes a full-space address mode, and the test process further includes: first, randomly writing or reading back a number of full-space addresses of the target entry, wherein the written value is a random value; second, randomly writing or reading back addresses from the addresses extracted in the first extraction and from the addresses not extracted in the first extraction, wherein the written value is a random value; repeating the first and second operations a second set number of times; and comparing the readbacks of all full-space addresses of the target entry.

[0018] As described above, by randomly selecting several addresses across the entire memory space for random writing or reading back and writing random values, the test coverage of real-world scenarios can be further improved.

[0019] In one possible implementation of the first aspect, the address access mode further includes a custom address set mode for testing several custom addresses.

[0020] As shown above, testing custom addresses using a custom address set mode improves the efficiency of testing for special purposes such as troubleshooting or testing high-priority addresses.

[0021] Secondly, embodiments of the present invention provide a test apparatus for table entry access, comprising: a pattern acquisition module, configured to acquire a table entry access pattern of a target table entry, wherein the table entry access pattern includes at least a direct table entry pattern and an indirect table entry pattern, wherein the direct table entry pattern is accessed through a table entry address, and the indirect table entry pattern is accessed through a register; a process construction module, configured to set an address access pattern and construct a test process for the table entry access pattern according to the address access pattern, wherein the address access pattern includes at least a one-hot access pattern, wherein the one-hot access pattern tests each one-hot address, the minimum address, and the maximum address of the target table entry, wherein one corresponding bit in each one-hot address is 1, and the other bits are 0; and a table entry testing module, configured to test the target table entry according to the table entry access pattern and the test process.

[0022] As described above, by testing the one-hot access mode addresses of direct and indirect table entries, compared to the traditional method of testing direct table entries only through the full space table entry addresses, this invention covers more CPU table entry access scenarios, and the testing speed is faster, thus improving the correctness verification effect of direct and indirect table entries in EDA simulation.

[0023] In one possible implementation of the second aspect, the process construction module is further configured to set a write data sample, the write data sample including one of the following: all 0s, all 5s, all as, and all fs; and to construct a test process for the table entry access mode based on the address access mode, including: constructing the test process based on the address access mode and the write data sample.

[0024] As shown above, by using write data samples of all 0s, all 5s, all as, and all fs, not only are the scenarios of 0s and 1s for each bit of the target table entry covered, but also the scenarios of mutually exclusive and non-mutually exclusive adjacent bits are covered.

[0025] In one possible implementation of the second aspect, the written data sample further includes a random value.

[0026] Based on the above, using write data samples with all 0s, all 5s, all as, and all fs, we further simulated the actual scenario by using write data samples with random values.

[0027] In one possible implementation of the second aspect, the process construction module is further configured to set an address order mode, the address order mode including at least one of the following modes: ascending order mode, descending order mode, and random order mode; and is further configured to construct a test process for the table entry access mode based on the address access mode, including: constructing the test process based on the address access mode and the address order mode, the test process covering at least the ascending order mode, descending order mode, and random order mode.

[0028] As shown above, the influence of adjacent addresses can be detected through forward and reverse order modes. Based on the forward and reverse order modes, the random order mode was used to more realistically simulate and test the actual scenario.

[0029] In one possible implementation of the second aspect, when the access mode is the indirect entry mode, the process construction module is further configured to construct the test process based on the address access mode, the written data sample, and the write mask sample, wherein the write mask sample includes at least one of the following: all 5s, all a's, and all f's. In some embodiments, the process construction module is further configured to construct the test process based on the address access mode, the current value of the entry, the written data sample, and the write mask sample.

[0030] As shown above, by using write mask samples with all 5s, all as, and all fs, we can cover tests for various write mask scenarios.

[0031] In one possible implementation of the second aspect, the write mask sample further includes a random value.

[0032] Based on the above, the actual scenario was simulated and tested more realistically using write mask samples with all 5s, all as, and all fs, and then with write mask samples with random values.

[0033] In one possible implementation of the second aspect, the address access mode further includes one of the following: a full-space address mode, wherein the test process further includes: first, randomly writing or reading back a number of full-space addresses of the target entry, wherein the written value is a random value; second, randomly writing or reading back addresses from the addresses extracted in the first extraction and from the addresses not extracted in the first extraction, wherein the written value is a random value; repeating the first and second operations a second set number of times; and comparing the readbacks of all full-space addresses of the target entry.

[0034] As described above, by randomly selecting several addresses across the entire memory space for random writing or reading back and writing random values, the test coverage of real-world scenarios can be further improved.

[0035] In one possible implementation of the second aspect, the address access mode further includes a custom address set mode for testing several custom addresses.

[0036] As shown above, testing custom addresses using a custom address set mode improves the efficiency of testing for special purposes such as troubleshooting or testing high-priority addresses.

[0037] Thirdly, embodiments of the present invention provide a computing device, including:

[0038] bus;

[0039] A communication interface, which is connected to the bus;

[0040] At least one processor connected to the bus; and

[0041] At least one memory is connected to the bus and stores program instructions that, when executed by the at least one processor, cause the at least one processor to perform any of the embodiments of the first aspect of the present invention.

[0042] Fourthly, embodiments of the present invention provide a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform any of the embodiments described in the first aspect of the application. Attached Figure Description

[0043] Figure 1 This is a flowchart illustrating a test method for table access according to the present invention, in embodiment one.

[0044] Figure 2 This is a schematic diagram of the test process for the direct entry mode in Embodiment 2 of the test method for table access according to the present invention.

[0045] Figure 3 This is a schematic diagram of the test process for the indirect entry pattern in Embodiment 2 of the test method for table access according to the present invention.

[0046] Figure 4 This is a schematic diagram of a test device for table access according to a first embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of a second embodiment of the test device for table access according to the present invention;

[0048] Figure 6 A schematic diagram of the structure of a computing device according to various embodiments of the present invention. Detailed Implementation

[0049] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] In the following description, the terms “first, second, third, etc.” or module A, module B, module C, etc. are used only to distinguish similar objects or different embodiments and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0051] In the following description, the labels of the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this way. The order of the steps can be interchanged or executed simultaneously if permitted.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0053] This invention provides a method, apparatus, device, and storage medium for testing table entry access. The method includes: obtaining the table entry access mode of a target table entry, wherein the table entry access mode includes at least a direct table entry mode and an indirect table entry mode, wherein the direct table entry mode accesses the table entry via a table entry address, and the indirect table entry mode accesses the table entry via a register; setting an address access mode and constructing a test flow for the table entry access mode based on the address access mode, wherein the address access mode includes at least a one-hot access mode, wherein the one-hot access mode tests each one-hot address, minimum address, and maximum address of the target table entry; and testing the target table entry according to the table entry access mode and the test flow. The technical solution of this invention covers more CPU table entry access scenarios and has a fast testing speed, improving the correctness verification effect of direct and indirect table entries in EDA (Electronic Design Automation) simulation.

[0054] The following is based on Figures 1 to 3 This paper introduces various embodiments of a test method for table entry access according to the present invention. First, based on... Figure 1 Example 1 of a test method for table entry access is introduced.

[0055] In an embodiment of a test method for table entry access, the table entry access mode of the target table entry is obtained. The table entry access mode includes at least a direct table entry mode and an indirect table entry mode. The direct table entry mode accesses the table entry via its address, and the indirect table entry mode accesses the table entry via a register. An address access mode is set, and a test flow for the table entry access mode is constructed based on the address access mode. The address access mode includes at least a one-hot access mode, which tests each one-hot address, minimum address, and maximum address of the target table entry. The target table entry is then tested according to the table entry access mode and the test flow. This invention covers more CPU table entry access scenarios and offers faster testing speeds, improving the correctness verification effect of direct and indirect table entries in EDA simulation.

[0056] Figure 1 A flow diagram of a test embodiment of table entry access is shown, including steps S110 to S130.

[0057] S110: Obtain the table access mode of the target table entry.

[0058] The target entry is a table entry in the CPU's EDA code. Each entry includes several data items, and each data item has an address.

[0059] The table entry access modes include at least direct table entry mode and indirect table entry mode. Direct table entry mode accesses each address in the target table entry through the table entry address, while indirect table entry mode accesses each address in the target table entry through registers. Registers store table entry addresses and write data, etc. Table entries accessed through direct table entry mode are direct table entries, and table entries accessed through indirect table entry mode are indirect table entries.

[0060] S120: Set the address access mode and construct a test process for the table entry access mode based on the address access mode.

[0061] The address access mode (one-hot mode) includes a single-hot access mode. The single-hot access mode tests each single-hot address, minimum address, and maximum address of the target entry. In each single-hot address, one corresponding bit is set to 1, and the other bits are 0. For example, if the entry address is represented by 8 bits, it has 8 single-hot addresses. In the nth single-hot address, the (n-1)th bit is 1, and the other bits are 0. The single-hot access mode covers each single-hot address, minimum address, and maximum address of the target entry, thus reducing testing time while traversing every address bit of the target entry.

[0062] In some embodiments, the address access mode further includes a full-space address mode, and the test process further includes: First, randomly writing or reading back a number of full-space addresses of the target table entry, wherein the written value is a random value; Second, randomly writing or reading back addresses from the addresses extracted in the first extraction and from the addresses not extracted in the first extraction, wherein the written value is a random value; Repeating the first and second operations a second set number of times; Comparing the readback of all full-space addresses of the target table entry.

[0063] For example, the random read or write operation involves writing random values ​​to 50% of the addresses and reading back to 50% of the addresses, with a first set ratio of 50% and a second set number of 100 times.

[0064] In some embodiments, the address access mode may also include a custom address set mode. For example, when troubleshooting CPU EDA code, a custom address set mode is set to test the addresses with problems in the target table entries, resulting in higher testing efficiency.

[0065] In some embodiments, write data samples are also provided. A test process for constructing corresponding table entry access patterns based on address access patterns and write data samples is constructed. The write data samples are represented in decimal and include at least one of the following: all 0s, all 5s, all a's, and all f's. Write data samples can be combined with address access patterns. The write data samples of all 0s, all 5s, all a's, and all f's not only cover the scenario of 0s and 1s for each bit of the target table entry, but also cover the scenario of adjacent bits being mutually exclusive and not mutually exclusive.

[0066] In some embodiments, an address order mode is also set, and a test process for the corresponding table entry access mode is constructed based on the address access mode and the address order mode. The address order mode includes at least one of the following modes: ascending order mode, descending order mode, and out-of-order mode. The test process covers at least the ascending order mode, descending order mode, and out-of-order mode. The address order mode can be combined with written data samples and / or address access modes. Among them, the ascending order mode and descending order mode can detect the influence of adjacent addresses, and the out-of-order mode can detect the influence between out-of-order addresses.

[0067] In some embodiments, when using the out-of-order modulus, an address is first randomly selected from the addresses to be tested in the target entry for testing, and then another address is randomly selected from the remaining addresses to be tested for testing, and so on until all addresses to be tested have been tested. This out-of-order modulus can avoid testing duplicate addresses.

[0068] In some embodiments, when the access mode of the target table entry is direct table entry mode, a test process is constructed based on the address access mode, the written data sample, and the address order mode.

[0069] In some embodiments, when the access mode of the target entry is an indirect entry mode, a test procedure for constructing the corresponding entry access mode is performed based on the address access mode and a write mask sample. The write mask sample is hexadecimal and includes at least one of the following: all 5s, all a's, and all f's. The write mask sample can be combined with the address sequence mode and / or the write data sample and / or the address access mode. In some embodiments, the write mask sample also includes a random value.

[0070] The write mask is used to update the fields of the table entries that you want to update. For example, when a bit of the write mask is 1, the corresponding bit of the table entry is written; when a bit of the write mask is 0, the corresponding bit of the table entry is not written.

[0071] In some embodiments, the registers in the indirect entry mode include an address register, a data register, a command register, a write mask register, and a ready register (shot register). The address register stores the address of the target entry, the data register stores the write or read-back data of the target entry, the command register stores the write or write command, the write mask register stores the write mask, and the ready register stores whether access has been initiated, i.e., whether a write or read-back has been initiated. The ready register is written to after the corresponding values ​​are written to the address register, data register, command register, and write mask register, respectively, to initiate the corresponding write or read-back.

[0072] In some embodiments, when any of the address register, data register, command register, write mask register, or ready register occupies less than 32 bits, it can share a 32-bit register with one or more other registers. In this case, the address register, data register, command register, write mask register, and ready register can be represented by address register field, data register field, command register field, write mask register field, or ready register field.

[0073] In some embodiments, when the access mode of the target table entry is the indirect table entry mode, the test process is constructed based on the address access mode, the written data sample, the write mask sample, and the address order mode.

[0074] S130: Test the target table entries according to the table entry access mode and build test process.

[0075] In summary, in the first embodiment of the multicast message forwarding method, the L2 layer multicast member table has fewer entries and each entry has simple information, making it easy to maintain. The L2 layer multicast member table and the multicast leaf table are stored separately, resulting in high query efficiency for the L2 layer multicast member table. This not only saves hardware resources but also improves the efficiency of L2 layer multicast.

[0076] In summary, Embodiment 1 of the test method for table entry access covers table entry access scenarios in both direct and indirect table entry modes, and the test covers all one-hot addresses, minimum addresses, and maximum addresses of the target table entry. The technical solution of this invention covers more CPU table entry access scenarios, has a fast testing speed, and improves the correctness verification effect for direct and indirect table entries in EDA simulation.

[0077] The second embodiment of the test method for table entry access inherits the method of the first embodiment of the multicast packet forwarding method and has all the advantages of the first embodiment of the multicast packet forwarding method. For table entries in the direct table entry mode, the test process for the direct table entry mode is constructed based on the combination of address access mode, written data sample, and address order mode; for table entries in the indirect table entry mode, the test process for the indirect table entry mode is constructed based on the combination of address access mode, written data sample, address order mode, and write mask sample.

[0078] Figure 1 The following is a flowchart of a test method embodiment two for table entry access, with enhancements to the method for constructing the test flow in step S120. First, an address access mode, a write data sample, and an address order mode are set. For the indirect table entry mode, a write mask sample is also set. Based on the combination of the above settings, test flows for the direct table entry mode and the indirect table entry mode are constructed.

[0079] For the indirect entry mode, the constructed test process must at least cover the testing of the combination of the current value of each bit of the entry, the value of each bit of the written sample, and the value of each bit of the write mask.

[0080] Figure 2 The following is an embodiment of a test method for table entry access, which includes a test flow for the direct table entry mode, comprising steps S210 to S295.

[0081] S210: Write 0xffff…f (all f) sequentially to each access address in the address access order, and read back and compare the correctness in sequence.

[0082] This step can be understood as performing an all-1 test on each bit of the target entry. In this embodiment, the access address for this step and the following steps is the address of the target entry in one-hot mode.

[0083] S220: Write 0x5555…5 (all 5s) sequentially to each access address in the address access order, and read back and compare the correctness in turn.

[0084] This step involves testing the writing of 1 when the even bit of the target entry is 1 and the writing of 0 when the odd bit is 1, while preventing the interleaving of adjacent bits during the writing process.

[0085] S230: Write 0xaaaa…a (all a) sequentially to each access address in the address access order, and then read back and compare the correctness.

[0086] This step involves testing the writing of 0 when the even bits of the target entry are 1 and the writing of 1 when the odd bits are 0, while preventing the interleaving of adjacent bits during the writing process.

[0087] S240: Write 0x5555…5 sequentially to each access address in the address access order, and read back and compare the correctness in sequence.

[0088] This step involves testing the writing of 1 when the even bit of the target entry is 0 and the writing of 0 when the odd bit is 1. The even and odd bits are flipped simultaneously, and the writing process prevents adjacent bits from interleaving.

[0089] S250: Write 0x0000…0 (all 0s) sequentially to each access address in the address access order, and read back and compare the correctness in sequence.

[0090] This step involves testing writing 0 when the even bits of the target entry are 1 and writing 0 when the odd bits are 0.

[0091] The above steps S210 to S250 cover all the scenarios shown in Table 1.

[0092] Table 1: Direct Entry Bit Test Scenario

[0093] Current bit value Write bits Bits after writing 0 0 0 0 1 1 1 0 0 1 1 1

[0094] S260: Write random values ​​sequentially to each access address in reverse order of address access, and read them back and compare their correctness.

[0095] S270: Write random values ​​sequentially to each access address in the address access order, and read them back and compare their correctness.

[0096] S280: Write random values ​​sequentially to each access address according to the address access disorder, and read them back and compare their correctness.

[0097] As described above, steps S260 to S280 cover the scenarios of random write tests under address access in ascending, descending, and out-of-order conditions.

[0098] S290: Randomly select any access address and perform 50% reads or 50% writes. Randomly select any access address again and perform 50% reads or 50% writes. The 50% of addresses are the same as the addresses selected in the first operation. Repeat the above two steps 100 times.

[0099] Of these, 50% of the writes are random values.

[0100] S295: Read back the table entries in ascending order of address access and check for correctness by comparing the full address space.

[0101] As described above, steps S290 to S295 cover the scenario of randomly selecting access addresses and writing random values ​​multiple times.

[0102] Figure 3An embodiment of a test method for table access is shown, which includes a test flow for indirect table entry patterns, comprising steps S310 to S360.

[0103] S310: Verify the combination of the current value, written value, and write mask value of each bit in the target table entry according to the address access order.

[0104] This step includes the following sub-steps.

[0105] (1) Write operations are performed on each access address in the order of address access with a write mask of 0xffff…f and a write data of 0xaaaa…a, and the correctness is read back in sequence.

[0106] In this embodiment, the access address in this step and the following steps is the address of the target table entry in one-hot mode. Before this step is executed, the value of the data corresponding to each access address of the target table entry is 0x0000…0, and after execution, it is 0xaaaa…a. If the value of the data corresponding to each access address of the target table entry is not 0x0000…0 before this step is executed, then write operations can be performed on each access address in ascending order of address access, with a write mask of 0xffff…f and write data of 0x0000…0, so that the value of the data corresponding to each access address of the target table entry is 0x0000…0.

[0107] (2) Write operations are performed on each access address in the order of address access with a write mask of 0xaaaa…a and a write data of 0xaaaa…a, and the correctness is read back in sequence.

[0108] Before this step, the value of the data corresponding to each access address of the target table entry is 0xaaaa…a, and after execution, it is 0xaaaa…a.

[0109] (3) Write to each access address in the order of address access with a write mask of 0x5555…5 and write data of 0x5555…5, and then read back to check for correctness.

[0110] Before this step, the value of the data corresponding to each access address of the target table entry is 0xaaaa…a, and after execution, it is 0xffff…f.

[0111] (4) Write operations are performed on each access address in the order of address access with a write mask of 0xffff…f and a write data of 0xaaaa…a, and the correctness is read back in sequence.

[0112] Before this step, the value of the data corresponding to each access address of the target table entry is 0xffff…f, and after execution, it is 0xaaaa…a.

[0113] (5) Write to each access address in the order of address access with a write mask of 0x5555…5 and write data of 0xaaaa…a, and read back the data in sequence to check for correctness.

[0114] Before this step, the value of the data corresponding to each access address of the target table entry is 0xaaaa…a, and after execution, it is 0xaaaa…a.

[0115] (6) Write to each access address in the order of address access with a write mask of 0xaaaa…a and write data of 0x5555…5, and then read back to check for correctness.

[0116] Before this step, the value of the data corresponding to each access address of the target table entry is 0xaaaa…a, and after execution, it is 0x0000…0.

[0117] (7) Write to each access address in the order of address access with a write mask of 0xffff…f and write data of 0x5555…5, and then read back to check for correctness.

[0118] Before this step, the value of the data corresponding to each access address of the target table entry is 0x0000…0, and after execution, it is 0x5555…5.

[0119] (8) Write to each access address in the order of address access with a write mask of 0x5555…5 and write data of 0x5555…5, and then read back to check for correctness.

[0120] Before this step, the value of the data corresponding to each access address of the target table entry is 0x5555…5, and after execution, it is 0x5555…5.

[0121] (9) Write operations are performed on each access address in the order of address access with a write mask of 0xaaaa…a and a write data of 0xaaaa…a, and the correctness is read back in sequence.

[0122] Before this step, the value of the data corresponding to each access address of the target table entry is 0x5555…5, and after execution, it is 0xffff…f.

[0123] (A) Write operations are performed on each access address in the order of address access, with a write mask of 0xffff…f and a write data of 0x5555…5, and the correctness is checked back in turn.

[0124] Before this step, the value of the data corresponding to each access address of the target table entry is 0xffff…f, and after execution, it is 0x5555…5.

[0125] (B) Write operations are performed on each access address in the order of address access, with a write mask of 0xaaaa…a and a write data of 0x5555…5, and the correctness is read back in sequence.

[0126] Before this step, the value of the data corresponding to each access address of the target table entry is 0x5555…5, and after execution, it is 0x5555…5.

[0127] (C) Write to each access address in the order of address access with a write mask of 0x5555…5 and write data of 0xaaaa…a, and then read back to check for correctness.

[0128] Before this step, the value of the data corresponding to each access address of the target table entry is 0x5555…5, and after execution, it is 0x0000…0.

[0129] Table 2 shows the changes in the entries of each sub-step in step S310 before and after writing them.

[0130]

[0131]

[0132] Note: True value = Data written to the entry bit * 4 + Write mask of the entry bit * 2 + Previous value of the entry bit

[0133] As shown above, the truth value represents various test scenarios for the table entry bits, with a total of 8 test scenarios from 0 to 7. According to Table 2, it can be seen that each sub-step of step S310 covers all test scenarios for the indirect table entry bits.

[0134] S320: Write random values ​​sequentially to each access address in reverse order of address access, and read them back and compare their correctness.

[0135] The "write random value" indicates that both the write mask and the written data are random values.

[0136] S330: Write random values ​​sequentially to each access address in the order of address access, and read them back and compare their correctness.

[0137] The "write random value" indicates that both the write mask and the written data are random values.

[0138] S340: Write random values ​​sequentially to each access address according to the address access disorder, and read them back and compare their correctness.

[0139] The "write random value" indicates that both the write mask and the written data are random values.

[0140] As described above, steps S320 to S340 cover the scenarios of random write tests under address access in ascending, descending, and out-of-order conditions, and both the write mask and the written data are random values.

[0141] S350: Randomly select any access address and perform 50% reads or 50% writes. Then randomly select any access address again and perform 50% reads or 50% writes. The 50% of the addresses are the same as the addresses selected in the first operation. Repeat the above two steps 100 times.

[0142] Of these, 50% of the writes involve writing random values, where both the write mask and the written data are random.

[0143] S360: Read back the entire address space sequentially according to the address access order and compare the correctness.

[0144] As described above, steps S350 to S360 cover the scenario of randomly selecting access addresses and writing random values ​​multiple times.

[0145] In summary, Embodiment 2 of the test method for table entry access constructs a test flow for direct table entry mode entries based on a combination of address access mode, written data samples, and address order mode. For indirect table entry mode entries, it constructs a test flow based on a combination of address access mode, written data samples, address order mode, and write mask samples. This embodiment further expands the access scenario to CPU table entries, further improving the correctness verification effect of direct and indirect table entries in EDA simulation.

[0146] The following is based on Figures 4 to 5 This invention introduces various embodiments of a test apparatus for table entry access.

[0147] Figure 4 The structure of a test apparatus for table access according to the present invention is shown in one embodiment, which includes: a pattern acquisition module 410, a process construction module 420 and a table entry testing module 430.

[0148] The pattern acquisition module 410 is used to acquire the table access pattern of the target table entry. For its specific principles and advantages, please refer to step S110 of Embodiment 1 of a test method for table access.

[0149] The process construction module 420 is used to set the address access mode and construct the test process of the table entry access mode according to the address access mode. For its specific principles and advantages, please refer to step S120 of the first embodiment of a test method for table entry access.

[0150] The table entry testing module 430 tests the target table entry using a test process based on the table entry access mode of the target table entry. For the specific principles and advantages, please refer to step S130 of an embodiment of a table entry access test method.

[0151] Figure 5 The structure of a second embodiment of the multicast message forwarding device of the present invention is shown, which includes: a pattern acquisition module 510, a process construction module 420 and an entry testing module 430.

[0152] The pattern acquisition module 510 is used to acquire the table access pattern of the target table entry. For its specific principles and advantages, please refer to step S110 of Embodiment 1 of a test method for table access.

[0153] The process construction module 520 is used to set the address access mode, address order mode, and write data samples. It constructs a test process for the direct table entry mode (Example 2) and a write mask for the indirect table entry mode (Example 2). For its advantages and principles, please refer to the test processes for the direct and indirect table entry modes in Example 2.

[0154] The table entry testing module 530 tests the target table entry based on the table entry access mode and the constructed test process. For the specific principles and advantages, please refer to step S130 of an embodiment of a table entry access testing method.

[0155] This invention also provides a computing device, which will be described below in conjunction with... Figure 6 Detailed introduction.

[0156] The computing device 600 includes a processor 610, a memory 620, a communication interface 630, and a bus 640.

[0157] It should be understood that the communication interface 630 in the computing device 600 shown in the figure can be used to communicate with other devices.

[0158] The processor 610 can be connected to the memory 620. The memory 620 can be used to store the program code and data. Therefore, the memory 620 can be a storage unit inside the processor 610, an external storage unit independent of the processor 610, or a component that includes both the storage unit inside the processor 610 and the external storage unit independent of the processor 610.

[0159] Optionally, the computing device 600 may also include a bus 640. The memory 620 and communication interface 630 can be connected to the processor 610 via the bus 640. The bus 640 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 640 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one line is used in this figure, but this does not mean that there is only one bus or one type of bus.

[0160] It should be understood that in this embodiment of the invention, the processor 610 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 610 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in this embodiment of the invention.

[0161] The memory 620 may include read-only memory and random access memory, and provides instructions and data to the processor 610. A portion of the processor 610 may also include non-volatile random access memory. For example, the processor 610 may also store device type information.

[0162] When the computing device 600 is running, the processor 610 executes computer execution instructions stored in the memory 620 to perform the operation steps of each method embodiment.

[0163] It should be understood that the computing device 600 according to the embodiments of the present invention can correspond to the corresponding subject in executing the methods according to the various embodiments of the present invention, and the above and other operations and / or functions of each module in the computing device 600 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0164] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0165] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0166] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0167] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0168] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0169] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0170] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the operation steps of the various method embodiments.

[0171] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0172] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0173] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0174] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0175] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A method of testing for table entry access, characterized by, The method comprises the following steps: acquiring a table item access mode of a target table item, the table item access mode comprising at least a direct table item mode and an indirect table item mode, the direct table item mode being accessed by a table item address, and the indirect table item mode being accessed by a register; setting an address access mode, and constructing a test flow of the table item access mode according to the address access mode, the address access mode comprising at least a one-hot access mode, the one-hot access mode testing each one-hot address, a minimum address and a maximum address of the target table item, each one-hot address having one corresponding bit being 1 and other bits being 0; wherein a write data sample is further set, the write data sample comprising one of all 0, all 5, all a and all f; the test flow of the table item access mode is constructed according to the address access mode and the write data sample; wherein when the access mode is the indirect table item mode, the test flow of the table item access mode is constructed according to the address access mode, a write data sample and a write mask sample, the write mask sample comprising at least one of all 5, all a and all f; and the target table item is tested according to the table item access mode and the test flow.

2. The method of claim 1, wherein, The write data sample further comprises a random value.

3. The method of claim 1, wherein, The method further comprises the following steps: setting an address sequence mode, the address sequence mode comprising at least one of a positive sequence mode, a reverse sequence mode and a random sequence mode; the test flow of the table item access mode is constructed according to the address access mode and the address sequence mode, the test flow covering at least the positive sequence mode, the reverse sequence mode and the random sequence mode.

4. The method of claim 1, wherein, The write mask sample further comprises a random value.

5. The method according to any one of claims 1 to 4, characterized in that, The address access mode further comprises a full space address mode, and the test flow further comprises the following steps: firstly, extracting a plurality of full space addresses of the target table item for random writing or reading back, wherein the value of the writing is a random value; secondly, extracting a first set proportion of the addresses from the extracted addresses in the first step and extracting (1-first set proportion) of the addresses from the addresses not extracted in the first step, and then performing random writing or reading back, wherein the value of the writing is a random value; repeating the first and second steps for a second set number of times; performing reading back and comparison on all full space addresses of the target table item.

6. A test apparatus for table entry access, characterized in that, The method comprises the following steps: a mode acquisition module is configured to acquire a table item access mode of a target table item, the table item access mode comprising at least a direct table item mode and an indirect table item mode, the direct table item mode being accessed by a table item address, and the indirect table item mode being accessed by a register; The flow construction module is configured to set an address access mode, and construct a test flow of the table item access mode according to the address access mode. The address access mode at least includes a one-hot access mode. The one-hot access mode tests each one-hot address, a minimum address and a maximum address of a target table item. Each one-hot address has one corresponding bit being 1 and other bits being 0. A write data sample is also set. The write data sample includes one of all 0, all 5, all a and all f. The test flow of the table item access mode is constructed according to the address access mode. The test flow is constructed according to the address access mode and the write data sample. When the access mode is the indirect table item mode, the test flow of the table item access mode is constructed according to the address access mode. The test flow is constructed according to the address access mode, the write data sample and a write mask sample. The write mask sample at least includes one of all 5, all a and all f. The table item test module is configured to test a target table item according to the table item access mode and the test flow.

7. A computing device, comprising: The system comprises: a bus; a communication interface connected to the bus; at least one processor connected to the bus; at least one memory connected to the bus and storing program instructions. The program instructions, when executed by the at least one processor, cause the at least one processor to perform the method of any one of claims 1 to 5. A computer readable storage medium having stored thereon program instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, ​

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