A signal aggregation method, device, storage medium and electronic equipment
By classifying and dividing signals in the FPGA and aggregating signals using time-division multiplexing, the timing violation problem caused by unreasonable signal combination is solved, signal transmission delay is optimized, and signal transmission efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- S2C
- Filing Date
- 2023-03-30
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies fail to effectively consider the correlation between signals and the location distribution of signal drivers and loads in user designs, resulting in unreasonable signal combinations, increased signal transmission delays, and timing violations.
By pairing multiple FPGAs together, signals are classified and divided according to the timing characteristics and signal location characteristics of the timing path. Signals are aggregated using time division multiplexing to ensure that signals share the basis of TDM and reduce timing violations.
This approach optimizes signal combination while considering signal correlation and location distribution, reducing timing violations caused by excessive signal transmission delay and improving signal transmission efficiency.
Smart Images
Figure CN116341436B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic design automation technology, specifically to a signal aggregation method, apparatus, storage medium, and electronic device. Background Technology
[0002] As user designs grow in scale, logic verification often necessitates the use of multi-FPGA systems. This requires dividing the user design into a specified number of parts, each allocated to a different FPGA. These FPGAs are connected via interconnects, which are significantly spaced relative to the internal dimensions of the FPGA, resulting in substantial signal delays. An FPGA typically consists of several Super Logic Regions (SLRs), also known as dies. These dies exhibit a specific topological distribution. Dies within the same FPGA are connected using High Width Low Latency Connections (HLConnects), which typically offer low latency, low power consumption, and high throughput.
[0003] Signal grouping aggregates signals into a group. Signals in the same group will be transmitted using time division multiplexing (TDM) on a single physical connection. Therefore, choosing which signals to group is an important issue, affecting the routing paths and connection resource consumption between dies within the same FPGA.
[0004] Existing technologies do not take into account the correlation between signals and the location distribution of signal drivers and loads. This often results in signals with weak correlation being grouped together and sharing a single physical wire for transmission. This increases the wiring cost of signals within the group and causes excessive delays in the transmission of many signals with strict timing requirements, leading to timing violations. Summary of the Invention
[0005] In view of this, embodiments of the present disclosure provide a signal aggregation method, apparatus, storage medium, and electronic device, which realizes signal aggregation by taking into account the correlation between signals and the location distribution of signal driving nodes and load nodes, providing a basis for multi-signal shared TDM, and solving the problem of timing violations caused by excessive delay in signal transmission due to strict timing requirements.
[0006] In a first aspect, embodiments of this disclosure provide a signal aggregation method, the method comprising:
[0007] By pairing multiple FPGAs in the network, a multi-threaded concurrent die-level signal group is obtained.
[0008] Based on the timing characteristics of the timing path, the signal lines between a pair of FPGAs in the die-level signal group are classified to obtain the total number of signals and the signal group ratio of each type of signal group;
[0009] The signals in each signal group are divided according to the total number of signals, the ratio of signal groups, and the signal location characteristics, so that the divided signals are aggregated using time-division multiplexing.
[0010] Preferably, the signal lines between a pair of FPGAs in a die-level signal group are classified according to the timing characteristics of the timing path to obtain the total number of signals and the signal group ratio for each type of signal group, including:
[0011] Based on the propagation direction of the signal lines between a pair of FPGAs in a die-level signal group, the signal lines between a pair of FPGAs in a die-level signal group are divided into two main categories;
[0012] Based on the timing characteristics of the timing paths of a pair of signal lines between FPGAs in a die-level signal group, the signal lines of each major category are classified to obtain the total number of signals and the ratio of signal groups in each category.
[0013] Preferably, the signals in each signal group are divided according to the total number of signals in each signal group, the ratio of signal groups, and the signal location characteristics, including:
[0014] The subgroup value for each type of signal group is obtained based on the total number of signals in each signal group and the ratio of signal groups.
[0015] The signals are divided into groups equally according to the subgroup values and signal location characteristics of each signal group, thus obtaining the signals within the subgroups of each signal group.
[0016] Preferably, the signal location characteristics include the distance between signal load nodes, the distance between signal drive nodes, the signal clock domain, and the signal hierarchy.
[0017] Preferably, the signals that are equally divided into each signal group based on the subgroup value and signal location characteristics include:
[0018] The number of signals in each subgroup is obtained by dividing each type of signal group into subgroups and the total number of signals in each type of signal group.
[0019] The signals in each signal group are divided according to the principle of minimizing the sum of the distances between signal load nodes and the distances between signal drive nodes within each signal group.
[0020] Preferably, the signals in each signal group are divided according to the principle of minimizing the sum of the distances between signal load nodes and the distances between signal drive nodes within each signal group, including:
[0021] When the sum of the distance between the signal load nodes and the distance between the signal drive nodes of each signal group is the same, the signals that are in the same signal clock domain as the reference node or the signals that are closest to the reference node in the signal hierarchy are divided into the same subgroup, so that each subgroup has the same number of signals as the signal number.
[0022] Preferably, signals in the same clock domain as the reference node are grouped into the same partition group, such that each partition group contains several signals, including:
[0023] If the number of signals in the same clock domain as the reference node is greater than the number of signals in the group, the signals in each group with the same number of signals are grouped into the same group according to the order of increasing signal hierarchy distance from the reference node.
[0024] Secondly, embodiments of this disclosure provide a signal aggregation system, the system comprising:
[0025] The grouping module is used to group multiple FPGAs in the network into pairs to obtain multi-threaded concurrent die-level signal groups;
[0026] The classification module is used to classify the signal lines between a pair of FPGAs in the die-level signal group according to the timing characteristics of the timing path, and obtain the total number of signals and the signal group ratio of each type of signal group;
[0027] The partitioning module is used to partition the signals of each signal group according to the total number of signals, the ratio of signal groups, and the signal position characteristics, so that the partitioned signals are aggregated in a time-division multiplexing manner.
[0028] Thirdly, embodiments of this disclosure provide a storage medium storing a computer program thereon, characterized in that the program is executed by a processor to implement the method described above.
[0029] Fourthly, embodiments of this disclosure provide an electronic device, including: a processor and a memory storing a computer program, the processor being configured to implement the method described above when running the computer program.
[0030] The signal aggregation method in this embodiment of the disclosure involves pairing multiple FPGAs in a network to obtain multi-threaded concurrent die-level signal groups. The signal lines between a pair of FPGAs in each die-level signal group are classified according to the timing characteristics of the timing path, resulting in the total number of signals and the signal group ratio for each type of signal group. The signals in each type of signal group are then divided based on the total number of signals, the signal group ratio, and the signal location characteristics, allowing the divided signals to be aggregated using time-division multiplexing (TDM). This technical solution enables signal aggregation considering the correlation between signals and the location distribution of signal driving nodes and load nodes, providing a basis for multi-signal shared TDM, while simultaneously solving the problem of timing violations caused by excessive transmission delays for signals with strict timing requirements. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic flowchart of a signal aggregation method provided in an embodiment of the present disclosure;
[0033] Figure 2 This is a schematic diagram of the initial signal grouping of a pair of FPGAs provided in an embodiment of the present disclosure;
[0034] Figure 3 A schematic diagram of a method flow that further defines step S3 in the embodiments of this disclosure;
[0035] Figure 4 This is a schematic diagram of a method for calculating the distance between nodes within a signal group provided in an embodiment of this disclosure;
[0036] Figure 5 This is a schematic diagram illustrating the further signal partitioning result of a pair of FPGAs provided in an embodiment of this disclosure;
[0037] Figure 6 A schematic diagram of a signal aggregation device provided in an embodiment of this disclosure;
[0038] Figure 7 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0039] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0040] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0041] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0042] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0043] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0044] The basic idea of this application is to provide a signal aggregation method, apparatus, storage medium, and electronic device. This involves randomly grouping N FPGAs in a network to form multi-threaded concurrent die-level signal groups; coarsely grouping these signals according to timing characteristics, especially timing urgency; and further dividing these signal groups according to the location characteristics (clock domain, distance, hierarchical relationship) of individual signals, making signal sharing TDM (Time Management Decision Making) reliable. This reduces many timing violation problems caused by excessive transmission delays of signals with strict timing requirements.
[0045] Figure 1 This is a schematic flowchart illustrating a signal aggregation method provided in an embodiment of this disclosure. This method is applicable to the electronic design process of integrated circuits, such as... Figure 1 As shown, the method may include:
[0046] Step S1: Group the multiple FPGAs in the network into pairs to obtain multi-threaded concurrent die-level signal groups.
[0047] Among them, networking is the sum of the hardware resources of the verification system, including the number of FPGAs, the connection relationship between FPGAs, the number of connections, and other information.
[0048] In one example, assume there are N FPGAs in the network that have not yet completed signal grouping. Randomly pair these N FPGAs together to form N / 2 pairs of FPGAs. Simultaneously, create N / 2 threads, each processing the die-level signal grouping between a pair of FPGAs. Once all external connections of each FPGA have been grouped, the die-level signal grouping is complete. Perform die-level signal grouping for each pair of FPGAs. Finally, search for all remaining FPGAs with incomplete signal grouping and repeat the above steps until all FPGAs in the network have completed die-level signal grouping.
[0049] Step S2: Classify the signal lines between a pair of FPGAs in the die-level signal group according to the timing characteristics of the timing path, and obtain the total number of signals and the signal group ratio of each type of signal group.
[0050] For the pair of FPGAs obtained in step S1, assuming there are M timing paths between them, timing analysis is performed on each path to obtain the setup time margin S_set and hold time margin S_hold. Since the path between the pair of FPGAs is relatively long and the transmission delay is large, the possibility of hold time violations is low. That is, the hold time (the time a signal needs to be held at a sampling point; the longer the path, the larger the margin for signal holding, and the lower the possibility of hold time violations) can be satisfied. While the hold time can be satisfied due to the long transmission path between FPGAs, the setup time (set time) may not. Therefore, the timing urgency of each timing path (a variable balancing the setup time (set time) and hold time (hold time) can be considered only in terms of setup time (set time), i.e., only the size of the setup time margin S_set on each timing path needs to be considered. The smaller the setup time margin S_set, the smaller the proportion of each signal group. The formula for calculating the timing urgency of each timing path is as follows:
[0051] Timing_urgency = 1 / (α*S_set + (1-α)* S_hold) Formula (1);
[0052] Where α is a parameter between [0, 1]. Since the time margin S_set is established on each time path in the current scenario has a significant impact, the value of α can be chosen to be smaller as needed, and no limitation is made here.
[0053] The interconnects (signal lines between nodes) between the circuits of the two FPGAs are sorted and classified according to the timing urgency of each timing path. In other words, the interconnects between the circuits of the two FPGAs are sorted and classified according to the timing characteristics of the timing path.
[0054] In one example, the signal lines between a pair of FPGAs in a die-level signal group are classified according to the timing characteristics of the timing path to obtain the total number of signals and the signal group ratio for each type of signal group. This can include:
[0055] Based on the propagation direction of the signal lines between a pair of FPGAs in a die-level signal group, the signal lines between a pair of FPGAs in a die-level signal group are divided into two main categories;
[0056] Based on the timing characteristics of the timing paths of a pair of signal lines between FPGAs in a die-level signal group, the signal lines of each major category are classified to obtain the total number of signals and the ratio of signal groups in each category.
[0057] For example, when classifying a pair of signal lines between FPGAs, they are first divided into two main categories according to the direction of signal propagation. The direction of signal propagation includes two directions: from the left end of the signal to the right end of the signal and from the right end of the signal to the left end of the signal. The left end of the signal can be the driving node of the signal and the right end of the signal can be the load node of the signal, or the left end of the signal can be the load node of the signal and the right end of the signal can be the driving node of the signal. No restrictions are imposed here.
[0058] After dividing the signal lines between a pair of FPGAs in a die-level signal group into two categories according to their propagation direction, for each category of signals, the group ratio of each category of signals is set according to the timing characteristics of the signals, namely the size of the timing margin setup slack, the total number of physical connections between the two FPGAs and the total number of signals to be transmitted, so that the timing margin setup slack of each category of signal group is relatively balanced.
[0059] Figure 2 This is a schematic diagram of the initial signal grouping of a pair of FPGAs provided in an embodiment of this disclosure.
[0060] like Figure 2 As shown, there are 8 physical connections between a pair of FPGAs, and a total of 112 signals to be transmitted between them. Of these, 32 signals propagate from right to left, and 80 signals propagate from left to right. To ensure a more balanced setup slack across the signal groups, the signal lines between the FPGAs can be categorized as follows: Group A has 32 signals, propagating from right to left, resulting in a TDM ratio of 8:1; Group B has 48 signals, propagating from left to right, resulting in a TDM ratio of 24:1; and Group C has 32 signals, propagating from left to right, resulting in a TDM ratio of 16:1. By setting the proportion of each major signal group, the timing margin setup slack of each major signal group can be made more balanced, and the total number of each type of signal group can be obtained.
[0061] Step S3: Divide the signals of each signal group according to the total number of signals, the ratio of signal groups, and the signal position characteristics, so that the divided signals are aggregated in a time-division multiplexing manner.
[0062] According to step S2, we can know the number of signals that need to be transmitted between any two FPGAs, the signal group ratio, and the location and number of physical connections between a pair of FPGAs at the die level. The current step is to determine which signals are divided into a group, that is, to share a physical connection between FPGAs in the form of time division multiplexing (TDM).
[0063] Figure 3 A schematic diagram of a method flow that further defines step S3 in the embodiments of this disclosure.
[0064] In one example, such as Figure 3 As shown, the signals in each signal group are divided according to the total number of signals, the ratio of signal groups, and the signal location characteristics. This can include:
[0065] Step S31: Obtain the subgroup value for each type of signal group based on the total number of signals and the ratio of signal groups in each type of signal group.
[0066] For example, if there are 32 signals in group A in step S2, and the group ratio is 8:1, then group A needs to be divided into 4 subgroups, with 8 signals in each subgroup. Which 8 signal lines are included in each subgroup is closely related to the location of the 32 driver nodes and 32 load nodes of group A, and also to the usage of physical wires and die connections between FPGAs.
[0067] Step S32: Divide the signals of each signal group equally according to the subgroup value and signal position characteristics of each signal group to obtain the signals within the subgroup of each signal group.
[0068] The signal location characteristics may include the distance between signal load nodes, the distance between signal drive nodes, the signal clock domain, and the signal hierarchy.
[0069] Figure 4 This is a schematic diagram of a method for calculating the distance between nodes within a signal group, provided in an embodiment of this disclosure.
[0070] like Figure 4 As shown, assuming there are a total of 4 signals and a group ratio of 2:1, the signals should be divided into two groups. To simplify the problem, when dividing the signal groups, we can consider only the driver node and the load node (driver and load are proper nouns representing the signal sender and receiver, respectively). For example... Figure 4As shown, if the nodes in the left FPGA represent the driver and the nodes in the right FPGA represent the load, then the nodes in the left FPGA are driver nodes and the nodes in the right FPGA represent load nodes. A line with an arrow can be used to represent the path from the driver node to the load node. Similarly, the same method is used for the case where the nodes in the left FPGA represent the load and the nodes in the right FPGA represent the driver; no restrictions are imposed here.
[0071] The goal of signal aggregation between a pair of FPGAs is to group signals with the closest overall distance together. This overall distance considers the distances between the load nodes and the driver nodes in both FPGAs. Because the driver nodes of two signals are close together, their corresponding load nodes may be far apart. Figure 4 The diagram shows two nodes, a and b. This means that when the number of nodes within each group is the same, the sum of the distances within each group is minimized.
[0072] The distance between two signals is the sum of the number of dies crossing between signal driving nodes (dies crossing is the gap between adjacent die in the same FPGA) and the number of dies crossing between signal load nodes.
[0073] The following is based on Figure 4 The calculation of the distance between signal load nodes and the distance between signal drive nodes is explained using the example of signal a between drive node a and load node a, and signal b between drive node b and load node b.
[0074] like Figure 4 As shown, the number of die crossings between driver nodes a and b in the left FPGA is 0, while the number of die crossings between load nodes a and b in the right FPGA is 3. Therefore, the distance between signal a and signal b is 4. Similarly, the distances between other signals can be calculated.
[0075] In one example, signals that are equally divided into each signal group based on the subgroup value and signal location characteristics can include:
[0076] The number of signals in each subgroup is obtained by dividing each type of signal group into subgroups and the total number of signals in each type of signal group.
[0077] The signals in each signal group are divided according to the principle of minimizing the sum of the distances between signal load nodes and the distances between signal drive nodes within each signal group.
[0078] Figure 5This is a schematic diagram illustrating the further signal partitioning result of a pair of FPGAs provided in an embodiment of this disclosure.
[0079] For example, such as Figure 5 As shown, taking the driver nodes in the left FPGA as the operation object, the driver nodes distributed at both ends of the FPGA are selected as signal group seed 1 and signal group seed 2. The signals closest to the two seeds are grouped into the same signal group. The above operation is repeated for the remaining signals until all signals are grouped, so that the number of signals in each group is the same as the number of signals in each subgroup. This can avoid the situation where two nodes that are very far apart, such as driver node 1 and driver node 8, are grouped together.
[0080] In one example, when the sum of the distances between signal load nodes and the distances between signal drive nodes in each signal group is the same, signals that are in the same signal clock domain as the reference node or signals that are closest to the reference node in signal hierarchy are grouped into the same subgroup, such that each subgroup contains a number of signals. If the number of signals in the same signal clock domain as the reference node is greater than the number of signals in a subgroup, then signals within each subgroup that are equal in number to the number of signals in the subgroup are grouped into the same subgroup according to their signal hierarchy distance from the reference node in ascending order.
[0081] Among them, the signal hierarchy distance can be the hierarchical position information of the signal in the syntax tree.
[0082] For example, the information format of the driver or load node of a signal in the syntax tree is top / mod1 / submod1 / ssubmod2. Here, ' / ' represents an additional level, and the level name is randomized for the algorithm.
[0083] For example, when there are many nodes with a minimum distance, exceeding the number of signals in each group, selection can be based on whether the signals belong to the same clock domain or the proximity of their hierarchical information. Specifically, under the condition of equal distance (where the sum of the difference in diescrossings between the driving nodes and the load nodes of two signals is the same), the signal belonging to the same clock domain as the seed node (e.g., driving node 1 above) is selected as the group to be grouped with the seed signal. If there are redundant signals, the hierarchical distance can be compared to determine which signal's driving and load nodes are closer in hierarchy to the current seed signal's driving and load nodes. Weights can be assigned to each character in the hierarchical position name of the signal, with earlier characters having higher weights and later characters having lower weights.
[0084] For example, the hierarchy information of two nodes are: Alevel1name / Alevel2name / Alevel3name / ... and Blevel1name / Blevel2name / Blevel3name / Blevel4name..., and the number of levels of the two nodes can be different. Then, we first compare their first-level names, Alevel1name and Blevel1name, to see how different they are. A simple way is to compare the proportion of the two strings having the same characters; a more complex (and more effective) approach is to compare the proportion of the length of the longest common contiguous substring in both strings to their total length, etc. No specific limitations are imposed here. Among them, the similarity of the names at the first level has a significant impact. If the first level positions of two nodes are far apart, the difference will become larger and larger in the later levels. If two nodes show some differences at the last (deeper) level, but are the same at the previous levels, then these two nodes are actually still very close. This means that the signals corresponding to the two nodes are closer in the syntax tree and are more similar in position. Similar signals are more suitable to be assigned to the same group, which is beneficial to the timing effect of the entire signal group division. It is not necessary to increase the routing difficulty of the entire signal group because the timing requirements of a certain signal are particularly high.
[0085] The influence weight of signal hierarchy can be set as follows: the first level has an influence weight of K, the next deeper level has an influence weight of K / M, decreasing in a geometric progression, or any other decreasing form is acceptable. There are no restrictions here, as long as the similarity of higher levels is more important than that of lower levels. Because the similarity of earlier levels is more meaningful for signal grouping, priority is given to ensuring that two signals are close in distance at higher levels. The distance between signal hierarchy names A and B can be defined as: Distance(A, B) = Sum of the weights of overlapping characters between A and B / (Sum of the weights of each character in name A + Sum of the weights of each character in name B). This allows signals to be grouped into the same group based on their signal hierarchy distance to the reference node when the sum of the distances between signal load nodes and signal drive nodes in each signal group is the same, and the number of signals in the same signal clock domain as the reference node is greater than the number of signals in the group. This ensures that each group has the same number of signals as the reference node.
[0086] The signal aggregation method in this embodiment can achieve signal aggregation considering the correlation between signals and the location distribution of signal driving nodes and load nodes, providing a basis for multi-signal shared TDM, and solving the problem of timing violations caused by excessive delay in signal transmission due to strict timing requirements.
[0087] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.
[0088] Figure 6 This is a schematic diagram of a signal aggregation device provided in an embodiment of this disclosure. Figure 6 As shown, the device may include:
[0089] Grouping module 601 is used to group multiple FPGAs in the network into pairs to obtain multi-threaded concurrent die-level signal groups;
[0090] The classification module 602 is used to classify the signal lines between a pair of FPGAs in the die-level signal group according to the timing characteristics of the timing path, and obtain the total number of signals and the signal group ratio of each type of signal group;
[0091] The partitioning module 603 is used to partition the signals of each type of signal group according to the total number of signals, the ratio of signal groups, and the signal position characteristics, so that the partitioned signals are aggregated in a time-division multiplexing manner.
[0092] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0093] In some embodiments, the area power consumption optimization system apparatus for VLSI may incorporate the area power consumption optimization method features of any embodiment of VLSI, and vice versa, which will not be elaborated here.
[0094] In an embodiment of the present invention, an electronic device is provided, comprising: a processor and a memory storing a computer program, wherein the processor is configured to perform a method for area and power consumption optimization of a very large-scale integrated circuit according to any embodiment of the present invention when running the computer program.
[0095] Figure 3 The diagram illustrates a method for implementing embodiments of the present invention or an electronic device 1000 for implementing embodiments of the present invention. In some embodiments, it may include more or fewer electronic devices than illustrated. In some embodiments, it may be implemented using a single or multiple electronic devices. In some embodiments, it may be implemented using cloud-based or distributed electronic devices.
[0096] Figure 7 This is a schematic diagram of the structure of the electronic device 10 provided in an embodiment of this application. Figure 7 As shown, the electronic device 1000 includes a processor 1001, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 1002 or programs and / or data loaded from storage portion 1008 into random access memory (RAM) 1003. The processor 1001 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 1001 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device 1000 are also stored in RAM 1003. The processor 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.
[0097] The processor and memory described above are used together to execute programs stored in the memory. When the program is executed by the computer, it can implement the methods, steps, or functions described in the above embodiments.
[0098] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, touchscreen, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 1010 as needed so that computer programs read from it can be installed into storage section 1008 as needed. Figure 7 The diagram only shows a portion of the components and does not imply that the computer system 1000 only includes... Figure 7 The components shown.
[0099] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.
[0100] Although not shown, in embodiments of the present invention, a storage medium is provided storing a computer program configured to execute, when run, any of the file-difference-based compilation methods of the present invention.
[0101] Storage media in embodiments of the present invention include articles that are permanent and non-permanent, removable and non-removable, capable of storing information by any method or technology. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.
[0102] The methods, programs, systems, apparatuses, etc., in embodiments of the present invention can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.
[0103] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.
[0104] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0105] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to embodiments applicable to at least one, but not all, of the present invention. The above terms do not necessarily refer to the same embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples.
[0106] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A signal aggregation method, characterized in that, The method includes: By pairing multiple FPGAs in the network, a multi-threaded concurrent die-level signal group is obtained. Based on the timing characteristics of the timing path, the signal lines between a pair of FPGAs in the die-level signal group are classified to obtain the total number of signals and the signal group ratio of each type of signal group; The signals of each signal group are divided according to the total number of signals, the ratio of signal groups, and the signal position characteristics of each signal group, so that the divided signals are aggregated in a time-division multiplexing manner; The process of classifying the signal lines between a pair of FPGAs in a die-level signal group based on the timing characteristics of the timing path, and obtaining the total number of signals and the signal group ratio for each type of signal group, includes: Based on the propagation direction of the signal lines between a pair of FPGAs in the die-level signal group, the signal lines between a pair of FPGAs in the die-level signal group are divided into two main categories; Based on the magnitude of the timing characteristics of the timing paths of the signal lines between a pair of FPGAs in the die-level signal group, the signal lines of each major category are classified to obtain the total number of signals and the signal group ratio of each category.
2. The signal aggregation method according to claim 1, characterized in that, The step of classifying the signals of each signal group according to the total number of signals, the ratio of signal groups, and the signal position characteristics of each signal group includes: The subgroup value for each type of signal group is obtained based on the total number of signals and the ratio of signal groups in each type of signal group. The signals are divided into groups equally according to the subgroup values and signal location characteristics of each signal group, thus obtaining the signals within the subgroups of each signal group.
3. The signal aggregation method according to claim 2, characterized in that, The signal location features include the distance between signal load nodes, the distance between signal drive nodes, the signal clock domain, and the signal hierarchy.
4. The signal aggregation method according to claim 3, characterized in that, The signals that are equally divided into each signal group based on the subgroup value and signal location characteristics of each signal group include: The number of signals in each division group is obtained based on the division group value of each type of signal group and the total number of signals in each type of signal group; The signals in each signal group are divided according to the principle of minimizing the sum of the distances between signal load nodes and the distances between signal drive nodes within each signal group.
5. The signal aggregation method according to claim 4, characterized in that, The process of dividing each signal group based on the number of signals within each subgroup and minimizing the sum of the distances between signal load nodes and signal drive nodes within each subgroup includes: When the sum of the distance between the signal load nodes and the distance between the signal drive nodes of each type of signal group is the same, the signals that are in the same signal clock domain as the reference node or the signals that are closest to the reference node in terms of signal hierarchy are divided into the same subgroup, so that each subgroup has the same number of signals as the number of signals.
6. The signal aggregation method according to claim 5, characterized in that, The step of grouping signals that are in the same clock domain as the reference node into the same partition group, such that each partition group contains several signals, includes: If the number of signals in the same signal clock domain as the reference node is greater than the number of signals in the group, the signals in each group that have the same number of signals are grouped into the same group according to the order of increasing signal hierarchy distance from the reference node.
7. A signal aggregation device, characterized in that, The device includes: The grouping module is used to group multiple FPGAs in the network into pairs to obtain multi-threaded concurrent die-level signal groups; The classification module is used to classify the signal lines between a pair of FPGAs in a die-level signal group according to the timing characteristics of the timing path, and to obtain the total number of signals and the signal group ratio of each type of signal group. The classification of the signal lines between a pair of FPGAs in a die-level signal group according to the timing characteristics of the timing path to obtain the total number of signals and the signal group ratio of each type of signal group includes: Based on the propagation direction of the signal lines between a pair of FPGAs in the die-level signal group, the signal lines between a pair of FPGAs in the die-level signal group are divided into two main categories; Based on the magnitude of the timing characteristics of the timing path of the signal line between a pair of FPGAs in the die-level signal group, the signal lines of each major category are classified to obtain the total number of signals and the signal group ratio of each category. The partitioning module is used to partition the signals of each type of signal group according to the total number of signals, the ratio of signal groups, and the signal position characteristics of each type of signal group, so that the partitioned signals are aggregated in a time-division multiplexing manner.
8. A storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the method as described in any one of claims 1-6.
9. An electronic device, characterized in that, include: A processor and a memory storing a computer program, the processor being configured to implement the method of any one of claims 1-6 when the computer program is executed.