Display device

Abstract

A display apparatus includes a display panel including a data line, first through nth data driving integrated circuits (ICs) (where n is a natural number greater than 1) that supply a data voltage to the data line, a controller that controls the first through nth data driving ICs, and a power supply that supplies power to the first through nth data driving ICs. The first data driving IC includes a lock signal switching unit that receives or blocks a lock signal from the power supply, a pull-up resistor is provided between a second data driving IC and a lock signal line to which the lock signal is supplied from the power supply, and the lock signal supplied to the first data driving IC or the second data driving IC is transmitted to the controller through the first through nth data driving ICs.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0187071, filed on December 24, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] In display devices, in order to synchronize the driving timing of data driver integrated circuits (ICs), lock signals are continuously transmitted to the data driver ICs while displaying images.

[0005] In display devices, when continuously displaying the same image based on identical image data, the controller may not transmit image data to the data driver IC. This mode is called Low Power Tx Drive (LPTD) mode. In this case, the latch signal is also not transmitted to the data driver IC.

[0006] Subsequently, when the image data changes, the controller uses a locking signal to synchronize the data driver IC, and then transmits the image data to the data driver IC.

[0007] In this situation, the transmission speed of the lock signal is reduced due to parasitic capacitance generated in the data driver IC and in the lines through which the lock signal is transmitted. Therefore, a delay in the lock signal occurs.

[0008] Therefore, after the LPTD mode ends, the image that should be output first may not be output correctly, and as a result, the quality of the display device may be reduced. Summary of the Invention

[0009] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One aspect of this disclosure is to provide a display device capable of increasing the transmission speed or current magnitude of a lock signal to prevent delay in the lock signal.

[0011] Additional advantages and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon examination of the following, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures specifically pointed out in the written description and claims and the accompanying drawings.

[0012] To achieve these and other advantages, in accordance with the purposes of this disclosure, as specifically presented and summarized herein, a display device is provided, comprising: a display panel including data lines; first data driver integrated circuits to nth data driver integrated circuits (ICs) (where n is a natural number greater than 1) supplying data voltages to the data lines; a controller controlling the first data driver ICs to nth data driver ICs; and a power supply supplying power to the first data driver ICs to nth data driver ICs, wherein the first data driver IC includes a lock signal switching unit that receives or blocks a lock signal from the power supply, a pull-up resistor is disposed between a second data driver IC and a lock signal line, the lock signal is supplied from the power supply to the lock signal line, and the lock signal supplied to the first data driver IC or the second data driver IC is transmitted to the controller via the first data driver ICs to the nth data driver IC.

[0013] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0015] Figure 1 This is an exemplary view showing the configuration of a display device according to the present disclosure;

[0016] Figure 2 This is an exemplary view showing the structure of a pixel applied to a display device according to the present disclosure;

[0017] Figure 3 This is an exemplary view showing the configuration of a controller applied to a display device according to the present disclosure;

[0018] Figure 4 This is an exemplary view showing a display panel applied to a display device according to the present disclosure;

[0019] Figure 5 and Figure 6 This is an exemplary view showing the structure of each data driver integrated circuit (IC) applied to a display device according to the present disclosure;

[0020] Figure 7 and Figure 8 This is another exemplary view showing the structure of each data driver IC applied to a display device according to the present disclosure;

[0021] Figure 9This is another exemplary view showing the structure of each data driver IC applied to a display device according to the present disclosure; and

[0022] Figure 10 This is an exemplary view illustrating a driving method for a display device according to the present disclosure. Detailed Implementation

[0023] Reference will now be made in detail to exemplary embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0024] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be complete and fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0025] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the illustrated details. Similar reference numerals all refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions unnecessarily obscure the essential points of this disclosure. Where terms such as "comprising," "having," and "including" are used in this specification, another component may be added unless "only" is used. Singular terms may include plural forms unless the opposite is stated.

[0026] When interpreting a component, the component is interpreted as including a range of errors or tolerances, even if there is no explicit description of such a range of errors or tolerances.

[0027] When describing positional relationships, for example, when the positional relationship between two components is described as “on top of,” “above,” “below,” and “beside,” one or more other components may be placed between the two components, unless more restrictive terms such as “only” or “directly” are used.

[0028] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “only,” “immediately,” or “directly” are used.

[0029] It should be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0030] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to distinguish the corresponding element from other elements, and the nature, order, or number of the corresponding elements shall not be limited by these terms. For the description of an element being “connected,” “joined,” or “adhered” to another element or layer, the element or layer may be directly connected or adhered to the other element or layer, or indirectly connected or adhered to the other element or layer where one or more intermediate elements or layers are “set” or “inserted” between the elements or layers, unless otherwise stated.

[0031] The term "at least one" should be understood to include any or all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items, as well as all items derived from the first, second, or third item.

[0032] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may interact and be technically driven differently from each other as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent manner.

[0033] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is an exemplary view showing the configuration of a display device according to the present disclosure. Figure 2 This is an exemplary view showing the structure of pixels applied to a display device according to the present disclosure. Figure 3 This is an exemplary view showing the configuration of a controller applied to a display device according to the present disclosure.

[0035] The display device according to this disclosure can constitute various electronic devices. For example, electronic devices may include smartphones, tablet computers (PCs), televisions (TVs), and monitors.

[0036] like Figure 1As shown, the display device according to this disclosure may include: a display panel 100, the display panel 100 including a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a gate driver 200, the gate driver 200 supplying gate signals to a plurality of gate lines GL1 to GLg disposed in the display area 120 of the display panel 100; a data driver 300, the data driver 300 supplying data voltage to a plurality of data lines DL1 to DLd disposed in the display panel 100; a controller 400, the controller 400 controlling the driving of the gate driver 200 and the data driver 300; and a power supply 500, the power supply 500 supplying power to the controller 400, the gate driver 200 and the data driver 300 of the display panel 100.

[0037] In the display device according to this disclosure, such as Figure 1 As shown, the data driver 300 may include at least two data driver integrated circuits (ICs) 310. The at least two data driver ICs 310 may supply data voltage to the data lines DL1 to DLd.

[0038] In this disclosure, the controller 400 can transmit image data to the data driver IC 310. This approach may be referred to as an embedded panel interface (hereinafter referred to as EPI).

[0039] In a display device using EPI, when the display device is turned on, the data driver IC 310 can be synchronized by a lock signal. When the lock signal is received normally, the display device can transmit multiple image data (Data) to the data driver IC 310, so that the display panel 100 can display images.

[0040] In display devices using EPI, a lock signal can be continuously transmitted to the controller 400 via the data driver IC 310 while the image is being displayed. Therefore, it is possible to determine whether the data driver IC 310 is synchronized.

[0041] A lock signal can be supplied to at least one data driver IC 310.

[0042] The basic components of a display device using EPI will be described below.

[0043] First, the display panel 100 may include a display area 120 and a non-display area 130. Gate lines GL1 to Glg, data lines DL1 to DLd, and pixels 110 may be disposed in the display area 120. Therefore, the display area 120 can display an image. Here, g and d can both be natural numbers. The non-display area 130 may surround the outer portion of the display area 120.

[0044] like Figure 2As shown, the pixel 110 included in the display panel 100 may include a light-emitting area, which includes a pixel driving circuit PDC and a light-emitting device ED. The pixel driving circuit PDC includes a switching transistor Tsw1, an energy storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2.

[0045] The first terminal of the driving transistor Tdr can be connected to the high voltage supply line PLA (the high voltage EVDD is supplied through the high voltage supply line PLA), and the second terminal of the driving transistor Tdr can be connected to the light-emitting device ED.

[0046] The first terminal of the switching transistor Tsw1 can be connected to the data line DL, the second terminal of the switching transistor Tsw1 can be connected to the gate of the driving transistor Tdr, and the gate of the switching transistor Tsw1 can be connected to the gate line GL.

[0047] The data voltage Vdata can be supplied to the data line DL, and the gate signal GS can be supplied to the gate line GL.

[0048] The sensing transistor Tsw2 can be configured to measure the threshold voltage or mobility of the driving transistor. The first terminal of the sensing transistor Tsw2 can be connected to the second terminal of the driving transistor Tdr and the light-emitting device ED. The second terminal of the sensing transistor Tsw2 can be connected to the sensing line SL (the reference voltage Vref is supplied through the sensing line SL). The gate of the sensing transistor Tsw2 can be connected to the sensing control line SCL (the sensing control signal SS is supplied through the sensing control line SCL).

[0049] The structure of pixel 110 applied in this disclosure is not limited to Figure 2 The structure shown. Therefore, the structure of pixel 110 can be changed into various shapes.

[0050] Furthermore, this disclosure can be applied to liquid crystal display (LCD) devices including liquid crystal display panels and devices including… Figure 2 The light-emitting display device shown is a light-emitting device. That is, this disclosure can be applied to various display devices currently in use. However, in the following description, for ease of description, the light-emitting display device will be described as an example of this disclosure.

[0051] The data driver 300 can supply the data voltage Vdata to the data lines DL1 to DLd.

[0052] The data driver 300 may include at least two data driver ICs 310. Each of the at least two data driver ICs 310 may be connected to at least one data line DL.

[0053] Each of at least two data driver ICs 310 can receive multiple image data Data corresponding to the data lines connected thereto from the controller 400, convert the received image data Data into data voltage, and supply the data voltage to the data lines.

[0054] A lock signal LOCK received by at least one of the at least two data driver ICs 310 can be sequentially supplied to all data driver ICs 310, so that it can ultimately be received by the controller 400.

[0055] The LOCK signal can synchronize all data driver ICs 310 and initialize them. When the LOCK signal is received normally, the controller 400 can determine that all data driver ICs 310 are synchronized and driving normally.

[0056] For example, in Figure 1 In the display device shown, the LOCK signal supplied to the second data driver IC (second from the left) can be supplied to the first data driver IC (first from the left) and the third data driver IC (third from the left), and the LOCK signal supplied to the third data driver IC (third from the left) can be sequentially supplied to the data driver IC located to the right of the third data driver IC. Figure 1 In the display device shown, the LOCK signal, which is transmitted to the data driver IC located on the far right, can be transmitted to the controller 400.

[0057] In this case, the LOCK signal can initialize all data driver ICs 310.

[0058] The controller 400 can use timing synchronization signals transmitted from an external system to realign input video data transmitted from an external system, and can generate data control signals DCS to be supplied to the data driver 300 and gate control signals GCS to be supplied to the gate driver 200.

[0059] For this purpose, the controller 400 may include: a data aligner 430, which realigns the input video data to generate image data Data and supplies the image data Data to the data driver 300; a control signal generator 420, which uses a timing synchronization signal to generate a gate control signal GCS and a data control signal DCS; an input unit 410, which receives the timing synchronization signal and the input video data transmitted from an external system and transmits the timing synchronization signal and the input video data to the data aligner and the control signal generator, respectively; and an output unit 440, which supplies the image data Data generated by the data aligner and the data control signal DCS generated by the control signal generator to the data driver 300, and supplies the gate control signal GCS generated by the control signal generator to the gate driver 200.

[0060] The controller 400 may include a storage unit 450 for storing various information.

[0061] The control signal generator 420 can generate a power control signal PCS for controlling the power supply 500. When the power control signal PCS is supplied to the power supply 500, the power supply 500 can supply a lock signal LOCK to at least one of the data driver ICs 310.

[0062] The data control signal DCS used to control the data driver 300 may include a lock control signal LCS for allowing a lock signal to be supplied to at least one of the data driver ICs 310.

[0063] The LOCK signal can be supplied to the data driver IC310 that has received the LOCK control signal LCS.

[0064] An external system can perform the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a TV, the external system can receive various audio, video, and text information via a communication network, and can transmit the received video information to the controller 400. In this case, the image information may include input video data.

[0065] The power supply 500 can generate various types of electricity and can supply the generated electricity to the controller 400, the gate driver 200, the data driver 300 and the display panel 100.

[0066] In addition, the power supply 500 can supply a lock signal LOCK to at least one of the data driver ICs 310 based on the control of the controller 400.

[0067] Finally, the gate driver 200 can be configured as an IC and mounted in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) type. When using the GIP type, the transistors constituting the gate driver 200 can be disposed in the non-display area using the same process as the transistors included in each pixel 110.

[0068] Gate driver 200 can supply gate pulses GP1 to GPg to gate lines GL1 to GLg. When the gate pulse generated by gate driver 200 is supplied to switching transistor Tsw1 included in pixel 110, switching transistor Tsw1 can be turned on. When switching transistor Tsw1 is turned on, data voltage supplied through data lines can be supplied to pixel 110. When a gate cutoff signal generated by gate driver 200 is supplied to switching transistor Tsw1, switching transistor Tsw1 can be turned off. When switching transistor Tsw1 is turned off, data voltage can no longer be supplied to pixel 110. The gate signal GS supplied to gate line GL can include the gate pulse GP and the gate cutoff signal.

[0069] Figure 4 This is an exemplary view showing a display panel applied to a display device according to the present disclosure. Reference will be made below. Figure 4 The normal mode and low-power Tx drive (LPTD) mode applied in this disclosure are described.

[0070] Specifically, in the following description, such as Figure 4 As shown, the normal mode and LPTD mode will be described with reference to the display panels shown as quadrilaterals 131 to 134 and circle 135.

[0071] First, the normal mode can represent the period during which the controller 400 transmits image data to the full data driver IC 310 to display the image.

[0072] For example, different data voltages should be output to pixels connected to gate lines located in region A1 in order to demonstrate... Figure 4 The circle 135 in the middle. Therefore, the controller 400 should supply image data Data corresponding to area A1 to all data driver ICs 310.

[0073] Therefore, region A1 can correspond to the normal mode.

[0074] Second, the LPTD mode can represent the period during which the controller 400 does not transmit multiple image data to the full data driver IC 310.

[0075] For example, the same image data (Data) can correspond to the setting only when set. Figure 4Gate lines in region B1 of quadrilaterals 131 to 134 and circle 135, specifically the left side line 132 and the right side line 133.

[0076] In other words, when the nth to mth gate lines (where n is a natural number and m is a natural number greater than n) are located in region B1, the image data Data corresponding to the nth to mth gate lines can be the same. For additional description, the multiple image data Data corresponding to the nth gate line, the multiple image data Data corresponding to the (n+1)th gate line, and the multiple image data Data corresponding to the mth gate line can be the same.

[0077] In this case, the controller 400 can supply the data driver IC 310 with multiple image data Data corresponding to the nth gate line, but not with multiple image data Data corresponding to the (n+1)th gate line and multiple image data Data corresponding to the mth gate line.

[0078] To this end, the controller 400 can analyze all input video data received from the external system and determine, based on the analysis results, that multiple image data Data corresponding to the nth to mth gate lines are the same. When it is determined that the multiple image data Data corresponding to the nth to mth gate lines are the same, as described above, the controller 400 can supply the multiple image data Data corresponding to the nth gate line to the data driver IC 310, but not supply the multiple image data Data corresponding to the (n+1)th gate line and the multiple image data Data corresponding to the mth gate line to the data driver IC 310.

[0079] In this case, the data voltage Vdata corresponding to the nth gate line can be stored in a buffer included in the data driver IC 310. The data voltage Vdata corresponding to the nth gate line can correspond to multiple image data Data corresponding to the nth gate line.

[0080] When a gate pulse is supplied to gate lines n through m, the data driver IC 310 can continuously output multiple image data Data stored in the buffer. Therefore, the images corresponding to gate lines n through m can be identical, and thus the left side line 132 and the right side line 133 of the quadrilateral can be shown in region B2.

[0081] Therefore, region B2 can correspond to the LPTD pattern.

[0082] It is possible Figure 4This operation is performed in the same way in region B1 shown. Therefore, region B1 can also correspond to the LPTD mode.

[0083] In other words, in LPTD mode, the same image data (Data) does not need to be transmitted from controller 400 to data driver IC 310. Therefore, the power consumption of a display device using LPTD mode can be reduced compared to the power consumption of a display device without LPTD mode.

[0084] The upper side line 131 of the quadrilateral is shown at the upper end of region B1. In this case, the upper side line 131 of the quadrilateral can be shown in normal mode.

[0085] The lower edge line 134 of the quadrilateral is shown at the lower end of region B2. That is, the lower edge line 134 of the quadrilateral is shown in the region corresponding to the (m+1)th gate line. The lower edge line 134 of the quadrilateral shown at the lower end of region B2 may be different from the left edge line 132 and the right edge line 133 of the quadrilateral shown in region B2.

[0086] Therefore, the controller 400 should supply the data driver IC 310 with multiple image data Data (i.e., multiple image data Data corresponding to the (m+1)th gate line) for illustrating the lower side line 134 of the quadrilateral. Therefore, the region A2 located at the lower end of region B2 can correspond to the normal mode.

[0087] In normal mode, power supply 500 can transmit a lock signal LOCK to at least one of the data driver ICs 310 based on the control of controller 400.

[0088] In LPTD mode, power supply 500 can, based on the control of controller 400, not transmit the lock signal LOCK to data driver IC 310. That is, in LPTD mode, multiple image data (Data) can be withheld from controller 400 to data driver IC 310, and the lock signal LOCK can be withheld from power supply 500 to data driver IC 310.

[0089] However, when switching from LPTD to normal mode, power supply 500 can transmit a lock signal LOCK to at least one of the data driver ICs 310 based on the control of controller 400.

[0090] In other words, the image corresponding to region B2 can be displayed, and immediately before the lower quadrilateral line 134 of the quadrilateral is shown in the region corresponding to the (m+1)th gate line, the lock signal LOCK can be supplied to the data driver IC 310 again. After the lock signal LOCK is supplied, the lower quadrilateral line 134 of the quadrilateral can be displayed in the display panel 100.

[0091] When switching from normal mode to LPTD mode, if the LOCK signal, which is not supplied in LPTD mode, is supplied to the data driver IC 310, the transmission speed of the LOCK signal may be reduced due to parasitic capacitance generated in the data driver IC and in the lines through which the LOCK signal is transmitted. Therefore, a delay in the LOCK signal occurs.

[0092] When a delay occurs in the lock signal, the timing of transmitting multiple image data Data corresponding to the (m+1)th gate line to the data driver IC 310 may be delayed. Therefore, in display devices of the related art, the quadrilateral lower side line 134 may not be shown in the region corresponding to the m-th gate line.

[0093] However, in the display device according to this disclosure, the lock signal LOCK can be activated without delay when switching from LPTD mode to normal mode. Therefore, in the display device according to this disclosure, the lower quadrilateral line 134 can be accurately shown in the region corresponding to the (m+1)th gate line.

[0094] The following section describes the structure and method for preventing delays in the LOCK signal.

[0095] Figure 5 and Figure 6 This is an exemplary view illustrating the structure of each data driver IC applied to a display device according to this disclosure. Figure 5 and Figure 6 In the accompanying drawings, reference numerals 311, 312, 313, and 314 denote data driver ICs. That is, 310 represents the general name for the data driver IC, and 311, 312, 313, and 314 represent the first through fourth data driver ICs. Furthermore, the elements represented by 311a, 312a, 313a, and 314a can be logic circuit units included in the first through fourth data driver ICs 311 and 314. Each of the logic circuit units 311a, 312a, 313a, and 314a can perform the basic functions of the data driver IC 310. That is, the logic circuit units 311a, 312a, 313a, and 314a can perform the function of outputting data voltage to the data lines. The logic circuit units 311a, 312a, 313a, and 314a can be initialized or synchronized by a lock signal LOCK. Furthermore, Figure 5 and Figure 6 The reference numeral PC shown in the figure can represent the parasitic capacitance generated in the line through which the lock signal LOCK is transmitted.

[0096] The display device according to this disclosure may include a display panel 100 including data lines DL1 to DLd, a first data driver IC to an nth data driver IC (where n is a natural number greater than 1) transmitting a data voltage Vdata to the data lines DL1 to DLd, a controller 400 controlling the first data driver IC to the nth data driver IC, and a power supply 500 supplying power to the first data driver IC to the nth data driver IC.

[0097] In other words, the data driver 300 may include a first data driver IC to an nth data driver IC. In the following text, for ease of description, as... Figure 5 and Figure 6 As shown, a display device equipped with four data driver ICs 310 is described as an example of this disclosure. The four data driver ICs 310 may include a first data driver IC 311 to a fourth data driver IC 314. That is, in the following description, n can be 4.

[0098] First, refer to Figure 5 This disclosure is described.

[0099] First, the first data driver IC 311 may include a lock signal switch unit 320 that receives or blocks the lock signal LOCK from the power supply 500. Furthermore, a pull-up resistor Rpu may be provided between the second data driver IC 312 and the lock signal line 510 (from which the lock signal LOCK is supplied from the power supply 500).

[0100] In this configuration, the LOCK signal supplied to the first data driver IC 311 or the second data driver IC 312 can be transmitted to the controller 400 via the first data driver IC 311 to the fourth data driver IC 314. The LOCK signal can be a high voltage VCC generated by the power supply 500.

[0101] For example, the LOCK signal supplied to the second data driver IC 312 can be supplied to the first data driver IC 311 and the third data driver IC 313, and the LOCK signal supplied to the third data driver IC 313 can be supplied to the fourth data driver IC 314. The LOCK signal supplied to the fourth data driver IC 314 can be supplied to the controller 400.

[0102] Furthermore, the lock signal LOCK supplied to the first data driver IC 311 can be supplied to the fourth data driver IC 314 through the second data driver IC 312 and the third data driver IC 313, and the lock signal LOCK supplied to the fourth data driver IC 314 can be supplied to the controller 400.

[0103] In normal mode, the LOCK signal can be transmitted to the second data driver IC 312. In LPTD mode, as mentioned above... Figure 4 The lock signal LOCK may not be transmitted to the first data driver IC 311 to the fourth data driver IC 314.

[0104] In normal mode, the LOCK signal supplied to the second data driver IC 312 can be supplied to the first data driver IC 311 and the third data driver IC 313, the LOCK signal supplied to the third data driver IC 313 can be supplied to the fourth data driver IC 314, and the LOCK signal supplied to the fourth data driver IC 314 can be supplied to the controller 400.

[0105] As described above, the normal mode can represent a period or pattern in which multiple image data are transmitted from the controller 400 to the first data driver IC 311 to the fourth data driver IC 314.

[0106] The LPTD mode can represent a period or pattern during which multiple image data are not transmitted to the first data driver IC 311 through the fourth data driver IC 314.

[0107] Therefore, in LPTD mode, the display panel can display the same image. For example, in LPTD mode, as in Figure 4 In region B2, left line 132 and right line 133 with the same shape can be shown.

[0108] After LPTD mode and before the start of normal mode, the LOCK signal can be transmitted to the first data driver IC 311 and the second data driver IC 312.

[0109] The transmission speed of the lock signal LOCK transmitted via the first data driver IC 311 to the fourth data driver IC 314 after LPTD mode and before the start of normal mode can be faster than the transmission speed of the lock signal LOCK transmitted to the first data driver IC 311 to the fourth data driver IC 314 in normal mode.

[0110] This is because after LPTD mode and before the start of normal mode, the lock signal LOCK is supplied to the first data driver IC 311 through the lock signal switch unit 320 contained in the first data driver IC 311.

[0111] The lock signal switching unit 320 may include a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) Tlock.

[0112] The current transfer speed in a PMOSFET Tlock can be faster than that in an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) and various other transistors.

[0113] Therefore, the transmission speed of the lock signal LOCK from the lock signal switch unit 320 can be faster than the transmission speed of the lock signal LOCK supplied to the second data driver IC 312 through the pull-up resistor Rpu.

[0114] Therefore, the lock signal LOCK supplied by the first data driver IC 311 after LPTD mode and before the start of normal mode can be transmitted to the controller 400 earlier than the lock signal LOCK transmitted to the controller 400 by the second data driver IC 312 in normal mode.

[0115] Therefore, after LPTD mode and before the start of normal mode, the LOCK signal can be transmitted to the controller 400, so that the display panel can display images normally in normal mode after LPTD mode.

[0116] Finally, the PMOSFET Tlock that constitutes the lock signal switch unit 320 can be turned on or off by the lock control signal LCS transmitted from the controller 400.

[0117] For this purpose, the gate of the PMOSFET Tlock can be connected to the controller 400, and the lock control signal LCS can be supplied to the gate of the PMOSFET Tlock.

[0118] In other words, when a latching control signal LCS is supplied to turn on the PMOSFET Tlock, the latching signal LOCK can be supplied to the first data driver IC 311, and when a latching control signal LCS is supplied to turn off the PMOSFET Tlock, the latching signal LOCK may not be supplied to the first data driver IC 311.

[0119] In this configuration, the PMOSFET Tlock can be turned on after the LPTD mode and before the start of the normal mode. Therefore, the lock signal LOCK transmitted via the PMOSFET Tlock can be quickly transmitted to the controller 400 via the fourth data driver IC 314.

[0120] Secondly, refer to Figure 6 This disclosure is described.

[0121] As described above, in this disclosure, the lock signal LOCK transmitted through the lock signal switch unit 320 can be quickly transmitted to the controller 400 after the LPTD mode and before the start of the normal mode. Therefore, in the normal mode after the LPTD mode, the display panel can display images normally.

[0122] The locking signal switch unit 320 that performs the above functions may be further included in at least one of the third data driver IC 313 and the fourth data driver IC 314. The locking signal switch unit further included in at least one of the third data driver IC 313 and the fourth data driver IC 314 may be referred to as the auxiliary locking signal switch unit 321.

[0123] In other words, the auxiliary lock signal switch unit 321 that receives or blocks the lock signal LOCK can be further included in at least one of the third data driver IC 313 and the fourth data driver IC 314, and the configuration and function of the auxiliary lock signal switch unit 321 can be the same as the configuration and function of the lock signal switch unit 320.

[0124] Therefore, the auxiliary lock signal switch unit 321 can be a PMOSFET Tlock, and the PMOSFET Tlock can be turned on or off by the lock control signal LCS.

[0125] The delay of the LOCK signal supplied after LPTD mode and before the start of normal mode can be further reduced by the auxiliary LOCK signal switching unit 321. Therefore, the display panel can display images normally in normal mode after LPTD mode.

[0126] Figure 7 and Figure 8 This is another exemplary view illustrating the structure of each data driver IC applied to a display device according to the present disclosure. In the following description, brief descriptions are omitted or will be referenced above. Figures 1 to 6 The details described are the same or similar.

[0127] The display device according to this disclosure may include a display panel 100, the display panel 100 including data lines DL1 to DLd, a first data driver IC to an nth data driver IC (where n is a natural number greater than 1) for supplying a data voltage Vdata to the data lines DL1 to DLd, a controller 400 for controlling the first data driver IC to the nth data driver IC, and a power supply 500 for supplying power to the first data driver IC to the nth data driver IC.

[0128] In other words, the data driver 300 may include a first data driver IC to an nth data driver IC. In the following text, for ease of description, as... Figure 7 and Figure 8 As shown, a display device equipped with four data driver ICs 310 is described as an example of this disclosure. The four data driver ICs 310 may include a first data driver IC 311 to a fourth data driver IC 314. That is, in the following description, n can be 4.

[0129] First, refer to Figure 7 This disclosure is described.

[0130] A pull-up resistor Rpu can be provided between the second data driver IC 312 and the lock signal line 510 (the lock signal LOCK is supplied from the power supply 500 to the lock signal line 510), and a current source 330 connected to the pull-up resistor Rpu can be included in the second data driver IC 312.

[0131] In this case, the LOCK signal supplied to the second data driver IC 312 can be transmitted to the controller 400 through the first data driver IC 311, the third data driver IC 313, and the fourth data driver IC 314.

[0132] The current source 330 can increase the current of the lock signal LOCK, so that the lock signal LOCK supplied to the second data driver IC 312 can be quickly transmitted to the controller 400.

[0133] Therefore, after LPTD mode and before the start of normal mode, the LOCK signal can be quickly transmitted to the controller 400, so the display panel can display images normally in normal mode after LPTD mode.

[0134] For additional description, when the current magnitude of the lock signal LOCK is increased through the current source 330, the RC delay caused by the resistance and parasitic capacitance generated in the line through which the lock signal LOCK is transmitted can be reduced, thus enabling the lock signal LOCK to be transmitted quickly.

[0135] Specifically, according to Figure 7 The present disclosure, as shown, can improve the transmission speed of the lock signal LOCK supplied in normal mode, in addition to the lock signal LOCK supplied after LPTD mode and before the start of normal mode.

[0136] In this case, the current level based on current source 330 can be set differently based on the transmission speed of the lock signal LOCK supplied after LPTD mode and before the start of normal mode.

[0137] In other words, the current level based on current source 330 can be set based on the timing of the initial output data voltage in normal mode after LPTD mode. Based on the current level based on current source 330 set according to the timing of the initial output data voltage in normal mode after LPTD mode, the delay of the LOCK signal supplied after LPTD mode and before the start of normal mode can be avoided, therefore, the image can be displayed normally in normal mode after LPTD mode.

[0138] Secondly, refer to Figure 8 This disclosure is described.

[0139] like Figure 8 As shown, the second data driver IC 312 may include a variable resistor unit 340, which controls the magnitude of the current through the current source 330.

[0140] The variable resistor unit 340 can be configured with a variable resistor.

[0141] The resistance value of the variable resistor unit 340 can be changed by the variable resistor control signal RCS transmitted from the controller.

[0142] The resistance value of the variable resistor unit 340 after LPTD mode and before the start of normal mode can be less than the resistance value of the variable resistor unit 340 in normal mode.

[0143] Therefore, after the LPTD mode and before the start of the normal mode, the controller 400 can transmit a variable resistor control signal RCS to the variable resistor unit 340 to reduce the resistance value of the variable resistor unit 340, so that the resistance value of the variable resistor unit 340 can be less than the resistance value of the variable resistor unit 340 in the normal mode.

[0144] After the LPTD mode and before the start of the normal mode, when the resistance value of the variable resistor unit 340 decreases, a current greater than the current flowing through the current source 330 and the variable resistor unit 340 in the normal mode can be transmitted to the controller 440 through the second data driver IC 312.

[0145] Therefore, based on the reference Figure 7 The principle described is that the lock signal LOCK supplied after LPTD mode and before the start of normal mode can be transmitted to the controller 400 faster than the lock signal LOCK supplied in normal mode.

[0146] Therefore, the image can be displayed normally in the normal mode following the LPTD mode.

[0147] To provide additional descriptions, such as Figure 7As shown, in a display device that includes only current source 330, the transmission speed of the lock signal LOCK supplied in normal mode can be increased, in addition to the transmission speed of the lock signal LOCK supplied after LPTD mode and before the start of normal mode. However, in this case, due to the increase in the total supplied current, the power consumption of the display device may increase more than that of display devices in related technologies.

[0148] However, in Figure 8 In the display device shown, by changing the resistance value of the variable resistor unit 340, the current of the lock signal LOCK supplied in normal mode can be set to be less than the current of the lock signal LOCK supplied after LPTD mode and before the start of normal mode. Therefore, the power consumption in normal mode can be the same as that in related technologies.

[0149] Furthermore, the current magnitude of the lock signal LOCK supplied after LPTD mode and before the start of normal mode can be set to be greater than the current magnitude of the lock signal LOCK supplied in normal mode, thus reducing the delay of the lock signal LOCK supplied after LPTD mode and before the start of normal mode.

[0150] Therefore, the image can be displayed normally in the normal mode following the LPTD mode.

[0151] Furthermore, in the display device according to this disclosure, the current source 330 and the variable resistor unit 340 performing the above-described functions may be further included in at least one of the first data driver IC 311, the third data driver IC 313, and the fourth data driver IC 314. The current source and the variable resistor unit further included in at least one of the first data driver IC 311, the third data driver IC 313, and the fourth data driver IC 314 may be referred to as an auxiliary current source and an auxiliary variable resistor unit, respectively.

[0152] In other words, the auxiliary current source connected to the lock signal line 510 that receives the lock signal LOCK and the auxiliary variable resistor unit for controlling the magnitude of the current through the auxiliary current source can be included in at least one of the first data driver IC 311, the third data driver IC 313 and the fourth data driver IC 314.

[0153] The auxiliary current source and auxiliary variable resistor unit can further reduce the delay of the lockout signal LOCK supplied after LPTD mode and before the start of normal mode, so that the image can be displayed normally in normal mode after LPTD mode.

[0154] Figure 9This is another exemplary view illustrating the structure of each data driver IC applied to a display device according to the present disclosure. In the following description, brief descriptions related to the above references are omitted or will be omitted. Figures 1 to 8 The details described are the same or similar.

[0155] The above reference Figure 5 The described locking signal switch unit 320 and the above reference Figure 8 The described current source 330 and variable resistor unit 340 can both be applied to a display device.

[0156] That is to say, in the display device according to this disclosure, such as Figure 9 As shown, the lock signal switch unit 320 can be included in the first data driver IC 311, and the current source 330 and the variable resistor unit 340 can be included in the second data driver IC 312.

[0157] Furthermore, the auxiliary lock signal switch unit 321 may be further included in at least one of the third data driver IC 313 and the fourth data driver IC 314.

[0158] Furthermore, an auxiliary current source and an auxiliary variable resistor unit may be further included in at least one of the third data driver IC 313 and the fourth data driver IC 314.

[0159] Furthermore, the auxiliary lock signal switch unit 321 may be further included in the third data driver IC 313, and the auxiliary current source and auxiliary variable resistor unit may be further included in the fourth data driver IC 314.

[0160] Furthermore, the auxiliary current source and auxiliary variable resistor unit can be further included in the third data driver IC 313, and the auxiliary lock signal switch unit 321 can be further included in the fourth data driver IC 314.

[0161] In other words, in this disclosure, the delay of the lock signal LOCK supplied after the LPTD mode and before the start of the normal mode can be reduced by at least one of the data driver IC 310 including the lock signal switch unit 320 and the data driver IC 310 including the current source 330 and the variable resistor unit 340, so that the image can be displayed normally in the normal mode after the LPTD mode.

[0162] Figure 10 This is an exemplary view illustrating a driving method for a display device according to the present disclosure. In the following description, brief descriptions referenced above are omitted or omitted. Figures 1 to 9 The details described are the same or similar.

[0163] First, when the display device is turned on, the lock signal LOCK can be supplied to the second data driver IC 312, and the lock signal LOCK can be transmitted through the nth data driver IC.

[0164] When the LOCK signal is received normally, normal mode can be started, and the display panel can then display an image.

[0165] In normal mode Figure 5 The lock signal switch unit 320 shown can be turned off, and Figure 8 The resistance value of the variable resistor unit 340 shown can be the maximum value.

[0166] When multiple image data or multiple input image data corresponding to the nth to mth gate lines are the same, the display device can switch from normal mode to LPTD mode.

[0167] In LPTD mode, multiple image data are not transmitted from controller 400 to data driver IC 310, and data driver IC 310 can continuously output data voltages stored in the buffer. Therefore, the same image can be displayed.

[0168] Subsequently, the controller 400 can determine whether the plurality of image data (or input image data) corresponding to the m-th gate line are the same as the plurality of image data (or input image data) corresponding to the (m+1)-th gate line (602).

[0169] In other words, the controller 400 can determine whether to switch from LPTD mode to normal mode.

[0170] Subsequently, when it is determined that the mode of the display device should be switched from LPTD mode to normal mode, the controller 400 can transmit a lock control signal LCS that turns on the lock signal switch unit 320 to the lock signal switch unit 320, or it can transmit a variable resistance control signal RCS that allows the variable resistor unit 340 to have the minimum resistance value to the variable resistor unit 340.

[0171] Therefore, the lock signal switch unit 320 can be turned on, and the resistance value of the variable resistor unit 340 can be minimized (604).

[0172] When the lock signal switch unit 320 is turned on or the resistance value of the variable resistor unit 340 is at its minimum, the lock signal LOCK can be transmitted to the controller 400 through the data driver IC 310, thereby enabling the display of an image.

[0173] In other words, when the lock signal switch unit 320 is turned on or the resistance value of the variable resistor unit 340 is at its minimum, the delay of the lock signal LOCK can be reduced. Therefore, the image can be displayed normally in the normal mode after the LPTD mode.

[0174] Finally, when the predetermined time period has elapsed, the controller 400 can transmit a locking control signal LCS to the locking signal switch unit 320 to turn off, or it can transmit a variable resistor control signal RCS to the variable resistor unit 340 to maximize the resistance value of the variable resistor unit 340.

[0175] Therefore, the lock signal switch unit 320 can be turned off, and the resistance value of the variable resistor unit 340 can be maximized (606).

[0176] Here, the scheduled time period can be immediately after the image is displayed in normal mode following LPTD mode, or it can be after at least a few frames in normal mode following LPTD mode.

[0177] After a predetermined period of time, the display device can be in normal mode.

[0178] In normal mode, the lock signal will not be delayed even if it is transmitted continuously. Therefore, the image can be displayed normally.

[0179] In other words, according to this disclosure, the delay of the LOCK signal supplied after LPTD mode and before the start of normal mode can be prevented, thereby solving the problem of abnormal image display when switching from LPTD mode to normal mode.

[0180] Therefore, in this disclosure, the lock signal switch unit 320 can be turned on after the LPTD mode and before the start of the normal mode, or the resistance value of the variable resistor unit 340 can be minimized, so that the delay of the lock signal LOCK can be minimized.

[0181] According to this disclosure, the latch signal can be transmitted through a PMOSFET with a faster current transmission speed, thus preventing delay of the latch signal.

[0182] Furthermore, according to this disclosure, the magnitude of the current in the lock signal can be increased by using a current source, thereby preventing delay in the lock signal.

[0183] In other words, according to this disclosure, delays in the locking signal transmitted after LPTD mode can be prevented. Therefore, the image that should be output first after LPTD mode can be output normally, thus improving the quality of the display device.

[0184] The features, structures, and effects described above in this disclosure are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, those skilled in the art can implement the features, structures, and effects described in at least one embodiment of this disclosure by combining or modifying other embodiments. Therefore, anything related to combinations and modifications should be interpreted as falling within the scope of this disclosure.

[0185] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover any modifications and variations thereof that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: Display panel, the display panel including data cable; The first data driver IC to the nth data driver IC, that is, the first data driver IC to the nth data driver IC, supply data voltage to the data line, where n is a natural number greater than 1; Controller, the controller controls the first data driver IC to the nth data driver IC; as well as The power supply supplies power to the first data driver IC through the nth data driver IC. The first data driver IC includes a lock signal switch unit, which receives or blocks a lock signal from the power supply. A pull-up resistor is provided between the second data driver IC and the lock signal line, wherein the lock signal is supplied from the power supply to the lock signal line, and The lock signal supplied to the first data driver IC or the second data driver IC is transmitted to the controller via the first data driver IC to the nth data driver IC.

2. The display device according to claim 1, wherein, In normal mode, the lock signal is transmitted to the second data driver IC. In low-power Tx drive mode, i.e., LPTD mode, the lock signal is not transmitted to the first data driver IC to the nth data driver IC, and After the LPTD mode and before the start of the normal mode, the lock signal is transmitted to the first data driver IC and the second data driver IC.

3. The display device according to claim 2, wherein, In the normal mode, multiple image data are transmitted from the controller to the first data driver IC through the nth data driver IC, and In the LPTD mode, multiple image data are not transmitted from the controller to the first data driver IC to the nth data driver IC.

4. The display device according to claim 3, wherein, In the LPTD mode, the display panel displays the same image.

5. The display device according to claim 2, wherein, The transmission speed of the lock signal transmitted from the first data driver IC to the nth data driver IC after the LPTD mode and before the start of the normal mode is faster than the transmission speed of the lock signal transmitted from the first data driver IC to the nth data driver IC in the normal mode.

6. The display device according to claim 1, wherein, The lock signal switching unit includes a P-type metal-oxide-semiconductor field-effect transistor, i.e., a PMOSFET.

7. The display device according to claim 6, wherein, The PMOSFET is turned on or off by a latching control signal transmitted from the controller.

8. The display device according to claim 7, wherein, The PMOSFET turns on after LPTD mode and before the start of normal mode. In the normal mode, multiple image data are transmitted from the controller to the first data driver IC through the nth data driver IC, and In the LPTD mode, multiple image data are not transmitted from the controller to the first data driver IC to the nth data driver IC.

9. The display device according to claim 1, wherein, At least one of the third to the nth data driver ICs includes an auxiliary lock signal switch unit, which receives or blocks the lock signal.

10. The display device according to claim 9, wherein, The auxiliary lock signal switching unit includes a P-type metal-oxide-semiconductor field-effect transistor, i.e., a PMOSFET.

11. The display device according to claim 1, wherein, The second data driver IC includes: A current source, the current source being connected to the pull-up resistor; and A variable resistor unit that controls the magnitude of the current passing through the current source.

12. The display device according to claim 11, wherein, At least one of the third to nth data driver ICs includes: An auxiliary current source, the auxiliary current source being connected to an auxiliary pull-up resistor, the auxiliary pull-up resistor being connected to the lock signal line receiving the lock signal; and An auxiliary variable resistor unit controls the magnitude of the current passing through the auxiliary current source.

13. The display device according to claim 11, wherein, The resistance value of the variable resistor unit is changed by a variable resistor control signal transmitted from the controller.

14. The display device according to claim 13, wherein, The resistance value of the variable resistor unit after LPTD mode and before the start of normal mode is less than the resistance value of the variable resistor unit in normal mode. In the normal mode, multiple image data are transmitted from the controller to the first data driver IC through the nth data driver IC, and In the LPTD mode, multiple image data are not transmitted from the controller to the first data driver IC to the nth data driver IC.

15. A display device, comprising: Display panel, the display panel including data cable; The first data driver IC to the nth data driver IC, that is, the first data driver IC to the nth data driver IC, supply data voltage to the data line, where n is a natural number greater than 1; Controller, the controller controls the first data driver IC to the nth data driver IC; as well as The power supply supplies power to the first data driver IC through the nth data driver IC. A pull-up resistor is provided between the second data driver IC and the lock signal line, and the lock signal is supplied from the power supply to the lock signal line. The second data driver IC includes a current source connected to the pull-up resistor, and The lock signal supplied to the second data driver IC is transmitted to the controller via the first data driver IC and the third data driver IC to the nth data driver IC.

16. The display device according to claim 15, wherein, The second data driver IC includes a variable resistor unit that controls the magnitude of the current passing through the current source.

17. The display device according to claim 16, wherein, The resistance value of the variable resistor unit is changed by a variable resistor control signal transmitted from the controller.

18. The display device according to claim 17, wherein, The resistance value of the variable resistor unit after LPTD mode and before the start of normal mode is less than the resistance value of the variable resistor unit in normal mode. In the normal mode, multiple image data are transmitted from the controller to the first data driver IC through the nth data driver IC, and In the LPTD mode, multiple image data are not transmitted from the controller to the first data driver IC to the nth data driver IC.

19. The display device according to claim 15, wherein, The first data driver IC and at least one of the third to nth data driver ICs include: An auxiliary current source, the auxiliary current source being connected to an auxiliary pull-up resistor, the auxiliary pull-up resistor being connected to the lock signal line receiving the lock signal; and An auxiliary variable resistor unit controls the magnitude of the current passing through the auxiliary current source.

20. The display device according to claim 15, wherein, The first data driver IC includes a lock signal switch unit, which is used to receive or block the lock signal.

Images