Gate driver, display device including the same, and method of operating the gate driver

Abstract

A gate driver, a display including the same, and a method for operating the gate driver are provided. The gate driver includes a plurality of stages for sequentially providing a gate signal to a plurality of gate lines, each stage including: an input circuit for receiving an (n-1)th gate signal transmitted through an (n-1)th gate line and a gate clock signal, and applying a first voltage and a second voltage having a polarity opposite to that of the first voltage to Q and QB nodes, respectively; an output circuit for generating an nth gate signal by outputting a low voltage corresponding to the first voltage or a high voltage corresponding to the second voltage, and outputting the generated nth gate signal to an nth gate line; and a stabilization capacitor disposed between the nth gate line and a high voltage source for providing the high voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0180412, filed on December 16, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display devices and methods for driving display devices, and more specifically, to display devices capable of reducing power consumption and improving the quality of displayed images, and methods for driving the display devices. Background Technology

[0004] With the development of an information-oriented society, the demand for display devices for displaying images has increased. To meet these needs, various types of display devices have been developed and utilized, such as liquid crystal displays (LCDs) and electroluminescent displays (ELDs).

[0005] ELD devices include quantum dot (QD) light-emitting display devices, inorganic light-emitting display devices, and organic light-emitting display devices.

[0006] Such a display device may include multiple pixels arranged in a matrix. Each pixel may be connected to a gate line and a data line, and displays an image by sequentially receiving data signals in response to a gate signal. Summary of the Invention

[0007] The circuitry of each pixel in a display device is becoming increasingly complex. Furthermore, ripple in the gate signal provided through the gate lines by parasitic capacitors can degrade image quality. In particular, in the case of electroluminescent display devices, image quality degradation can be prevented by allowing the pixel to emit light after compensating for the difference in threshold voltages of the driving transistors included in the pixel. Gate lines included in a display device are susceptible to noise and drive signals, and ripple is thus prone to appear in the gate signal transmitted through the gate lines. To address these problems, embodiments of this disclosure provide a display device capable of preventing or reducing ripple and image quality degradation that may occur in the gate signal, as well as a method for driving the display device.

[0008] The implementation methods and examples of this disclosure discussed below are not limited to solving the problems described above, and other problems not described above will become apparent to those skilled in the art from the following detailed description.

[0009] According to one aspect of this disclosure, a gate driver is provided, comprising multiple stages for sequentially providing gate signals to multiple gate lines. Each of the multiple stages includes: an input circuit for receiving a (n-1)th gate signal and a gate clock signal transmitted through a (n-1)th gate line, and applying a first voltage and a second voltage with a polarity opposite to the first voltage to a Q node and a QB node, respectively; an output circuit for generating an nth gate signal by outputting a low voltage or a high voltage corresponding to the first voltage and the second voltage, and outputting the generated nth gate signal to the nth gate line; and a stabilizing capacitor disposed between the nth gate line and a high voltage source for providing the high voltage.

[0010] According to one aspect of this disclosure, a display device is provided, the display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, a plurality of emitter lines, and a plurality of pixels connected to the plurality of data lines, the plurality of gate lines, and the plurality of emitter lines; a data driver for applying a data signal to the plurality of data lines when connected to the plurality of data lines; and a gate driver for applying a gate signal and an emitter signal to the plurality of gate lines and the plurality of emitter lines respectively when connected to the plurality of gate lines and the plurality of emitter lines. The gate driver includes multiple stages for sequentially providing gate signals to multiple gate lines, and each of the multiple stages includes: an input circuit for receiving a (n-1)th gate signal and a gate clock signal transmitted through the (n-1)th gate line, and applying a first voltage and a second voltage with the opposite polarity to the first voltage to the Q node and the QB node, respectively; an output circuit for generating an nth gate signal by outputting a low voltage or a high voltage corresponding to the first voltage and the second voltage, and outputting the generated nth gate signal to the nth gate line; and a stabilizing capacitor disposed between the nth gate line and a high voltage source for providing the high voltage.

[0011] According to embodiments of this disclosure, a display device can be provided that can reduce or prevent image quality degradation by reducing or preventing ripple that may occur in the gate signal.

[0012] The effects of implementing the embodiments of this disclosure are not limited to those mentioned above. Furthermore, the embodiments of this disclosure are not limited to those described above, and other additional embodiments, including variations thereof, will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0013] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate various aspects of this disclosure and, together with the specification, serve to illustrate the principles of this disclosure. In the drawings:

[0014] Figure 1 The system configuration of the display device according to various aspects of this disclosure is shown;

[0015] Figure 2 It is a circuit diagram of pixels used in a display device according to various aspects of this disclosure;

[0016] Figure 3A and Figure 3B It shows in Figure 1 The display panel used in the display device displays the image;

[0017] Figure 4 Is only shown Figure 2 The diagram shows a partial circuit diagram of the connection between the driving transistor, the first transistor, and the second transistor included in the pixel.

[0018] Figure 5 It is a timing diagram showing the waveforms of the first gate signal and the second gate signal applied to the pixel;

[0019] Figure 6 Gate drivers according to various aspects of this disclosure are shown;

[0020] Figure 7 It shows Figure 6 One of the multiple levels shown in the figure;

[0021] Figure 8 It is shown Figure 6 The circuit diagram of the stage shown in the figure; and

[0022] Figure 9A and Figure 9B This shows the input to Figure 8 The waveforms of the example gate signal and example gate clock signal for the stage are shown in the figure. Detailed description

[0023] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. The embodiments set forth below are described in the context of specific embodiments and are provided only to fully disclose this disclosure and to inform those skilled in the art to which embodiments of this disclosure belong. However, it will be understood that these embodiments can be implemented in various different forms, and in turn, many variations, modifications, additions, and improvements are possible. Therefore, the scope of this disclosure is not limited to the embodiments described below and should be defined by the scope of the appended claims.

[0024] The shapes, sizes, ratios, angles, numbers, etc., shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally denote similar elements. In the following description, detailed descriptions of well-known functions and configurations incorporated herein will be omitted where it is determined that such detailed descriptions may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “consisting of,” and “made up of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless the context clearly indicates otherwise, the singular forms used herein are intended to include the plural forms.

[0025] In interpreting any element or feature in the implementation of this disclosure, it should be understood that any size and relative dimensions of layers, regions, and extents include tolerances or error ranges, even when no specific description is given.

[0026] In this document, spatially relative terms such as “above,” “on top,” “above,” “below,” “below,” “under,” “below,” “above,” “near,” “close to,” “adjacent,” etc., may be used to describe the relationship between one element or feature shown in the figure and another element or feature, and unless terms such as “directly” or “only” are used, it should be interpreted that one or more elements may be further “inserted” between these elements.

[0027] In this document, relative time terms such as “after,” “following,” “next,” and “before” used to describe temporal relationships between events, operations, etc., are generally intended to include events, situations, circumstances, operations, etc., that would not occur consecutively unless terms such as “directly” or “only” are used.

[0028] For example, when discussing implementations related to signal flow, an implementation of sending a signal from node A to node B may include the transmission of the signal from node A to node B through another node using terms such as "directly" or "only".

[0029] When terms such as "first," "second," etc., are used herein to describe various elements or components, it should be understood that these elements or components are not limited thereto. These terms are used only to distinguish elements from other elements. Therefore, in the technical concept of this disclosure, the first element mentioned below may be a second element.

[0030] Elements or features of the various exemplary embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be interlocked and operated in a variety of technical ways as can be fully understood by those skilled in the art, and the various exemplary embodiments may be performed independently or in association with each other.

[0031] Gate drivers according to various aspects of this disclosure include multiple stages for sequentially providing gate signals to multiple gate lines.

[0032] Each of the multiple stages may include: an input circuit for receiving a (n-1)th gate signal and a gate clock signal transmitted through the (n-1)th gate line, and applying a first voltage and a second voltage with the opposite polarity to the first voltage to the Q node and the QB node, respectively; an output circuit for generating an nth gate signal by outputting a low voltage or a high voltage corresponding to the first voltage and the second voltage, and outputting the generated nth gate signal to the nth gate line; and a stabilizing capacitor disposed between the nth gate line and a high voltage source for providing the high voltage.

[0033] The gate clock signal can be kept low during the first period of the (n-1)th gate signal with a high voltage input.

[0034] The input circuitry may include: a first input circuitry for applying a first voltage to a Q node via a gate clock signal and a (n-1)th gate signal; and a second input circuitry for applying a second voltage to a QB node in response to the (n-1)th gate signal.

[0035] The first input circuit may include a first switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the (n-1)th gate line, the Q node, and a clock signal line for transmitting the gate clock signal. The second input circuit may include: a second switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the clock signal line for transmitting the gate clock signal, the QB node, and the first node; a third switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the first node, a high voltage source, and the (n-1)th gate line; a fourth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the Q node, the high voltage source, and the QB node; and a first capacitor, which includes a first electrode and a second electrode respectively connected to the clock signal line and the first node.

[0036] The output circuit may include: a first output circuit for selectively outputting a low voltage to the nth gate line in response to a first voltage applied to the Q node; and a second output circuit for selectively outputting a high voltage to the nth gate line in response to a second voltage applied to the QB node.

[0037] The first output circuit may include a fifth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a low-voltage source, an nth gate line, and a Q node. The second output circuit may include: a sixth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a high-voltage source, an nth gate line, and a QB node; and a seventh switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the gate of the sixth switch, a high-voltage source, and a Q node.

[0038] A display device according to various aspects of this disclosure includes: a display panel including a plurality of data lines, a plurality of gate lines, a plurality of emitter lines, and a plurality of pixels connected to the plurality of data lines, the plurality of gate lines, and the plurality of emitter lines; a data driver for applying data signals to the plurality of data lines when connected to the plurality of data lines; and a gate driver for applying gate signals and emitter signals to the plurality of gate lines and the plurality of emitter lines respectively when connected to the plurality of gate lines and the plurality of emitter lines. The gate driver includes a plurality of stages for sequentially providing gate signals to the plurality of gate lines, and each of the plurality of stages may include: an input circuit for receiving a (n-1)th gate signal and a gate clock signal transmitted through a (n-1)th gate line, and applying a first voltage and a second voltage with a polarity opposite to the first voltage to a Q node and a QB node respectively; an output circuit for generating an nth gate signal by outputting a low voltage or a high voltage corresponding to the first voltage and the second voltage, and outputting the generated nth gate signal to the nth gate line; and a stabilizing capacitor disposed between the nth gate line and a high voltage source for providing the high voltage.

[0039] The gate clock signal can be kept low during the first period of the (n-1)th gate signal with a high voltage input.

[0040] The input circuitry may include: a first input circuitry for applying a first voltage to a Q node via a (n-1)th gate signal and a gate clock signal; and a second input circuitry for applying a second voltage to a QB node in response to the (n-1)th gate signal.

[0041] The first input circuit may include a first switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the (n-1)th gate line, the Q node, and a clock signal line for transmitting the gate clock signal. The second input circuit may include: a second switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the clock signal line for transmitting the gate clock signal, the QB node, and the first node; a third switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the first node, a high voltage source, and the (n-1)th gate line; a fourth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the Q node, the high voltage source, and the QB node; and a first capacitor, which includes a first electrode and a second electrode respectively connected to the clock signal line and the first node.

[0042] The output circuit may include: a first output circuit for selectively outputting a low voltage to the nth gate line in response to a first voltage applied to the Q node; and a second output circuit for selectively outputting a high voltage to the nth gate line in response to a second voltage applied to the QB node.

[0043] The first output circuit may include a fifth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a low-voltage source, an nth gate line, and a Q node. The second output circuit may include: a sixth switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a high-voltage source, an nth gate line, and a QB node; and a seventh switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the gate of the sixth switch, a high-voltage source, and a Q node.

[0044] Each of the pixels may include: a driving transistor for providing a driving current flowing from a second node to a third node in response to a voltage at a first node; a light-emitting element capable of emitting light by receiving the driving current; a storage capacitor disposed between the first node and a driving power line and capable of maintaining the voltage of the first node; a first transistor for selectively electrically connecting the first node and the third node in response to a first gate signal; a second transistor for selectively transmitting a data signal to the second node in response to a second gate signal; a third transistor for selectively transmitting a driving voltage to the second node in response to a transmission signal; a fourth transistor for electrically connecting the third node and the light-emitting element in response to a transmission signal; a fifth transistor for providing a first initialization voltage to the third node via a third gate signal; and a sixth transistor for providing a second initialization voltage to the anode electrode of the light-emitting element via a third gate signal.

[0045] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1The system configuration of the display device according to various aspects of this disclosure is shown.

[0047] Reference Figure 1 The display device 100 may include a display panel 110, a data driver 120, and a gate driver 130. The display device 100 may also include a timing controller 140.

[0048] The display panel 110 may include a plurality of data lines (DL1 to DLm) extending in a first direction and a plurality of gate lines (GL1 to GLn) extending in a second direction different from the first direction. The first direction and the second direction may be orthogonal to each other. However, embodiments of the present disclosure are not limited thereto.

[0049] Furthermore, the display panel 110 may include a plurality of pixels 101. The plurality of pixels 101 may, in response to gate signals transmitted via gate lines (GL1 to GLn), receive data signals transmitted via data lines (DL1 to DLm), enabling an image to be displayed on the display panel 110. The plurality of pixels 101 may be initialized in response to a first initialization signal and a second initialization signal.

[0050] The data driver 120 can be connected to multiple data lines (DL1 to DLm) and can provide data signals to multiple pixels 101 via the data lines (DL1 to DLm). The data driver 120 may include multiple source drivers. Each of the multiple source drivers can be implemented in an integrated circuit.

[0051] Gate driver 130 can be connected to multiple gate lines (GL1 to GLm) and can provide gate signals to the gate lines (GL1 to GLn). Data signals can be provided to pixels that provide gate signals to them via the gate lines.

[0052] although Figure 1 The diagram shows the gate driver 130 located outside the display panel 110, but embodiments of the invention are not limited thereto. For example, the gate driver 130 may be disposed within the display panel 110. Furthermore, the gate driver 130 may be disposed on the display panel 110 and include a gate signal generator for outputting one or more gate signals and one or more level shifters for providing one or more voltages and one or more clock cycles to the gate signal generator. Additionally, the gate driver 130 may be implemented using multiple integrated circuits.

[0053] although Figure 1The diagram shows a gate driver 130 located on one side or edge of the display panel 110, but embodiments of this disclosure are not limited thereto. For example, the gate driver 130 may be disposed on both sides or edges of the display panel 110, such as the left or right side or edge, the top or bottom side or edge, etc. Furthermore, a gate driver disposed on the left side or edge of the display panel 110 may be connected to odd-numbered gate lines, and a gate driver disposed on its right side or edge may be connected to even-numbered gate lines.

[0054] The gate driver 130 can sequentially provide transmit signals and initialization signals to multiple pixels.

[0055] The timing controller 140 can control the data driver 120 and the gate driver 130. The timing controller 140 can provide data control signals to the data driver 120 and data driver control signals to the gate driver 130. The data control signals and gate control signals may include clock signals, vertical synchronization signals, horizontal synchronization signals, and start pulses, etc. However, the signals provided from the timing controller 140 according to embodiments of this disclosure are not limited thereto.

[0056] The timing controller 140 can provide image signals to the data driver 120. The data driver 120 can use the image signals received from the timing controller 140 and one or more data control signals to generate data signals and output the generated data signals to the data lines (DL1 to DLm).

[0057] Figure 2 This is a circuit diagram of pixels used in a display device according to various aspects of this disclosure.

[0058] Reference Figure 2 Pixel 101 may include a driving transistor MD, a light-emitting element ED, and a storage capacitor Cst.

[0059] The driving transistor MD can generate a driving current flowing from the second node N2 to the third node N3 in response to the voltage at the first node N1. The voltage sent to the first node N1 can be obtained by adding the threshold voltage level of the driving transistor MD to the voltage level of the data signal Vdata, or by subtracting the threshold voltage level of the driving transistor MD from the voltage level of the data signal Vdata.

[0060] The driving transistor MD may have a first electrode, a second electrode, and a gate electrode connected to the second node N2, the third node N3, and the first node N1, respectively. Furthermore, a data signal Vdata can be selectively transmitted to the second node N2, and the data signal Vdata transmitted to the second node N2 can be transmitted to the first node N1 via the third node N3. The driving transistor MD may be an n-type MOS transistor.

[0061] The driving transistor MD can respond to the data signal Vdata sent to the first node N1, enabling the driving current to flow from the second node N2 to the third node N3.

[0062] The light-emitting element (ED) emits light by receiving a driving current flowing from the second node N2 to the third node N3. The ED may include an anode electrode, a cathode electrode, and an emitting layer disposed between the anode electrode and the cathode electrode.

[0063] When a low-level second driving voltage EVSS is applied to the cathode electrode of the light-emitting element ED, if a high-level voltage is applied to the anode electrode, current can flow from the anode electrode to the cathode electrode of the light-emitting element ED. The light-emitting element ED can emit light by the current flowing from the anode electrode to the cathode electrode.

[0064] The light-emitting element (ED) can be, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. When using an organic light-emitting diode as the light-emitting element (ED), its light-emitting layer (EL) can include an organic light-emitting layer containing organic materials.

[0065] The storage capacitor Cst enables the voltage at the first node N1 to be maintained. The storage capacitor Cst can be positioned between the first node N1 and the drive power line VLd used to provide the drive voltage EVDD.

[0066] Pixel 101 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

[0067] The first transistor M1 can switch the driving transistor MD to a diode-connected state. The first transistor M1 may include a first electrode, a second electrode, and a gate electrode connected to the first node N1, the third node N3, and the first gate line GL1, respectively. The first transistor M1 can be turned on / off in response to a first gate signal gate1 transmitted through the first gate line GL1.

[0068] The second transistor M2 can selectively transmit the data signal Vdata provided via the data line DL to the second node N2. The second transistor M2 may include a first electrode, a second electrode, and a gate electrode connected to the data line DL, the second node N2, and the second gate line GL2, respectively. The second transistor M2 can be turned on / off in response to a second gate signal gate2 transmitted via the second gate line GL2.

[0069] The third transistor M3 can selectively send the drive voltage EVDD to the second node N2. The third transistor M3 may include a first electrode, a second electrode, and a gate electrode respectively connected to the drive power line VLd, the second node N2, and the emitter line EML for providing the drive voltage EVDD. The third transistor M3 can be turned on / off in response to the transmit signal ems sent through the emitter line EML.

[0070] The fourth transistor M4 can selectively send the drive current flowing through the driving transistor MD to the light-emitting element ED. The fourth transistor M4 may include a first electrode, a second electrode, and a gate electrode connected to the third node N3, the anode electrode of the light-emitting element ED, and the emitter line EML, respectively. The fourth transistor M4 can be turned on / off in response to the emission signal ems transmitted through the emitter line EML.

[0071] The fifth transistor M5 can selectively send a first initialization voltage Vint1 to the third node N3. The fifth transistor M5 may include a first electrode, a second electrode, and a gate electrode respectively connected to a first initialization voltage line VL1 for sending the first initialization voltage Vint1, the third node N3, and a third gate line GL3. The fifth transistor M5 can be turned on / off in response to a third gate signal gate3 sent through the third gate line GL3. The fifth transistor M5 may have a dual-gate structure, thereby reducing leakage current and preventing voltage drops at the third node N3.

[0072] The voltage level of the first initialization voltage Vint1 can be higher than the voltage level of the drive voltage for a predefined period of time. When the first initialization voltage Vint1 with a level higher than the drive voltage is sent to the drive transistor MD, the hysteresis of the drive transistor MD can be eliminated.

[0073] The sixth transistor M6 can selectively send a second initialization voltage Vint2 to the anode electrode of the light-emitting device ED. The sixth transistor M6 may include a first electrode, a second electrode, and a gate electrode respectively connected to a second initialization voltage line VL2 for sending the second initialization voltage Vint2, the anode electrode of the light-emitting device ED, and a third gate GL3. The sixth transistor M6 can be turned on / off in response to a third gate signal gate3 sent through the third gate line GL3. The voltage level of the second initialization voltage Vint2 may be lower than the threshold voltage of the light-emitting device ED.

[0074] Here, the first transistor M1 can be a p-type MOS transistor, and the driving transistor MD and the second transistors M2 to M6 can be n-type MOS transistors, or all transistors can be either p-type or n-type MOS transistors. However, embodiments of this disclosure are not limited thereto. Furthermore, the first transistor M1 or all transistors can be oxide semiconductor transistors in which the active layer includes oxide semiconductor, and the active layer of the driving transistor MD and the second transistors M2 to M6 or all transistors can include low-temperature polysilicon.

[0075] Figure 3A and Figure 3B It shows in Figure 1 The display panel used in the display device displays the image.

[0076] Figure 3A It is shown that only gray is displayed on the entire display panel 110. Figure 3B The diagram shows black displayed in the first region (110a) and the second region (110b) of the display panel 110, and gray displayed in the third region (110c) to the fifth region (110e).

[0077] In such Figure 3A As shown, when only gray is displayed across the entire display panel 110, the overall brightness of the display panel 110 remains constant. However, when the display panel 110 displays as... Figure 3B In the case of the image shown, the third region 110c, which is set between the first region (110a) and the second region (110b) that displays black, represents a higher brightness than the fourth region (110d) or the fifth region (110e) that displays gray.

[0078] Figure 4 Is only shown Figure 2 The diagram shows a partial circuit diagram of the connection between the driving transistor, the first transistor, and the second transistor included in the pixel. Figure 5 It is a timing diagram showing the waveforms of the first gate signal and the second gate signal applied to the pixel.

[0079] Reference Figure 4 A parasitic capacitor Cp can be formed between the first node N1 and the first gate line GL1. When the first transistor M1 and the second transistor M2 are turned on in the pixel 101 disposed in the first region 110a and the third region 110c, the data signal Vdata transmitted through the data line DL can be applied to the first node N1 through the operation of the second transistor M2 and the first transistor M1.

[0080] Since the data signal Vdata provided to the pixel 101 in the first region 110a corresponds to black, and the data signal Vdata provided to the pixel 101 in the third region 110c corresponds to gray, the voltage level of the data signal provided to the pixel 101 in the first region 110a is higher than the voltage level of the data signal provided to the pixel 101 in the third region 110c.

[0081] Reference Figure 5 When the voltage corresponding to the data signal is applied to the first node N1 of pixel 101, the second gate signal gate2 has a low level, while the first gate signal gate1 has a high level. In this case, the time period during which the second gate signal gate2 remains at a low level can be as short as approximately one horizontal time period (1H).

[0082] When the data signal Vdata is applied to the first node N1 of pixel 101 through the first gate signal gate1, the voltage at the first node N1 can rise due to the data signal Vdata. At this time, the parasitic capacitor Cp can also cause the voltage on the first gate line GL1 to rise. Furthermore, the voltage on the first gate line GL1 will decrease over time. As a result, as... Figure 5 As shown, this results in ripple Vr in the first gate signal gate1.

[0083] When a data signal corresponding to black is applied to pixel 101 in the first region 110a and a data signal corresponding to gray is applied to the third region 110c, the data signal corresponding to black and the parasitic capacitor Cp cause the voltage on the first gate line GL1 in pixel 101 of the first region 110a to rise. Furthermore, the voltage on the first gate line GL1 will decrease again over time. When a data signal corresponding to gray is applied to a pixel in the third region 110c due to the decrease in voltage on the first gate line GL1, a voltage lower than a predefined voltage can be applied to the first node N1 of the pixel in the third region 110c.

[0084] Therefore, a voltage lower than a predefined voltage, namely the voltage VGS represented by the dashed line, can be applied between the gate electrode and the source electrode of the driving transistor MD.

[0085] The voltage VGS between the source and gate electrodes of the driving transistor MD of the pixel in the third region 110c is lower than a predefined voltage, causing an increase in the brightness of pixel 101. Therefore, display non-uniformity may exist, so that even if the third region 110c displays the grayscale displayed by the fourth region 110d and the fifth region 110e, the third region 110c is brighter than the fourth region 110d and the fifth region 110e.

[0086] Figure 6 Gate drivers according to various aspects of this disclosure are shown, and Figure 7 It shows Figure 6 One of the multiple levels shown.

[0087] Reference Figure 6 and Figure 7 The gate driver 130 may include multiple stages 131 that sequentially send gate signals to multiple gate lines GL.

[0088] The first stage can receive the start pulse GST and the gate clock signal GCLK, and thus output the gate signal. Furthermore, each of the remaining stages, including the second stage, can receive the previous gate signal from the gate line connected to the previous stage, and output its own gate signal using the clock signal and the previous gate signal. Therefore, multiple stages 131 can sequentially output their respective gate signals.

[0089] Furthermore, the stabilizing capacitor Cs connected to each stage 131 of the corresponding gate line enables a stable output of the gate signal from the corresponding gate line.

[0090] like Figure 7 As shown, each of the plurality of stages 131 may include: an input circuit 1311 for receiving a (n-1)th gate signal gate(n-1) and a gate clock signal GCLK provided through the (n-1)th gate line, and applying a first voltage and a second voltage having a polarity different from the first voltage to Q node Q and QB node QB, respectively; an output circuit 1312 for generating an nth gate signal gate(n) by outputting a low voltage or a high voltage corresponding to the first voltage and the second voltage, and outputting the generated nth gate signal gate(n) to the nth gate line GL(n); and a stabilizing capacitor Cs disposed between the nth gate line GL(n) and the output circuit 1312.

[0091] Multiple gate lines can be disposed in the display device and include a (n-1)th gate line and an nth gate line. The (n-1)th gate line can be the gate line to which the (n-1)th gate signal gate(n-1) output from the (n-1)th stage of the multiple stages is output, and the nth gate line can be the gate line to which the nth gate signal gate(n) output from the nth stage of the multiple stages is output.

[0092] Because the stabilizing capacitor maintains a high voltage on the gate line GL, the gate signal can be stably driven on the gate line GL, thus effectively preventing ripple in the gate signal. Therefore, as... Figure 5 As shown, this can prevent or reduce the increase in brightness in the third region 110c.

[0093] Figure 8 It is shown Figure 6 The circuit diagram of the stage is shown in the figure.

[0094] Reference Figure 7 and Figure 8 Stage 131 may include: a first input circuit 1311a for enabling a first voltage to be applied to Q node Q via a gate clock signal GCLK and a (n-1)th gate signal gate(n-1); and a second input circuit 1311b for enabling a second voltage to be applied to QB node QB in response to the (n-1)th gate signal gate(n-1). The first voltage and the second voltage may have opposite polarities. Therefore, when the first voltage is high, the second voltage may be low, and when the first voltage is low, the second voltage may be high.

[0095] In addition, stage 131 may include: a first output circuit 1312a, which is used to selectively output a low voltage VGL to the nth gate line in response to a first voltage sent to the Q node Q; and a second output circuit 1312b, which is used to selectively output a high voltage VGH to the nth gate line in response to a second voltage sent to the QB node QB.

[0096] The first input circuit 1311a may include a first switch SW1, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a (n-1)th gate line for providing a (n-1)th gate signal gate(n-1), a Q node Q, and a clock signal line for providing a gate clock signal GCLK. Here, the (n-1)th gate signal gate(n-1) may be a gate signal output from the previous stage.

[0097] The second input circuit 1311b may include: a second switch SW2, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a clock signal line for providing the gate clock signal GCLK, a QB node QB, and a first node N11; a third switch SW3, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the first node N11, a high voltage source VGH, and the (n-1)th gate line; a fourth switch SW4, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a Q node Q, a high voltage source VGH for providing a high voltage, and a QB node QB; and a first capacitor C1, which includes a first electrode and a second electrode respectively connected to the clock signal line for providing the gate clock signal GCLK and the gate electrode of the second switch SW2.

[0098] The first output circuit 1312a may include: a fifth switch SW5, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a low-voltage source for providing a low voltage VGL, an nth gate line, and a Q node Q. The second output circuit 1312b may include: a sixth switch SW6, which includes a first electrode, a second electrode, and a gate electrode respectively connected to a high-voltage source for providing a high voltage VGH, an nth gate line, and a QB node QB; and a seventh switch SW7, which includes a gate electrode respectively connected to the sixth switch SW6, a high-voltage source for providing a high voltage VGH, and a first electrode, a second electrode, and a gate electrode respectively connected to the Q node Q.

[0099] The nth gate line GL(n) refers to the line used to supply the nth gate signal gate(n) output at this stage. Figure 2 The gate line of pixel 101 is shown in the figure. The nth gate signal gate(n) refers to the gate line applied to the pixel. Figure 2 The gate signal of the gate electrode of the first transistor M1 of pixel 101 is shown in the figure.

[0100] The first switch (SW1) through the seventh switch (SW7) can be, for example, an n-type MOS transistor. The active layer of the first switch (SW1) through the seventh switch (SW7) can include, for example, low-temperature polysilicon.

[0101] Figure 9A and Figure 9B This shows the input to Figure 8 The waveforms of the example gate signal and example gate clock signal for the stage are shown in the figure.

[0102] Reference Figure 9AStage 130 can receive the (n-1)th gate signal G(n-1) with a low level in the first time period T1, the (n-1)th gate signal with a high level in the second time period T2, and the (n-1)th gate signal G(n-1) with a low level in the third time period T3. Furthermore, in each of the first time period (T1) to the third time period (T3), the gate clock signal GCLK can repeat the high and low levels multiple times.

[0103] During the first time period T1, a (n-1)th gate signal G(n-1) with a low level can be provided. The gate clock signal GCLK can repeat low and high levels once or more. When the gate clock signal GCLK is low, the first switch SW1 can be turned on. When the first switch SW1 is turned on, a first voltage with a low level can be applied to the Q node Q through the (n-1)th gate signal G(n-1).

[0104] When a low-level (n-1)th gate signal G(n-1) is applied to the gate electrode of the third switch SW3, the third switch SW3 can be turned on. When the third switch SW3 is turned on, a high voltage VGH can be sent to the gate of the second switch SW2. The second switch SW2 is in the off state.

[0105] When a first voltage with a low level is applied to Q node Q, the fifth switch SW5 can be turned on, and a low voltage VGL can be sent to the nth gate line GL(n). Furthermore, when the seventh switch SW7 is turned on by the first voltage with a low level applied to Q node Q, a high voltage VGH can be sent to QB node QB, and a second voltage with a high level can be applied to QB node QB.

[0106] The sixth switch SW6 can be turned off by a second voltage with a high level applied to the QB node QB, and thus, the high voltage VGH cannot be sent to the nth gate line GL(n).

[0107] During the second time period T2, a (n-1)th gate signal gate(n-1) with a high level can be transmitted, and a gate clock signal GCLK with a low level can be transmitted, which repeats the low and high levels once or more. The first switch SW1 can be turned on by the gate clock signal GCLK with a low level, and thus, the (n-1)th gate signal gate(n-1) with a high level can be transmitted to the Q node Q.

[0108] Furthermore, when the (n-1)th gate signal G(n-1) with a high level is applied to the gate electrode of the third switch SW3, the third switch SW3 can be turned off. Therefore, the gate electrode of the second switch SW2 can become floating. After the gate electrode of the second switch SW2 becomes floating, when the gate clock signal GCLK changes from high to low, the voltage at the gate electrode of the second switch SW2 can decrease through the first capacitor C1, and the second switch SW2 can be turned on. At this time, since the gate clock signal GCLK is low, a second voltage with a low level can be applied to the QB node QB.

[0109] When a low-level second voltage is applied to node QB, the low-level second voltage can be applied to the gate electrode of the fourth switch SW4, and thus, the fourth switch SW4 can be turned on. When the fourth switch SW4 is turned on, a high voltage can be applied to node Q, and a high-level first voltage can be applied to node Q.

[0110] During the second time period T2, since a first voltage with a high level is applied to node Q and a second voltage with a low level is applied to node QB, the fifth switch SW5 and the sixth switch SW5 can be turned off. Furthermore, the seventh switch SW7 can be turned off. Therefore, the nth gate signal G(n) with a high level can be output to the nth gate line GL(n).

[0111] Furthermore, during the second time period T2, when the gate clock signal GCLK changes from low to high again, and the voltage at the gate electrode of the second switch SW2 rises and the second switch SW2 is turned off, the QB node QB can become floating and maintain a low second voltage. Therefore, even if the gate clock signal GCLK repeatedly changes between high and low levels during the second time period T2, the nth gate signal gate(n) with a high level can be continuously output to the nth gate line GL(n).

[0112] During the third time period T3, a (n-1)th gate signal G(n-1) with a low level can be provided. When the gate clock signal GCLK, which repeats low and high levels once or more, is low, the first switch SW1 can be turned on. When the first switch SW1 is turned on, a first voltage with a low level can be applied to the Q node Q through the (n-1)th gate signal G(n-1).

[0113] Furthermore, when the (n-1)th gate signal gate(n-1) with a low level is applied to the gate electrode of the third switch SW3, the third switch SW3 can be turned on. When the third switch SW3 is turned on, a high voltage VGH is sent to the gate of the second switch SW2, and the second switch SW2 can be turned off. Therefore, the QB node QB becomes a floating state. In the second time period T2, when the QB node QB maintains a low level second voltage, the QB node QB can maintain its previous state, and a high level second voltage can be applied to the QB node QB.

[0114] When a first voltage with a low level is applied to Q node Q, the fifth switch SW5 can be turned on, and the low voltage can be sent to the nth gate line. When a second voltage with a high level is applied to QB node QB, the sixth switch SW6 can be turned off, and the high voltage cannot be sent to the nth gate line.

[0115] At this point, the stabilizing capacitor Cs can be placed between the high-voltage source used to transmit the high voltage VGH and the nth gate line G(n). Therefore, when the nth gate line G(n) outputs a high voltage VGH as the nth gate signal, the output can be stabilized by the stabilizing capacitor Cs, and thus, when the data signal is input to... Figure 2 When the first node N11 of pixel 101 is shown, ripples that may occur in the first gate signal can be prevented or reduced.

[0116] In addition, such as Figure 9B As shown, the gate clock signal GCLK can remain low during the second time period T2, during which the (n-1)th gate signal G(n-1) remains high. While the gate clock signal GCLK remains low, the first switch SW1 remains on, without repeated on / off cycles. Consequently, the fifth switch SW5 remains off, and simultaneously, the second switch SW2 remains on, without repeated on / off cycles via the gate clock signal GCLK input to the second switch SW2. Therefore, the occurrence of ripple in the low-level second voltage applied to the QB node QB can be prevented or reduced.

[0117] Therefore, when the high voltage continuously drives the nth gate line Gn, the occurrence of ripple in the nth gate signal gate(n) can be prevented or reduced.

[0118] The (n-1)th gate signal can correspond to the first gate signal transmitted through the first gate line GL1, which is input to... Figure 2 The gate electrode of the first transistor M1 in pixel 101 is shown.

[0119] Although a stage configured to receive the (n-1)th gate signal gate(n-1) is shown, when this stage is the first of a plurality of stages that outputs the first gate signal, the start pulse GST instead of the (n-1)th gate signal gate(n-1) can be provided to the stage corresponding to the first stage.

[0120] The above description has been presented to enable those skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. Although exemplary embodiments have been described for illustrative purposes, those skilled in the art will recognize that various modifications and applications are possible without departing from the essential features of this disclosure. For example, various modifications can be made to specific components of the exemplary embodiments. The above description and drawings provide examples of the technical concept of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of this disclosure. Therefore, the scope of this disclosure is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of this disclosure is to be interpreted according to the claims, and all technical concepts within the scope of the claims should be interpreted as being included within the scope of the invention.

Claims

1. A gate driver, comprising: Multiple stages, each of which includes: sequentially providing gate signals to multiple gate lines. An input circuit is provided for receiving a (n-1)th gate signal and a gate clock signal transmitted through a (n-1)th gate line, and for applying a first voltage and a second voltage having a polarity opposite to that of the first voltage to the Q node and the QB node, respectively. An output circuit, configured to generate an nth gate signal by outputting a low voltage corresponding to the first voltage or a high voltage corresponding to the second voltage, and to output the generated nth gate signal to the nth gate line; and A stabilizing capacitor is disposed between the nth gate line and a high-voltage source for providing the high voltage. The stabilizing capacitor is directly connected to the high-voltage source; and The high voltage source continuously supplies the high voltage to the stabilizing capacitor.

2. The gate driver according to claim 1, wherein, The gate clock signal remains low during the first time period when the (n-1)th gate signal with the high voltage is input.

3. The gate driver according to claim 1, wherein, The input circuit includes: A first input circuit, configured to apply the first voltage to the Q node in response to the gate clock signal and the (n-1)th gate signal; and A second input circuit is used to apply the second voltage to the QB node in response to the (n-1)th gate signal.

4. The gate driver according to claim 3, wherein, The first input circuit includes a first switch, which includes a first electrode, a second electrode, and a gate electrode respectively connected to the (n-1)th gate line, the Q node, and a clock signal line for transmitting the gate clock signal. The second input circuit includes: The second switch includes a first electrode, a second electrode, and a gate electrode respectively connected to the clock signal line for transmitting the gate clock signal, the QB node, and the first node; The third switch includes a first electrode, a second electrode, and a gate electrode respectively connected to the first node, the high voltage source, and the (n-1)th gate line; A fourth switch, comprising a first electrode, a second electrode, and a gate electrode respectively connected to the Q node, the high voltage source, and the QB node; and A first capacitor, comprising a first electrode and a second electrode respectively connected to the clock signal line and the first node.

5. The gate driver according to claim 1, wherein, The output circuit includes: A first output circuit, the first output circuit being configured to selectively output the low voltage to the nth gate line in response to the first voltage applied to the Q node; and A second output circuit is configured to selectively output the high voltage to the nth gate line in response to the second voltage applied to the QB node.

6. The gate driver according to claim 5, wherein, The first output circuit includes a fifth switch, the fifth switch including a first electrode, a second electrode, and a gate electrode respectively connected to a low voltage source, the nth gate line, and the Q node, and the second output circuit includes: A sixth switch, comprising a first electrode, a second electrode, and a gate electrode respectively connected to the high voltage source, the nth gate line, and the QB node; and The seventh switch includes a gate electrode connected to the sixth switch, a first electrode, a second electrode, and a gate electrode respectively connected to the high voltage source and the Q node.

7. A display device, comprising: The display panel includes a plurality of data lines, a plurality of gate lines, a plurality of emission lines, and a plurality of pixels connected to the plurality of data lines, the plurality of gate lines, and the plurality of emission lines; A data driver, the data driver being used to apply a data signal to the plurality of data lines when connected to the plurality of data lines; as well as A gate driver, configured to apply a gate signal and a transmit signal to the plurality of gate lines and the plurality of emitter lines, respectively, when connected to the plurality of gate lines and the plurality of emitter lines. The gate driver includes multiple stages for sequentially providing the gate signal to the plurality of gate lines, each of the plurality of stages comprising: An input circuit is provided for receiving a (n-1)th gate signal and a gate clock signal transmitted through a (n-1)th gate line, and for applying a first voltage and a second voltage having a polarity opposite to that of the first voltage to the Q node and the QB node, respectively. An output circuit, configured to generate an nth gate signal by outputting a low voltage corresponding to the first voltage or a high voltage corresponding to the second voltage, and to output the generated nth gate signal to the nth gate line; and A stabilizing capacitor is disposed between the nth gate line and a high-voltage source for providing the high voltage. The stabilizing capacitor is directly connected to the high-voltage source; and The high voltage source continuously supplies the high voltage to the stabilizing capacitor.

8. The display device according to claim 7, wherein, The gate clock signal remains low during the first time period when the (n-1)th gate signal with the high voltage is input.

9. The display device according to claim 7, wherein, The input circuit includes: A first input circuit, the first input circuit being configured to apply the first voltage to the Q node in response to the gate clock signal and the (n-1)th gate signal; and A second input circuit is used to apply the second voltage to the QB node in response to the (n-1)th gate signal.

10. The display device according to claim 9, wherein, The first input circuit includes A first switch, comprising a first electrode, a second electrode, and a gate electrode respectively connected to the (n-1)th gate line, the Q node, and a clock signal line for transmitting the gate clock signal, and... The second input circuit includes: The second switch includes a first electrode, a second electrode, and a gate electrode respectively connected to the clock signal line for transmitting the gate clock signal, the QB node, and the first node; The third switch includes a first electrode, a second electrode, and a gate electrode respectively connected to the first node, the high voltage source, and the (n-1)th gate line; A fourth switch, comprising a first electrode, a second electrode, and a gate electrode respectively connected to the Q node, the high voltage source, and the QB node; and A first capacitor, comprising a first electrode and a second electrode respectively connected to the clock signal line and the first node.

11. The display device according to claim 7, wherein, The output circuit includes: A first output circuit, the first output circuit being configured to selectively output the low voltage to the nth gate line in response to the first voltage applied to the Q node; and A second output circuit is configured to selectively output the high voltage to the nth gate line in response to the second voltage applied to the QB node.

12. The display device according to claim 11, wherein, The first output circuit includes a fifth switch, the fifth switch including a first electrode, a second electrode, and a gate electrode respectively connected to a low voltage source, the nth gate line, and the Q node, and the second output circuit includes: A sixth switch, comprising a first electrode, a second electrode, and a gate electrode respectively connected to the high voltage source, the nth gate line, and the QB node; and The seventh switch includes a gate electrode connected to the sixth switch, a first electrode, a second electrode, and a gate electrode respectively connected to the high voltage source and the Q node.

13. The display device according to claim 7, wherein, Each of the plurality of pixels includes: A driving transistor, the driving transistor being configured to provide a driving current flowing from the second node to the third node in response to a voltage at the first node. A light-emitting element, which is capable of emitting light by receiving the driving current; A storage capacitor is disposed between the first node and the drive power line and is capable of maintaining the voltage of the first node; A first transistor is configured to selectively electrically connect the first node and the third node in response to a first gate signal; The second transistor is used to selectively transmit a data signal to the second node in response to a second gate signal; A third transistor is configured to selectively send a drive voltage to the second node in response to a transmit signal; A fourth transistor is used to electrically connect the third node and the light-emitting element in response to the transmitted signal; A fifth transistor, the fifth transistor being configured to provide a first initialization voltage to the third node via a third gate signal; and A sixth transistor, the sixth transistor being used to provide a second initialization voltage to the anode electrode of the light-emitting element via the third gate signal.

14. The display device of claim 7, further comprising a timing controller, the timing controller providing a data control signal to the data driver and a data driver control signal to the gate driver.

15. A method of operating a gate driver according to any one of claims 1 to 6, comprising: During the first time period, a (n-1)th gate signal with a high level and a gate clock signal with a low level are transmitted to the stage of the plurality of stages of the gate driver configured to receive the (n-1)th gate signal; and During the second time period, a (n-1)th gate signal with a low level and a gate clock signal with alternating low and high levels are sent to the stage. The first time period and the second time period alternate.

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