Display device and driving circuit

Abstract

A display device can include a display panel including a plurality of sub-pixels, a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines and output a feedback voltage, a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines, a power management circuit configured to supply a plurality of driving voltages to the gate driving circuit and the data driving circuit, and supply a compensation high positive gate voltage to the gate driving circuit based on the feedback voltage transferred from the gate driving circuit. The display device can further include a timing controller configured to control the gate driving circuit, the data driving circuit, and the power management circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices and driving circuits. Background Technology

[0002] Representative display devices for displaying images based on digital data include liquid crystal display (LCD) devices that use liquid crystals and organic light-emitting display devices that use organic light-emitting diodes.

[0003] Among these display devices, organic light-emitting displays (OLEDs) utilize light-emitting diodes (LEDs), thus offering advantages in terms of fast response time, contrast ratio, luminous efficiency, brightness, and viewing angle. In this case, LEDs can be implemented using either inorganic or organic materials.

[0004] Organic light-emitting diode (OLED) displays include light-emitting diodes arranged in sub-pixels on a display panel, and the LEDs are made to emit light by controlling the current flowing to them, thereby controlling the brightness represented by each sub-pixel while displaying an image.

[0005] In this display device, the display panel may have multiple sub-pixels, each sub-pixel including a light-emitting element and a sub-pixel circuit for driving the light-emitting element. For example, the sub-pixel circuit includes a driving transistor for controlling the driving current flowing through the light-emitting element and at least one scanning transistor for controlling the gate-source voltage of the driving transistor according to a scan signal. The scanning transistor of the sub-pixel circuit can be controlled by a scan signal output from a gating driving circuit disposed on the substrate of the display panel.

[0006] Since the display device includes a display area that serves as the area for displaying images and a non-display area that serves as the area for not displaying images, as the size of the non-display area decreases, the size of the boundary or border of the display device can decrease and the size of the display area can increase.

[0007] Accordingly, various methods are being investigated to reduce the size of the gating drive circuitry located in non-display areas.

[0008] However, simplifying the gating drive circuit increases the likelihood of errors occurring within it. Furthermore, the gating drive circuit comprises multiple transistors (e.g., each transistor has its own distinct characteristic values), and the degradation and lifetime of the gating drive integrated circuit (GDIC) can be determined or limited by the transistors within the gating drive circuit most likely to degrade. Summary of the Invention

[0009] Accordingly, the inventors of this disclosure provide a display device and a driving circuit capable of effectively detecting errors in the gating driving circuit and compensating for changes in the gating driving circuit over time.

[0010] Embodiments of this disclosure can provide a display device and a drive circuit capable of detecting errors in a gating drive circuit by detecting level changes in a high-potential gating voltage supplied to the gating drive circuit.

[0011] Embodiments of this disclosure can provide a display device and a drive circuit capable of effectively detecting errors in a gating drive circuit by utilizing a data drive circuit to detect level changes in a high-potential gating voltage.

[0012] The embodiments of this disclosure can provide a display device and a drive circuit that can effectively detect errors in the gating drive circuit by detecting changes in the level of the high-potential gating voltage and simultaneously controlling the level of the high-potential gating voltage that reflects the current of the feedback transistor disposed at the output terminal of the gating drive circuit.

[0013] Embodiments of this disclosure can provide a display device and a drive circuit capable of detecting errors in a gating drive circuit by utilizing a dummy channel to detect level changes in a high-potential gating voltage.

[0014] Embodiments of this disclosure may provide a display device comprising: a display panel including a plurality of sub-pixels; a gating driving circuit configured to supply a plurality of scan signals to the display panel via a plurality of gating lines; a data driving circuit configured to supply a plurality of data voltages to the display panel via a plurality of data lines; a power management circuit configured to supply a plurality of driving voltages to the gating driving circuit and the data driving circuit, and to supply a compensated high-potential gating voltage to the gating driving circuit based on a feedback voltage transmitted from the gating driving circuit; and a timing controller configured to control the gating driving circuit, the data driving circuit, and the power management circuit.

[0015] Embodiments of this disclosure may provide a gating drive circuit configured to supply multiple scan signals to a display panel having multiple sub-pixels via multiple gating lines. The gating drive circuit includes multiple gating drive integrated circuits, wherein at least one of the multiple gating drive integrated circuits is configured as a feedback gating drive integrated circuit including a feedback circuit and configured to receive a compensated high-potential gating voltage generated by a power management circuit using a feedback voltage generated by the feedback circuit.

[0016] Embodiments of this disclosure provide a power management circuit that supplies a drive voltage to a gating drive circuit that supplies multiple scan signals to a display panel via multiple gating lines. The power management circuit includes a high-potential gating voltage compensation circuit configured to supply a compensation high-potential gating voltage to the gating drive circuit based on a feedback voltage transmitted from the gating drive circuit.

[0017] Embodiments of this disclosure provide a data driving circuit that supplies multiple data voltages to a display panel via multiple data lines. The data driving circuit includes: an analog-to-digital converter (ADC) that senses the voltage of a sensing line and converts the voltage into digital data; a feature value sensing switch that controls the connection between the sensing line and a node supplied with a sensing reference voltage; a gating sensing switch that controls the connection between the sensing line and a node supplied with a compensated high-potential gating voltage transmitted from a power management circuit; and a sampling switch that controls the connection between the sensing line and the ADC.

[0018] According to embodiments of the present disclosure, a display device and a driving circuit capable of effectively detecting errors in a gating driving circuit can be provided.

[0019] According to embodiments of the present disclosure, a display device and a drive circuit can be provided that can detect errors in the gating drive circuit by detecting level changes in the high-potential gating voltage supplied to the gating drive circuit.

[0020] Embodiments of this disclosure can provide a display device and a drive circuit that can effectively detect errors in a gating drive circuit by utilizing a data drive circuit to detect level changes in a high-potential gating voltage.

[0021] According to embodiments of this disclosure, a display device and a drive circuit can be provided that can effectively detect errors in a gating drive circuit by simultaneously controlling the level of a high-potential gating voltage that reflects the current of a feedback transistor disposed at the output terminal of the gating drive circuit, through detecting changes in the level of a high-potential gating voltage.

[0022] According to embodiments of the present disclosure, a display device and a drive circuit can be provided that can detect errors in a gating drive circuit by detecting level changes of a high-potential gating voltage using a dummy channel. Attached Figure Description

[0023] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 This is a view that schematically illustrates the configuration of a display device according to various embodiments of the present disclosure;

[0025] Figure 2 This is a view illustrating an example of a system of display devices according to embodiments of the present disclosure;

[0026] Figure 3 This is a view illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure;

[0027] Figure 4 This is a view illustrating an example of a display panel in which the gating drive circuitry in a display device according to an embodiment of the present disclosure is implemented in a GIP type.

[0028] Figure 5 This is a block diagram illustrating the configuration of the GIP circuitry in a display device according to an embodiment of the present disclosure.

[0029] Figure 6 This is a view illustrating the configuration of multiple stages of circuitry constituting a gating drive circuit according to an embodiment of the present disclosure;

[0030] Figure 7 This is a view illustrating a gating driver integrated circuit constituting a gating driver circuit in a display driver circuit according to an embodiment of the present disclosure.

[0031] Figure 8 This is a view illustrating an example of a structure for compensating for the deterioration of a gating drive circuit in a display device according to an embodiment of the present disclosure.

[0032] Figure 9 and Figure 10 This is a conceptual illustration of the effect of reducing the degradation of a gating drive circuit by means of a process for compensating for a high-potential gating voltage applied to the gating drive circuit in a display device, according to an embodiment of the present disclosure.

[0033] Figure 11 This is a view illustrating an example of providing a gating driver integrated circuit including a feedback circuit in a display device according to an embodiment of the present disclosure;

[0034] Figure 12 This is a diagram illustrating an example of a defective state of a feedback circuit in a gating driver integrated circuit embedded in a display device according to an embodiment of the present disclosure.

[0035] Figure 13 This is a view illustrating an example circuit structure of a driving transistor in a sensing display device according to an embodiment of the present disclosure;

[0036] Figure 14This is a view illustrating an example of the configuration of a feedback circuit in a feedback gating driver integrated circuit built into a display device for detecting errors according to an embodiment of the present disclosure;

[0037] Figure 15 This is a view illustrating an example of a power management circuit according to an embodiment of the present disclosure for selectively supplying a compensation high-potential gating voltage and a display drive reference voltage in a display device; and

[0038] Including parts (a) and (b) Figure 16 This is a view illustrating an example of a structure in which sensing channels and dummy channels are arranged in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0039] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of example, and in the drawings, the same reference numerals and symbols may be used to designate the same or similar components, even if they are shown in different drawings. Additionally, in the following description of examples or embodiments of the invention, descriptions will be omitted where it is determined that detailed descriptions of well-known functions and components incorporated herein would make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0040] The elements of the present invention may be described herein using terms such as “first,” “second,” “A,” “B,” “(A),” or “(B).” Each of these terms is not intended to define the nature, order, sequence, or number of the elements, but is merely used to distinguish the corresponding element from the others.

[0041] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0042] When using time-related terms such as “after,” “following,” “next,” or “before” to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “immediately” or “exactly” are used together.

[0043] Furthermore, when referring to any size, relative size, etc., the numerical value or corresponding information (e.g., level, range, etc.) of a component or feature should be considered to include tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "can" fully encompasses all the meanings of the term "able to".

[0044] In the following description, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a view that schematically illustrates the configuration of a display device according to various embodiments of the present disclosure.

[0046] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110 in which multiple gate lines GL are connected to data lines DL and multiple sub-pixels SP are arranged in a matrix, a gate driving circuit 120 that drives multiple gate lines GL, a data driving circuit 130 that supplies data voltage through multiple data lines DL, a timing controller 140 that controls the gate driving circuit 120 and the data driving circuit 130, and a power management circuit (power management integrated circuit (IC)) 150.

[0047] The display panel 110 displays images based on scan signals transmitted from the gating drive circuit 120 via multiple gating lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0048] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-panel switching (IPS) mode, or edge field switching (FFS) mode. In the case of an organic light-emitting display, the display panel 110 may be implemented as a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0049] In the display panel 110, multiple pixels can be arranged in a matrix, and each pixel can include sub-pixels SP with different colors, such as white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels, and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0050] A sub-pixel SP may include, for example, a thin-film transistor (TFT) formed at the intersection between a data line DL and a gate line GL, a light-emitting element such as an organic light-emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0051] For example, when a display device 100 with a resolution of 2,160 × 3,840 includes four sub-pixels SP representing white (W), red (R), green (G), and blue (B), 3,840 data lines DL can be connected to 2,160 gating lines GL and the four sub-pixels WRGB, and therefore, 3,840 × 4 = 15,360 data lines DL can be set. Each sub-pixel SP is located at the intersection between the gating line GL and the data line DL.

[0052] The gating drive circuit 120 can be controlled by the controller 140 to sequentially output scanning signals to multiple gating lines GL arranged in the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0053] In a display device 100 with a resolution of 2,160 × 3,840, sequentially outputting scan signals to 2,160 gate lines GL from the first gate line to the 2,160th gate line can be referred to as 2,160-phase driving. Sequentially outputting scan signals to each unit of four gate lines GL (for example, sequentially outputting scan signals to the fifth to eighth gate lines after sequentially outputting scan signals to the first to fourth gate lines) can be referred to as 4-phase driving. In other words, sequentially outputting scan signals to every N gate lines GL can be referred to as N-phase driving.

[0054] The gating drive circuit 120 may include one or more gating drive integrated circuits (GDICs). Depending on the driving scheme, the gating drive circuit 120 may be located on only one or both of the two opposite sides of the display panel 110. The gating drive circuit 120 may be implemented as a gate in panel (GIP) embedded in the bezel area of ​​the display panel 110.

[0055] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, when the data voltage is output to each data line DL according to the timing of the scan signal applied through the gate line GL, each sub-pixel SP connected to the data line DL displays a light-emitting signal with a brightness corresponding to the data voltage.

[0056] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 in the tape auto-bonding (TAB) type or chip-on-glass (COG) type, or may be directly disposed on the display panel 110.

[0057] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type, and in this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 through the circuit film.

[0058] The timing controller 140 supplies various control signals to the gating drive circuit 120 and the data drive circuit 130, and controls the operation of the gating drive circuit 120 and the data drive circuit 130. In other words, the timing controller 140 can control the gating drive circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, transmit image data DATA received from the outside to the data drive circuit 130.

[0059] In this case, along with the image data DATA, the timing controller 140 also receives several timing signals from the external host system 200, including, for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK.

[0060] The host system 200 can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0061] Accordingly, the timing controller 140 can generate control signals based on various timing signals received from the host system 200, and transmit the control signals to the gating drive circuit 120 and the data drive circuit 130.

[0062] For example, timing controller 140 outputs several gating control signals, including, for example, a gating start pulse GSP, a gating clock GCLK, and a gating output enable signal GOE, to control gating drive circuit 120. The gating start pulse GSP controls the timing for the start of operation of one or more gating drive integrated circuits GDIC constituting gating drive circuit 120. The gating clock GCLK is a clock signal that is common to one or more gating drive integrated circuits GDIC and controls the shift timing of the scan signal. The gating output enable signal GOE specifies timing information regarding one or more gating drive integrated circuits GDIC.

[0063] The timing controller 140 outputs various data control signals, including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE, to control the data drive circuit 130. The source start pulse SSP controls the timing of data sampling for one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SCLK is a clock signal that controls the timing of the sampled data in the source driver integrated circuits (SDICs). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0064] The display device 100 may also include a power management circuit 150 that supplies various voltages or currents to, for example, a display panel 110, a gating drive circuit 120, and a data drive circuit 130, or controls the various voltages or currents to be supplied.

[0065] The power management circuit 150 regulates the DC input voltage Vin supplied from the host system 200, thereby generating the power necessary to drive the display panel 110, the gating drive circuit 120, and the data drive circuit 130.

[0066] Subpixels SP are positioned at the intersection between the gate line GL and the data line DL, and light-emitting elements can be disposed in each subpixel SP. For example, an organic light-emitting diode (OLED) display can include a light-emitting element such as an OLED in each subpixel SP, and can display images by controlling the current flowing to the light-emitting element according to the data voltage.

[0067] The display device 100 can be one of various types of devices such as a liquid crystal display, an organic light-emitting diode display, or a plasma display panel.

[0068] Figure 2 This is a view illustrating an example of a system of display devices according to embodiments of the present disclosure.

[0069] Reference Figure 2 In the display device 100 according to an embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 is implemented as a chip-on-film (COF) type among various types (e.g., TAB, COG, or COF), and the gate driver circuit 120 is implemented as a gate-in-panel (GIP) type among various types (e.g., TAB, COG, COF, or GIP).

[0070] When the gate drive circuit 120 is implemented in GIP type, the multiple gate drive integrated circuits (GDICs) included in the gate drive circuit 120 can be directly formed in the bezel area of ​​the display panel 110. In this case, the gate drive integrated circuits (GDICs) can receive various signals necessary for generating the scan signal (e.g., clock signal, gate high-level voltage, gate low-level voltage, etc.) through the gate drive related signal lines provided in the bezel area.

[0071] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on a source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0072] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0073] The other side of the active driver integrated circuit (SDIC) mounted on the source film SF can be connected to at least one source printed circuit board (SPCB). In other words, one side of the active driver integrated circuit (SDIC) mounted on the source film SF can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board (SPCB).

[0074] The timing controller 140 and the power management circuit (power management IC) 150 can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gating drive circuit 120. The power management circuit 150 can supply drive voltage or current to the display panel 110, the data drive circuit 130, and the gating drive circuit 120, and control the supplied voltage or current.

[0075] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitally connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit board (FPC) or a flexible flat cable (FFC). At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0076] The display device 100 may also include a setup board 170 electrically connected to a control printed circuit board (CPCB). In this case, the setup board 170 may also be referred to as a power board. A main power management circuit (M-PMC) 160 for managing the total power of the display device 100 may be provided on the setup board 170. The main power management circuit 160 may cooperate with the power management circuit 150.

[0077] In the display device 100 configured in this way, a driving voltage is generated in the setting board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage necessary for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is supplied via a source driver integrated circuit SDIC to emit light in the display panel 110 or sense specific sub-pixels SP.

[0078] Each of the sub-pixels SP arranged in the display panel 110 of the display device 100 may include a light-emitting element and a circuit element (e.g., a driving transistor) for driving an organic light-emitting diode.

[0079] The type and number of circuit elements constituting each sub-pixel SP can vary depending on the functions and design schemes to be provided.

[0080] Figure 3 This is a view illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure.

[0081] Reference Figure 3 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors, and may have a light-emitting element disposed therein.

[0082] For example, a sub-pixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting diode ED.

[0083] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node through which the data voltage Vdata is applied from the data driving circuit 130 via the data line DL when the switching transistor SWT is turned on.

[0084] The second node N2 of the driving transistor DRT can be connected to the anode electrode of the light-emitting diode ED, and can be either a source node or a drain node.

[0085] The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL to which the sub-pixel driving voltage EVDD is applied, and can be a drain node or a source node.

[0086] In this scenario, during the display driving period, the subpixel driving voltage EVDD necessary for displaying the image can be supplied to the drive voltage line DVL. For example, the subpixel driving voltage EVDD necessary for displaying the image can be 27V.

[0087] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gating line GL is connected to the gate node. Therefore, the switching transistor SWT operates according to the first scan signal SCAN1 supplied via the gating line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata supplied via the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0088] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gating line GL is connected to the gate node. The sensing transistor SENT operates according to the second scan signal SCAN2 supplied through the gating line GL. When the sensing transistor SENT is turned on, the reference voltage Vref supplied through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0089] In other words, when the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DRT are controlled so that current can be supplied to drive the light-emitting diode ED.

[0090] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown below: the switching transistor SWT and the sensing transistor SENT are connected to different gate lines, where the switching transistor SWT and the sensing transistor SENT can be independently controlled by a first scan signal SCAN1 and a second scan signal SCAN2 transmitted via different gate lines GL.

[0091] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be controlled simultaneously by a first scan signal SCAN1 or a second scan signal SCAN2 transmitted via a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0092] The transistors set in the sub-pixel SP can be n-type transistors or p-type transistors, and in the example shown, the transistors are n-type transistors.

[0093] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0094] The storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT, depending on the type of driving transistor DRT. The anode of the light-emitting diode ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be applied to the cathode of the organic light-emitting diode ED.

[0095] The base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the driving state. For example, the base voltage EVSS during display driving and the base voltage EVSS during sensing driving can be set to be different from each other.

[0096] The switching transistor SWT and the sensing transistor SENT can be referred to as scanning transistors controlled by scanning signals SCAN1 and SCAN2.

[0097] The structure of a subpixel SP may also include one or more transistors, or in some cases, one or more capacitors.

[0098] In order to effectively sense characteristic values ​​of the driving transistor DRT, such as threshold voltage or mobility, the display device 100 of this disclosure can use a method for measuring the current flowing due to the voltage charged into the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT (this is referred to as current sensing).

[0099] In other words, the characteristic value or change of characteristic value of the driving transistor DRT can be determined by measuring the current flowing due to the voltage charged into the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT in the sub-pixel SP.

[0100] In this case, the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel. Therefore, the reference voltage line RVL can also be referred to as a sensing line or sensing channel.

[0101] More specifically, the characteristic value or change of the characteristic value of the driving transistor DRT can correspond to the difference between the gate node voltage and the source node voltage of the driving transistor DRT.

[0102] Compensation for the characteristic values ​​of the driving transistor DRT can be performed by using external compensation circuitry to sense and compensate for the characteristic values ​​of the driving transistor DRT, or by sensing and compensating for the characteristic values ​​of the driving transistor DRT inside the sub-pixel SP, instead of using internal compensation with additional external configuration.

[0103] In this case, external compensation can be performed before the display device 100 leaves the factory, and internal compensation can be performed after the display device 100 leaves the factory. However, even after the display device 100 leaves the factory, internal and external compensation can be performed together.

[0104] Figure 4 This is a view illustrating an example of a display panel in which the gating drive circuitry in a display device according to an embodiment of the present disclosure is implemented in a GIP type.

[0105] Reference Figure 4 In the display device 100 according to an embodiment of the present disclosure, 2n gate lines GL(1) to GL(2n) (where n is a natural number) can be provided in the display area A / A for displaying images in the display panel 110.

[0106] In this case, the gating drive circuit 120 may include 2n GIP circuits GIPC corresponding to 2n gating lines GL(1) to GL(2n) and (e.g., along the edge) built into and disposed in a non-display area corresponding to the outer portion of the display area A / A of the display panel 110.

[0107] Accordingly, 2n GIP circuits GIPC can output the scan signal SCAN to 2n gate lines GL(1) to GL(2n).

[0108] Thus, when the gating drive circuit 120 is implemented in GIP type, it is not necessary to form a separate integrated circuit with gating drive function and integrate it into the display panel 110. Therefore, the number of integrated circuits can be reduced and the process of connecting integrated circuits to the display panel 110 can be omitted. The size of the bezel area in the display panel 110 used for integrating integrated circuits can also be reduced.

[0109] 2n GIP circuits GIPC can be represented as GIPC(1), GIPC(2), ... GIPC(2n) in order to distinguish them from each other and identify the correspondence between the 2n gate lines GL(1) to GL(2n).

[0110] This example shows 2n GIP circuits GIPC(1) to GIPC(2n) arranged on both sides of the division of display area A / A. For example, among the 2n GIP circuits GIPC(1) to GIPC(2n), the odd-numbered GIP circuits GIPC(1), GIPC(3), ..., GIPC(2n-1) can drive the odd-numbered gating lines GL(1), GL(3), ..., GL(2n-1). Among the 2n GIP circuits GIPC(1) to GIPC(2n), the even-numbered GIP circuits GIPC(2), GIPC(4), ..., GIPC(2n) can drive the even-numbered gating lines GL(2), GL(4), ..., GL(2n).

[0111] Alternatively, 2n GIP circuits GIPC(1) to GIPC(2n) can be set on only one side of the display area A / A.

[0112] Multiple clock signal lines CL, which are necessary for transmitting the gating clock required to generate the scan signal SCAN and output it to the gating drive circuit 120, can be set in a non-display area corresponding to the outer portion of the display area A / A of the display panel 110.

[0113] Figure 5 This is a block diagram illustrating the configuration of the GIP circuitry in a display device according to an embodiment of the present disclosure.

[0114] Reference Figure 5 In the display device 100 according to an embodiment of the present disclosure, a GIP circuit GIPC may include a shift register 122 and a buffer circuit 124.

[0115] The GIP circuit GIPC can start operating based on the strobe start pulse GSP and output the scan signal SCAN according to the strobe clock GCLK. The scan signal SCAN output from the GIP circuit GIPC is shifted sequentially and supplied sequentially through the strobe line GL.

[0116] The buffer circuit 124 has two nodes, Q and QB, which are important for the gating drive state, and may include a pull-up transistor TU and a pull-down transistor TD. The gate node of the pull-up transistor TU may correspond to the Q node, and the gate node of the pull-down transistor TD may correspond to the QB node.

[0117] Shift register 122 can also be referred to as shift logic circuit, and can be used to generate the scan signal SCAN synchronously with the strobe clock GCLK.

[0118] The shift register 122 can control the Q node and QB node connected to the buffer circuit 124, so that the buffer circuit 124 can output the scan signal SCAN, and for this purpose, it can include multiple transistors.

[0119] Shift register 122 begins generating the scan signal SCAN, and its output is sequentially enabled according to the gating clock GCLK. In other words, the output timing of shift register 122 can be controlled by using the gating clock GCLK to transmit the logic state used to sequentially determine the on / off state of the gating line GL.

[0120] According to shift register 122, the corresponding voltage states of the Q node and QB node of buffer circuit 124 can be different. Accordingly, buffer circuit 124 can output a voltage to the corresponding gating line G to enable the corresponding gating line GL (e.g., corresponding to a high-level voltage or a low-level voltage, and may be, for example, a clock signal with a gating high-level voltage VGH), or output a voltage to the corresponding gating line G to enable the corresponding gating line GL (e.g., corresponding to a low-level voltage or a high-level voltage, and may be, for example, a base voltage VSS with a gating low-level voltage VGL).

[0121] In addition to shift register 122 and buffer circuit 124, a GIP circuit GIPC may also include a level shifter.

[0122] In this case, the shift register 122 and the buffer circuit 124 that constitute the GIP circuit GIPC can be connected in various structures.

[0123] Figure 6 This is a view illustrating the configuration of multiple stages of circuitry constituting a gating drive circuit according to an embodiment of the present disclosure.

[0124] Reference Figure 6 According to another embodiment of the present disclosure, the gating drive circuit 120 may include a first-level circuit ST(1) to a k-th-level circuit ST(k) (where k is a positive integer greater than zero), a gating drive voltage line 131, a clock signal line 132, a line sensing preparation signal line 133, and a reset signal line 134.

[0125] The gating drive circuit 120 may also include a previous dummy stage circuit DST1 disposed before the first stage circuit ST(1) and a subsequent dummy stage circuit DST2 disposed after the k-th stage circuit ST(k).

[0126] The gating drive voltage line 131 applies the high-potential gating voltage GVDD and the low-potential gating voltage GVSS supplied from the power management circuit 150 to each of the first-stage circuit ST(1) to the k-th stage circuit ST(k), the previous dummy stage circuit DST1 and the subsequent dummy stage circuit DST2.

[0127] The gating drive voltage line 131 may include multiple high-potential gating voltage lines supplying multiple high-potential gating voltages with different voltage levels, and multiple low-potential gating voltage lines supplying multiple low-potential gating voltages with different voltage levels.

[0128] For example, the gating drive voltage line 131 may include three high-potential gating voltage lines supplied with a first high-potential gating voltage GVDD1, a second high-potential gating voltage GVDD2, and a third high-potential gating voltage GVDD3, each with different voltage levels, and three low-potential gating voltage lines supplied with a first low-potential gating voltage GVSS1, a second low-potential gating voltage GVSS2, and a third low-potential gating voltage GVSS3, each with different voltage levels. However, this is merely an example, and the number of lines included in the gating drive voltage line 131 may vary depending on the implementation.

[0129] Clock signal line 132 supplies each of the first-stage circuit ST(1) to the k-th-stage circuit ST(k), the previous dummy stage circuit DST1 and the subsequent dummy stage circuit DST2 with multiple clock signals CLK supplied from the timing controller 140, such as carry clock signals or scan clock signals.

[0130] Line sensing preparation signal line 133 supplies the line sensing preparation signal LSP from the timing controller 140 to the first stage circuit ST(1) to the kth stage circuit ST(k). Optionally, line sensing preparation signal line 133 may be additionally connected to the previous dummy stage circuit DST1.

[0131] The reset signal line 134 sends a reset signal RESET supplied from the timing controller 140 to each of the first-level circuit ST(1) to the k-th-level circuit ST(k), the previous dummy level circuit DST1, and the subsequent dummy level circuit DST2.

[0132] The panel signal line 135 sends the panel signal POS supplied from the timing controller 140 to each of the first-level circuit ST(1) to the k-th-level circuit ST(k), the previous dummy level circuit DST1 and the subsequent dummy level circuit DST2.

[0133] In addition to the lines 131, 132, 133, and 134 shown, lines used for supplying other signals can be additionally connected to the first-stage circuit ST(1) through the k-th-stage circuit ST(k), the previous dummy stage circuit DST1, and the subsequent dummy stage circuit DST2. For example, the line used to supply the gating start pulse GSP to the previous dummy stage circuit DST1 can be additionally connected to the previous dummy stage circuit DST1.

[0134] The previously dummy stage circuit DST1 outputs the previous carry signal C in response to the input of the strobe start pulse GSP supplied from the timing controller 140.

[0135] The carry signal C can be supplied to any one of the first-stage circuit ST(1) to the k-th-stage circuit ST(k).

[0136] The subsequent dummy stage circuit DST2 outputs the subsequent carry signal C. The subsequent carry signal C can be supplied to any one of the first stage circuit ST(1) to the kth stage circuit ST(k).

[0137] The first-level circuit ST(1) to the k-th-level circuit ST(k) can be connected to each other step by step or in a cascade manner.

[0138] The first-level circuit ST(1) to the k-th-level circuit ST(k) each outputs j scan signals (where j is a positive integer greater than zero) and a carry signal C. In other words, each level of the circuit outputs the first scan signal to the j-th scan signal and a carry signal C.

[0139] For example, each stage of the circuit outputs four scan signals (SCAN) and one carry signal (C). For example, the first stage circuit ST(1) outputs the first scan signal (SCAN(1), the second scan signal (SCAN(2), the third scan signal (SCAN(3)) and the fourth scan signal (SCAN(4)) and the first carry signal (C(1)), and the second stage circuit ST(2) outputs the fifth scan signal (SCAN(5), the sixth scan signal (SCAN(6), the seventh scan signal (SCAN(7)), the eighth scan signal (SCAN(8)) and the second carry signal (C(2)). Therefore, in this embodiment, j is 4.

[0140] The number of scan signals output from the first-stage circuit ST(1) to the k-th-stage circuit ST(k) matches the number n of the gate lines 15 provided on the display panel 10. As described above, each stage of the circuit outputs j scan signals. Therefore, the equation j×k=n holds true.

[0141] For example, when j = 4, the number of stage circuits k is 1 / 4 of the number of gate lines GL n. However, the number of scan signals output by each stage circuit is not limited to this. In other words, in embodiments of this disclosure, each stage circuit may output one, two, or three scan signals, or it may output five or more scan signals. The number of stage circuits can vary depending on the number of scan signals output by each stage circuit.

[0142] The scan signal SCAN output from the first-stage circuit ST(1) to the k-th-stage circuit ST(k) can be a scan signal used to sense the threshold voltage of the driving transistor DRT, and can also be a gating signal used to display an image. The carry signal C output from the first-stage circuit ST(1) to the k-th-stage circuit ST(k) can be supplied to different stage circuits respectively. The carry signal supplied from a previous stage circuit to any stage circuit is called the previous stage carry signal, and the carry signal supplied from a subsequent stage circuit is called the subsequent carry signal.

[0143] Figure 7 This is a view illustrating a gating driver integrated circuit constituting a gating driver circuit in a display driver circuit according to an embodiment of the present disclosure.

[0144] Reference Figure 7 The gating driver integrated circuit (GDIC) according to the embodiments of this disclosure may include an M node, a Q node, and a QB node, and may include a line selection unit 502, a Q node control unit 504, a Q node stabilization unit 506, an inverter unit 508, a QB node stabilization unit 510, a carry signal output unit 512, and a scan signal output unit 514.

[0145] Line selection unit 502 charges node M based on carry signal C(k-2) from the previous stage in response to input of line sensing preparation signal LSP. In response to input of reset signal RESET, line selection unit 502 charges node Q to the level of the first high-level gating voltage GVDD1 based on the charging voltage of node M. Line selection unit 502 discharges or resets node Q to the level of the third low-level gating voltage GVSS3 in response to input of signal POS on the panel.

[0146] The line selection unit 502 includes a first transistor T11 to a seventh transistor T17 and a pre-charge capacitor CA.

[0147] The first transistor T11 and the second transistor T12 are connected between the first high-potential gating voltage line transmitting the first high-potential gating voltage GVDD1 and the M node. The first transistor T11 and the second transistor T12 are connected in series with each other.

[0148] In response to the input of the line sensing preparation signal LSP, the first transistor T11 outputs the previous carry signal C(k-2) to the first connection node NC1.

[0149] In response to the input of the line sensing preparation signal LSP, the second transistor T12 electrically connects the first connection node NC1 to the M node. For example, when the high-voltage line sensing preparation signal LSP is input to the first transistor T11 and the second transistor T12, the first transistor T11 and the second transistor T12 are turned on simultaneously, causing the M node to be charged to the level of the first high-potential gating voltage GVDD1.

[0150] When the voltage level of node M is high, the third transistor T13 is turned on, thereby supplying the first high-level gating voltage GVDD1 to the first connection node NC1. When the first high-level gating voltage GVDD1 is supplied to the first connection node NC1, the voltage difference between the gating voltage of the first transistor T11 and the first connection node NC1 increases.

[0151] Accordingly, when the low-level line sensing preparation signal LSP is input to the gate node of the first transistor T11, causing the first transistor T11 to turn off, the first transistor T11 can remain in a fully off state due to the voltage difference between the gate voltage of the first transistor T11 and the first connection node NC1. This prevents current leakage from the first transistor T11 and voltage drop at node M, thus ensuring a stable voltage at node M.

[0152] A pre-charged capacitor CA is connected between the first high-potential gating voltage line that transmits the first high-potential gating voltage GVDD1 and the M node, thereby storing the difference between the first high-potential gating voltage GVDD1 and the voltage charged into the M node.

[0153] If the first transistor T11, the second transistor T12, and the third transistor T13 are turned on, the pre-charge capacitor CA stores the high voltage of the previous carry signal C(k-2). If the first transistor T11, the second transistor T12, and the third transistor T13 are turned off, the pre-charge capacitor CA maintains the voltage of node M at the stored voltage for a predetermined time.

[0154] The fourth transistor T14 and the fifth transistor T15 are connected between the first high-potential gating voltage line transmitting the first high-potential gating voltage GVDD1 and the Q node. The fourth transistor T14 and the fifth transistor T15 are connected in series with each other.

[0155] The fourth transistor T14 and the fifth transistor T15, in response to the input of the M node voltage and the reset signal RESET, charge the Q node using the first high-level gating voltage GVDD1.

[0156] When the voltage at node M is high, the fourth transistor T14 is turned on to transmit the first high-potential gating voltage GVDD1 to the shared node of the fourth transistor T14 and the fifth transistor T15.

[0157] The fifth transistor T15 is turned on by the high-level reset signal RESET to supply the voltage of the shared node to the Q node. Correspondingly, if the fourth transistor T14 and the fifth transistor T15 are turned on simultaneously, the Q node is charged using the first high-level gating voltage GVDD1.

[0158] The sixth transistor T16 and the seventh transistor T17 are connected between the Q node and the third low-level gating voltage line that transmits the third low-level gating voltage GVSS3. The sixth transistor T16 and the seventh transistor T17 are connected in series with each other.

[0159] The sixth transistor T16 and the seventh transistor T17, in response to the input of the signal POS on the panel, discharge the Q node to the third low-level gating voltage GVSS3. Discharging the Q node to the third low-level gating voltage GVSS3 can be represented as resetting the Q node.

[0160] The seventh transistor T17 is turned on by the input of the high-level signal POS on the panel to supply the third low-level gating voltage GVSS3 to the QH node.

[0161] The sixth transistor T16 is turned on by the high-level input signal POS on the panel, electrically connecting the Q node and the QH node. Correspondingly, if the sixth transistor T16 and the seventh transistor T17 are turned on simultaneously, the Q node is discharged or reset to the third low-level gating voltage GVSS3.

[0162] The Q-node control unit 504 charges the Q-node to the level of the first high-level gating voltage GVDD1 in response to the input of the previous carry signal C(k-2), and discharges the Q-node to the level of the third low-level gating voltage GVSS3 in response to the input of the subsequent carry signal C(k+2).

[0163] Q-node control unit 504 includes first transistor T21 through eighth transistor T28.

[0164] The first transistor T21 and the second transistor T22 are connected between the first high-potential gating voltage line transmitting the first high-potential gating voltage GVDD1 and the Q node. The first transistor T21 and the second transistor T22 are connected in series with each other.

[0165] The first transistor T21 and the second transistor T22 charge the Q node to the first high-potential gating voltage GVDD1 in response to the input of the previous carry signal C(k-2).

[0166] The first transistor T21 is turned on by the input of the previous carry signal C(k-2) to supply the first high-level gating voltage GVDD1 to the second connection node NC2.

[0167] The second transistor T22 is turned on by the input of the previous carry signal C(k-2) to electrically connect the second connection node NC2 to the Q node. Accordingly, if the first transistor T21 and the second transistor T22 are turned on simultaneously, the first high-level gating voltage GVDD1 is supplied to the Q node.

[0168] The fifth transistor T25 and the sixth transistor T26 are connected to the third high-level gating voltage line that transmits the third high-level gating voltage GVDD3. In response to the third high-level gating voltage GVDD3, the fifth transistor T25 and the sixth transistor T26 supply the third high-level gating voltage GVDD3 to the second connection node NC2.

[0169] The fifth transistor T25 and the sixth transistor T26 are simultaneously turned on by the third high-level gating voltage GVDD3, so as to always supply the third high-level gating voltage GVDD3 to the second connection node NC2, thereby increasing the gate voltage of the first transistor T21 and the voltage difference between the second connection node NC2. Accordingly, when a low-level carry signal C(k-1) is input to the gate node of the first transistor T21, causing the first transistor T21 to be turned off, the first transistor T21 can remain in a completely off state due to the voltage difference between the gate voltage of the first transistor T21 and the second connection node NC2.

[0170] Correspondingly, current leakage from the first transistor T21 and the resulting voltage drop at the Q node can be prevented, thus ensuring that the voltage at the Q node remains stable.

[0171] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 remains negative (-) due to the third high-potential gating voltage GVDD3 supplied to the drain electrode.

[0172] Accordingly, when a low-level carry signal C(k-2) is input to the gate node of the first transistor T21, causing the first transistor T21 to turn off, the first transistor T21 remains in a completely off state, thereby preventing leakage current.

[0173] The third high-potential gating voltage GVDD3 is set to a lower voltage level than the first high-potential gating voltage GVDD1.

[0174] The third transistor T23 and the fourth transistor T24 are connected between the Q node and the third low-level gating voltage line that transmits the third low-level gating voltage GVSS3. The third transistor T23 and the fourth transistor T24 are connected in series with each other.

[0175] The third transistor T23 and the fourth transistor T24 discharge the Q node and QH node to the third low-level gating voltage GVSS3 level in response to the input of the subsequent carry signal C(k+2).

[0176] The fourth transistor T24 is turned on upon input of the subsequent carry signal C(k+2) to discharge node QH to the level of the third low-level gating voltage GVSS3. The third transistor T23 is turned on upon input of the subsequent carry signal C(k+2) to electrically connect node Q to node QH. Accordingly, if both transistors T23 and T24 are turned on simultaneously, node Q and node QH are each discharged or reset to the level of the third low-level gating voltage GVSS3.

[0177] The seventh transistor T27 and the eighth transistor T28 are connected between the first high-potential gating voltage line transmitting the first high-potential gating voltage GVDD1 and the Q node, and between the first high-potential gating voltage line transmitting the first high-potential gating voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 are connected in series with each other.

[0178] The seventh transistor T27 and the eighth transistor T28 supply a first high-level gating voltage GVDD1 to the QH node in response to the voltage of the Q node. When the voltage of the Q node is high, the seventh transistor T27 is turned on to supply the first high-level gating voltage GVDD1 to the shared node of the seventh transistor T27 and the eighth transistor T28.

[0179] When the voltage at node Q is high, the eighth transistor T28 is turned on to electrically connect the shared node to node QH. Correspondingly, when the voltage at node Q is high, both the seventh transistor T27 and the eighth transistor T28 are turned on to supply the first high-level gating voltage GVDD1 to node QH.

[0180] If the first high-level gating voltage GVDD1 is supplied to the QH node, the voltage difference between the gate node of the third transistor T23 and the QH node increases. Correspondingly, when a low-level subsequent carry signal C(k+2) is input to the gate node of the third transistor T23, causing it to turn off, the voltage difference between the gate voltage of the third transistor T23 and the QH node allows it to remain fully off. This prevents current leakage from the third transistor T23 and the resulting voltage drop at the Q node, thus maintaining a stable voltage at the Q node.

[0181] Q-node stabilization unit 506 discharges the Q-node and QH-node to the level of the third low-level gating voltage GVSS3 in response to the voltage of the QB-node. Q-node stabilization unit 506 may include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 are connected between the Q-node and the third low-level gating voltage line that transmits the third low-level gating voltage GVSS3. The first transistor T31 and the second transistor T32 are connected in series with each other.

[0182] The first transistor T31 and the second transistor T32 discharge the Q node and the QH node to the level of the third low-level gating voltage GVSS3 in response to the voltage of the QB node. When the voltage of the QB node is high, the second transistor T32 turns on to supply the third low-level gating voltage GVSS3 to the shared node of the first transistor T31 and the second transistor T32.

[0183] When the voltage at node QB is high, the first transistor T31 is turned on to electrically connect node Q to node QH. Correspondingly, if both transistors T31 and T32 are turned on simultaneously in response to the voltage at node QB, then nodes Q and QH are each discharged or reset to the level of the third low-potential gating voltage GVSS3.

[0184] Inverter unit 508 changes the voltage level of node QB according to the voltage level of node Q. Inverter unit 508 includes first transistor T41 through fifth transistor T45.

[0185] The second transistor T42 and the third transistor T43 are connected between the second high-potential gating voltage line transmitting the second high-potential gating voltage GVDD2 and the third connection node NC3. The second transistor T42 and the third transistor T43 are connected in series with each other.

[0186] The second transistor T42 and the third transistor T43 supply the second high-level gating voltage GVDD2 to the third connection node NC3 in response to the second high-level gating voltage GVDD2. The second transistor T42 is turned on by the second high-level gating voltage GVDD2 to supply the second high-level gating voltage GVDD2 to the shared node of the second transistor T42 and the third transistor T43.

[0187] The third transistor T43 is turned on by the second high-level gating voltage GVDD2 to electrically connect the shared node of the second transistor T42 and the third transistor T43 to the third connection node NC3. Accordingly, if the second transistor T42 and the third transistor T43 are turned on simultaneously by the second high-level gating voltage GVDD2, the third connection node NC3 is charged to the level of the second high-level gating voltage GVDD2.

[0188] The fourth transistor T44 is connected between the third connection node NC3 and the second low-potential gating voltage line that transmits the second low-potential gating voltage GVSS2.

[0189] The fourth transistor T44 supplies the second low-level gating voltage GVSS2 to the third connection node NC3 in response to the voltage at the Q node. When the voltage at the Q node is high, the fourth transistor T44 turns on to discharge or reset the third connection node NC3 to the second low-level gating voltage GVSS2.

[0190] The first transistor T41 is connected between the second high-potential gating voltage line that transmits the second high-potential gating voltage GVDD2 and the QB node.

[0191] The first transistor T41 supplies the second high-level gating voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. When the voltage of the third connection node NC3 is high, the first transistor T41 is turned on to charge the QB node to the level of the second high-level gating voltage GVDD2.

[0192] The fifth transistor T45 is connected between the QB node and the third low-potential gating voltage line that transmits the third low-potential gating voltage GVSS3.

[0193] The fifth transistor T45 supplies the third low-level gating voltage GVSS3 to the QB node in response to the voltage at the Q node. When the voltage at the Q node is high, the fifth transistor T45 turns on to discharge or reset the QB node to the level of the third low-level gating voltage GVSS3.

[0194] The QB node stabilization unit 510, in response to the input of the subsequent carry signal C(k-2), the input of the reset signal RESET, and the charging voltage of the M node, discharges the QB node to the third low-level gating voltage GVSS3. The QB node stabilization unit 510 may include the first transistor T51 to the third transistor T53.

[0195] The first transistor T51 is connected between the QB node and the second low-potential gating voltage line that transmits the third low-potential gating voltage GVSS3.

[0196] The first transistor T51 supplies the third low-level gating voltage GVSS3 to the QB node in response to the input of the subsequent carry signal C(k-2).

[0197] The second transistor T52 and the third transistor T53 are connected between the QB node and the third low-potential gating voltage line that transmits the third low-potential gating voltage GVSS3. The second transistor T52 and the third transistor T53 are connected in series with each other.

[0198] The second transistor T52 and the third transistor T53 discharge the QB node to the third low-level gating voltage GVSS3 level in response to the input of the reset signal RESET and the charging voltage of the M node.

[0199] When the voltage at node M is high, the third transistor T53 is turned on to supply the third low-level gating voltage GVSS3 to the shared node of the second transistor T52 and the third transistor T53.

[0200] The second transistor T52 is turned on by the input of the reset signal RESET, electrically connecting the shared node of the second transistor T52 and the third transistor T53 to the QB node. Correspondingly, if the reset signal RESET is input while the voltage of the M node is at a high level, the second transistor T52 and the third transistor T53 are turned on simultaneously to discharge or reset the QB node to the third low-level gating voltage GVSS3.

[0201] The carry signal output unit 512 outputs the carry signal C(k) based on the voltage level of the Q node or the voltage level of the QB node, the voltage level of the carry clock signal CRCLK(k), or the level of the third low-level gating voltage GVSS3.

[0202] The carry signal output unit 512 includes a first transistor T61, a second transistor T62, and a boost capacitor CC.

[0203] The first transistor T61 is connected between the clock signal line transmitting the carry clock signal CRCLK(k) and the first output node NO1. The boost capacitor CC is connected between the gate node and the source node of the first transistor T61.

[0204] The first transistor T61 responds to the voltage at node Q by outputting a high-level carry signal C(k) through the first output node NO1 based on the carry clock signal CRCLK(k). When the voltage at node Q is high, the first transistor T61 is turned on to supply the high-level carry clock signal CRCLK(k) to the first output node NO1. Accordingly, a high-level carry signal C(k) is output.

[0205] When the carry signal C(k) is output, the boost capacitor CC, in sync with the high-level carry clock signal CRCLK(k), bootstraps the voltage of the Q node to a boost voltage level higher than the first high-level gating voltage GVDD1. If the voltage of the Q node is bootstrap, the high-level carry clock signal CRCLK(k) can be output quickly and without distortion as the carry signal C(k).

[0206] The second transistor T62 is connected between the first output node NO1 and the third low-potential gating voltage line that transmits the third low-potential gating voltage GVSS3.

[0207] The second transistor T62, in response to the voltage at node QB, outputs a low-level carry signal C(k) through the first output node NO1 based on the third low-level gating voltage GVSS3. When the voltage at node QB is high, the second transistor T62 is turned on to supply the third low-level gating voltage GVSS3 to the first output node NO1. Accordingly, a low-level carry signal C(k) is output.

[0208] The scan signal output unit 514 outputs multiple scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) based on the voltage level of the Q node or the voltage level of the QB node, the first low-level gating voltage GVSS1 level, or the voltage levels of multiple scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3) (where i is a positive integer greater than zero).

[0209] The scan signal output unit 514 includes a first transistor T71 to an eighth transistor T78 and boost capacitors CS1, CS2, CS3 and CS4.

[0210] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 are connected between the clock signal lines that transmit the scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3) and the second output node NO2 to the fifth output node NO5.

[0211] Boost capacitors CS1, CS2, CS3 and CS4 are connected between the gate node and source node of the first transistor T71, the third transistor T73, the fifth transistor T75 and the seventh transistor T77.

[0212] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 respond to the voltage of the Q node by outputting high-level scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively.

[0213] When the voltage at node Q is high, transistors T71, T73, T75, and T77 are turned on, supplying high-level scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3) to output nodes NO2, NO3, NO4, and NO5, respectively. Correspondingly, high-level scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) are output.

[0214] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 each correspond to a pull-up transistor.

[0215] When the output scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) are executed, the bootstrap capacitors CS1, CS2, CS3, and CS4, in sync with the high-level scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3), bootstrap or increase the voltage of the Q node to a bootstrap voltage level higher than the first high-level gating voltage GVDD1. If the voltage of the Q node is bootstrap, the high-level scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3) can be output quickly and without distortion as the scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3).

[0216] The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 respond to the voltage of the QB node by outputting low-level scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively, based on the first low-level gating voltage GVSS1.

[0217] When the voltage at node QB is high, transistors T72, T74, T76, and T78 are turned on, supplying the first low-level gating voltage GVSS1 to output nodes NO2, NO3, NO4, and NO5, respectively. Correspondingly, low-level scan signals SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3) are output.

[0218] The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 each correspond to a pull-down transistor.

[0219] The following example is described: three high-level gating voltages GVDD1, GVDD2, and GVDD3, set to different levels, and three low-level gating voltages GVSS1, GVSS2, and GVSS3, set to different levels, are supplied to each stage of the circuit. For example, the first high-level gating voltage GVDD1, the second high-level gating voltage GVDD2, and the third high-level gating voltage GVDD3 can be set to 20V, 16V, and 14V, respectively, and the first low-level gating voltages GVSS1, the second low-level gating voltage GVSS2, and the third low-level gating voltage GVSS3 can be set to -6V, -10V, and -12V, respectively. These values ​​are merely examples, and the levels of the high-level and low-level gating voltages can be set differently depending on the implementation.

[0220] Since the gate driver integrated circuit (GDIC) comprises multiple transistors (e.g., each of which may have its own slightly different characteristic values), the degradation and lifetime of the GDIC can be determined by the transistor that degrades the most among them.

[0221] Typically, in a gated driver integrated circuit (GDIC), the stability of the Q node plays a crucial role. Therefore, it can be said that the stress applied to transistors T31 and T32, which constitute the Q node stabilization unit 506, is relatively large.

[0222] Accordingly, in order to extend the lifespan of the gate driver integrated circuit GDIC, a structure for sensing and compensating for the degradation of transistors T31 and T32 constituting the Q-node stabilization unit 506 according to the driving time of the display device 100 is preferred.

[0223] Figure 8 This is a view illustrating an example of a structure for compensating for the deterioration of a gating drive circuit in a display device according to an embodiment of the present disclosure.

[0224] Reference Figure 8 In the display device 100 according to an embodiment of the present disclosure, the feedback circuit 516 may be included in at least one or more of the multiple gating drive integrated circuits (GDICs) constituting the gating drive circuit 120.

[0225] Accordingly, a gating driver integrated circuit with feedback circuit 516 can be represented as a feedback gating driver integrated circuit GDIC(FB), and a gating driver integrated circuit without feedback circuit 516 can be represented as a typical gating driver integrated circuit.

[0226] Feedback circuit 516 may include at least one or more feedback transistors FT1, FT2, and FT3 whose gate nodes are connected to the QB node. An example is shown here: Feedback circuit 516 includes three feedback transistors FT1, FT2, and FT3 and is connected to the rear end of carry signal output unit 512 (scan signal output unit 514 is omitted).

[0227] The gate nodes of feedback transistors FT1, FT2, and FT3 are connected to the QB node of the feedback gating driver integrated circuit GDIC (FB), and the drain nodes of feedback transistors FT1, FT2, and FT3 are connected to the first low-level gating voltage GVSS1. The source nodes of feedback transistors FT1, FT2, and FT3 are jointly connected and connected to the feedback line.

[0228] Accordingly, the high-level gating voltage compensation circuit 152 receives the feedback voltage GVDD_FB through the feedback circuit 516 configured in the feedback gating driver integrated circuit GDIC (FB), and generates a compensated high-level gating voltage PGVDD to be applied to the multiple gating driver integrated circuits GDIC. The compensated high-level gating voltage PGVDD can be applied to both the feedback gating driver integrated circuit GDIC (FB) with feedback circuit 516 and the gating driver integrated circuit GDIC without feedback circuit 516.

[0229] The feedback voltage GVDD_FB can be the source node voltage of the feedback transistors FT1, FT2, and FT3.

[0230] In this case, in order to reduce the stress on transistors T31 and T32, it is effective to supply a compensation high-potential gating voltage PGVDD generated by the high-potential gating voltage compensation circuit 152 as a second high-potential gating voltage GVDD2 corresponding to the driving voltage of transistors T41, T42, T43 and T44 constituting inverter unit 508, so as to reduce the gate-source voltage of transistors T31 and T32 constituting Q-node stabilization unit 506.

[0231] The high-potential gating voltage compensation circuit 152 can be set in the power management circuit 150.

[0232] The high-potential gating voltage compensation circuit 152 may include an amplifier AMP having a non-inverting input terminal (+) for receiving feedback voltage GVDD_FB, a reference resistor Rref connected to the inverting input terminal (-) of the amplifier AMP to transmit a reference voltage Vref, at least one setting resistor R1 and R2 connected to the non-inverting input terminal (+) of the amplifier AMP to transmit at least one setting voltage V1 and V2, and a feedback resistor Rfb connected between the inverting input terminal (-) and the output terminal of the amplifier AMP.

[0233] Accordingly, the high-level gating voltage compensation circuit 152 can cooperate with the feedback voltage GVDD_FB transmitted from the feedback circuit 516 of the feedback gating driver integrated circuit GDIC (FB) to control the level of the compensation high-level gating voltage PGVDD applied to the multiple gating driver integrated circuits GDIC.

[0234] In this case, the values ​​of the reference resistor Rref, setting resistors R1 and R2, and feedback resistor Rfb can be determined based on the level of the compensation high-level gating voltage PGVDD controlled by the feedback voltage GVDD_FB applied to the non-inverting input terminal (+).

[0235] Figure 9 and Figure 10 This is a conceptual illustration of the effect of reducing the degradation of a gating drive circuit by means of a process for compensating for a high-potential gating voltage applied to the gating drive circuit in a display device, according to an embodiment of the present disclosure.

[0236] Reference Figure 9 As the driving time of the display device 100 according to the embodiments of the present disclosure increases, the threshold voltage Vth of transistors T31 and T32 constituting the Q-node stabilization unit 506 of the gating drive circuit 120 increases.

[0237] In this case, the voltage corresponding to the difference between the high-potential gating voltage GVDD2 and the threshold voltage Vth increases, and acts as stress in the transistors T31 and T32 that constitute the Q-node stabilization unit 506.

[0238] If the high-potential gating voltage GVDD2 applied to the gating drive circuit 120 remains at a constant level, the stress applied to the transistors T31 and T32 constituting the Q-node stabilization unit 506 increases due to the large difference between the high-potential gating voltage GVDD2 and the threshold voltage Vth during the initial driving period of the display device 100 (stress 1).

[0239] The stress (stress 2) on transistors T31 and T32 constituting the Q-node stabilization unit 506 can be alleviated by supplying a compensation high-potential gating voltage PGVDD that reflects the lower level of the feedback voltage GVDD_FB supplied by the feedback circuit 516 configured in the gating drive circuit 120 than the high-potential gating voltage GVDD2 applied to the gating drive circuit 120.

[0240] As a result, the degradation rate of transistors T31 and T32 constituting the Q-node stabilization unit 506 can be reduced, and the lifetime of the gating drive circuit 120 can be increased.

[0241] Figure 10The graph illustrates the result of extending the lifespan of the gating drive circuit 120 by supplying a compensation high-potential gating voltage PGVDD that reflects a lower level of the feedback voltage GVDD_FB supplied by the feedback circuit 516 configured in the gating drive circuit 120 than the high-potential gating voltage GVDD2 applied to the gating drive circuit 120.

[0242] Although the high-potential gating voltage compensation circuit 152 can generate a compensation high-potential gating voltage PGVDD to linearly correspond to the feedback voltage GVDD_FB supplied by the feedback circuit 516 configured in the gating drive circuit 120, the level of the compensation high-potential gating voltage PGVDD can also be gradually changed using a scaler.

[0243] Figure 11 This is a view illustrating an example of a gating driver integrated circuit including a feedback circuit in a display device according to an embodiment of the present disclosure.

[0244] Reference Figure 11 In the display device 100 according to an embodiment of the present disclosure, a feedback gating driver integrated circuit GDIC (FB) with a built-in feedback circuit 516 may be disposed in a portion of the display panel 110.

[0245] For example, a feedback gating driver integrated circuit (GDIC) (FB) can be disposed in the upper / lower / left / right corners of the display panel 110 to compensate for the deterioration distribution of the display panel 110.

[0246] In this case, the degradation state of the gating driver integrated circuit GDIC can be determined based on the position of the display panel 110 by receiving feedback voltage GVDD_FB from the feedback gating driver integrated circuit GDIC (FB) located in the upper / lower / left / right corners of the display panel 110.

[0247] As a result, the degradation state of the gate driver integrated circuit GDIC can be detected according to various positions within the display panel 110, and a compensation high-potential gate voltage PGVDD reflecting the degradation state can be generated according to the corresponding position in the display panel 110.

[0248] The display device 100 of this disclosure can also use the compensated high-potential gating voltage PGVDD to identify whether the feedback circuit 516 built into the feedback gating driver integrated circuit GDIC (FB) is defective.

[0249] Figure 12 This is a diagram illustrating an example of a feedback circuit and defect state built into a gating driver integrated circuit in a display device according to an embodiment of the present disclosure.

[0250] Reference Figure 12In the display device 100 according to an embodiment of the present disclosure, the feedback circuit 516 built in the feedback gating driver integrated circuit GDIC (FB) may cause various defects in the connection lines.

[0251] For example, there may be a situation where the gate node and source node of the third feedback transistor FT3 in the last stage of the feedback transistors FT1, FT2 and FT3 constituting the feedback circuit 516 are short-circuited (Case 1), the gate node and drain node of the third feedback transistor FT3 are short-circuited (Case 2), the drain node and source node of the third feedback transistor FT3 are short-circuited, or the feedback line is open (Case 4).

[0252] When the gate and source nodes of the third feedback transistor FT3 are short-circuited (Case 1), the third feedback transistor FT3 is turned off. In this case, the feedback voltage GVDD_FB is incorrect, and the compensation high-level gating voltage PGVDD is not generated normally, resulting in a horizontal row defect in the display panel 110.

[0253] When the gate and drain nodes of the third feedback transistor FT3 are short-circuited (Case 2), the third feedback transistor FT3 is also turned off. As a result, the feedback voltage GVDD_FB is incorrect, and the compensating high-level gating voltage PGVDD is not generated normally, thus causing a horizontal row defect in the display panel 110.

[0254] When the drain and source nodes of the third feedback transistor FT3 are short-circuited (Case 3), the third feedback transistor FT3 remains in the on state. Correspondingly, the feedback voltage GVDD_FB is generated normally, but the degradation caused by the feedback circuit 516 progresses rapidly, thus accelerating defects in the feedback gating driver integrated circuit GDIC (FB). In this case, this type of error in the gating driver circuit 120 causes defects in the display panel 110.

[0255] When the feedback line extending from the source node of the third feedback transistor FT3 is open (Case 4), the third feedback transistor FT3 remains in the off state. Accordingly, the feedback voltage GVDD_FB is not transmitted to the high-level gating voltage compensation circuit 152, causing the compensation high-level gating voltage PGVDD to remain at the same level (e.g., compensation cannot be properly performed). As a result, it may be impossible to achieve the reduction in degradation of the gating drive circuit 120 caused by the high-level gating voltage GVDD.

[0256] Accordingly, it is desirable to detect errors in the feedback circuit 516 built into the feedback gating driver integrated circuit GDIC (FB), and when an error occurs, to control the compensation high-level gating voltage PGVDD by displaying or reflecting the error.

[0257] The circuitry used to sense the characteristic value of the driving transistor DRT constituting the sub-pixel SP can be used to detect errors in the feedback circuitry 516 built into the feedback gating driver integrated circuit GDIC (FB). For example, the circuitry used to sense the characteristic value of the driving transistor DRT constituting the sub-pixel SP can be reused to perform the additional function of detecting errors in the feedback circuitry 516.

[0258] Figure 13 This is a view illustrating an example circuit structure of a driving transistor in a sensing display device according to an embodiment of the present disclosure.

[0259] Reference Figure 13 The display device 100 according to embodiments of the present disclosure may include components for compensating for deviations in the characteristic values ​​of the driving transistor DRT.

[0260] For example, during the sensing period of the display device 100, the characteristic value or change of the characteristic value of the driving transistor DRT can be applied as the voltage of the second node N2 of the driving transistor DRT (e.g., Vdata-Vth).

[0261] When the sensing transistor SENT is in the ON state, the voltage at the second node N2 of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL. The line capacitor Cline on the reference voltage line RVL can be charged by the voltage at the second node N2 of the driving transistor DRT. Due to the sensed voltage Vsen of the line capacitor Cline being charged, the reference voltage line RVL can have a voltage corresponding to the voltage at the second node N2 of the driving transistor DRT.

[0262] The display device 100 may include an analog-to-digital converter (ADC) that senses the voltage of a reference voltage line RVL corresponding to the voltage of the second node N2 of the driving transistor DRT and converts the voltage into digital data, as well as switching circuits SAM and SPRE for sensing characteristic values ​​of the driving transistor DRT.

[0263] The switching circuits SAM and SPRE used to control the sensing drive may include a feature value sensing switch SPRE for controlling the connection between each reference voltage line RVL and the sensing node Npres supplied with the reference voltage, and a sampling switch SAM for controlling the connection between each reference voltage line RVL and the analog-to-digital converter ADC.

[0264] The eigenvalue sensing switch SPRE is a switch used to control the sensing drive operation, and the reference voltage supplied by the eigenvalue sensing switch SPRE to the reference voltage line RVL becomes the sensing reference voltage VpreS.

[0265] The switching circuit used to sense the characteristic values ​​of the driving transistor DRT may include a display driver switch RPRE for controlling display driving operation. The display driver switch RPRE can control the connection between each reference voltage line RVL and the display driver reference voltage node Nprer to which the reference voltage is supplied.

[0266] The display drive switch RPRE is a switch used for display drive operation, and the reference voltage supplied by the display drive switch RPRE to the reference voltage line RVL corresponds to the display drive reference voltage VpreR.

[0267] In this scenario, the feature value sensing switch SPRE and the display drive switch RPRE can be set separately or integrated into a single switch. The sensing reference voltage VpreS and the display drive reference voltage VpreR can have the same voltage value or different voltage values.

[0268] The timing controller 140 of the display device 100 may include a memory MEM for storing data transmitted from the analog-to-digital converter (ADC) or previously stored reference values, and a compensation circuit COMP for comparing the reference values ​​stored in the memory MEM with the received data and compensating for deviations in the feature values. In this case, the compensation value calculated by the compensation circuit COMP can be stored in the memory MEM.

[0269] Accordingly, the timing controller 140 can compensate the digital image data DATA supplied to the data drive circuit 130 by using the compensation value calculated by the compensation circuit COMP, and can output the compensated digital image data DATA_comp to the data drive circuit 130.

[0270] Accordingly, the data driving circuit 130 can convert the compensated digital image data DATA_comp into an analog signal type data voltage Vdata via a digital-to-analog converter (DAC), and output the converted data voltage Vdata to the data line DL via an output buffer (BUF). As a result, deviations in the characteristic values ​​of the driving transistor DRT in the corresponding sub-pixel SP (e.g., deviations in threshold voltage or mobility) can be compensated.

[0271] The data driver circuit 130 may include a data voltage output circuit 136 comprising a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF). In some cases, the data driver circuit 130 may also include an analog-to-digital converter (ADC) and various switches (SAM, SPRE, and RPRE). Alternatively, the ADC and the various switches (SAM, SPRE, and RPRE) may be located externally to the data driver circuit 130.

[0272] The compensation circuit COMP can exist inside or outside the timing controller 140. The memory MEM can be located outside the timing controller 140, or it can be implemented inside the timing controller 140 in the form of a register.

[0273] The display device 100 of this disclosure can use a circuit that senses the characteristic value of the driving transistor DRT to detect errors in the feedback circuit 516 built into the feedback gating driver integrated circuit GDIC (FB).

[0274] Figure 14 This is a view illustrating an example of the configuration of a feedback circuit in a feedback gating driver integrated circuit built into a display device for detecting errors according to an embodiment of the present disclosure.

[0275] Reference Figure 14 In the display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 may include a data voltage output circuit 136 comprising a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF). In some cases, the data driving circuit 130 may also include an analog-to-digital converter (ADC) and various switches SAM, SPRE, RPRE, and SGVDD. The ADC and the various switches SAM, SPRE, RPRE, and SGVDD may be disposed externally to the data driving circuit 130.

[0276] The switching circuits SAM, SPRE, and SGVDD for controlling the sensing drive may include: a feature value sensing switch SPRE for controlling the connection between a reference voltage line RVL corresponding to the sensing line used to detect the feature value of the driving transistor DRT and a sensing reference voltage node Npres supplied with a sensing reference voltage VpreS; a gating sensing switch SGVDD for controlling the transmission path of a compensated high-level gating voltage PGVDD supplied from the high-level gating voltage compensation circuit 152; and a sampling switch SAM for controlling the connection between analog-to-digital converters (ADCs).

[0277] The eigenvalue sensing switch SPRE is a switch used to control the eigenvalue sensing of the drive transistor DRT, and the reference voltage supplied by the eigenvalue sensing switch SPRE to the reference voltage line RVL becomes the sensing reference voltage VpreS.

[0278] The gating sensing switch SGVDD is used to control the sensing of the compensation high-potential gating voltage PGVDD transmitted from the high-potential gating voltage compensation circuit 152, and the operation of the gating sensing switch SGVDD applies the compensation high-potential gating voltage PGVDD to the reference voltage line RVL.

[0279] If the sampling switch SAM is turned on at the same time as the gating sensing switch SGVDD is turned on, the timing controller 140 can detect the compensated high-level gating voltage PGVDD supplied to the reference voltage line RVL. In this way, the sensing circuit can switch between the characteristic value of the sensing drive transistor DRT and the sensing compensated high-level gating voltage PGVDD.

[0280] The switching circuit used to sense the characteristic values ​​of the driving transistor DRT may include a display driver switch RPRE for controlling display driving operation. The display driver switch RPRE can control the connection between each reference voltage line RVL and the display driver reference voltage node Nprer to which the reference voltage is supplied.

[0281] The display drive switch RPRE is a switch used for display drive operation, and the reference voltage supplied by the display drive switch RPRE to the reference voltage line RVL corresponds to the display drive reference voltage VpreR.

[0282] The timing controller 140 can determine whether there is an error in the feedback gating driver integrated circuit GDIC(FB) based on the level or change of the compensation high-level gating voltage PGVDD, and when it is determined that an error has occurred in the feedback gating driver integrated circuit GDIC(FB), it outputs a gating error signal GBD or controls the high-level gating voltage compensation circuit 152 to change the level of the compensation high-level gating voltage PGVDD.

[0283] Therefore, the display device 100 of this disclosure effectively determines errors in the gating drive circuit 120 by detecting the level change of the compensation high-potential gating voltage PGVDD via the gating sensing switch SGVDD formed on the reference voltage line RVL of the data drive circuit 130, while controlling the level of the compensation high-potential gating voltage PGVDD, which reflects the feedback voltage GVDD_FB of the feedback circuit 516 provided at the output of the feedback gating drive integrated circuit GDIC(FB), to detect the level change of the compensation high-potential gating voltage PGVDD.

[0284] In addition, in the display device 100 of this disclosure, the power management circuit 150 can selectively supply the compensation high-potential gating voltage PGVDD and the display drive reference voltage VpreR according to timing.

[0285] Figure 15 This is a view illustrating an example of a power management circuit for selectively supplying a compensation high-potential gating voltage and a display drive reference voltage in a display device, according to an embodiment of the present disclosure.

[0286] Reference Figure 15In the display device 100 according to an embodiment of the present disclosure, the power management circuit 150 may include switches SPRER and SGVDD, and an amplifier Amp, which selectively supply the compensation high-potential gating voltage PGVDD and the display drive reference voltage VpreR according to timing.

[0287] In this case, since the display drive reference voltage VpreR may be different from the compensation high-level gating voltage PGVDD generated by the high-level gating voltage compensation circuit 152, a scaler 154 may be included to adjust the compensation high-level gating voltage PGVDD to a level close to the display drive reference voltage VpreR.

[0288] The display sensing switch SPRER is used to control the timing of supplying the display drive reference voltage VpreR to the amplifier Amp, and the gating sensing switch SGVDD is used to control the timing of supplying the compensated high-level gating voltage PGVDD transmitted from the high-level gating voltage compensation circuit 152 to the amplifier Amp.

[0289] Therefore, by operating the display sensing switch SPRER and the gating sensing switch SGVDD, the amplifier Amp can be used to apply either the display drive reference voltage VpreR or the compensation high-level gating voltage PGVDD to the reference voltage line RVL. In this way, the sensing circuitry for the sub-pixel can switch between the characteristic value of the sensing drive transistor DRT and the sensing compensation high-level gating voltage PGVDD.

[0290] The on / off operation of amplifier Amp can be controlled by amplifier control signal OPC.

[0291] Thus, when the power management circuit 150 selectively supplies the compensation high-potential gating voltage PGVDD and the display drive reference voltage VpreR according to the timing, it is not necessary to set up a gating sensing switch SGVDD in the data drive circuit 130 for controlling the compensation high-potential gating voltage PGVDD.

[0292] In order to minimize the deviation of the analog-to-digital converter (ADC), the display device 100 of this disclosure can sense the compensation high-potential gating voltage PGVDD and characteristic value through a dummy channel, thereby reducing the offset noise of the ADC.

[0293] Figure 16 This is a view illustrating an example of a structure in which sensing channels and dummy channels are arranged in a display device according to an embodiment of the present disclosure.

[0294] Reference Figure 16According to embodiments of the present disclosure, the display device 100 can supply a compensation high-potential gating voltage PGVDD or a virtual reference voltage VRTA through virtual channels CHd1 to CHdn under the control of the gating sensing switch SGVDD and the virtual sensing switch SRTA.

[0295] One or more dummy channels CHd1 to CHdn, supplied with a compensated high-potential gating voltage PGVDD or a dummy reference voltage VRTA, can be configured between sensing channels CH1 to CHn connected to the sub-pixels constituting the display panel 110. Figure 16 (a) or can be arranged in a row on the left or right side of sensing channels CH1 to CHn. Figure 16 (b)

[0296] Sensing channels CH1 to CHn are connected to the sensing lines corresponding to the sub-pixels via sampling switches SAM1 to SAMn, respectively, so as to detect the compensation high-potential gating voltage PGVDD or the sensing voltage reflecting the characteristic value (threshold voltage or mobility) of the sub-pixel SP.

[0297] Accordingly, the dummy channels CHd1 to CHdn can receive the dummy reference voltage VRTA or the compensation high-potential gating voltage PGVDD through the dummy sampling switches SAMd1 to SAMdn to compensate for the gain or offset of the analog-to-digital converter (ADC).

[0298] The above implementation methods are briefly described below.

[0299] The display device 100 disclosed herein may include: a display panel 110 having a plurality of sub-pixels SP; a gating drive circuit 120 configured to supply a plurality of scan signals SCAN to the display panel 110 via a plurality of gating lines GL; a data drive circuit 130 configured to supply a plurality of data voltages Vdata to the display panel 110 via a plurality of data lines DL; a power management circuit 150 configured to supply a plurality of drive voltages to the gating drive circuit 120 and the data drive circuit 130 based on a feedback voltage GVDD_FB transmitted from the gating drive circuit 120 and to supply a compensated high-potential gating voltage PGVDD to the gating drive circuit 120; and a timing controller 140 configured to control the gating drive circuit 120, the data drive circuit 130 and the power management circuit 150.

[0300] The gating drive circuit 120 may include a plurality of gating drive integrated circuits (GDICs). At least one of the plurality of gating drive integrated circuits (GDICs) may be configured as a feedback gating drive integrated circuit (FB) including feedback circuitry 516.

[0301] The feedback gating driver integrated circuit GDIC (FB) can be located in one or more corners of the display panel 110.

[0302] The gating driver integrated circuit (GDIC) may include: a line selection unit 502 configured to charge an M node based on a previous carry signal C(k-2) in response to an input to a line sensing preparation signal LSP; a Q node control unit 504 configured to charge a Q node to a first high-level gating voltage GVDD1 in response to a previous carry signal C(k-2), and to discharge a Q node to a third low-level gating voltage GVSS3 in response to an input to a subsequent carry signal C(k+2); a Q node stabilization unit 506 configured to discharge both the Q node and the QH node to the third low-level gating voltage GVSS3 in response to the voltage of the QB node; an inverter unit 508 configured to change the voltage level of the QB node according to the voltage level of the Q node; and a QB node stabilization unit 510 configured to... In response to the subsequent carry signal C(k+2), the reset signal RESET, and the charging voltage of the M node, the QB node is discharged to the level of the third low-level gating voltage GVSS3; the carry signal output unit 512 is configured to output the carry signal C(k) based on the voltage level of the Q node or the QB node, the voltage level of the carry clock signal CRCLK(k), or the level of the third low-level gating voltage GVSS3; and the scan signal output unit 514 is configured to output multiple scan signals SCAN based on the voltage level of the Q node or the QB node, the voltage level of multiple scan clock signals SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3), or the level of the first low-level gating voltage GVSS1.

[0303] The compensation high-potential gating voltage PGVDD can correspond to the second high-potential gating voltage GVDD2 driving the inverter unit 508.

[0304] The feedback circuit 516 may include at least one feedback transistor FT1, FT2, and FT3 having a gate node connected to the QB node, a drain node connected to the first low-potential gating voltage GVSS1, and a source node connected to the feedback line to which the feedback voltage GVDD_FB is transmitted.

[0305] The power management circuit 150 may include a high-potential gating voltage compensation circuit 152 configured to supply a compensation high-potential gating voltage PGVDD to a plurality of gating driver integrated circuits GDICs using a feedback voltage GVDD_FB transmitted via feedback circuit 516.

[0306] The high-potential gating voltage compensation circuit 152 may include an amplifier AMP having a non-inverting input terminal (+) to which a feedback voltage GVDD_FB is applied, a reference resistor Rref connected to the inverting input terminal (-) of the amplifier to transmit a reference voltage, at least one setting resistor R1 and R2 connected to the non-inverting input terminal (+) of the amplifier AMP to transmit at least one setting voltage, and a feedback resistor Rfb connected between the output terminal and the inverting input terminal (-) of the amplifier AMP.

[0307] The high-potential gating voltage compensation circuit 152 may also include a scaler that changes the level of the compensation high-potential gating voltage PGVDD.

[0308] The data driving circuit 130 may include an analog-to-digital converter (ADC) that senses the voltage of the sensing line and converts the voltage into digital data, a characteristic value sensing switch SPRE that controls the connection between the sensing line and the node supplied with a sensing reference voltage VpreS, a gating sensing switch SGVDD that controls the connection between the sensing line and the node supplied with a compensated high-potential gating voltage PGVDD, and a sampling switch SAM that controls the connection between the sensing line and the ADC.

[0309] The sensing line can be connected to the dummy channel CHd to which a dummy reference voltage VRTA is applied. The characteristic value sensing switch SPRE controls the connection between the dummy channel CHd and the node supplied with the dummy reference voltage VRTA. The gating sensing switch SGVDD controls the connection between the dummy channel CHd and the node supplied with a compensated high-potential gating voltage PGVDD.

[0310] A gating drive circuit 120 according to an embodiment of the present disclosure, configured to supply multiple scan signals SCAN through multiple gating lines GL to a display panel 110 having multiple sub-pixels SP, may include multiple gating drive integrated circuits GDIC. At least one of the multiple gating drive integrated circuits GDIC may be configured to include a feedback gating drive integrated circuit GDIC (FB) including a feedback circuit 516, and configured to receive a compensated high-level gating voltage PGVDD generated by the power management circuit 150 using the feedback voltage GVDD_FB generated by the feedback circuit 516.

[0311] A power management circuit 150 according to an embodiment of the present disclosure may include a high-potential gating voltage compensation circuit 152 configured to supply a compensation high-potential gating voltage PGVDD to the gating drive circuit 120 based on a feedback voltage GVDD_FB transmitted from the gating drive circuit 120.

[0312] According to an embodiment of the present disclosure, a data driving circuit 130 that supplies multiple data voltages Vdata to the display panel 110 via multiple data lines DL may include an analog-to-digital converter (ADC) that senses the voltage of the sensing lines and converts the voltage into digital data, a feature value sensing switch SPRE that controls the connection between the sensing lines and the nodes supplied with the sensing reference voltage, a gating sensing switch SGVDD that controls the connection between the sensing lines and the nodes supplied with a compensation high-potential gating voltage PGVDD transmitted from the power management circuit 150, and a sampling switch SAM that controls the connection between the sensing lines and the ADC.

[0313] The above description has been provided to enable those skilled in the art to form and use the technical concepts of the invention, and has been provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will readily be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but is given the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as being included within the scope of the invention.

[0314] Cross-reference to related applications

[0315] This application claims priority to Korean Patent Application No. 10-2021-0185146, filed in Korea on December 22, 2021, the entire contents of which are hereby incorporated by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel, the display panel comprising a plurality of sub-pixels; A gating drive circuit is configured to supply multiple scan signals to the display panel through multiple gating lines and output a feedback voltage; A data driving circuit, configured to supply multiple data voltages to the display panel via multiple data lines; Power management circuit, the power management circuit being configured to: Multiple driving voltages are supplied to the gating drive circuit and the data drive circuit, and Based on the feedback voltage transmitted from the gating drive circuit, a compensated high-potential gating voltage is supplied to the gating drive circuit; as well as A timing controller configured to control the gating drive circuit, the data drive circuit, and the power management circuit. The timing controller is configured to determine errors in the gating drive circuit based on the compensated high-potential gating voltage, and to output a gating error signal or control the high-potential gating voltage.

2. The display device according to claim 1, wherein, The gating drive circuit includes multiple gating drive integrated circuits, and At least one of the plurality of gating driver integrated circuits is configured as a feedback gating driver integrated circuit including a feedback circuit for outputting the feedback voltage.

3. The display device according to claim 2, wherein, The feedback gating driver integrated circuit is located in the corner of the display panel.

4. The display device according to claim 2, wherein, The at least one of the plurality of gating driver integrated circuits includes: A line selection unit, configured to charge the M-node based on a previous carry signal in response to an input of a line sensing readiness signal; Q-node control unit, the Q-node control unit being configured to charge the Q-node to a first high-level gating voltage in response to the previous carry signal, and to discharge the Q-node to a third low-level gating voltage in response to the input of a subsequent carry signal; Q-node stabilization unit, the Q-node stabilization unit being configured to discharge the Q-node and QH-node to the level of the third low-potential gating voltage in response to the voltage of the QB-node; An inverter unit configured to change the voltage level of the QB node according to the voltage level of the Q node; QB node stabilization unit, the QB node stabilization unit being configured to discharge the QB node to the level of the third low potential gating voltage in response to the subsequent carry signal, reset signal and the charging voltage of the M node; A carry signal output unit, configured to output a current carry signal based on the voltage level of the Q node or the voltage level of the QB node, the voltage level of the carry clock signal, or the level of the third low-level gating voltage; and A scan signal output unit is configured to output multiple scan signals based on the voltage level of the Q node or the voltage level of the QB node, the voltage level of multiple scan clock signals, or the level of a first low-potential gating voltage.

5. The display device according to claim 4, wherein, The compensation high-potential gating voltage corresponds to the second high-potential gating voltage that drives the inverter unit.

6. The display device according to claim 4, wherein, The feedback circuit includes at least one feedback transistor having a gate node connected to the QB node, a drain node connected to a node for supplying the first low-potential gating voltage, and a source node connected to a feedback line for transmitting the feedback voltage.

7. The display device according to claim 2, wherein, The power management circuit includes a high-potential gating voltage compensation circuit configured to supply the compensation high-potential gating voltage to the plurality of gating driver integrated circuits based on the feedback voltage output by the feedback circuit.

8. The display device according to claim 7, wherein, The high-potential gating voltage compensation circuit includes: An amplifier having a non-inverting input terminal to which the feedback voltage is applied; A reference resistor is connected to the inverting input terminal of the amplifier to transmit a reference voltage; At least one setting resistor is connected to the non-inverting input terminal of the amplifier to deliver at least one setting voltage; and A feedback resistor is connected between the inverting input terminal and the output terminal of the amplifier.

9. The display device according to claim 7, wherein, The high-potential gating voltage compensation circuit also includes a scaler configured to change the level of the compensated high-potential gating voltage.

10. The display device according to claim 7, wherein, The power management circuit includes: A gating sensor switch configured to control the connection between nodes supplied with the compensated high-potential gating voltage; A display sensing switch, configured to control the connection between nodes supplied with a display drive reference voltage; and An amplifier configured to supply the compensated high-potential gating voltage or the display drive reference voltage to the data drive circuit under the control of the gating sensing switch and the display sensing switch.

11. The display device according to claim 2, wherein, The data driving circuit includes: An analog-to-digital converter, configured to sense the voltage of a sensing line and convert the voltage into digital data; A feature value sensing switch, the feature value sensing switch being configured to control the connection between the sensing line and the node supplied with a sensing reference voltage; A gating sensor switch configured to control the connection between the sensing line and a node supplied with the compensated high-potential gating voltage; and A sampling switch configured to control the connection between the sensing line and the analog-to-digital converter.

12. The display device according to claim 11, wherein, The sensing line is connected to a dummy channel supplied with a dummy reference voltage. The feature value sensing switch is configured to control the connection between the dummy channel and the node supplied with the dummy reference voltage, and The gating sensor switch is configured to control the connection between the dummy channel and the node supplied with the compensated high-potential gating voltage.

13. A gating driving circuit configured to supply multiple scan signals to a display panel having multiple sub-pixels via multiple gating lines, the gating driving circuit comprising: Multiple gating driver integrated circuits, At least one of the plurality of gating driver integrated circuits is configured as a feedback gating driver integrated circuit including a feedback circuit, and is configured to receive a compensated high-potential gating voltage generated by a power management circuit based on a feedback voltage generated by the feedback circuit. Specifically, based on the compensated high-potential gating voltage, the timing controller controls the gating drive circuit, determines the error in the gating drive circuit, and outputs a gating error signal or controls the high-potential gating voltage.

14. The gating drive circuit according to claim 13, wherein, The at least one of the plurality of gating driver integrated circuits includes: A line selection unit, configured to charge the M-node based on a previous carry signal in response to an input of a line sensing readiness signal; Q-node control unit, the Q-node control unit being configured to charge the Q-node to a first high-level gating voltage in response to the previous carry signal, and to discharge the Q-node to a third low-level gating voltage in response to the input of a subsequent carry signal; Q-node stabilization unit, the Q-node stabilization unit being configured to discharge the Q-node and QH-node to the level of the third low-potential gating voltage in response to the voltage of the QB-node; An inverter unit configured to change the voltage level of the QB node according to the voltage level of the Q node; QB node stabilization unit, the QB node stabilization unit being configured to discharge the QB node to the level of the third low potential gating voltage in response to the subsequent carry signal, reset signal and the charging voltage of the M node; A carry signal output unit, configured to output a current carry signal based on the voltage level of the Q node or the voltage level of the QB node, the voltage level of the carry clock signal, or the level of the third low-level gating voltage; and A scan signal output unit is configured to output multiple scan signals based on the voltage level of the Q node or the voltage level of the QB node, the voltage level of multiple scan clock signals, or the level of a first low-potential gating voltage.

15. The gating drive circuit according to claim 14, wherein, The compensation high-potential gating voltage corresponds to the second high-potential gating voltage that drives the Q-node stabilization unit.

16. The gating drive circuit according to claim 14, wherein, The feedback circuit includes at least one feedback transistor having a gate node connected to the QB node, a drain node connected to a node for supplying the first low-potential gating voltage, and a source node connected to a feedback line for transmitting the feedback voltage.

17. A power management circuit configured to supply a drive voltage to a gating drive circuit for supplying multiple scan signals to a display panel via multiple gating lines, the power management circuit comprising: High-potential gating voltage compensation circuit, wherein the high-potential gating voltage compensation circuit is configured as follows: Receive feedback voltage from the gating drive circuit, and Based on the feedback voltage transmitted from the gating drive circuit, a compensated high-potential gating voltage is supplied to the gating drive circuit, and Specifically, based on the compensated high-potential gating voltage, the timing controller controls the power management circuit and the gating drive circuit, determines the error in the gating drive circuit, and outputs a gating error signal or controls the high-potential gating voltage.

18. The power management circuit according to claim 17, wherein, The high-potential gating voltage compensation circuit includes: An amplifier having a non-inverting input terminal to which the feedback voltage is applied; A reference resistor is connected to the inverting input terminal of the amplifier to transmit a reference voltage; At least one setting resistor is connected to the non-inverting input terminal of the amplifier to deliver at least one setting voltage; and A feedback resistor is connected between the inverting input terminal and the output terminal of the amplifier.

19. A data driving circuit that supplies multiple data voltages to a display panel via multiple data lines, the data driving circuit comprising: An analog-to-digital converter, configured to sense the voltage of a sensing line connected to a sub-pixel and convert the voltage into digital data; A feature value sensing switch, the feature value sensing switch being configured to control the connection between the sensing line and the node supplied with a sensing reference voltage; A gating sensor switch configured to control the connection between the sensing line and a node supplied with a compensated high-potential gating voltage from a power management circuit. as well as A sampling switch, configured to control the connection between the sensing line and the analog-to-digital converter, and Specifically, based on the compensated high-potential gating voltage, the timing controller controls the data driving circuit to determine errors in the gating driving circuit that supplies multiple scan signals to the display panel, and outputs a gating error signal or controls the high-potential gating voltage.

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