Display devices and their display panels used to improve display quality

Abstract

This disclosure relates to a display device and a display panel thereof for improving display quality. In particular, a display panel includes: pixels located in a display area of ​​the display panel, each pixel comprising: a light-emitting device configured to emit light in response to a driving current; a driving transistor configured to supply the driving current; and a plurality of switching transistors configured to control the supply of the driving current to the light-emitting device via the driving transistor, wherein at least one of the plurality of switching transistors is configured to provide a path for grounding within the pixel, wherein the excitation current is discharged through the path for grounding. Therefore, brightness phenomena caused by unintentional increases in current in pixels adjacent to vias can be improved, thereby improving image quality.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0185276, filed on December 22, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display devices and display panels, and more specifically, to display devices and display panels capable of improving brightness phenomena around vias. Background Technology

[0004] Display devices that display various information on a screen are an important technology in the information and communication era, and they have been continuously developing towards thinner, lighter, more portable, and higher-performance designs. Therefore, display devices that can be manufactured in a lightweight and slim form have always attracted much attention. Display devices using self-emissive elements not only have advantages in power consumption due to low-voltage operation, but also offer excellent high-speed response, high luminous efficiency, wide viewing angle, and high contrast, and are being researched as next-generation display devices. Display devices realize images through multiple sub-pixels arranged in a matrix. Each of these sub-pixels includes a light-emitting device and pixel circuitry such as multiple transistors that independently drive the light-emitting device.

[0005] Specific examples of such display devices (e.g., flat panel displays) can include liquid crystal displays (LCDs), quantum dot displays (QDs), field emission display devices (FEDs), organic light-emitting diode (OLED) displays, and the like. Organic light-emitting diode (OLED) displays, which do not require a separate light source and are gaining attention as devices for compact devices and lifelike color displays, use organic light-emitting diodes (OLEDs) to emit light themselves and have advantages such as fast response time, high contrast, high luminous efficiency, high brightness, and wide viewing angle.

[0006] With the development of technology, in addition to image display functions, display devices can also provide shooting functions and various detection functions. Therefore, display devices are required to include optical electronic devices (also known as light receiving devices or sensors) such as cameras and detection sensors.

[0007] Because the optoelectronic devices are required to receive light from the front of the display device, they need to be mounted in a position advantageous for light reception. Therefore, the camera (camera lens) and detection sensor can be exposed on the front surface of the display device. For this purpose, through-holes or recesses can be formed in certain display areas of the display panel, and the camera or detection sensor can be mounted in these portions (in other words, in these display areas). The through-holes are light-transmitting areas that allow light to pass through to the camera or detection sensor.

[0008] If through-holes are formed in some display areas of the display panel, a defect may occur where charged substances enter (deeply) into the interior of the display panel. This can be a factor that reduces satisfaction with the image quality of the display device.

[0009] Therefore, various driving techniques have been developed to address image anomalies. Furthermore, to improve image quality, operational performance can be improved by controlling the driving conditions of pixels. Summary of the Invention

[0010] The purpose of embodiments of this disclosure is to provide a display device and display panel that can improve the brightness (bright white) around vias by eliminating the excitation current of pixel circuits caused by charged charges.

[0011] In one embodiment, a display panel includes: pixels located in a display area of ​​the display panel, the pixels including: a light-emitting device configured to emit light in response to a drive current; a drive transistor configured to supply the drive current; and a plurality of switching transistors configured to control the supply of the drive current to the light-emitting device via the drive transistor, wherein at least one of the plurality of switching transistors is configured to provide a path for grounding within the pixel, wherein an excitation current is discharged through the path for grounding.

[0012] In one embodiment, a display panel includes: a light-emitting device including a first electrode, a light-emitting layer, and a second electrode; a driving transistor configured to drive the light-emitting device; a bias transistor configured to control the connection between the drain electrode or source electrode of the driving transistor and an initialization voltage line; and a driving power transistor configured to control the electrical connection between the initialization voltage line and the second electrode of the light-emitting device.

[0013] In one embodiment, a display device includes: a display panel comprising an optical region and a non-optical region, the optical region including a (light) transmittance region, and the non-optical region including light-emitting devices located in light-emitting regions of pixels; and a protective glass cover on the display panel, FP22-2573 / LGD / CN.

[0014] The pixel is configured to provide a grounding path within the pixel, through which excitation current is discharged, and the grounding path does not include the light-emitting device.

[0015] In addition to the technical problems of this disclosure described above, other features and advantages of this disclosure may be described below, or will be clearly understood by those skilled in the art from such description.

[0016] According to embodiments of this disclosure, brightness issues arising from unintentional (non-intentional) increases in current in pixels adjacent to vias can be mitigated, thereby improving image quality.

[0017] The effects of this disclosure are not limited to those illustrated above, and may include a wide variety of other effects. Attached Figure Description

[0018] Figure 1A , Figure 1B and Figure 1C This is a plan view of a display device according to an embodiment of the present disclosure.

[0019] Figure 2 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0020] Figure 3 This is a cross-sectional view of the display area of ​​the display panel in a display device according to an embodiment of the present disclosure.

[0021] Figure 4 This is an enlarged plan view illustrating the optical region structure of a display panel in a display device according to an embodiment of the present disclosure.

[0022] Figure 5 According to embodiments of this disclosure along Figure 4 A cross-sectional view of line II′ (cut) in the optical region.

[0023] Figure 6 This is an exemplary cross-sectional view of the area where the through-hole of the display panel is located in a display device according to an embodiment of the present disclosure.

[0024] Figure 7 This is an equivalent circuit diagram of the pixel circuit in a display device according to an embodiment of the present disclosure.

[0025] Figure 8A and Figure 8B The embodiments of this disclosure are used for explanation. Figure 7 The graphics driven by the pixel circuitry in a display device.

[0026] Figure 9A and Figure 9B These are graphics illustrating examples in a display device that are comparative examples and embodiments of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as the methods for implementing them, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided merely to explain that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification will be defined by the scope of the claims.

[0028] The shapes, sizes (dimensions), ratios, angles, quantities, etc., disclosed in the accompanying drawings used to explain the embodiments in this specification are exemplary, and the embodiments in this specification are not limited to the illustrated matters. Furthermore, in describing embodiments, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the essential points of the embodiments.

[0029] In this specification, the use of terms such as “comprising,” “having,” and “including” should be understood to imply that additional parts or elements can be added, unless “only” is used. When an element is represented in the singular, it is understood to include the plural unless otherwise expressly stated.

[0030] In addition, when interpreting components, even if there is no separate explicit description, it should be interpreted as including the error range.

[0031] In descriptions related to spatial relationships, such as when using terms like “on,” “above,” “above,” “below,” “below,” “under,” “below,” “near,” “close to,” or “adjacent” to describe the positional relationship between two elements, unless terms like “directly” or “only” are used, it should be interpreted as one or more elements being able to be further “inserted” between the elements.

[0032] When describing temporal relationships, such as when the temporal relationship is described as "after", "next", "immediately following", "then", "before", discontinuous situations may be included unless "immediately" or "directly" is used.

[0033] When terms such as "first" and "second" are used herein to describe various elements or components (assemblies), it should be understood that these elements or components are not limited thereto. These terms are used only herein to distinguish one element from other elements. Therefore, the first element mentioned below may be a second element within the technical concept of this disclosure.

[0034] The term "at least one" should be understood to include all possible combinations of one or more related elements. For example, "at least one of the first, second, and third elements" may mean all combinations of two or more of the first, second, and third elements, as well as each of the first, second, and third elements.

[0035] The features of the various embodiments in this specification can be combined or coupled to each other in part or in whole, and can be linked or operated in various ways. Furthermore, the various embodiments can be implemented independently of each other, or they can be implemented together in a related manner.

[0036] FP22-2573 / LGD / CN

[0037] In the following description, embodiments of the display device according to the present disclosure will be described with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible, even if they are indicated in different drawings. In addition, since the proportions of the components shown in the drawings may differ from the actual proportions for ease of description, the proportions shown in the drawings are not limited thereto.

[0038] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1A , Figure 1B and Figure 1C This is a plan view of a display device according to an embodiment of the present disclosure.

[0040] refer to Figure 1A , Figure 1B and Figure 1C The display device 100 according to embodiments of the present disclosure may include a display panel 110 for displaying images and one or more optoelectronic devices 11 and 12 (e.g., optical devices).

[0041] The display panel 110 may include a display area (or effective area) AA in which an image is displayed and a non-display area (or ineffective area) NDA in which no image is displayed.

[0042] Multiple sub-pixels can be set in the display area AA, and various signal lines for driving the multiple sub-pixels can be set.

[0043] The non-display area NDA can be the area outside the display area AA. Multiple signal lines can be set in the non-display area NDA, and multiple drive circuits can be connected to it. The non-display area NDA can be bent so that it is not visible from the front, or it can be covered by a casing (not shown). The non-display area NDA is also referred to as a border or border area.

[0044] refer to Figure 1A , Figure 1B and Figure 1C In the display device 100 according to an embodiment of the present disclosure, one or more optical electronics 11 and 12 may be disposed below the display panel 110 (e.g., on the opposite side of the viewing surface).

[0045] The one or more optical electronic devices 11 and 12 may be devices that receive light transmitted through the display panel 110 and perform a predetermined function based on the received light. For example, the one or more optical electronic devices 11 and 12 may include an image capturing device such as a camera (image sensor) and one or more detection sensors such as a proximity sensor and an illumination sensor.

[0046] refer to Figure 1A , Figure 1B and Figure 1C The display panel 110 according to embodiments of the present disclosure may include one or more optical regions OA1 and OA2.

[0047] refer to Figure 1A , Figure 1B and Figure 1C One or more optical regions OA1 and OA2 may be regions that overlap with one or more of the optical electronics 11 and 12. In one embodiment, the optical regions OA1 and OA2 do not have transistors.

[0048] This is shown based on a combination of the previous view and the side view (specifically, the right-side view). Figure 1A For example, the display area AA may include (contain) the first optical area OA1 and the non-optical area NA. FP22-2573 / LGD / CN

[0049] The non-optical region NA is a region that does not overlap with the one or more optical electronic devices (11) and may be referred to as a normal region. The non-optical region NA may be positioned to surround (enclose) the first optical region OA1. Here, at least a portion of the first optical region OA1 may overlap with the first optical electronic device 11. Furthermore, the non-optical region NA is also referred to as a normal region.

[0050] Presented based on a combination of the previous view, left view, and right view. Figure 1B For example, the display area AA may include a first optical area OA1, a second optical area OA2, and a non-optical area NA. The non-optical area NA may be positioned around the first optical area OA1 and the second optical area OA2. Figure 1BIn the example, the non-optical region NA can exist between the first optical region OA1 and the second optical region OA2. Here, at least a portion of the first optical region OA1 can overlap with the first optoelectronic device 11, and at least a portion of the second optical region OA2 can overlap with the second optoelectronic device 12.

[0051] Presented based on a combination of the previous view, left view, and right view. Figure 1C For example, the display area AA may include a first optical area OA1, a second optical area OA2, and a non-optical area NA. The non-optical area NA may be positioned around the first optical area OA1 and the second optical area OA2. Figure 1C In the example, there may be no non-optical region NA between the first optical region OA1 and the second optical region OA2. That is, the first optical region OA1 and the second optical region OA2 are in contact with each other. Here, at least a portion of the first optical region OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical region OA2 may overlap with the second optoelectronic device 12.

[0052] At least one optical region, namely, the first optical region OA1 and / or the second optical region OA2, needs to include a light-transmitting (light transmission) structure. It is required that a light-transmitting structure for transmitting (transferring) light to one or more optical electronic devices 11 and 12 be formed in one or more optical regions OA1 and OA2.

[0053] The one or more optical electronic devices 11 and 12 are devices that require light reception, but are positioned behind (below, opposite to the viewing surface) the display panel 110 to receive light transmitted through the display panel 110.

[0054] One or more optoelectronic devices 11 and 12 may be exposed on the front surface (viewing surface) of the display panel 110.

[0055] For example, the first optical electronic device 11 can be a camera, and the second optical electronic device 12 can be a detection sensor such as a proximity sensor or a brightness sensor. For example, the detection sensor can be an infrared sensor for detecting infrared light.

[0056] FP22-2573 / LGD / CN

[0057] Conversely, the first optical electronic device 11 can be a detection sensor, and the second optical electronic device 12 can be a camera.

[0058] In the following text, for ease of description, it is assumed that the first optical electronic device 11 is a camera and the second optical electronic device 12 is a detection sensor. Here, the camera can be a camera lens or an image sensor.

[0059] When the first optical electronic device 11 is a camera, the camera is located behind (below) the display panel 110, but it can also be a front-facing camera used to capture images of the front side of the display panel 110. Therefore, the user can take pictures with the camera while looking at the viewing surface of the display panel 110.

[0060] The first optical region OA1 can have various shapes such as circular, elliptical, (regular) square, hexagonal, or octagonal. The second optical region OA2 can have various shapes such as circular, elliptical, (regular) square, hexagonal, or octagonal. The first optical region OA1 and the second optical region OA2 can have the same shape or different shapes.

[0061] refer to Figure 1C When the first optical region OA1 and the second optical region OA2 are in contact with each other, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes such as circles, ellipses, (regular) squares, hexagons or octagons.

[0062] In the following text, for ease of explanation, each of the first optical region OA1 and the second optical region OA2 is illustrated as a circular shape.

[0063] In a display device 100 according to an embodiment of the present disclosure, if optical regions OA1 and OA2 are surrounded by display region AA, the display device 100 according to an embodiment of the present disclosure may be referred to as a display using effective area aperture (HIAA) technology.

[0064] Therefore, in the display device 100 according to an embodiment of the present disclosure, it is not necessary to form a notch for camera exposure in the display panel 110. The display device 100 according to an embodiment of the present disclosure may have a camera hole for camera exposure.

[0065] Since there is no need to form a notch in the display panel 110, the size of the bezel area can be reduced, which reduces design constraints and increases design freedom.

[0066] Figure 2 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0067] refer to Figure 2 The display device 100 may include a display driving circuit and a display panel 110 as components for displaying images.

[0068] The display driving circuit is a circuit used to drive the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, etc.

[0069] Display panel 110 may include a display area (or effective area) AA in which an image is displayed and a non-display area (or ineffective area) NA in which no image is displayed. (Non-display area NDA FP22-2573 / LGD / CN)

[0070] It can be the area outside the display area AA, also known as the border area. All or part of the non-display area NDA can be an area visible from the front side of the display device 100, or an area that is curved and invisible from the front side of the display device 100.

[0071] The display panel 110 may include a substrate SUB and a plurality of sub-pixels disposed on the substrate SUB. Additionally, the display panel 110 may further include various types of signal lines to drive the plurality of sub-pixels SP.

[0072] The display device 100 according to embodiments of the present disclosure may be a liquid crystal display device or the like, or a self-emissive display device in which the display panel 110 emits its own light. In the case where the display device 100 according to embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0073] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting diode (OLED) display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as a light-emitting diode based on inorganic materials. As another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device implemented using quantum dots as light-emitting devices, wherein quantum dots are self-emissive semiconductor crystals.

[0074] The structure of each of the plurality of sub-pixels SP can vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device in which the sub-pixels SP emit their own light, then each sub-pixel SP includes a light-emitting device for emitting light, one or more transistors, and one or more capacitors.

[0075] For example, various types of signal lines may include multiple data lines DL for transmitting data signals (also known as data voltages or image signals) and multiple gate lines GL for transmitting gate signals (also known as scan signals).

[0076] The plurality of data lines DL and the plurality of gate lines GL may intersect each other. Each of the plurality of data lines DL may be configured to extend in a first direction. Each of the plurality of gate lines GL may be configured to extend in a second direction different from the first direction.

[0077] Here, the first direction can be the column direction, and the second direction can be the row direction. Alternatively, the first direction can be the row direction, and the second direction can be the column direction.

[0078] The data driving circuit 220 is used to drive the multiple data lines DL and can output data signals to the multiple data lines DL. The gate driving circuit 230 is used to drive the multiple gate lines GL and can output gate signals to the multiple gate lines GL.

[0079] FP22-2573 / LGD / CN

[0080] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing of the multiple data lines DL and the driving timing of the multiple gate lines GL.

[0081] The display controller 240 can supply the data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply the gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0082] The display controller 240 can receive input image data from the host system 250 and supply image data to the data drive circuit 220 based on the input image data.

[0083] The data driving circuit 220 can supply data signals to the multiple data lines DL according to the driving timing control of the display controller 240.

[0084] The data driving circuit 220 can receive digital image data from the display controller 240 and convert the received image data into analog data signals to output the converted signals to the multiple data lines DL.

[0085] The gate driving circuit 230 can supply gate signals to the plurality of gate lines GL according to the driving timing control of the display controller 240. The gate driving circuit 230 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage along with various gate driving control signals GCS to generate a gate signal, and can supply the generated gate signal to the plurality of gate lines GL.

[0086] For example, the data drive circuit 220 can be connected to the display panel 110 via tape-on-brush (TAB) method, or via chip-on-glass (COG) method or chip-on-panel (COP) method, or via chip-on-film (COF) method to connect to the display panel 110.

[0087] The gate driving circuit 230 can be connected to the display panel 110 via tape-and-reel bonding (TAB), or to the pads of the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP) methods, or to the display panel 110 via chip-on-film (COF) methods. Alternatively, the gate driving circuit 230 can be formed in the non-display area NDA of the display panel 110 as a gate-in-panel (GIP) type. The gate driving circuit 230 can be disposed on the substrate SUB or connected to the substrate SUB. That is, in the case of the GIP type, the gate driving circuit 230 can be disposed in the non-display area NDA of the substrate SUB. In the case of chip-on-glass (COG), chip-on-film (COF), etc., the gate driving circuit 230 can be connected to the substrate SUB.

[0088] FP22-2573 / LGD / CN

[0089] Meanwhile, at least one of the data driving circuit 220 and the gate driving circuit 230 can be disposed in the display area AA of the display panel 110. For example, at least one of the driving circuits of the data driving circuit 220 and the gate driving circuit 230 can be configured not to overlap with the sub-pixel SP, or can be configured to partially or completely overlap with the sub-pixel SP.

[0090] The data driving circuit 220 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 220 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 110.

[0091] The gate drive circuit 230 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gate drive circuit 230 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to at least two of the four sides of the display panel 110.

[0092] The display controller 240 can be implemented as a component separate from the data drive circuit 220, or it can be integrated with the data drive circuit 220 and implemented as an integrated circuit.

[0093] The display controller 240 may be a timing controller used in conventional display technologies, or a control device capable of further performing other control functions (including timing controllers), or a control device different from a timing controller, or circuitry within a control device. The display controller 240 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0094] The display controller 240 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 through the printed circuit board, flexible printed circuit, etc.

[0095] The display controller 240 can transmit signals to and receive signals from the data drive circuit 220 according to one or more predetermined interfaces. Here, for example, the interface may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, and a Serial Peripheral Interface (SPI).

[0096] To provide touch sensing and image display functions, the display device 100 according to embodiments of the present disclosure may include a touch sensor and a touch sensing circuit for detecting whether a touch object, such as a finger or a pen, has been touched by sensing the touch sensor or detecting the touch position.

[0097] The touch sensing circuit may include a touch driver circuit 260 that drives and senses touch sensors to generate and output touch sensing data, and a touch controller 270 that can use the touch sensing data to detect the occurrence of a touch or to detect the touch position.

[0098] The touch sensor may include multiple touch electrodes. The touch sensor may further include multiple touch lines for electrically connecting the multiple touch electrodes and the touch driving circuitry 260.

[0099] The touch sensor can exist outside the display panel 110 in the form of a touch panel, or it can exist inside the display panel 110. When the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor can be referred to as an external touch sensor. If the touch sensor is an external touch sensor, the touch panel and the display panel 110 can be manufactured separately and combined during the assembly process. An external touch panel can include a touch panel substrate and a plurality of touch electrodes located on the touch panel substrate.

[0100] If the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate SUB together with the signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0101] The touch driving circuit 260 can supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0102] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0103] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.).

[0104] According to the self-capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0105] When a touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0106] According to the mutual capacitance sensing method, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0107] The touch driver circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented as separate (discrete) devices or as a single device. Additionally, the touch driver circuit 260 and data driver circuit 220 can be implemented as separate devices or as a single device.

[0108] The display device 100 may further include a power supply circuit (power supply circuit) for supplying various types of power (electricity) to the display driving circuit and / or touch sensing circuit.

[0109] FP22-2573 / LGD / CN

[0110] The display device 100 according to the embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet computer, or a monitor or television of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0111] Figure 3 This is a cross-sectional view of the display area of ​​the display panel in a display device according to an embodiment of the present disclosure.

[0112] refer to Figure 3The substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be positioned between the first substrate SUB1 and the second substrate SUB2. The substrate SUB is configured to include the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2 to prevent or at least reduce moisture penetration. For example, the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI) substrates. The first substrate SUB1 may be referred to as the primary PI substrate, and the second substrate SUB2 may be referred to as the secondary PI substrate.

[0113] refer to Figure 3 Various patterns (ACT, SD1, and GATE), various insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, and PAS0), and various metal patterns (TM, GM, ML1, and ML2) can be set on the substrate SUB.

[0114] refer to Figure 3 Multiple buffer layers (MBUF) can be provided on the second substrate SUB2, and a first active buffer layer (ABUF1) can be provided on the multiple buffer layers (MBUF).

[0115] A first metal layer ML1 and a second metal layer ML2 can be disposed on the first active buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 can be light-shielding layers LS for shielding light.

[0116] A second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. The active layer ACT for driving the transistor DRT can be disposed on the second active buffer layer ABUF2.

[0117] The gate insulating layer GI can be disposed on the second active buffer layer ABUF2, while covering the active layer ACT.

[0118] The gate electrode (or gate electrode) GATE of the driving transistor DRT can be disposed on the gate insulating layer GI. In this case, the gate material layer GM can be disposed on the gate insulating layer GI together with the gate electrode GATE of the driving transistor DRT at a location different from the formation location of the driving transistor DRT.

[0119] The first interlayer insulating layer (ILD1) can be disposed on the gate insulating layer (GI), simultaneously covering the gate electrode (GATE) and the gate material layer (GM). A metal pattern (TM) can be disposed on the first interlayer insulating layer (ILD1). The metal pattern (TM) can be located at a different position than the formation location of the driving transistor (DRT). FP22-2573 / LGD / CN

[0120] The second interlayer insulating layer ILD2 can be disposed on the first interlayer insulating layer ILD1, while covering the metal pattern TM.

[0121] Two first source-drain electrode patterns SD1 can be disposed on the second interlayer insulating layer ILD2. One of the two first source-drain electrode patterns SD1 is the source node of the driving transistor DRT, and the other of the two first source-drain electrode patterns SD1 is the drain node of the driving transistor DRT.

[0122] The two first source-drain electrode patterns SD1 can be electrically connected to the first and second sides of the active layer ACT through the contact holes of the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0123] At the same time, refer to Figure 3 The second interlayer insulating layer ILD2 may include a second-first interlayer insulating layer ILD2-1 and a second-second interlayer insulating layer ILD2-2. The second-first interlayer insulating layer ILD2-1 may be positioned on the first interlayer insulating layer ILD1 and simultaneously cover the metallic pattern TM. The second-second interlayer insulating layer ILD2-2 may be disposed on the second-first interlayer insulating layer ILD2-1.

[0124] The portion of the active layer ACT that overlaps with the gate electrode GATE is the channel region. One of the two first source-drain electrode patterns SD1 can be connected to one side of the channel region in the active layer ACT, and the other of the two first source-drain electrode patterns SD1 can be connected to the other side of the channel region in the active layer ACT.

[0125] The passivation layer PAS0 can be disposed on the second interlayer insulating layer ILD2-2, simultaneously covering the two first source-drain electrode patterns SD1. The planarization layer PLN can be disposed on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0126] The first planarization layer PLN1 can be set on the passivation layer PAS0.

[0127] The second source-drain electrode pattern SD2 can be disposed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 through the contact holes of the first planarization layer PLN1 (e.g., Figure 3 The second node N2 of the driving transistor DRT in the sub-pixel SP.

[0128] The second planarization layer PLN2 can be disposed on the first planarization layer PLN1, and simultaneously cover the second source-drain electrode pattern SD2. The light-emitting device ED can be disposed on the second planarization layer PLN2.

[0129] In the stacked structure of the light-emitting device (ED), the anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source-drain electrode pattern SD2 through the contact holes of the second planarization layer PLN2.

[0130] FP22-2573 / LGD / CN

[0131] The dam can be set on the second planarization layer PLN2, while covering a portion of the anode electrode AE. A portion of the dam corresponding to the light-emitting region EA of the sub-pixel SP can be open.

[0132] A portion of the anode electrode AE ​​can be exposed through an opening (opening portion) in the dam bank. The luminescent layer EL can be positioned on the side surface of the dam bank and on the opening (opening portion) of the dam bank. All or part of the luminescent layer EL can be located between adjacent dams.

[0133] In the opening of the dam BANK, the light-emitting layer EL can contact the anode electrode AE. The cathode electrode CE can be disposed on the light-emitting layer EL.

[0134] A light-emitting device (ED) can be formed from an anode electrode (AE), a light-emitting layer (EL), and a cathode electrode (CE). The light-emitting layer (EL) may include an organic layer.

[0135] The encapsulation layer ENCAP can be set on the aforementioned light-emitting device ED.

[0136] The ENCAP encapsulation layer can have a single-layer or multi-layer structure. For example, Figure 3 As shown, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0137] For example, each of the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be an inorganic layer, and the second encapsulation layer PCL can be an organic layer. The second encapsulation layer PCL can be the thickest of the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2. Therefore, the second encapsulation layer PCL can be used as a planarization layer. The first encapsulation layer PAS1 can also be called the first inorganic encapsulation layer, the second encapsulation layer PCL can also be called the organic encapsulation layer, and the third encapsulation layer PAS2 can also be called the second inorganic encapsulation layer.

[0138] The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and can be positioned closest to the light-emitting device ED. The first encapsulation layer PAS1 can be formed from an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer PAS1 can be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Because the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere, it can prevent damage to the light-emitting layer EL, which includes organic materials susceptible to high-temperature atmospheres, during the deposition process.

[0139] The second encapsulation layer PCL can have a smaller area than the first encapsulation layer PAS1. In this case, the second encapsulation layer PCL can be formed to expose both ends of the first encapsulation layer PAS1. The second encapsulation layer PCL can serve as a buffer layer to alleviate interlayer stress caused by bending of the display device 100, and can also be used to enhance planarization performance. For example, the second encapsulation layer PCL can be made of acrylic FP22-2573 / LGD / CN.

[0140] It can be made of acid resin, epoxy resin, polyimide, polyethylene, silicon-oxygen carbon (SiOC), etc., and can also be formed from organic insulating materials. For example, the second encapsulation layer PCL can be formed by inkjet printing.

[0141] The third encapsulation layer PAS2 can be formed on a substrate SUB on which the second encapsulation layer PCL is formed, so as to cover the upper and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS1, respectively. The third encapsulation layer PAS2 can reduce or prevent external moisture or oxygen from penetrating into the first encapsulation layer PAS1 and the second encapsulation layer PCL. For example, the third encapsulation layer PAS2 can be formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0142] refer to Figure 3 If the touch sensor TS is the type embedded in the display panel 110, then the touch sensor TS can be disposed on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail below.

[0143] The touch buffer layer T-BUF can be placed on the encapsulation layer ENCAP. The touch sensor TS can be placed on the touch buffer layer T-BUF.

[0144] The touch sensor TS may include a touch sensor metal TSM and a bridging metal BRG positioned on different layers.

[0145] The interlayer insulating layer (T-ILD) can be placed between the touch sensor metal (TSM) and the bridging metal (BRG).

[0146] For example, the touch sensor metal TS may include a first touch sensor and a second touch sensor. The first and second touch sensors may be formed by the touch sensor metal TSM. The first and second touch sensors may be electrically connected by a bridging metal BRG located on a different layer than the touch sensor metal TSM.

[0147] When the touch sensor TS is formed on the display panel 110, chemical solutions (developers or etchants, etc.) or moisture used in its manufacturing process may be generated from the outside. The touch sensor TS is disposed on the touch buffer layer T-BUF so as to prevent or at least reduce the penetration of chemical solutions or moisture into the light-emitting layer EL, which includes organic materials, during the manufacturing process of the touch sensor TS. Therefore, the touch buffer layer T-BUF can prevent damage to the light-emitting layer EL, which is susceptible to chemical solutions or moisture.

[0148] The touch buffer layer T-BUF can be formed at a low temperature (e.g., 100 degrees Celsius) to prevent or at least reduce damage to the light-emitting layer EL containing organic materials susceptible to high temperatures, and can be formed from an organic insulating material with a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF can be formed from acrylic-based, epoxy-based, or silicon-based materials. When the display device 100 is bent or folded, the encapsulation layer ENCAP may be damaged, and the touch sensor metal positioned on the touch buffer layer FP22-2573 / LGD / CNT-BUF may break. Even when the display device 100 is bent, the touch buffer layer T-BUF, made of an organic insulating material and having planarization properties, can prevent damage to the encapsulation layer ENCAP and / or breakage of the touch sensor metal TSM and bridging metal BRG constituting the touch sensor TS.

[0149] The passivation layer PAC can be disposed on the interlayer insulating layer T-ILD, while simultaneously covering the touch sensor TS. The passivation layer PAC can be an organic insulating layer.

[0150] Figure 4 This is an enlarged plan view illustrating the optical region structure of a display panel in a display device according to an embodiment of the present disclosure.

[0151] refer to Figure 4 The optical region OA is set within the display region AA. Pixels (not shown) can be set around the optical region OA (i.e., surrounding the optical region OA). The optical region OA can be either the first optical region OA1 or the second optical region OA2 described above.

[0152] refer to Figure 4The optical region OA may include a via TH and a surrounding area SA. A rough pattern RP may be located in the surrounding area SA. Subpixels used to display images may not be located in the optical region OA. In one embodiment, the via TH is a light-transmitting area that transmits external light to a camera or sensor that overlaps with the optical region OA.

[0153] Through-holes (THs) can be formed by removing substrate along trimming lines. The shape of a through-hole (TH) can be as follows: Figure 4 The shape shown is a circle, but it can also have various shapes such as ellipse, (square), hexagon or octagon.

[0154] The rough pattern RP may include an inner (or inner side) rough pattern IRP (e.g., a first rough pattern) and an outer (or outer side) rough pattern ORP (e.g., a second rough pattern). In one embodiment, the inner rough pattern IRP is a first protrusion, and the outer rough pattern ORP is a second protrusion.

[0155] refer to Figure 4 In the surrounding area SA, an inner dam DMI can be set between the inner rough pattern IRP and the outer rough pattern ORP to separate the two patterns (i.e., the inner rough pattern IRP and the outer rough pattern ORP).

[0156] An outer dam (not shown) can be further positioned within the display area AA outside the inner rough pattern IRP. The outer dam can be configured to prevent the second encapsulation layer PCL from overflowing the display area AA.

[0157] The inner dam DMI has a shape corresponding to the shape of the through-hole TH and has a closed curve shape surrounding the through-hole TH. The inner dam DMI and the through-hole TH can have different closed curve shapes, or they can have closed curves with the same shape but different sizes. For example, the inner dam DMI and the through-hole TH can have concentric circle shapes and can be arranged to be spaced apart from each other at predetermined intervals.

[0158] FP22-2573 / LGD / CN

[0159] The rough pattern RP has a closed curve shape that surrounds and corresponds to the shape of the through hole TH. The rough pattern RP can have a different closed curve shape than the through hole TH, or it can have a closed curve shape with the same shape but a different size. For example, as... Figure 4 As shown, the rough pattern RP and the through hole TH can have the same shape and can be spaced apart from each other by a predetermined interval. In one embodiment, the outer rough pattern ORP surrounds the through hole T, and the inner rough pattern IRP surrounds the outer rough pattern ORP and the through hole T.

[0160] Meanwhile, the sub-pixels disposed in the display area AA may include light-emitting devices. When the light-emitting device is an organic light-emitting device, a light-emitting layer (not shown) may be positioned in the display area AA, and the light-emitting layer may be an organic light-emitting layer comprising organic materials.

[0161] The organic light-emitting layer can be extended to at least a portion of the optical region OA.

[0162] Meanwhile, when moisture seeps into the organic light-emitting layer, defects such as sub-pixel darkening may occur. Moisture infiltration is possible in the area where the via (TH) is located.

[0163] The aforementioned inorganic encapsulation layer (e.g., PAS1) can be positioned on a rough pattern RP. Moisture may penetrate the inorganic encapsulation layer, and the rough pattern RP can have the effect of extending the path of moisture through which it penetrates the inorganic encapsulation layer. Therefore, the rough pattern RP can prevent or at least reduce the amount of moisture introduced from the via TH from reaching the light-emitting layer positioned in the display area AA.

[0164] Figure 5 According to one embodiment, along Figure 4 A cross-sectional view of line II′ (cut) in the optical region.

[0165] refer to Figure 5 The optical area OA includes the through-hole TH and the peripheral area SA, and the display area AA can be located outside the peripheral area SA.

[0166] An optical electronic device positioned below the display panel and positioned such that at least a portion of it overlaps with the through-hole TH can be positioned within the through-hole TH. Such an optical electronic device may be the first optical electronic device 11 described above.

[0167] refer to Figure 5 The display device according to embodiments of the present disclosure may include a “dam structure” such as an outer dam DMO located in the display area AA and an inner dam DMI located in the peripheral area SA. The dam structure may have a three-layer structure formed perpendicular to the substrate SUB. For example, the dam structure may include a first layer formed by a planarization layer PLN, a second layer formed by a dam BANK, and a third layer formed by spacers (not shown).

[0168] refer to Figure 5 The first planarization layer PLN1 and the second planarization layer PLN2 are simply illustrated as planarization layer PLN. In this dam structure, at least a portion of the light-emitting layer EL can be disposed on the spacer.

[0169] FP22-2573 / LGD / CN

[0170] Some components constituting the light-emitting device can be stacked on the inner dam DMI. For example, the light-emitting layer EL and the common electrode (not shown) can be stacked in a shape that climbs over the inner dam DMI. That is, the light-emitting layer EL is located on the inner dam DMI.

[0171] The rough pattern RP is located on the inner (e.g., first side) and outer (e.g., second side) sides of the inner dam DMI. The rough pattern RP may include hills (e.g., protrusions) and valleys, wherein the hills include an insulating layer (e.g., ILD1, ILD2-1, ILD2-2, etc.), and at least a portion of the insulating layer is removed from the valleys.

[0172] The light-emitting layer EL can be positioned within at least a portion of the rough pattern RP. The light-emitting layer EL can be an organic light-emitting layer comprising organic materials. The light-emitting layer EL can extend from the display area AA to at least a portion of the peripheral area SA.

[0173] refer to Figure 5 The light-emitting layer EL can be discontinuously positioned within the inner rough pattern IRP and the outer rough pattern ORP. That is, the portion of the light-emitting layer EL located in the peripheral region SA extends discontinuously on the inner rough pattern IRP and the outer rough pattern ORP, creating an interruption within the light-emitting layer EL. Therefore, even if moisture introduced from the through-hole TH reaches the light-emitting layer EL positioned in the peripheral region SA, the moisture will not penetrate into the light-emitting layer EL positioned in the display region AA. In other words, because the light-emitting layer EL is discontinuously positioned within the rough pattern RP, in addition to extending the moisture penetration path, it also provides the effect of preventing or at least reducing the diffusion of moisture flowing into the light-emitting layer EL into the display region AA.

[0174] At the same time, refer to Figure 5 The height of the mountain can differ between the inner roughness pattern (IRP) and the outer roughness pattern (ORP). The height of the mountain in the inner roughness pattern (IRP) can be greater than the height of the mountain in the outer roughness pattern (ORP).

[0175] The difference in the height of the mountain in the inner rough pattern (IRP) and the outer rough pattern (ORP) may be attributed to the fact that the interlayer insulation layers (e.g., ILD1, ILD2-1, ILD2-2) contained in the mountain are different.

[0176] For example, refer to Figure 5 The mountain portion of an inner rough pattern IRP may include a second-2 interlayer insulation layer ILD2-2, but may exclude the second-1 interlayer insulation layer ILD2-1 and the first interlayer insulation layer ILD1. The mountain portion of an outer rough pattern ORP may include the second-1 interlayer insulation layer ILD2-1 and the first interlayer insulation layer ILD1, but may exclude the second-2 interlayer insulation layer ILD2-2.

[0177] At the same time, refer to Figure 5 The bottom surface of the valley in the outer rough pattern ORP can be located at a lower position than the bottom surface of the valley in the inner rough pattern IRP.

[0178] FP22-2573 / LGD / CN

[0179] For example, valleys in an outer roughening pattern ORP can be formed by removing at least a portion of the first interlayer insulation layer ILD1 and the second interlayer insulation layer ILD2 (e.g., the second-1 interlayer insulation layer ILD2-1).

[0180] refer to Figure 5 During the process of removing the first interlayer insulating layer ILD1 from the outer rough pattern ORP to form the valley of the rough pattern RP, there is a risk that the gate insulating layer GI may be damaged or that the insulating layer located below the gate insulating layer GI (e.g., ABUF, MBUF, etc.) may be damaged.

[0181] Therefore, the metal pattern MP can be located in the valleys described below, where the valleys are located within the outer roughness pattern ORP. Each metal pattern can be located in a valley between two hills in the outer roughness pattern ORP.

[0182] refer to Figure 5 For example, a metallic pattern MP can be set in the peripheral region SA to have the same shape as the valley located in the outer rough pattern ORP. The metallic pattern MP located to correspond to the valley of the rough pattern RP can be used as an "etching stop".

[0183] Alternatively, the metallic pattern MP can be positioned to overlap with the mountain portion located within the outer roughness pattern ORP. That is, the metallic pattern MP can be positioned extensively below the outer roughness pattern ORP. In this case, the metallic pattern MP can also function to prevent microcracks generated in the via TH from propagating to the display area AA. In this case, the metallic pattern MP can act not only as an etching barrier but also as a crack barrier.

[0184] The metal pattern MP can be positioned on the gate insulating layer GI. The metal pattern MP can be formed by the above... Figure 3 The gate electrode of the driving transistor DRT is formed of the same material as the gate electrode.

[0185] The metal pattern MP can be made of a different material than the insulating layers above and below the metal pattern MP (e.g., gate insulating layer GI, first interlayer insulating layer ILD1). Therefore, even if the insulating layer covering the metal pattern MP (e.g., first interlayer insulating layer ILD1) is removed during processes such as etching, the insulating layer below the metal pattern MP (e.g., gate insulating layer GI) can be protected.

[0186] Simultaneously, the alignment mark MNT can be located in the surrounding area SA. The alignment mark MNT can also be referred to as an "alignment key". The alignment mark MNT can be set on the substrate SUB to form a through-hole TH by etching a predetermined area in the substrate SUB.

[0187] The alignment mark MNT can be set to a shape that corresponds to the shape of the via TH in the surrounding area SA, or it can be set to a shape that is different from the shape of the via TH. For example, the alignment mark MNT can be located only in some areas of the via TH, such as the top, bottom, left, and right sides.

[0188] Simultaneously, the alignment mark MNT can be located on the same layer as the metal pattern MP. For example, the alignment mark MNT can be formed from the same material as the gate electrode GATE. The alignment mark MNT can be used in FP22-2573 / LGD / CN

[0189] The alignment mark MNT is located on the gate insulating layer GI. It can be located on the gate insulating layer GI and covered by the first interlayer insulating layer ILD1.

[0190] For example, the alignment mark MNT can be located in the region that overlaps with the inner dam DMI. For example, the alignment mark MNT can be located between the inner roughness pattern IRP and the outer roughness pattern ORP.

[0191] Figure 6 This is an exemplary cross-sectional view of the area where the through-hole of the display panel is located in a display device according to an embodiment of the present disclosure.

[0192] refer to Figure 6 It can form including, for example Figure 3-5 The display panel 110 shown includes a substrate SUB, an organic light-emitting device (OLED), an encapsulation layer ENCAP, and a touch sensor TS. A backplate BP can be disposed on the rear surface of the display panel 110. When the substrate of the display panel 110 is made of a plastic material such as polyimide, the manufacturing process of the display device 100 is performed with a support substrate made of glass disposed on the rear surface of the display panel 110, and the support substrate can be separated and released after the manufacturing process is completed. Since components for supporting the display panel 110 are needed even after the support substrate is released, the backplate BP for supporting the display panel 110 can be disposed on the rear surface of the display panel 110.

[0193] The backsheet (BP) can prevent or at least reduce the adhesion of foreign matter (external substances) to the underside of the substrate (SUB) and can be used to cushion impacts from the outside. The backsheet (BP) can be formed from a plastic film made of a polymer such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or a combination of these polymers.

[0194] A metal plate MEP (e.g., a metal layer) can be disposed on the rear surface of the backplate BP. The metal plate MEP can be made of a metal material such as stainless steel (SUS) and can serve to radiate heat from the display device, ground, and protect the rear surface. In other words, the metal plate MEP can be a composite heat sink.

[0195] A polarizing plate (POL) (e.g., a polarizer) can suppress the reflection of external light on the display panel 110. In one embodiment, the polarizer is located in the non-optical region NA, not in the optical region OA. If the display device 100 is used outdoors, external natural light can be introduced and reflected by a reflective layer included in the anode of the electroluminescent element, or by electrodes made of metal disposed below the electroluminescent element. The image on the display device 100 may not be easily identifiable by reflected light. The polarizing plate (POL) can polarize light introduced from the outside in a specific direction and prevent reflected light from being emitted back to the outside of the display device 100.

[0196] A polarizing plate (POL) can be a polarizing plate composed of a polarizer and a protective film protecting the polarizer, or it can be formed by coating a polarizing material to achieve flexibility. FP22-2573 / LGD / CN is used to protect the display panel 110.

[0197] The outer protective glass (glass cover) CG can be attached to and disposed on the polarizing plate POL using an adhesive layer OCA inserted between the protective glass CG and the polarizing plate POL. That is, the protective glass CG is provided to cover the front surface of the display panel 110 and to protect the display panel 110.

[0198] A light-shielding pattern BM can be formed on the rear edge of the protective glass CG. Alternatively, the light-shielding pattern BM can be formed around the through-hole TH (forming around the through-hole TH). The light-shielding pattern BM can extend and be formed to overlap with a portion of the underlying adhesive layer OCA, polarizing plate POL, and display panel 110, or it can be configured as a separate layer. The light-shielding pattern BM can be coated with black ink.

[0199] refer to Figure 6Triboelectric charges generated on the surface of the protective glass CG can propagate through the via TH and pass through the encapsulation layer ENCAP surrounding the via TH, thereby entering the pixels within the display panel 110. In this case, the triboelectric charges may be transferred to the pixels adjacent to the via TH via the cathode electrode, which is a conductive common layer. That is, the triboelectric charges entering the display panel 110 may be supplied to the pixels to cause the organic light-emitting diode (OLED) to emit light. Therefore, it is possible for pixels near the via to emit light unnecessarily due to triboelectric charges.

[0200] As mentioned above, reference will be made Figure 7 Figure 8 illustrates the pixel circuit configuration and drive for preventing bright spots around vias caused by triboelectric charge.

[0201] Figure 7 This is an equivalent circuit diagram of the pixel circuit in a display device according to an embodiment of the present disclosure.

[0202] refer to Figure 7 Each of the plurality of pixels P may include a pixel circuit and a light-emitting device OLED connected to the pixel circuit, wherein the pixel circuit includes a driving transistor DT.

[0203] The pixel circuit can drive the OLED by controlling the driving current Id flowing through it. The pixel circuit may include a driving transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst. Each of transistors DT and T1 to T6 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode (or source electrode), and the other of the first and second electrodes may be a drain electrode (or drain electrode).

[0204] Each of transistors DT, T1 through T7 can be a PMOS transistor or an NMOS transistor. An example is given below in which the first transistor T1 is an NMOS transistor, while the other transistors DT, T2 through T7 are PMOS transistors. Thus, the first transistor T1 is turned on by applying a logic high voltage to its gate node, while the other transistors DT, T2 through T7 are turned on by applying a logic low voltage to their gate nodes.

[0205] According to the example, the first transistor T1 can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, and the third and fourth transistors T3 and T4 can be used as light-emitting control transistors. FP22-2573 / LGD / CN

[0206] The fifth and sixth transistors, T5 and T6, can be used as bias transistors, and the seventh transistor, T7, can be used as a drive power transistor.

[0207] An OLED (Optical Display Panel) device may include pixel electrodes (or anode electrodes) and cathode electrodes. The pixel electrodes of the OLED device may be connected to a fifth node N5, and the cathode electrodes of the OLED device may be connected to a second driving power (source) VSSEL.

[0208] The driving transistor DT may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode connected to a second node N2. The driving transistor DT may provide a driving current Id to the light-emitting device OLED based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst, which will be described later).

[0209] The first transistor T1 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode for receiving a first scan signal SC1(n). The first transistor T1 can be turned on in response to the first scan signal SC1(n) and can transmit the data signal Vdata applied to the third node N3 to the second node N2. The first transistor T1 may be connected as a diode between the second node N2 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0210] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data signal Vdata), a second electrode connected to the first node N1, and a gate electrode for receiving the second scan signal SC2(n). The second transistor T2 can be turned on in response to the second scan signal SC2(n) and can transmit the data signal Vdata to the first node N1. The second transistor T2 may be a data supply transistor.

[0211] The third transistor T3 and the fourth transistor T4 (or the first and second emission control transistors) can be connected between the first driving power (power supply) VDDEL and the light-emitting device OLED, and can form a current path through which the driving current Id generated by the driving transistor DT flows.

[0212] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the first drive power (electricity) ELVDD, a second electrode connected to the first node N1, and a gate electrode for receiving the transmit signal EM(n).

[0213] Similarly, the fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the pixel electrode of the light-emitting device OLED), and a gate electrode for receiving the emission signal EM(n).

[0214] FP22-2573 / LGD / CN

[0215] The third transistor T3 and the fourth transistor T4 can be turned on in response to the emission signal EM(n), and in this case, the driving current Id is provided to the light-emitting device OLED, and the light-emitting device OLED can emit light with a brightness corresponding to the driving current Id.

[0216] The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode receiving a first bias voltage Vini, and a gate electrode for receiving a third scan signal SC3(n). The fifth transistor T5 may be turned on in response to the third scan signal SC3(n) and may selectively transmit an on-bias stress voltage Vobs (hereinafter referred to as "stress voltage") and an initialization voltage Vini to the third node N3. The fifth transistor T5 applies the voltage output from the gate drive circuit 230 to the drive transistor DT.

[0217] Because the fifth transistor T5 controls the high drain-source voltage Vds formed between the first and second electrodes of the driving transistor DT, the fifth transistor T5 may be sensitive to the shift in its threshold voltage Vth. Furthermore, since the fifth transistor T5 is a PMOS transistor, its threshold voltage Vth may be shifted positively (negatively) due to the triboelectric charge on the shielding glass CG. Therefore, the fifth transistor T5 can be configured as a dual-gate structure to reduce transistor degradation. However, this disclosure is not limited to this, and the fifth transistor T5 can be configured as a single transistor.

[0218] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode connected to the second bias voltage VAR, and a gate electrode receiving the third scan signal SC3(n). The sixth transistor T6 may be turned on in response to the third scan signal SC3(n) before (or after) the OLED emits light, and the pixel electrode (or anode electrode) of the OLED may be initialized using the second bias voltage VAR. The OLED may have a parasitic capacitor formed between the pixel electrode and the cathode electrode. Furthermore, the parasitic capacitor may be charged while the OLED emits light, allowing the pixel electrode of the OLED to have a specific voltage. Therefore, the amount of charge accumulated in the OLED can be initialized by applying the second bias voltage VAR to the pixel electrode of the OLED via the sixth transistor T6.

[0219] The seventh transistor T7 may include a first electrode connected to the sixth node N6, a second electrode connected to the second power supply voltage VSSEL, and a gate electrode for receiving the transmit signal EM(n). The seventh transistor T7 may be turned on in response to the transmit signal EM(n) and may transmit the second drive power VSSEL to the sixth node N6. The seventh transistor T7 may be a drive power transistor.

[0220] To improve the positive offset of the threshold voltage Vth of the fifth transistor T5, the seventh transistor T7 can be turned on during the emitter period Te when the emitter signal EM(n) is at a low level, and the FP22-2573 / LGD / CN can be turned on.

[0221] Two driving powers, VSSEL, are continuously applied to the sixth node N6 to eliminate the excitation current. That is, the seventh transistor T7, which is turned on during the emitter period Te, provides a path to ground (e.g., VSSEL) to discharge the charge of the excitation current.

[0222] A capacitor Cst can be connected or formed between the second node N2 and the fourth node N4. The capacitor Cst can store or maintain the provided data signal Vdata.

[0223] Figure 8A and Figure 8B This is based on an embodiment for explanation. Figure 7 The graphics driven by the pixel circuitry in a display device.

[0224] refer to Figure 8A and Figure 8B Each of the plurality of pixels P can initialize the voltage charged or remaining in the pixel circuit. Specifically, the influence of the data voltage Vdata and driving voltage VDD stored in the previous frame can be removed. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata.

[0225] The operation of a pixel circuit may include at least one initialization period, a sampling period, and an emission period, but this is just an example and is not necessarily limited to this order.

[0226] The display device according to the embodiments of this disclosure can be respectively composed of Figure 8A The refresh frames shown are Figure 8B The reset frame is shown. In the refresh frame, the data voltage Vdata is programmed in each pixel P, and the OLED emits light. Alternatively, the reset frame can be a vertical blank frame, and the anode electrode of the OLED can be reset during the reset frame.

[0227] In a display device according to an embodiment of the present disclosure, a refresh frame can be divided into a conduction bias stress period Tobs (hereinafter referred to as a "stress period"), an initial period Ti, a sampling period Ts, an emission period Te, and an anode reset period (shown as a second conduction bias stress period Tobs, hereinafter referred to as a "reset period"). The stress period Tobs is the period during which bias stress is applied to a first node N1, which serves as the source electrode of a driving transistor DT. The initial period Ti is the period used to initialize the voltage of a third node N3, which serves as the drain electrode of the driving transistor DT. The sampling period Ts is the period used to sample the threshold voltage Vth of the driving transistor DT and program the data voltage Vdata. The emission period Te is the period during which the organic light-emitting diode (OLED) emits light according to the driving current through the source-gate voltage of the programmed driving transistor DT. The reset period is the period during which the voltage level of the anode electrode of the organic light-emitting diode OLED is fixed at a reset voltage VAR for the remaining periods other than the emission period Te.

[0228] Specifically, refer to Figure 8A During the first stress period (Tobs), the third scan signal SC3(n) is at a low level as the on-state. Therefore, the sixth transistor T6 is turned on to apply the reset voltage VAR to the fifth node N5. That is, the anode electrode of the OLED is reset. FP22-2573 / LGD / CN

[0229] To reset the voltage VAR, the fifth transistor T5 is also turned on to apply the stress voltage Vobs from the digital initialization voltage line DVini to the third node N3. The stress voltage Vobs can be selected within a voltage range sufficiently higher than the operating voltage of the organic light-emitting diode (OLED) and can be set to be equal to or lower than the first drive power VDDEL. That is, a bias stress can be applied to the third node N3, which serves as the drain electrode of the drive transistor DT, during the stress period Tobs to reduce the gate-source voltage Vgs of the drive transistor DT. Therefore, the hysteresis effect of the drive transistor DT can be reduced by allowing the source-drain current Ids of the drive transistor DT to flow during the stress period Tobs.

[0230] In this scenario, since the fifth transistor T5 operates as a switching transistor to supply the stress voltage Vobs to the third node N3, there may be undesirable current flow towards the organic light-emitting diode (OLED) due to triboelectric charge caused by the deterioration of the transistor's turn-off characteristics. Therefore, to prevent this problem, it is important to prevent the threshold voltage Vth from shifting.

[0231] Additionally, refer to Figure 8ADuring the initial period Ti, the first scan signal SC1(n) is at a high level as the on-state, while the third scan signal SC3(n) is at a low level as the on-state. Therefore, the first transistor T1 and the fifth transistor T5 are turned on to apply the initialization voltage Vini from the digital initialization voltage line DVini to the second node N2. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting diode (OLED) and can be set to be equal to or lower than the second driving power VSSEL. Additionally, during the initial period Ti, the sixth transistor T6 is turned on again, and the bias voltage VAR is applied to the fifth node N5.

[0232] Additionally, refer to Figure 8A During the sampling period Ts, the first scan signal SC1(n) is at a high level as the on-state, while the second scan signal SC2(n) is at a low level as the on-state. Therefore, during the sampling period Ts, the second transistor T2 is turned on, and the data voltage Vdata is applied to the first node N1. Additionally, since the first transistor T1 is also turned on, the driving transistor DT is connected by a diode, and the gate and drain of the driving transistor DT are short-circuited, thus the driving transistor DT operates like a diode.

[0233] During the sampling period Ts, current Ids flows between the source and drain electrodes of the driving transistor DT. Since the gate and drain electrodes of the driving transistor DT are in a diode-connected state, the voltage of the second node N2 can vary (e.g., it can increase) until the gate-source voltage Vgs of the driving transistor DT becomes the threshold voltage Vth of the driving transistor DT through the current flowing from the source electrode to the drain electrode.

[0234] FP22-2573 / LGD / CN

[0235] Additionally, refer to Figure 8A During the second stress period Tobs, the third scan signal SC3(n) is at a low level, which is the on-state. Therefore, the sixth transistor T6 is turned on to apply the reset voltage VAR to the fifth node N5. That is, the anode electrode of the OLED is reset to the reset voltage VAR. Additionally, the fifth transistor T5 is turned on to apply the stress voltage Vobs to the third node N3. In other words, the hysteresis effect of the driving transistor DT can be reduced by applying bias stress to the third node N3, which serves as the drain electrode of the driving transistor DT, during the second stress period Tobs.

[0236] Additionally, refer to Figure 8ADuring the transmission period Te, the transmitted signal EM(n) is at a low level, which is the on-state. Therefore, the third transistor T3 is turned on to apply the first drive power VDDEL to the first node N1. Furthermore, since the second node N2 is coupled to the first drive power VDDEL through the storage capacitor Cst, the first drive power VDDEL is also reflected in the second node N2. Additionally, the fourth transistor T4 is also turned on to form a current path between the third node N3 and the fourth node N4. As a result, the drive current Ioled through the source and drain electrodes of the driving transistor DT is applied to the organic light-emitting diode (OLED).

[0237] Additionally, refer to Figure 8A When the transmit signal EM(n) is at a low level, the seventh transistor T7 is turned on to apply the second drive power VSSEL to the sixth node N6.

[0238] As triboelectric charges formed on the surface of the protective glass CG pass through the via TH into the pixel, the threshold voltage Vth of the fifth transistor T5 may be positively offset. As a result, the potential difference between the drain and source voltages Vds of the fifth transistor T5 may increase, and therefore the transistor's turn-off characteristics may deteriorate. Consequently, during the emission period Te, the current of the OLED, which emits light according to the driving current, unnecessarily increases, causing the pixels around the via TH to emit bright light.

[0239] Therefore, the seventh transistor T7 can be connected between the sixth node N6, which is the source electrode of the fifth transistor T5, and the cathode of the organic light-emitting diode OLED, which is supplied with the second driving power VSSEL, and can be turned on according to the emission signal EM(n), thereby eliminating the excitation current.

[0240] In other words, in the display device according to an embodiment of the present disclosure, a grounding path (e.g., a grounding path) is formed in the fifth transistor T5 by the seventh transistor T7, thereby eliminating (e.g., reducing or dissipating) the excitation current generated as triboelectric charge on the surface of the shield glass CG penetrates the pixels within the display panel 110 and causes a positive shift in the threshold voltage Vth of the fifth transistor T5. Therefore, the brightness phenomenon caused by the unintentional increase in current in the pixels adjacent to the via TH can be improved, and thus image quality can be improved.

[0241] FP22-2573 / LGD / CN

[0242] Additionally, refer to Figure 8BDuring the reset frame, the first scan signal SC1(n) remains at a low level, which is the off level, while the second scan signal SC2(n) remains at a high level, which is also the off level. Therefore, during the reset frame, the data voltage Vdata is not programmed into each pixel P.

[0243] However, the third scan signal SC3(n) can oscillate periodically. That is, due to the periodic oscillation of the third scan signal SC3(n), the reset frame can include multiple stress periods Tobs.

[0244] In other words, during the reset frame, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage VAR, and bias stress can be applied to the third node N3, which serves as the drain electrode of the driving transistor DT.

[0245] As a result, in the display device according to embodiments of the present disclosure, the anode electrode of the organic light-emitting diode (OLED) can be periodically reset during refresh frames and reset frames. Therefore, since a continuous increase in the voltage of the anode electrode of the OLED due to leakage current can be prevented, a constant voltage level (level) can be maintained at the anode electrode. Thus, brightness variations in the display device can be minimized, and image quality can be improved.

[0246] Figure 9A and Figure 9B These are graphics illustrating comparative examples and examples in a display device according to embodiments of the present disclosure.

[0247] refer to Figure 9A and Figure 9B , Figure 9A The comparative example is a photograph of the operation of a conventional pixel circuit, while Figure 9B The embodiment is a photograph of the operation of the pixel circuit, which further includes a seventh transistor T7.

[0248] like Figure 9A As shown, in the comparative example, there is a phenomenon where the pixel adjacent to the via TH emits bright light. However, as... Figure 9B As shown, in an example of an embodiment according to this disclosure, since the excitation current is eliminated by applying the second drive power VSSEL to the sixth node N6 when the transmit signal EM(n) is at the on level, the bright phenomenon as in the comparative example can be prevented and the image quality can be improved.

[0249] The display panel and display device according to embodiments of this specification can be described as follows.

[0250] In one embodiment, a display panel includes: pixels located in a display area of ​​the display panel, the pixels including: a light-emitting device configured to emit light in response to a drive current; a drive transistor configured to supply the drive current; and a plurality of switching transistors configured to control the supply of the drive current to the light-emitting device via the drive transistor, wherein at least one of the plurality of switching transistors is configured to provide a path for grounding within the pixel, wherein an excitation current is discharged through the path for grounding.

[0251] In one embodiment, the light-emitting device includes a cathode electrode, and the display panel further includes an initialization voltage line connected to the pixel, wherein the plurality of switching transistors include a drive power transistor configured to control an electrical connection between the initialization voltage line and the cathode electrode of the light-emitting device, and the grounding path includes the drive power transistor.

[0252] In one embodiment, the plurality of switching transistors further includes a bias transistor configured to control the connection between the source or drain electrode of the driving transistor and the initialization voltage line, wherein a ground path is configured between the source or drain electrode of the driving transistor and the cathode electrode, such that the ground path includes the bias transistor and the driving power transistor.

[0253] In one embodiment, the excitation current is generated based on a change in the threshold voltage of the bias transistor.

[0254] In one embodiment, at least one of the plurality of switching transistors configured to provide the path for grounding includes: a first transistor connected to the drain electrode or source electrode of the driving transistor; and a second transistor connected to the first transistor, the second transistor being configured to provide the path for grounding to the first transistor when the light-emitting device emits light.

[0255] In one embodiment, the plurality of switching transistors further includes a third transistor connected between the driving transistor and the light-emitting device, wherein the gate electrode of the third transistor is connected to the gate electrode of the second transistor.

[0256] In one embodiment, the second transistor is connected to the cathode electrode of the light-emitting device.

[0257] In one embodiment, a display panel includes: a light-emitting device including a first electrode, a light-emitting layer, and a second electrode; a driving transistor configured to drive the light-emitting device; a bias transistor configured to control the connection between the drain electrode or source electrode of the driving transistor and an initialization voltage line; and a driving power transistor configured to control the electrical connection between the initialization voltage line and the second electrode of the light-emitting device.

[0258] In one embodiment, the display panel further includes an emission control transistor configured to control light emission (light emission) of the light-emitting device, wherein the gate electrode of the driving power transistor is electrically connected to the gate electrode of the emission control transistor.

[0259] In one embodiment, the emission control transistor is located between the driving transistor and the light-emitting device.

[0260] In one embodiment, the bias transistor is connected to the drain or source electrode of the driving transistor, and the driving transistor is connected to the drain or source electrode of the bias transistor and the second electrode of the light-emitting device.

[0261] In one embodiment, a display device includes: a display panel including an optical region and a non-optical region, the optical region including a transmissive region and the non-optical region including a light-emitting device located in a light-emitting region of a pixel; and a protective glass located on the display panel, wherein the pixel is configured to provide a path for grounding within the pixel, wherein an excitation current is discharged through the path for grounding, the path for grounding not including the light-emitting device.

[0262] In one embodiment, the light-emitting device is configured to emit light in response to a driving current, the light-emitting device including a first electrode, a light-emitting layer, and a second electrode, wherein the pixel further includes: a driving transistor configured to supply the driving current; and a plurality of switching transistors configured to control the supply of the driving current to the light-emitting device via the driving transistor, the plurality of switching transistors including a driving power transistor configured to provide the grounding path, wherein an excitation current generated in the pixel is discharged through the grounding path.

[0263] In one embodiment, the driving power transistor is connected between an initialization voltage line and the second electrode, and the initialization voltage line is connected to the pixel.

[0264] In one embodiment, the plurality of switching transistors further includes: a bias transistor connected to the drain or source electrode of the driving transistor and the initialization voltage line, the bias transistor being configured to supply a voltage provided by the initialization voltage line to the drain or source electrode of the driving transistor, wherein the driving power transistor is connected between the second electrode of the light-emitting device and the drain or source electrode of the bias transistor.

[0265] In one embodiment, the display device further includes a polarizer located in the non-optical region but not in the optical region.

[0266] In one embodiment, the optical region contains no transistors.

[0267] In one embodiment, the display device further includes: a substrate comprising a first side and a second side opposite to the first side; and a metal layer located on the second side, the metal layer being configured to radiate at least heat from the display device.

[0268] FP22-2573 / LGD / CN

[0269] In one embodiment, the display device further includes an optical element that overlaps with the optical region.

[0270] In one embodiment, the excitation current is generated by allowing charged charges generated on the shield glass to pass through the transmission region into the pixel.

[0271] The features, structures, effects, etc., described in the examples above in this disclosure are included in at least one embodiment of this disclosure, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc., exemplified in at least one example of this disclosure can be combined or modified by those skilled in the art with respect to other examples. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of this disclosure.

[0272] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the invention. Therefore, the embodiments disclosed herein are not intended to limit the spirit of the invention, but rather to exemplify the invention, and the scope of the spirit of the invention is not limited by these embodiments. Thus, it should be understood that the above embodiments are illustrative and not restrictive in all respects. The scope of protection of the invention should be interpreted by the following claims, and all technical concepts within their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. A display panel comprising: Pixels located in the display area of ​​the display panel, and The initialization voltage line connected to the pixel, The pixels include: A light-emitting device configured to emit light in response to a driving current; A driving transistor, configured to supply the driving current; and Multiple switching transistors are configured to control the supply of the drive current, which is transmitted through the drive transistor, to the light-emitting device. At least one of the plurality of switching transistors is configured to provide a grounding path within the pixel, through which excitation current is discharged. The light-emitting device includes a cathode electrode. The plurality of switching transistors include a driving power transistor configured to control the electrical connection between the initialization voltage line and the cathode electrode of the light-emitting device, and the grounding path includes the driving power transistor.

2. The display panel according to claim 1, wherein, The plurality of switching transistors further include: A bias transistor configured to control the connection between the source or drain electrode of the drive transistor and the initialization voltage line. The grounding path is configured between the source or drain electrode of the driving transistor and the cathode electrode, such that the grounding path includes the bias transistor and the driving power transistor.

3. The display panel according to claim 2, wherein, The excitation current is generated based on the change in the threshold voltage of the bias transistor.

4. A display panel comprising: Pixels located in the display area of ​​the display panel, the pixels including: A light-emitting device configured to emit light in response to a driving current; A driving transistor, configured to supply the driving current; and Multiple switching transistors are configured to control the supply of the drive current, which is transmitted through the drive transistor, to the light-emitting device. At least one of the plurality of switching transistors is configured to provide a grounding path within the pixel, through which excitation current is discharged. Wherein, at least one of the plurality of switching transistors configured to provide the path for grounding includes: A first transistor connected to the drain or source electrode of the driving transistor; and A second transistor connected to the first transistor, the second transistor being configured to provide the grounding path to the first transistor when the light-emitting device emits light.

5. The display panel according to claim 4, wherein, The plurality of switching transistors further include: A third transistor connected between the driving transistor and the light-emitting device. The gate electrode of the third transistor is connected to the gate electrode of the second transistor.

6. The display panel according to claim 4, wherein, The second transistor is connected to the cathode electrode of the light-emitting device.

7. A display panel comprising: A light-emitting device, comprising a first electrode, a light-emitting layer, and a second electrode; A driving transistor configured to drive the light-emitting device; A bias transistor configured to control the connection between the drain or source electrode of the drive transistor and an initialization voltage line; as well as A driving power transistor is configured to control the electrical connection between the initialization voltage line and the second electrode of the light-emitting device and provide a path for grounding, wherein the excitation current is discharged through the path for grounding.

8. The display panel according to claim 7, further comprising: An emission control transistor is configured to control the light emission of the light-emitting device. The gate electrode of the driving power transistor is electrically connected to the gate electrode of the emitter control transistor.

9. The display panel according to claim 8, wherein, The emission control transistor is located between the driving transistor and the light-emitting device.

10. The display panel according to claim 7, wherein, The bias transistor is connected to the drain or source electrode of the driving transistor, and the driving transistor is connected to the drain or source electrode of the bias transistor and the second electrode of the light-emitting device.

11. A display device comprising: A display panel includes an optical region and a non-optical region, the optical region including a transmissive region, and the non-optical region including light-emitting devices located in the light-emitting region of a pixel; as well as The protective glass located on the display panel, The pixel is configured to provide a grounding path within the pixel, through which excitation current is discharged. The grounding path does not include the light-emitting device. The light-emitting device is configured to emit light in response to a driving current, and the light-emitting device includes a first electrode, a light-emitting layer, and a second electrode, wherein the pixel further includes: A driving transistor, configured to supply the driving current; and A plurality of switching transistors are configured to control the supply of the drive current, driven by the driving transistor, to the light-emitting device. The plurality of switching transistors include a driving power transistor configured to provide the grounding path, through which the excitation current generated in the pixel is discharged. The driving power transistor is connected between the initialization voltage line and the second electrode, and the initialization voltage line is connected to the pixel.

12. The display device according to claim 11, wherein, The plurality of switching transistors further include: A bias transistor is connected to the drain or source electrode of the driving transistor and the initialization voltage line, the bias transistor being configured to supply the voltage provided by the initialization voltage line to the drain or source electrode of the driving transistor. The driving power transistor is connected between the second electrode of the light-emitting device and the drain or source electrode of the bias transistor.

13. The display device according to claim 11, further comprising: A polarizer located in the non-optical region but not in the optical region.

14. The display device according to claim 11, wherein, The optical region contains no transistors.

15. The display device according to claim 11, further comprising: A substrate including a first side and a second side opposite to the first side; as well as A metal layer located on the second side, the metal layer being configured to radiate at least heat from the display device.

16. The display device according to claim 11, further comprising: Optical devices that overlap with the optical region.

17. The display device according to claim 11, wherein, The excitation current is generated by allowing charged charges generated on the protective glass to pass through the transmission region into the pixel.

Images