Semiconductor device and method of forming a semiconductor device

Abstract

A semiconductor device includes a first source / drain region including a first metal layer including a first metal and a conductive two-dimensional material on the first metal layer, an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer, a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material, and a gate stack on the two-dimensional semiconductor material. Embodiments of the present invention also provide methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly improving the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device, including: a first source / drain region including: a first metal layer including a first metal; and a conductive two-dimensional material located on the first metal layer; an isolation layer physically contacting the sidewalls of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material located on the isolation layer, wherein the sidewalls of the two-dimensional semiconductor material physically contact the sidewalls of the conductive two-dimensional material; and a gate stack located on the two-dimensional semiconductor material.

[0005] Other embodiments of the present invention provide a semiconductor device comprising: a first transistor including: a first drain region including a first two-dimensional (2D) contact material located above a first metal material; a first source region including a first two-dimensional contact material located above the first metal material; a first two-dimensional channel material extending from the first drain region to the first source region, wherein the first two-dimensional channel material physically contacts the sidewalls of the first two-dimensional contact material in the first drain region and the sidewalls of the first two-dimensional contact material in the first source region; a first gate dielectric material located on the first two-dimensional channel material; a first gate electrode material located on the first gate dielectric material; and a first doped layer extending over the first drain region, the first source region, the first gate dielectric material, and the first gate electrode material.

[0006] Some embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming a low-dimensional semiconductor layer on an isolation layer; forming a gate structure on the low-dimensional semiconductor layer; forming an opening in an isolation layer adjacent to the low-dimensional semiconductor layer; depositing a metal material in the opening; forming a low-dimensional contact layer on the metal material, wherein the sidewalls of the low-dimensional contact layer physically and electrically contact the sidewalls of the low-dimensional semiconductor layer; and depositing a doped layer over the low-dimensional contact layer and the gate structure. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of the invention will be best understood from the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B Top and cross-sectional views of intermediate stages in forming a transistor device according to some embodiments are shown.

[0009] Figure 14A and Figure 14B Top and cross-sectional views of intermediate stages in forming a transistor device according to some embodiments are shown.

[0010] Figure 15 A cross-sectional view is shown of an intermediate stage in the formation of a transistor device according to some embodiments.

[0011] Figure 16 A cross-sectional view is shown of an intermediate stage in the formation of a transistor device according to some embodiments.

[0012] Figure 17A and Figure 17BCross-sectional views are shown of intermediate stages in the formation of p-type and n-type transistors according to some embodiments.

[0013] Figure 18A and Figure 18B Cross-sectional views are shown of intermediate stages in the formation of p-type and n-type transistors according to some embodiments.

[0014] Figure 19A and Figure 19B Cross-sectional views are shown of intermediate stages in the formation of p-type and n-type transistors according to some embodiments.

[0015] Figure 20A and 20B A cross-sectional view is shown of an intermediate stage in the formation of p-type and n-type transistors according to some embodiments.

[0016] Figure 21A and Figure 21B A cross-sectional view is shown of an intermediate stage in the formation of p-type and n-type transistors according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples of various components for implementing the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] The embodiments discussed herein are intended to provide examples for implementing or using the subject matter of this disclosure, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, similar reference numerals are used to denote similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0020] In some embodiments, a transistor device is formed by forming a two-dimensional (2D) channel layer over an isolation layer. Source / drain regions are formed embedded in an isolation layer adjacent to the 2D channel layer. The source / drain regions are electrically contacted with the sidewalls of the 2D channel layer, which can allow for reduced contact resistance between the source / drain regions and the 2D channel layer. In some embodiments, the source / drain regions include a conductive contact layer located on a metal, wherein the contact layer physically and electrically contacts the sidewalls of the 2D channel layer. In some embodiments, the conductive contact layer is a 2D material. In some embodiments, a doped layer is formed over the conductive contact layer to provide doping to the 2D material of the conductive contact layer. In this way, self-aligned contacts to the 2D channel layer with reduced contact resistance can be formed. Furthermore, the techniques described herein allow for a lower risk of damage or contamination of the 2D channel layer.

[0021] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B The diagram illustrates the formation of a p-type transistor 130P and an n-type transistor 130N according to some embodiments of the present invention (see [link]). Figures 13A to 13B Top and cross-sectional views of intermediate stages in a transistor device. These views are numbered followed by the letter "A" or "B", where "A" indicates the corresponding view is a plan view (top view) and "B" indicates the corresponding view is a cross-sectional view. For example, Figure 1BIt shows along Figure 1A The cross-sectional view of reference section B-B' is shown. Unless otherwise stated, the diagram with the cross-sectional view is derived from the corresponding plan view. Figure 1A The reference section B-B' shown is obtained from a section similar to the one shown.

[0022] Figure 1A and Figure 1B Top and cross-sectional views of a substrate 100 according to some embodiments are shown. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 100 may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 100 may be a portion of a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on the substrate, typically on a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 100 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, silicon carbide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The substrate 100 can also be formed from other materials such as sapphire or indium tin oxide (ITO).

[0023] According to some embodiments, an isolation layer 102 is formed over a substrate 100. The isolation layer 102 may or may not be in physical contact with the substrate 100. In some embodiments, other layers and / or devices may be located between the isolation layer 102 and the substrate 100. Other layers or devices may include dielectric layers, such as interlayer dielectrics (ILDs), intermetallic dielectrics (IMDs), low-k dielectric layers, or combinations thereof. Other layers of the devices may include metallic components, such as conductive wiring, metal lines, vias, redistribution layers, metallization patterns, or combinations thereof. Integrated circuit devices, such as passive devices (capacitors, resistors, inductors, etc.) and / or active devices (transistors, diodes, etc.), may or may not be present between the isolation layer 102 and the substrate 100.

[0024] According to some embodiments of the present invention, the isolation layer 102 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, another dielectric material such as silicon carbide, silicon carbide, silicon oxynitride, silicon carbonitride, hexagonal boron nitride (hBN), or a high-k dielectric material such as aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, etc., or the isolation layer 102 comprises a nitride such as silicon nitride, an oxide such as silicon oxide, another dielectric material such as silicon carbide, silicon carbide, silicon oxynitride, silicon carbonitride, hexagonal boron nitride (hBN), or a high-k dielectric material such as aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, etc. The isolation layer 102 may be a crystalline layer (monocrystalline or polycrystalline) or an amorphous layer. In some embodiments, the isolation layer 102 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or combinations thereof, or the isolation layer 102 comprises phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or combinations thereof. The isolation layer 102 may have a single-layer structure or a composite structure comprising multiple layers. For example, the isolation layer 102 may include a bilayer structure, a trilayer structure, etc. A bilayer structure may include two layers formed of different materials, such as a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer. The ILD can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to an alternative embodiment of the invention, the ILD is formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0025] The formation process of the isolation layer 102 may include one or more deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), flowable chemical vapor deposition (FCVD), low-pressure chemical vapor deposition (LPCVD), spin coating, etc. According to some embodiments of the present invention, for example, when the isolation layer 102 comprises silicon oxide and when the substrate 100 is formed of or comprises silicon, the isolation layer 102 may also be formed by thermal oxidation, chemical oxidation, etc.

[0026] like Figure 1BAs shown, according to some embodiments, an etch stop layer 103 may be formed over the isolation layer 102. The etch stop layer 103 may be formed of or comprise a material having a different etch selectivity than the isolation layer 104 (described below). For example, the etch stop layer 103 may be an oxide such as silicon oxide, a nitride such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, metal oxide, or a high-k dielectric material such as aluminum oxide, hafnium oxide, zirconium oxide, or lanthanum oxide. Other materials are possible. Suitable techniques may be used to form the etch stop layer 103, such as those described above for the isolation layer 102. In other embodiments, the etch stop layer 103 is not formed.

[0027] In some embodiments, an isolation layer 104 is formed over an etch stop layer 103 (if present). The isolation layer 104 may comprise one or more layers of materials having an etch selectivity different from that of the underlying etch stop layer 103. In some embodiments, the isolation layer 104 comprises one or more materials described above for the isolation layer 102, but other materials are possible. Suitable techniques may be used to form the isolation layer 104, such as those described above for the isolation layer 102.

[0028] Similarly, Figure 1B As shown, according to some embodiments, substrate 100 may have a p-type region 10P and an n-type region 10N. The p-type region 10P can be used to form p-type devices, such as PMOS transistors, for example, p-type FinFETs or p-type planar transistors. The n-type region 10N can be used to form n-type devices, such as NMOS transistors, for example, n-type FinFETs or n-type planar transistors. Figure 1A and Figure 1B An embodiment is shown in which the p-type region 10P and the n-type region 10N are continuous. In other embodiments, the p-type region 10P may be physically separated from the n-type region 10N, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the p-type region 10P and the n-type region 10N.

[0029] exist Figure 2A and Figure 2BIn some embodiments, a semiconductor layer 106, a gate dielectric layer 108, and a conductive layer 110 are formed. The semiconductor layer 106 can be used as a channel layer or active layer in a subsequently formed transistor. According to some embodiments of the invention, the semiconductor layer 106 is formed of a two-dimensional (2D) material, which may include one or more monolayers. Therefore, a semiconductor layer formed of one or more monolayers of a 2D material may be referred to herein as a "2D semiconductor layer." In some embodiments, the semiconductor layer 106 may include a carbon nanotube network or aligned carbon nanotubes. The carbon nanotube network and aligned carbon nanotubes can be formed using methods such as impregnation or drop casting.

[0030] In some embodiments, the semiconductor layer 106 may include one or more 2D materials, such as transition metal dichalcogenides (TMDs). The TMD material may be a compound of a transition metal and a group VIA element (e.g., chalcogens). Transition metals may include W, Mo, Ti, V, Co, Ni, Zr, Tc, Rh, Pd, Hf, Ta, Re, Ir, Pt, etc. Group VIA elements may include sulfur, selenium, tellurium, etc. For example, the semiconductor layer 106 may be formed from or include MoS2, MoSe2, WS2, WSe2, ReS2, etc. The semiconductor layer 106 may include other materials, such as SnS2, InSe, phosphorene, tellurene, graphene, etc. The formation of the TMD material may include CVD, for example, using MoO3 powder and sulfur or selenium powder as precursors, and using N2 as a carrier gas. According to alternative embodiments of the invention, PECVD or another suitable method can be used to form the TMD material. According to some embodiments of the invention, the semiconductor layer 106 has a thickness in the range of about 0.3 nm to about 10 nm; however, other thicknesses are possible. The thickness of the semiconductor layer 106 can depend on the number of monolayers within the semiconductor layer 106.

[0031] However, the processes described above are intended to be illustrative only and are not intended to limit the embodiments. Instead, any suitable process for forming or placing the semiconductor layer 106 on the isolation layer 104 can be utilized. For example, CVD processes using precursors such as MoO3 and H2S or precursors such as Mo and H2S can also be utilized. In some embodiments, a physical vapor deposition (PVD) process utilizing a MoS2 target can be utilized. Furthermore, any other suitable process can be used, such as dissociation of spin-coated (NH4)2MoS4, or growth of the semiconductor layer 106 on a substrate (e.g., copper, nickel, sapphire, etc.) and then transfer of the semiconductor layer 106 to the isolation layer 104. In some embodiments, the TMD material for the semiconductor layer 106 can be formed separately from the substrate 100 in a bulk manner, and then the bulk semiconductor layer material is removed and placed on the isolation layer 104. Any suitable method for forming or placing the semiconductor layer 106 can be used, and all such methods are fully intended to be included within the scope of the embodiments.

[0032] A gate dielectric layer 108 can then be deposited over the semiconductor layer 106. According to some embodiments, the gate dielectric layer 108 comprises a high-k dielectric material such as HfO2, Al2O3, ZrO2, Y2O3, ErO2, hBN, etc., although other materials such as other metal oxides, silicon oxide, silicon nitride, etc., can be used. In some embodiments, the gate dielectric layer 108 comprises a variety of materials, such as a combination of one or more materials listed above. Deposition methods may include ALD, CVD, PECVD, etc. According to some embodiments, the thickness of the gate dielectric layer 108 is in the range of about 0.5 nm to about 50 nm. Other thicknesses are possible.

[0033] A conductive layer 110 can then be formed over the gate dielectric layer 108. The conductive layer 110 is then patterned to form the gate electrodes 110P / 110N (see [link to documentation]). Figures 4A to 4B The conductive layer 110 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Other materials are possible. For example, although in Figures 2A to 2BA single conductive layer 110 is shown, but the conductive layer 110 may include any number of seed layers, any number of pad layers, or any number of work function adjustment layers. The conductive layer 110 can be deposited by PVD, CVD, sputtering deposition, plating, or other techniques known and used in the art for depositing conductive materials. After the conductive layer 110 is formed, a planarization process such as chemical mechanical polishing (CMP) can be performed to planarize the top surface of the conductive layer 110. According to some embodiments, the thickness of the conductive layer 110 is in the range of about 10 nm to about 30 nm. Other thicknesses are possible.

[0034] Figures 3A to 4B Patterning of the conductive layer 110, gate dielectric layer 108, and semiconductor layer 106 according to some embodiments is shown. According to some embodiments, in... Figure 3A and Figure 3B In this process, a patterned mask 112 is formed above the conductive layer 110. For example, the patterned mask 112 can be formed by first depositing a mask material above the conductive layer 110. For example, the mask material can be a material such as an oxide, a nitride, a photoresist layer, or a multilayer photoresist structure. Suitable techniques such as CVD or spin coating can be used to deposit the mask material. Then, acceptable photolithography and etching techniques can be used to pattern the mask material to form the patterned mask 112.

[0035] exist Figure 4A and Figure 4B In some embodiments, the pattern of the patterned mask 112 is transferred to the conductive layer 110, the gate dielectric layer 108, and the semiconductor layer 106. For example, the patterned mask 112 can be used as an etching mask to perform an etching process. The etching process may include one or more suitable wet etching processes and / or dry etching processes, and the etching process may be anisotropic. In some embodiments, the etching process may be selective, such that the isolation layer 104 acts as an etch stop layer. In some embodiments, the patterned mask 112 may remain on the conductive layer 110 after the etching process.

[0036] like Figures 4A to 4B As shown, the etching process forms a semiconductor layer 106P in the p-type region 10P and a semiconductor layer 106N in the n-type region 10N. For example, semiconductor layer 106P forms the channel region of a p-type transistor in the p-type region 10P, and semiconductor layer 106N forms the channel region of an n-type transistor in the n-type region 10N. In other embodiments, multiple semiconductor layers 106P or multiple semiconductor layers 106N may be formed. In other embodiments, semiconductor layers 106P and 106N may be continuously formed from a single continuous region of semiconductor layer 106.

[0037] A patterned gate dielectric layer 108 forms a gate dielectric layer 108P over a semiconductor layer 106P in the p-type region 10P and a gate dielectric layer 108N over a semiconductor layer 106N in the n-type region 10N. A patterned conductive layer 110 forms a gate electrode 110P over the gate dielectric layer 108P in the p-type region 10P and a gate electrode 110N over the gate dielectric layer 108N in the n-type region 10N. The gate electrode 110P and the gate dielectric layer 108P can be collectively referred to as a "p-type gate stack" or a "p-type gate structure". Similarly, the gate electrode 110N and the gate dielectric layer 108N can be collectively referred to as an "n-type gate stack" or an "n-type gate structure". In some embodiments, the gate stack may have a length L1 in the range of about 5 nm to about 1000 nm; however, other lengths are possible.

[0038] Figures 5A to 8B The formation of source / drain metal 116 according to some embodiments is illustrated. Source / drain metal 116 and subsequently formed contact layer 118 (see [reference]). Figures 9A to 9B The source / drain regions 120P / 120N of the contact semiconductor layer 106 are formed (see...) Figures 11A to 11B ).exist Figures 5A to 5B In this process, a patterned photoresist 114 is formed above the isolation layer 104 and around the gate stack. For example, the photoresist 114 can be formed by spin coating or similar methods, and can also be patterned using suitable photolithography techniques. The patterned formation extends through the photoresist 114 to correspond to the source / drain metal 116 (see [reference]). Figures 7A to 8B Opening 113. Opening 113 can expose a region of the isolation layer 104 adjacent to the gate stack. For example... Figures 5A to 5B As shown, the gate stack can remain covered by the patterned mask 112.

[0039] exist Figure 6A and Figure 6B In some embodiments, openings 113 in the pattern of photoresist 114 extend through the isolation layer 104. The patterned photoresist 114 and a patterned mask 112 can be used as a combined etch mask to perform an etching process. For example, wet etching and / or dry etching processes can be performed to etch the portions of the isolation layer 104 exposed by the openings 113. The etching process can be anisotropic. Figures 6A to 6BAs shown, the etching process can stop at the etch stop layer 103. The etching process forms an opening 113 in the isolation layer 104 adjacent to the semiconductor layer 106. In some embodiments, the opening 113 in the isolation layer 104 can extend from one semiconductor layer 106 to another semiconductor layer 106, such as between two semiconductor layers 106P in the p-type region 10P, between two semiconductor layers 106N in the n-type region 10N, or between semiconductor layers 106P and 106N, as shown. Figures 6A to 6B As shown.

[0040] In other embodiments, the etch stop layer 103 may be absent. In some cases, the etching process may remove the upper portion of the patterned photoresist 114 and / or the patterned mask 112. In other embodiments, the etching process may not extend the opening completely through the isolation layer 104, or the etching process may also etch other layers beneath the isolation layer 104.

[0041] exist Figure 7A and Figure 7B In some embodiments, a source / drain metal 116 material is deposited. In some cases, the source / drain metal 116 can be deposited within the opening 113 in the isolation layer 104 and above some surfaces of the patterned photoresist 114 and / or the patterned mask 112. The source / drain metal 116 can be formed by ALD, PVD, CVD, sputtering deposition, plating (such as electroplating or electroless plating), or other techniques known and used in the art for depositing conductive materials. In some embodiments, the conductive material may include a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, nickel, titanium, tantalum, bismuth, tin, antimony, gold, platinum, palladium, niobium, copper, combinations thereof, or multilayers thereof. For example, although Figures 7A to 7B The source / drain metal 116 is shown, but the source / drain metal 116 may include more than one layer of conductive material.

[0042] As an example of forming the source / drain metal 116, a seed layer (not shown) can be formed over the patterned photoresist 114, over the patterned mask 112, and in the opening 113. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. The seed layer can be formed using, for example, PVD. A conductive material is formed on the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating.

[0043] In other embodiments, the material of the source / drain metal 116 in the p-type region 10P is different from the material of the source / drain metal 116 in the n-type region 10N. For example, the material of the source / drain metal 116 in each region 10P / 10N can be selected to have an appropriate work function for each region 10P / 10N. In some embodiments, different deposition processes can be used in the p-type region 10P and the n-type region 10N, wherein the n-type region 10N is covered by a mask (e.g., photoresist) during the deposition of one or more materials in the p-type region 10P, and wherein the p-type region 10P is covered by a mask during the deposition of one or more materials in the n-type region 10N. In this way, in some embodiments, more or different photolithography and patterning steps can be utilized. Other techniques or process steps are possible.

[0044] exist Figure 8A and Figure 8B In some embodiments, the patterned photoresist 114 and the patterned mask 112 are removed. The patterned photoresist 114 and the patterned mask 112 can be removed using acceptable ashing or etching processes, such as oxygen plasma, one or more wet etching processes, or combinations thereof. Removing the patterned photoresist 114 and the patterned mask 112 also removes portions of the seed layer and source / drain metal 116 deposited thereon. In some embodiments, once the patterned photoresist 114 and the patterned mask 112 have been removed, any remaining portions of the seed layer can be removed using a suitable etching process. After the patterned photoresist 114 and the patterned mask 112 are removed, portions of the source / drain metal 116 remain within openings 113 in the isolation layer 104. In this way, in some cases, the formation of the source / drain metal 116 can be considered a “self-aligned” deposition. Hereinafter, the seed layer and the remaining portions of the source / drain metal 116 may be collectively referred to as “source / drain metal 116”.

[0045] In some embodiments, the top surface of the source / drain metal 116 is located above the bottom surface of the semiconductor layer 106 and below the top surface of the semiconductor layer 106, such as... Figure 8BAs shown. In other words, the top surface of the source / drain metal 116 can be adjacent to the sidewall surface of the semiconductor layer 106. In other embodiments, the top surface of the source / drain metal 116 is located below the bottom surface of the semiconductor layer 106, substantially flush with the bottom surface of the semiconductor layer 106, above the top surface of the semiconductor layer 106, or substantially flush with the top surface of the semiconductor layer 106. In this way, the top surface of the source / drain metal 116 can be located below the top surface of the isolation layer 104, substantially flush with the top surface of the isolation layer 104, or above the top surface of the isolation layer 104. In some embodiments, the thickness of the source / drain metal 116 (e.g., the vertical position of the top surface) can be controlled by controlling deposition parameters during the deposition of the source / drain metal 116. For example, the thickness of the source / drain metal 116 can be controlled to allow the subsequently formed contact layer 118 (see Figures 9A to 9B The source / drain metal 116 is vertically aligned with the semiconductor layer 106. In some embodiments, the source / drain metal 116 may have a thickness in the range of about 5 nm to about 100 nm, however other thicknesses are possible.

[0046] exist Figure 9A and Figure 9B In some embodiments, a contact layer 118 is formed on the source / drain metal 116 to form source / drain regions 120P / 120N. The contact layer 118 physically and electrically contacts the sidewalls of the 2D semiconductor layer 106. In this way, the contact layer 118 is electrically coupled to the side surface or edge surface of a single layer of the 2D semiconductor layer 106. Figure 9B As shown, each region of the source / drain metal 116 and the contact layer 118 above it in the p-type region 10P forms a source / drain region 120P that contacts the sidewall of the semiconductor layer 106P, and each region of the source / drain metal 116 and the contact layer 118 above it in the n-type region 10N forms a source / drain region 120N that contacts the sidewall of the semiconductor layer 106N. The source / drain regions 120P / 120N are partially formed within the isolation layer 104 and therefore can in some cases be considered “embedded contacts” or “self-aligned contacts” to the semiconductor layer 106. In other embodiments, the source / drain metal 116 formed in the p-type region 10P may be a different material than the source / drain metal 116 formed in the n-type region 10N, and / or the contact layer 118 formed in the p-type region 10P may be a different material than the contact layer 118 formed in the n-type region.

[0047] In some cases, forming a contact layer 118 on the sidewalls of the 2D semiconductor layer 106 can allow for improved electrical connection between the source / drain regions 120P / 120N and the semiconductor layer 106. For example, in some cases, the electrical contact between the metal and the flat surface of the 2D monolayer may have a large Schottky resistance due to Fermi level pinning at the flat interface. Fermi level pinning can be largely independent of the specific metal used. Therefore, such Fermi level pinning can result in a large contact resistance between the metal contact and the flat surface of the 2D semiconductor layer. However, in some cases, the interface between the metal and the edge surface of the 2D monolayer may have little or no Fermi level pinning. Therefore, the electrical contact between the metal and the edge surface of the 2D monolayer can have a relatively small Schottky resistance. In this way, contacting the edge surface (e.g., the sidewalls) of the 2D semiconductor layer 106 instead of the flat surface (e.g., the top surface) of the 2D semiconductor layer 106 can allow for reduced contact resistance.

[0048] Furthermore, by forming the source / drain regions 120P / 120N on the sidewalls of the contact 2D semiconductor layer 106 as described herein, rather than on the top surface of the contact 2D semiconductor layer 106, damage to the upper monolayer of the 2D semiconductor layer 106 during the deposition of the material for the source / drain regions 120P / 120N can be avoided. Moreover, forming the source / drain regions 120P / 120N on the sidewalls of the contact 2D semiconductor layer 106 as described herein avoids processes that could leave photoresist residues or other types of process residues on the top surface of the semiconductor layer 106.

[0049] Still referencing Figure 9A and Figure 9B In some embodiments, the contact layer 118 may comprise one or more monolayers of conductive 2D material. In this way, the edge surface of the 2D monolayer of the contact layer 118 makes physical and electrical contact with the edge surface of the 2D monolayer of the semiconductor layer 106. By using the edge surface of the 2D contact layer 118 to make electrical contact with the 2D semiconductor layer 106, the effects of Fermi level pinning can be further reduced, and the contact resistance between the source / drain regions 120P / 120N and the semiconductor layer 106 can be reduced accordingly.

[0050] The contact layer 118 may include one or more conductive 2D materials, including graphene, transition metal dichalcogenides (TMDs), etc. The conductive 2D material may be doped or undoped. In some embodiments, a low-k doped layer 122P / 122N may be used to dope the monolayer of the contact layer 118. The following section discusses... Figures 10A to 10BA more detailed description is provided. A monolayer of contact layer 118 may be formed on source / drain metal 116. In some embodiments, the monolayer of contact layer 118 may comprise the same metal as source / drain metal 116. In some embodiments, the upper portion of source / drain metal 116 is bonded to the monolayer of contact layer 118.

[0051] In some embodiments, the contact layer 118 comprises a conductive TMD material. For example, the contact layer 118 may comprise a TMD material such as NbSe2, NbS2, PtSe2, PtS2, VSe2, VS2, etc. Other materials are possible. In some embodiments, at least the upper portion of the source / drain metal 116 comprises the same transition metal as the contact layer 118 above. For example, the upper portion of the source / drain metal 116 may comprise Nb, Pt, V, etc. In some embodiments, at least a portion of the TMD material of the contact layer 118 is formed by reacting a group VIA element (e.g., sulfur, selenium, tellurium, etc.) with the upper portion of the source / drain metal 116. For example, in some embodiments, the TMD material may be formed by exposing the top surface of the source / drain metal 116 to sulfur powder or selenium powder to sulfide or selenize the upper portion of the source / drain metal 116. In some embodiments, the group VIA elements react with the source / drain metal 116 at a process temperature ranging from about 250°C to about 700°C; however, other process temperatures are possible. In other embodiments, the TMD material of the contact layer 118 may be formed on the source / drain metal 116 without being bonded to it. In some embodiments, the contact layer 118 may comprise undoped (e.g., intrinsic) conductive TMD material. In other embodiments, another suitable technique or combination of techniques may be used to form the conductive TMD material, such as CVD, PECVD, ALD, MBE, etc. In some embodiments, an annealing process may be performed after the formation of the contact layer 118.

[0052] In some embodiments, the contact layer 118 may be formed of a doped TMD material. In some cases, the doped TMD material can enhance the conductivity of the contact layer 118. The TMD material may be similar to the conductive TMD materials described above, or it may be a different TMD material, such as MoS2, MoSe2, WS2, WSe2, ReS2, etc. In some embodiments, a dopant material may be introduced during the formation of the contact layer 118 (e.g., using in-situ doping). In some cases, the dopant material may act as an alternative dopant. For example, a vanadium precursor (e.g., V2O5, etc.) may be used during the formation of MoS2 to form a contact layer 118 comprising V-doped MoS2. This is an example, and other TMD materials, dopants, or precursors are possible. For example, in some embodiments, one or more other dopant materials, such as Fe, Nb, Re, Sn, Cl, N, O, etc., or combinations thereof, may be used. In other embodiments, another suitable technique or combination of techniques may be used to form the doped TMD material, such as CVD, PECVD, ALD, MBE, etc. In some embodiments, the doped TMD material can be formed using a process temperature in the range of about 250°C to about 700°C; however, other process temperatures are possible. In some embodiments, an annealing process can be performed after the formation of the doped contact layer 118.

[0053] In some embodiments, the doping of the contact layer 118 can be achieved using a low-k doped layer 122P / 122N that covers the contact layer 118 and provides a doping-like effect to the TMD material of the contact layer 118. This is described in more detail below. Figures 10A to 13B An embodiment is shown in which a low-k doped layer 122P / 122N is used to provide effective doping for the contact layer 118. The low-k doped layer 122P / 122N can be used in addition to, or instead of, other techniques used for doping the contact layer 118. In other embodiments, the low-k doped layer 122P / 122N is not formed, as described in more detail below. Figures 20A to 20B An embodiment without the low-k doped layer 122P / 122N is shown. In other embodiments, the contact layer 118 is not a 2D material, but rather comprises a conductive material layer such as a metal or metal alloy. More detailed description follows. Figures 21A to 21B An embodiment is shown in which the contact layer 118 is a conductive material layer.

[0054] In some embodiments, the top surface of the contact layer 118 is substantially flush with the top surface of the semiconductor layer 106, such as... Figure 9B As shown. In other embodiments, the top surface of the contact layer 118 is below the top surface of the semiconductor layer 106. In other embodiments, the top surface of the contact layer 118 is above the top surface of the semiconductor layer 106. The following refers to... Figures 18A to 18B An example embodiment is described where the top surface of the contact layer 118 is located above the top surface of the semiconductor layer 106. The top surface of the contact layer 118 may be above, substantially flush with, or below the top surface of the isolation layer 104. The bottom surface of the contact layer 118 may be above, substantially flush with, or below the bottom surface of the semiconductor layer 106. In this way, the contact area between the contact layer 118 and the semiconductor layer 106 may have a height substantially the same as the thickness of the semiconductor layer 106 or may have a height less than the thickness of the semiconductor layer 106. In other words, the contact layer 118 may partially or completely cover the sidewalls of the semiconductor layer 106.

[0055] In some embodiments, the contact layer 118 may have a thickness ranging from about 0.4 nm to about 50 nm, however other thicknesses are possible. The thickness of the contact layer 118 may be greater than, substantially the same as, or less than the thickness of the semiconductor layer 106. In some cases, increasing the thickness of the contact layer 118 to increase the contact area between the contact layer 118 and the semiconductor layer 106 may allow for a reduction in the contact resistance between the source / drain regions 120P / 120N and the semiconductor layer 106. For example, the thickness of the contact layer 118 can be controlled by controlling the number of monolayers formed within the contact layer 118. In some embodiments, the source / drain regions 120P / 120N may have a length L2 ranging from about 3 nm to about 500 nm, however other lengths are possible.

[0056] Figure 10A and Figure 10B A low-k doped layer 122P / 122N is shown formed over the source / drain regions 120P / 120N according to some embodiments. The low-k doped layer 122P / 122N is formed to provide a doping-like effect to the contact layer 118 of the source / drain regions 120P / 120N. Using the low-k doped layer 122P / 122N in this manner can improve the conductivity or contact resistance of the contact layer 118. Figure 10B In the illustrated embodiment, a low-k doped layer 122P is formed over the contact layer 118 and the p-type gate stack (e.g., gate electrode 110P and gate dielectric layer 108P) in the p-type region 10P, and a low-k doped layer 122N is formed over the contact layer 118 and the n-type gate stack (e.g., gate electrode 110N and gate dielectric layer 108N) in the n-type region 10N. The low-k doped layer 122P effectively dops the underlying contact layer 118 to form the p-type contact layer 118P, and the low-k doped layer 122N effectively dops the underlying contact layer 118 to form the n-type contact layer 118N.

[0057] In some embodiments, a low-k doped layer 122P can be formed in the p-type region 10P, for example, by first forming a mask, such as photoresist, over the p-type region 10P and the n-type region 10N, and then patterning the mask to expose the contact layer 118P and the p-type gate stack in the p-type region 10P. The low-k doped layer 122P can then be deposited on the exposed contact layer 118P and the gate stack. The mask can then be removed. Subsequently, another mask, such as photoresist, can be formed over the p-type region 10P, simultaneously exposing the contact layer 118N and the n-type gate stack in the n-type region 10N. The low-k doped layer 122N can then be deposited on the exposed contact layer 118N and the n-type gate stack. The mask can then be removed. This is an example, and other process steps are possible, such as forming the low-k doped layer 122N prior to forming the low-k doped layer 122P. Figures 10A to 10B A low-k doped layer 122P and 122N are shown laterally separated between a p-type region 10P and an n-type region 10N, with an undoped portion of contact layer 118 located between contact layer 118P and contact layer 118N. In other embodiments, the low-k doped layers 122P and 122N may be continuous, physically in contact with each other, or one may partially cover the other. In other embodiments, the low-k doped layers 122P / 122N may be formed in the p-type region 10P but not in the n-type region 10N, or vice versa.

[0058] The low-k doped layers 122P / 122N can be formed from any suitable material and can be deposited using any suitable process. The low-k doped layer 122P in the p-type region 10P can include one or more materials such as MoO3, WO3, V2O5, AuCl3, HAuCl4, F4TCNQ, TFSA, HNO3, NO2, etc., or combinations thereof. The low-k doped layer 122N in the n-type region 10N can include one or more materials such as silicon nitride, silicon oxide, silicon oxynitride, titanium dioxide, aluminum oxide, Cs2CO3, polyethyleneimine, benzyl viologen, another oxide material, another nitride material, etc., or combinations thereof. These are examples, and in other embodiments, the low-k doped layer 122P or low-k doped layer 122N can include other materials or dopants. The low-k doped layer 122P / 122N can be formed using any suitable technique such as CVD, PVD, ALD, spin coating, evaporation, or another technique. In some embodiments, the low-k doped layer 122P / 122N can be formed with a thickness ranging from about 0.8 nm to about 100 nm; however, other thicknesses are possible.

[0059] In some cases, the low-k doped layer 122P / 122N spontaneously provides effective doping to the underlying contact layer 118 when in physical contact with it. In other embodiments, an ion implantation process can be performed to implant dopant material into the low-k doped layer 122P / 122N and / or the underlying contact layer 118. In some cases, ion implantation parameters can be controlled to limit or minimize damage to the contact layer 118. In some embodiments, annealing can be performed to promote or enhance the doping effect of the low-k doped layer 122P / 122N and / or the ion implantation.

[0060] In some embodiments, the low-k doped layer 122P / 122N may conformally extend on the top surface of the contact layer 118, on the sidewalls of the gate dielectric layer 108, and on the sidewalls and top surface of the gate electrode 110P / 110N. In some embodiments, the low-k doped layer 122P / 122N may extend on the sidewalls of the semiconductor layer 106. In some cases, the presence of a low-k layer, such as the low-k doped layer 122P / 122N extending from the contact layer 118 to the gate electrode 110P / 110N, can reduce the parasitic capacitance between the contact layer 118 and the gate electrode 110P / 110N. Reducing parasitic capacitance in this way can improve the speed, efficiency, and reliability of the device.

[0061] Figure 11A and Figure 11B A dielectric layer 124 is shown formed over low-k doped layers 122P and 122N according to some embodiments. The dielectric layer 124 may comprise a material similar to that previously described for isolation layers 102 or 104, and may be formed using similar techniques. The dielectric layer 124 may comprise one layer or multiple layers of various materials. In some cases, the dielectric layer 124 may be an ILD or an IMD. In some embodiments, a planarization process is performed on the dielectric layer 124 after its formation.

[0062] exist Figure 12A and Figure 12B In some embodiments, contact openings 125 and 127 are formed. Contact opening 125 is formed through dielectric layer 124, low-k doped layers 122P / 122N, and contact layer 118 for subsequent formation of source / drain contacts 126 (see [link]). Figures 13A to 13B In some embodiments, the contact opening 125 may extend through the contact layer 118 and expose the source / drain metal 116. The contact opening 127 is formed through the dielectric layer 124 and the low-k doped layers 122P / 122N for subsequent formation of the gate contact 128 (see [link]). Figures 13A to 13BIn some embodiments, contact opening 127 may expose gate electrode 110P / 110N. Contact openings 125 and 127 may be formed using acceptable photolithography and etching techniques. Contact openings 125 and 127 may be formed in different processes or in the same process.

[0063] exist Figure 13A and Figure 13B In some embodiments, source / drain contacts 126 are formed in contact openings 125, and gate contacts 128 are formed in contact openings 127. In some embodiments, optional pads (not shown), such as diffusion barrier layers, adhesion layers, etc., and conductive materials are formed in openings 125 / 127. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive materials may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc., or combinations thereof. A planarization process such as CMP may be performed to remove excess material from the surface of dielectric layer 124. The remaining pads and conductive materials form source / drain contacts 126 and gate contacts 128 in openings 125 / 127. Source / drain contacts 126 are physically and electrically coupled to source / drain regions 120P / 120N. In some embodiments, the source / drain contact 126 can physically and electrically contact the top surface of the source / drain metal 116 and the sidewall surface of the contact layer 118. The gate contact 128 is physically and electrically coupled to the gate electrode 110P / 110N. The source / drain contact 126 and the gate contact 128 can be formed in different processes or in the same process. Although the source / drain contact 126 and the gate contact 128 are shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 126 and the gate contact 128 can be formed in a different cross-section, which can avoid short circuits in the contacts.

[0064] In this way, a transistor device can be formed including a p-type transistor 130P having a low-dimensional channel layer 106P and an n-type transistor 130N having a low-dimensional channel layer 106N. The p-type transistor 130P can be formed in the p-type region 10P and the n-type transistor 130N can be formed in the n-type region 10N. In some embodiments, the p-type transistor 130P and the n-type transistor 130N form a complementary metal-oxide-semiconductor (CMOS) transistor device, wherein the p-type transistor 130P is a PMOS device and the n-type transistor 130N is an NMOS device. For example, in Figures 13A to 13BIn the illustrated embodiment, a single source / drain contact 126 can contact both the source / drain region 120P of the p-type transistor 130P and the source / drain region 120N of the n-type transistor 130N. In other embodiments, the p-type transistor 130P and the n-type transistor 130N can be arranged and connected in other configurations. For example, the p-type transistor 130P or the n-type transistor 130N can be separated from other transistors or can have dedicated source / drain contacts 126. The following describes... Figures 17A to 21B Examples of isolated p-type transistor 130P and isolated n-type transistor 130N are described.

[0065] Furthermore, the layout of the p-type transistor 130P and the n-type transistor 130N can be consistent with... Figure 13A The differences are shown. As a non-limiting example, Figure 14A and Figure 14B It shows something similar to Figures 13A to 13B The p-type transistor 130P and n-type transistor 130N shown are arranged in a "U" shape instead of a linear arrangement. For clarity, Figures 14A to 14B Some labels and components have been omitted. Figure 14B along Figure 14A The segmented cross-section ABCD shown indicates that the corresponding positions A, B, C, and D are... Figure 14B The winning bid is provided for reference only. Other layouts, arrangements, or configurations are possible.

[0066] p-type transistor 130P or n-type transistor 130N can be configured to have the same characteristics as... Figures 1A to 13B The different process steps described herein. As a non-limiting example, Figure 15 A p-type transistor 130P and an n-type transistor 130N are shown according to some embodiments. Figure 15 The 130P / 130N transistor is similar to Figures 13A to 13B The transistors 130P / 130N shown have the exception that the low-k doped layer 122P / 122N has been removed from the top surface of the gate electrode 110P / 110N. For example, in the formation of transistors such as... Figures 11A to 11BFollowing the dielectric layer 124, a planarization process can be performed to remove the low-k doped layer 122P / 122N from the top surface of the gate electrode 110P / 110N. After the planarization process, the top surfaces of the low-k doped layer 122P / 122N, the gate electrode 110P / 110N, and the dielectric layer 124 can be horizontal. A dielectric layer 129 can then be deposited over the low-k doped layer 122P / 122N, the gate electrode 110P / 110N, and the dielectric layer 124. The dielectric layer 129 can be similar to the dielectric layer 124 and can be formed using similar techniques. In some embodiments, a planarization process can be performed on the dielectric layer 129. The source / drain contacts 126 and the gate contacts 128 can then be formed using suitable techniques, such as those described previously.

[0067] As another non-restrictive example, Figure 16 A p-type transistor 130P and an n-type transistor 130N are shown according to some embodiments. Figure 16 The 130P / 130N transistor is similar to Figures 13A to 13B The transistors 130P / 130N shown have a source / drain contact 126 that extends through the isolation layer 104 and contacts the sidewall of the source / drain region 120P / 120N. Figure 16 The source / drain contact 126 can be with Figures 13A to 13B The source / drain contacts 126 are similarly formed, except for the contact opening 125 (see [reference]). Figures 12A to 12B The source / drain contact 126 extends below the top surface of the source / drain metal 116. In this way, the source / drain contact 126 can physically and electrically contact the sidewalls of the source / drain metal 116 instead of the top surface of the source / drain metal 116. In some embodiments, the contact opening 125 can expose the etch stop layer 103, and thus the source / drain contact 126 is formed on the etch stop layer 103. Forming the contact opening 125 may include etching the source / drain regions 120P / 120N and / or etching the isolation layer 104. For example, in some embodiments, the source / drain regions 120P and 120N may be separated by a region of the isolation layer 104, which is removed during the etching of the contact opening 125 to expose the sidewalls of the source / drain regions 120P and 120N. In some embodiments, selective etching may be used to selectively remove material from the source / drain regions 120P / 120N or to selectively remove material from the isolation layer 104. In other embodiments, the source / drain contacts 126 may physically and electrically contact the sidewalls and top surface of the source / drain metal 116.

[0068] Although Figures 13A to 16The embodiments described herein depict a p-type transistor 130P connected to an n-type transistor 130N, but in other embodiments, the p-type transistor 130P or the n-type transistor 130N may be formed in an isolated manner. As a non-limiting example, according to some embodiments, Figure 17A A cross-sectional view of an isolated p-type transistor 130P is shown, and Figure 17B A cross-sectional view of an isolated n-type transistor 130N is shown. Figures 17A to 17B The transistors 130P / 130N shown are similar to those shown previously (e.g., Figures 13A to 13B (in China), and similar techniques can be used to form it. Figures 18A to 21B Various embodiments of isolated transistors 130P / 130N are shown. (For...) Figures 18A to 21B Some components described in the embodiments can be applied to other embodiments described herein, such as those for... Figures 13A to 13B Those described above.

[0069] Figure 18A and Figure 18B Cross-sectional views of a p-type transistor 130P and an n-type transistor 130N according to some embodiments are shown. Transistors 130P / 130N are similar to those previously described for... Figures 17A to 17B The described transistors 130P / 130N have the exception that the top surface of the contact layer 118 is higher than the top surface of the semiconductor layer 106. For example, the top surface of the contact layer 118 is higher than the bottom surface of the gate dielectric layer 108 but lower than the top surface of the gate dielectric layer 108. By forming the contact layer 118 extending from below the bottom surface of the semiconductor layer 106 to above the top surface of the semiconductor layer 106, the contact area between the sidewalls of the semiconductor layer 106 and the sidewalls of the contact layer 118 can be maximized. Furthermore, forming the contact layer 118 in this way can help ensure complete sidewall contact between the semiconductor layer 106 and the contact layer 118 in the event of potential process variations.

[0070] Figure 19A and Figure 19B Cross-sectional views of a p-type transistor 130P and an n-type transistor 130N according to some embodiments are shown. Transistors 130P / 130N are similar to those previously described for... Figures 17A to 17B The described transistor 130P / 130N, except that the gate dielectric layer 108 has been laterally recessed to allow the contact layer 118 to physically and electrically contact the top surface of the semiconductor layer 106 in addition to the sidewalls of the semiconductor layer 106. The sidewalls of the gate dielectric layer 108 can be recessed using suitable etching techniques and at any suitable process step. For example, in the case of… Figures 4A to 4BDuring the patterning of the described gate stack, the gate dielectric layer 108 can be recessed by over-etching the gate dielectric layer 108, by etching the gate dielectric layer 108 using relatively isotropic etching, or by selectively etching the sidewalls of the gate dielectric layer 108. These are examples, and other techniques and / or at different steps in the fabrication of transistors 130P / 130N can be used to recess the gate dielectric layer 108. In some embodiments, the sidewalls of the gate dielectric layer 108 can be recessed by a lateral distance ranging from about 0.1 nm to about 10 nm, however other distances are possible. The recessed sidewalls of the gate dielectric layer 108 can have a substantially vertical profile, a flat profile, a recessed profile, or an irregular profile. In some embodiments, recessing the gate dielectric layer 108 can allow a low-k doped layer 122P / 122N to be deposited beneath the gate electrode 110P / 110N, as... Figures 19A to 19B As shown. In other embodiments, a portion of the gate dielectric layer 108 may extend above the top surface of the contact layer 118. In some cases, electrically contacting the semiconductor layer 106 at both the top surface and sidewalls can reduce contact resistance.

[0071] Figure 20A and Figure 20B Cross-sectional views of a p-type transistor 130P and an n-type transistor 130N according to some embodiments are shown. Transistors 130P / 130N are similar to those previously described for... Figures 17A to 17B The described transistors 130P / 130N, except that a low-k doped layer 122P / 122N is not formed. For example, in some cases, the 2D contact layer 118 may be sufficiently conductive so that the low-k doped layer 122P / 122N is not required. This is an example, and the low-k doped layer 122P / 122N may be omitted for other reasons. In some embodiments, the low-k doped layer 122P / 122N may be omitted only from the p-type transistor 130P or only from the n-type transistor 130N.

[0072] Figure 21A and Figure 21B Cross-sectional views of a p-type transistor 130P and an n-type transistor 130N according to some embodiments are shown. Transistors 130P / 130N are similar to those previously described for... Figures 17A to 17BThe described transistors 130P / 130N differ from those comprising 2D material contact layer 118 by using contact layer 119P / 119N comprising a non-2D material. Contact layer 119P / 119N may comprise a highly conductive material that makes physical and electrical contact with the sidewalls of semiconductor layer 106. For example, contact layer 119P / 119N may comprise a metal or metal alloy, such as platinum, PtIn, PtBi, PtSb, another platinum alloy, another metal, or combinations thereof. In some embodiments, the metal or metal alloy may be doped to provide improved electrical connectivity to semiconductor layer 106. For example, the metal or metal alloy may be doped with sulfur or selenium; however, other dopants are possible. In other embodiments, contact layer 119P / 119N may comprise a conductive non-metallic material such as graphene, which may be doped or undoped. Contact layer 119P in p-type region 10P may be the same as or different from contact layer 119N in n-type region 10N. The contact layers 119P / 119N can be deposited using any suitable process. In other embodiments, a low-k doped layer 122P / 122N can be formed on the contact layers 119P / 119N.

[0073] Embodiments of the present invention have several advantageous features. By forming source / drain regions with contact layers having electrical contact with the sides of the 2D channel layer, effects such as Fermi level pinning can be reduced or eliminated. This can reduce the contact resistance between the source / drain regions and the 2D channel, which can improve device performance, improve device efficiency, or reduce device power consumption. The techniques described herein allow for the formation of source / drain regions using self-aligned processes, which can improve device design flexibility, improve process design flexibility, or improve yield. The techniques described herein can also allow for the formation of high work function contacts. Additionally, source / drain regions can be formed on the 2D channel material without depositing temporary materials such as photoresist, which can reduce the probability of damage to the 2D channel and the probability of residues remaining on the 2D channel. This can improve device yield and reliability. The techniques described herein allow for various doping techniques for contact layers, such as the use of doped layers. In some cases, the use of doped layers can also reduce parasitic capacitance between the gate electrode and the source / drain regions, which can improve device speed and performance. The techniques described herein also allow for the formation of complementary (e.g., CMOS) devices.

[0074] According to some embodiments of the present invention, a device includes a first source / drain region comprising: a first metal layer including a first metal; and a conductive two-dimensional material disposed on the first metal layer; an isolation layer physically contacting the sidewalls of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material disposed on the isolation layer, wherein the sidewalls of the two-dimensional semiconductor material physically contact the sidewalls of the conductive two-dimensional material; and a gate stack disposed on the two-dimensional semiconductor material. In embodiments, the device includes doped layers extending on the conductive two-dimensional material and on the gate stack, wherein the doped layers provide a doping effect to the conductive two-dimensional material. In embodiments, the doped layer comprises an oxide. In embodiments, the top surface of the two-dimensional semiconductor material does not contain conductive two-dimensional material. In embodiments, the conductive two-dimensional material comprises a first metal. In embodiments, the first metal is a transition metal. In embodiments, the two-dimensional semiconductor material comprises a transition metal dichalcogenide. In embodiments, the conductive two-dimensional material protrudes above the two-dimensional semiconductor material.

[0075] According to some embodiments of the present invention, the device includes a first transistor comprising: a first drain region including a first two-dimensional (2D) contact material located above a first metal material; a first source region including a first 2D contact material located above the first metal material; a first 2D channel material extending from the first drain region to the first source region, wherein the first 2D channel material physically contacts the sidewalls of the first 2D contact material of the first drain region and the sidewalls of the first 2D contact material of the first source region; a first gate dielectric material located on the first 2D channel material; a first gate electrode material located on the first gate dielectric material; and a first doped layer extending on the first drain region, the first source region, the first gate dielectric material, and the first gate electrode material. In one embodiment, the device includes a second transistor adjacent to the first transistor, wherein the second transistor includes: a second drain region including a second 2D contact material located above a second metal material; a second source region including a second 2D contact material located above a second metal material; a second 2D channel material extending from the second drain region to the second source region, wherein the second 2D channel material physically contacts the sidewalls of the second 2D contact material of the second drain region and the sidewalls of the second 2D contact material of the second source region; a second gate dielectric material located on the second 2D channel material; a second gate electrode material located on the second gate dielectric material; and a second doped layer extending on the second drain region, the second source region, the second gate dielectric material, and the second gate electrode material. In one embodiment, the first transistor is p-type and the second transistor is n-type. In one embodiment, the first drain region physically and electrically contacts the second drain region. In one embodiment, the first 2D channel material and the second 2D channel material comprise the same material. In one embodiment, a first drain region is adjacent to a second drain region, and a first source region is adjacent to a second source region. The device includes gate contacts that physically and electrically contact the first and second gate electrode materials. In another embodiment, a first 2D contact material physically contacts the top surface of a first 2D channel material. In yet another embodiment, the device includes source / drain contacts extending through the first 2D contact material to physically contact a first metal material.

[0076] According to some embodiments of the present invention, a method includes forming a low-dimensional semiconductor layer on an isolation layer; forming a gate structure on the low-dimensional semiconductor layer; forming an opening in an isolation layer adjacent to the low-dimensional semiconductor layer; depositing a metal material in the opening; forming a low-dimensional contact layer on the metal material, wherein the sidewalls of the low-dimensional contact layer physically and electrically contact the sidewalls of the low-dimensional semiconductor layer; and depositing a doped layer over the low-dimensional contact layer and the gate structure. In embodiments, forming the low-dimensional contact layer includes performing a sulfidation process or a selenization process on the metal material. In embodiments, forming the low-dimensional contact layer consumes an upper portion of the metal material. In embodiments, the method includes forming gate contacts extending through the doped layer to physically and electrically contact the gate structure.

[0077] The foregoing outlines the features of the embodiments described herein, enabling those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: The first source / drain region includes: A first metal layer, comprising a first metal; and A conductive two-dimensional material is located on the first metal layer; An isolation layer is physically in contact with the sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; A two-dimensional semiconductor material is located on the isolation layer, wherein the sidewalls of the two-dimensional semiconductor material are in physical contact with the sidewalls of the conductive two-dimensional material; and Gate stacks are located on the two-dimensional semiconductor material. The conductive two-dimensional material protrudes above the two-dimensional semiconductor material.

2. The semiconductor device of claim 1, further comprising a doped layer extending on the conductive two-dimensional material and on the gate stack, wherein, The doped layer provides a doping effect to the conductive two-dimensional material.

3. The semiconductor device according to claim 2, wherein, The doped layer comprises an oxide.

4. The semiconductor device according to claim 1, wherein, The top surface of the two-dimensional semiconductor material does not contain the conductive two-dimensional material.

5. The semiconductor device according to claim 1, wherein, The conductive two-dimensional material includes the first metal.

6. The semiconductor device according to claim 5, wherein, The first metal is a transition metal.

7. The semiconductor device according to claim 1, wherein, The two-dimensional semiconductor material includes transition metal dichalcogenides.

8. The semiconductor device according to claim 1, wherein, The gate stack includes a gate dielectric layer and a gate electrode located on the gate dielectric layer.

9. A semiconductor device, comprising: The first transistor includes: The first drain region includes a first two-dimensional (2D) contact material located above the first metallic material; The first source region includes the first two-dimensional contact material located above the first metal material; A first two-dimensional channel material extends from the first drain region to the first source region, wherein the first two-dimensional channel material physically contacts the sidewall of the first two-dimensional contact material in the first drain region and the sidewall of the first two-dimensional contact material in the first source region. The first gate dielectric material is located on the first two-dimensional channel material; The first gate electrode material is located on the first gate dielectric material; and A first doped layer extends over the first drain region, the first source region, the first gate dielectric material, and the first gate electrode material. The first two-dimensional contact material is in physical contact with the top surface of the first two-dimensional channel material.

10. The semiconductor device of claim 9, further comprising a second transistor adjacent to the first transistor, wherein, The second transistor includes: The second drain region includes a second two-dimensional contact material located above the second metallic material; The second source region includes the second two-dimensional contact material located above the second metal material; A second two-dimensional channel material extends from the second drain region to the second source region, wherein the second two-dimensional channel material physically contacts the sidewall of the second two-dimensional contact material in the second drain region and the sidewall of the second two-dimensional contact material in the second source region. The second gate dielectric material is located on the second two-dimensional channel material; The second gate electrode material is located on the second gate dielectric material; and The second doped layer extends over the second drain region, the second source region, the second gate dielectric material, and the second gate electrode material.

11. The semiconductor device according to claim 10, wherein, The first transistor is p-type, and the second transistor is n-type.

12. The semiconductor device according to claim 10, wherein, The first drain region is in physical and electrical contact with the second drain region.

13. The semiconductor device according to claim 10, wherein, The first two-dimensional channel material and the second two-dimensional channel material comprise the same material.

14. The semiconductor device according to claim 10, wherein, The first drain region is adjacent to the second drain region, wherein the first source region is adjacent to the second source region, and further includes a gate contact that physically and electrically contacts the first gate electrode material and the second gate electrode material.

15. The semiconductor device according to claim 9, wherein, The first two-dimensional contact material includes graphene or transition metal dichalcogenides.

16. The semiconductor device of claim 9, further comprising source / drain contacts extending through the first two-dimensional contact material to physically contact the first metallic material.

17. A method of forming a semiconductor device, comprising: A low-dimensional semiconductor layer is formed on the isolation layer; A gate structure is formed on the low-dimensional semiconductor layer; An opening is formed in the isolation layer adjacent to the low-dimensional semiconductor layer; Deposit metallic material in the opening; A low-dimensional contact layer is formed on the metal material, wherein the sidewalls of the low-dimensional contact layer are in physical and electrical contact with the sidewalls of the low-dimensional semiconductor layer; as well as A doped layer is deposited over the low-dimensional contact layer and the gate structure.

18. The method according to claim 17, wherein, Forming the low-dimensional contact layer includes performing a sulfurization or selenization process on the metal material.

19. The method according to claim 17, wherein, The formation of the low-dimensional contact layer consumes the upper portion of the metal material.

20. The method of claim 17, further comprising forming gate contacts extending through the doped layer to physically and electrically contact the gate structure.

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