A semiconductor structure and a method for preparing the semiconductor structure

Abstract

The disclosed embodiments relate to the semiconductor field, and provide a semiconductor structure and a method for preparing the semiconductor structure, wherein the semiconductor structure comprises: a substrate, wherein pads are arranged at intervals in the substrate; a first groove and a second groove are connected, wherein the first groove and the second groove are located in the substrate, wherein the first groove is located on a side of the second groove away from the pad, wherein the pad is exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate; and a redistribution layer, wherein the redistribution layer is located on the surface of the pad, and is also located on the inner wall of the first groove and the inner wall and bottom of the second groove. The disclosed embodiments can improve the problem of contamination or even damage of the test probe.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] With the rapid development of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry that constitutes electronic devices has also developed rapidly. The production process of semiconductors generally includes processes such as wafer manufacturing, wafer acceptance testing, chip packaging, and post-packaging testing.

[0003] In the chip packaging process, the chip's solder joint (I / O pad) position can be changed through a metal wiring process or a bump process. Generally, the chip's solder joint position can be changed by forming a redistribution layer (RDL) so that the chip can be electrically connected to different packaging substrates or other chips. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for preparing the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, in which pads are arranged at intervals; a first groove and a second groove that are connected, the first groove and the second groove are located in the substrate, the first groove is located on the side of the second groove away from the pad, the pad is exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate; a redistribution layer, the redistribution layer is located on the surface of the pad, and is also located on the inner wall of the first groove and the inner wall and bottom of the second groove.

[0006] In some embodiments, in a cross section perpendicular to the substrate surface direction, a cross-sectional shape of the first groove and / or a cross-sectional shape of the second groove is one of a circle, a square, a rectangle, a trapezoid, etc.

[0007] In some embodiments, a central axis of the first groove coincides with a central axis of the second groove and a central axis of the pad.

[0008] In some embodiments, in a direction from the first groove to the second groove, a depth of the first groove is greater than or equal to a depth of the second groove.

[0009] In some embodiments, the depth of the first groove is equal to the depth of the second groove, and along the arrangement direction of the pad, the width of the first groove d1 = d0 + 2*h / tan(a) + 2x, wherein d0 is the minimum width of the second groove, h is the depth of the second groove, a is the minimum angle formed by the inner wall surface of the second groove and the bottom of the second groove, and x is the width of the step formed between the first groove and the second groove.

[0010] In some embodiments, the semiconductor structure includes: at least two first grooves arranged in a direction perpendicular to the surface of the substrate; and along the arrangement direction of the first grooves pointing to the second grooves, the orthographic projection of any first groove on the substrate is located within the orthographic projection of the first groove on the substrate adjacent to and away from the second groove.

[0011] In some embodiments, in a direction perpendicular to the surface of the substrate, a cross-sectional shape of the opening surrounded by the redistribution layer is a trapezoid.

[0012] In some embodiments, along the arrangement direction of the pads, the ratio of the width of the top of the opening to the width of the pads is in the range of 1.5-1.

[0013] In some embodiments, the thickness of the redistribution layer at the bottom of the second groove is greater than 1 um.

[0014] In some embodiments, the material of the redistribution layer is aluminum, titanium, or titanium nitride.

[0015] In some embodiments, the substrate includes an initial substrate, a first passivation layer, a dielectric layer and a second passivation layer stacked in sequence, the pad is located on the initial substrate, the first passivation layer covers the pad surface, and the top surface of the first passivation layer is higher than the top surface of the pad.

[0016] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for preparing a semiconductor structure, including: providing a substrate, having spaced-apart solder pads formed in the substrate; patterning the substrate, forming a first groove and a second groove that are connected in the substrate, the first groove being formed on a side of the second groove away from the solder pad, the solder pad being exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate being located within the orthographic projection of the first groove on the substrate; forming a redistribution layer, the redistribution layer being formed on the surface of the solder pad, and also formed on the inner wall of the first groove and the inner wall and bottom of the second groove.

[0017] In some embodiments, the process steps of forming the connected first groove and the second groove include: patterning the substrate to form the first groove; and etching the exposed substrate at the bottom of the first groove to form the second groove.

[0018] In some embodiments, before forming the first groove, a first mask layer is formed on the top surface of the substrate, and the substrate is etched using the first mask layer as a mask to form the first groove; before forming the second groove, a second mask layer is formed on the top surface of the substrate, and the substrate is etched using the second mask layer as a mask to form the second groove.

[0019] In some embodiments, the process steps for forming a connected first groove and a second groove include: patterning the substrate to form a first groove, exposing a pad at the bottom of the first groove; etching a portion of the thickness of the substrate located outside the first groove, increasing the size of a portion of the first groove to form a first groove, and the remaining first groove serves as a second groove.

[0020] In some embodiments, before forming the first groove, a third mask layer is formed on the top surface of the substrate; using the third mask layer as a mask, the substrate is etched to form the first groove; before forming the first groove, a fourth mask layer is formed on the top surface of the substrate; using the fourth mask layer as a mask, a partial thickness of the substrate located outside the first groove is etched to form the first groove.

[0021] In some embodiments, the process steps for forming a redistribution layer include: forming a continuous conductive film, the conductive film being located on the inner wall of the first groove, the inner wall and bottom of the second groove, and the top surface of the substrate; etching the conductive film located on the top surface of the substrate, and the remaining conductive film serving as a redistribution layer.

[0022] In some embodiments, the process steps of forming the substrate include: providing an initial substrate, a plurality of pads spaced apart are formed on the surface of the initial substrate, and sequentially forming a stacked first passivation layer, a dielectric layer, and a second passivation layer on the initial substrate, wherein the first passivation layer covers the surface of the pad, and the top surface of the first passivation layer is higher than the top surface of the pad, and the initial substrate, the first passivation layer, the dielectric layer, and the second passivation layer together serve as the substrate.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] The first groove is connected to the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A step is formed between the first groove and the second groove. The step can help the first groove accommodate more redistribution layers, reducing the height difference between the top surface of the redistribution layer and the top surface of the pad, and avoiding the problem of contamination or even damage of the test probe due to difficulty in needle insertion, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0025] In addition, a first groove and a second groove are formed in communication through two etchings, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate, that is, along the direction of the pad arrangement, the width of the first groove is greater than the width of the second groove. Therefore, the width of the first groove can be greater than or equal to the width of the pad, thereby widening the opening of the redistribution layer to allow the test probe to enter the opening and reduce contact with the side wall of the redistribution layer, thereby improving the problem of test probe contamination or even test probe damage. The area where the first groove is located can be a test area for wafer acceptance testing. The substrate located below the test area is etched away, and the height difference between the top surface of the redistribution layer formed in the first groove and the top surface of the pad will be reduced, and the height of the redistribution layer will also be reduced, that is, the area of ​​contact or the movement trajectory of the test probe with the side wall of the redistribution layer is also reduced, which can improve the problem of test probe contamination or even test probe damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0028] Figure 2 A schematic structural diagram of a scribe line region of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 3 A schematic structural diagram of a chip region of a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figures 4 to 19 A schematic diagram of the structures corresponding to each step in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] As can be seen from the background art, there are problems in the semiconductor structure of the prior art that may cause the test probe to be contaminated or even damaged.

[0032] refer to Figure 1 , Figure 1It is a schematic diagram of the structure of a semiconductor structure, which includes: a substrate 100, in which pads 101 are arranged at intervals, and the substrate 100 also includes an initial substrate 109, a first passivation layer 102, a dielectric layer 103 and a second passivation layer 104; a groove 130, in which the groove 130 is located, and the pad 101 is exposed at the bottom of the groove 130; and a redistribution layer 110, in which the redistribution layer 110 is located on the surface of the pad 101 and the surface of the substrate 100, and is also located on the inner wall and the bottom of the groove 130. In order to describe the positional relationship between the pad 101 and the redistribution layer 110, one of the pads 101 is partially enlarged. It can be understood that the pads 101 are actually distributed at intervals, and the structure of each pad 101 is the same. The pad 101 serves as a test pad PAD of the semiconductor structure. In the test process before packaging, the test probe of the test equipment is inserted into the PAD to perform a wafer acceptability test (WAT), that is, the test probe is inserted into the pad 101 to perform a WAT ​​test. The substrate 100 has spaced-apart redistribution layers 110, the area between adjacent redistribution layers 110 is an isolation area 131, and the area where the redistribution layers 110 are located is a test area 132. The isolation area 131 is used to achieve electrical isolation between PADs without affecting the test. However, there is a large height difference between the top surface of the redistribution layer 110 away from the substrate 100 and the top surface of the pad 101, and the opening is small. Specifically, the height difference is greater than 5um. The height difference between the redistribution layer 110 and the pad 101 affects the movement trajectory of the test probe from the isolation area 131 to the test area 132. The small opening affects the test probe from entering the redistribution layer 110 to perform WAT test on the pad 101. Therefore, the test probe needs to be tilted at a certain angle to penetrate into the side wall. The test probes are located on the same row of probe cards. Therefore, the depth of penetration of each test probe of the probe card into the side wall will be different. When the test probe is taken out, the probe that penetrates deeper into the side wall will bring out some debris of the redistribution layer 110, causing test probe contamination or wafer contamination, and even damage to the test probe.

[0033] The disclosed embodiments provide a semiconductor structure and a method for preparing the semiconductor structure. The substrate can be etched twice to form a first groove and a second groove that are connected to each other. The pad is exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. The etching is added once, and the width of the first groove formed by etching is greater than the width of the second groove formed by etching. The area where the first groove is located can be the area formed by the test area. The part of the substrate located under the redistribution layer in the prior art is etched away, and the height difference between the top surface of the redistribution layer and the top surface of the pad is reduced, which can lessen the impact on the movement trajectory of the test probe from the isolation area to the test area, so that the test probe can enter the redistribution layer connected to the pad more easily, and the problem that the test probe cannot accurately align with the pad can be improved. At the same time, the width of the first groove is greater than the width of the second groove, and a step is formed between the first groove and the second groove. The step can help the first groove contain more redistribution layers, which is further beneficial to reducing the height difference between the top surface of the redistribution layer and the top surface of the pad. The height of the redistribution layer of the side wall is reduced, and the movement path and contact area of ​​the test probe with the side wall and the bottom are also reduced, which can improve the problem of test probe contamination or even test probe damage. In addition, the width of the first groove is greater than the width of the second groove, and the width of the opening of the redistribution layer in the first groove will also increase, shortening the movement path of the test probe from the isolation area to the test area, and also helping the test probe enter the opening, that is, reducing contact with the side wall, which is beneficial to improving the problem of test probe contamination or even test probe damage.

[0034] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0035] Figure 2 A schematic diagram of a structure of a scribe line region of a semiconductor structure provided by an embodiment of the present disclosure, Figure 3 A schematic structural diagram of a chip region of a semiconductor structure provided in one embodiment of the present disclosure.

[0036] refer to Figures 2 to 3The semiconductor structure includes: a substrate 200, in which pads 201 are arranged at intervals; a first groove 230 and a second groove 240 are connected, the first groove 230 and the second groove 240 are located in the substrate 200, the first groove 230 is located on the side of the second groove 240 away from the pad 201, the pad 201 is exposed at the bottom of the second groove 240, and the orthographic projection of the second groove 240 on the substrate 200 is located within the orthographic projection of the first groove 230 on the substrate 200; a redistribution layer 210, the redistribution layer 210 is located on the surface of the pad 201, and is also located on the inner wall of the first groove 230 and the inner wall and bottom of the second groove 240.

[0037] The wafer includes a chip area and a cutting road area. The chip area and the cutting road area have specific circuits composed of various semiconductor devices, such as transistors, resistors, and triodes. The cutting road area is used for subsequent cutting to be divided into individual chips. The semiconductor devices in the chip area have the same structure as the semiconductor devices in the cutting road area. The semiconductor devices in the cutting road area can be subjected to WAT testing to simulate and characterize the performance of the semiconductor devices in the chip area, thereby helping to improve the yield of the wafer. Exemplarily, the semiconductor structure provided in the embodiment of the present application can be a semiconductor structure formed in the cutting road area, including a substrate 200 and a pad 201, wherein various types of semiconductor devices are formed in the substrate 200.

[0038] It can be understood that, in order to describe the positional relationship between the pads 201 and the redistribution layer 210 , one of the pads 201 is partially enlarged, and the pads 201 are actually distributed at intervals, and each pad 201 has the same structure.

[0039] In some embodiments, the substrate 200 may be a laminated structure, and the substrate 200 may have electrical devices such as transistors, resistors or capacitors, and the pad 201 may be electrically connected to the port of the electrical device through a variety of conductive structures (not shown in the figure) to apply a working voltage / current and derive a test voltage / current. The material of the pad 201 may be aluminum, tungsten and copper. The resistance of aluminum, tungsten and copper is relatively small, which is conducive to improving the conductive performance of the pad 201, thereby facilitating the conductive ability of the pad 201 and the subsequently formed redistribution layer.

[0040] In some embodiments, substrate 200 includes a stacked initial substrate 209, a first passivation layer 202, a dielectric layer 203 and a second passivation layer 204, pad 201 is located on initial substrate 209, first passivation layer 202 covers the surface of pad 201, and the top surface of first passivation layer 202 is higher than the top surface of pad 201.

[0041] In some embodiments, the initial substrate 209 may be located in the scribe line area. The material of the first passivation layer 202 is an insulating material, which is used to electrically isolate the spaced pads 201. Specifically, in some embodiments, the material of the first passivation layer 202 is silicon oxide. In other embodiments, the material of the first passivation layer 202 may also be silicon nitride or silicon carbide.

[0042] In some embodiments, the material of the dielectric layer 203 is silicon nitride, which is used as an etching stop to prevent subsequent etching from being too deep and affecting the reliability of the semiconductor structure; the material of the second passivation layer 204 can be the same as that of the first passivation layer 202. In other embodiments, the material of the dielectric layer 203 can also be an insulating material such as silicon oxide, silicon carbide, or other high dielectric constant materials. The material of the second passivation layer 204 can be different from that of the first passivation layer 202.

[0043] It should be noted that the embodiment of the present disclosure does not limit the specific film layers in the substrate 200 (such as the initial substrate 209, the first passivation layer 202, the dielectric layer 203 and the second passivation layer 204). For example, the initial substrate 209 may only have a first passivation layer covering the pad 201.

[0044] In some embodiments, the first groove 230 and the second groove 240 serve as the process basis for forming the redistribution layer, and the redistribution layer can be located on the inner wall of the first groove 230, the inner wall of the second groove 240, and the bottom. The first groove 230 is connected to the second groove 240, and the orthographic projection of the second groove 240 on the substrate 200 is located within the orthographic projection of the first groove 230 on the substrate 200. A step is formed between the first groove 230 and the second groove 240. The step can assist in accommodating more redistribution layers 210 in the first groove 230, reduce the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201, and can lessen the impact on the movement trajectory of the test probe from the area where the redistribution layer 210 is not located to the area where the redistribution layer 210 is located, so that it is easier for the test probe to enter the redistribution layer 210 connected to the pad 201, the height of the redistribution layer 210 is reduced, and the movement path of the test probe sliding over the side wall and contacting the bottom is also reduced, which can improve the problem of test probe contamination or even test probe damage.

[0045] In some embodiments, on a cross-section perpendicular to the top surface of the substrate 200, the cross-sectional shape of the first groove 230 and the cross-sectional shape of the second groove 240 are one of the shapes of a circle, a square, a rectangle, a trapezoid, etc. Optionally, the cross-sectional shape of the first groove 230 and the cross-sectional shape of the second groove 240 are trapezoidal, that is, the inner wall surface of the first groove 230 and the inner wall surface of the second groove 240 are both inclined surfaces, and the surface of the redistribution layer 210 formed on the inner wall surface of the first groove 230 and the inner wall surface of the second groove 240 can be an inclined surface, and the extension direction of the inclined surface can guide the test probe, thereby facilitating the test probe to enter the opening 211 of the redistribution layer 210, which is beneficial to improving the accuracy of the test data. In addition, the cross-sectional shape of the first groove 230 is a trapezoid, which is the same as the cross-sectional shape of the first groove 230 being a rectangle. The volume of the first groove 230 is larger, and more redistribution layers 210 can be accommodated in the first groove 230, which is beneficial to reducing the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201. The movement path of the test probe sliding over the side wall and contacting the bottom is also reduced, which can improve the problem of test probe contamination or even test probe damage; the opening 211 in the redistribution layer 210 located in the first groove 230 will also be enlarged, shortening the movement path of the test probe from the area where the redistribution layer 210 is not located to the area where the redistribution layer 210 is located, and is also beneficial for the test probe to enter the opening, that is, to reduce contact with the side wall, which is beneficial to improve the problem of test probe contamination or even test probe damage. In other embodiments, one of the cross-sectional shape of the first groove or the cross-sectional shape of the second groove is a trapezoid.

[0046] In some embodiments, the central axis of the first groove 230 coincides with the central axis of the second groove 240 and the central axis of the pad 201; in the direction from the first groove 230 to the second groove 240, the depth of the first groove 230 is equal to the depth of the second groove 240, such as Figure 2 or Figure 3As shown, along the arrangement direction of the pads 201, the width of the first groove 230 is d1=d0+2*h / tan(a)+2x, where d0 is the width of the mask opening for etching to form the second groove, i.e., the width of the bottom of the second groove 240, h is the depth of the second groove 240, a is the minimum angle formed by the inner wall surface of the second groove 240 and the bottom of the second groove 240, and x is the width of the step formed between the first groove 230 and the second groove 240. It can be understood that due to isotropic etching, the sidewalls of the first groove 230 and the sidewalls of the second groove 240 are also etched, thereby forming a trapezoid, therefore, d0 corresponds to the minimum width of the second groove 240, and d1 corresponds to the minimum width of the first groove 230, i.e., the actual width of the first groove 230 can be greater than or equal to d1. For example, the width d0 of the bottom of the second groove 240 is 3um, the depth h of the second groove 240 is 4um, the width x of the step formed between the first groove 230 and the second groove 240 is 1um, and the minimum angle a formed by the inner wall surface of the second groove 240 and the bottom of the second groove 240 is 45°, then the first groove d1=3+2*4 / tan(45°)+2*1=13(um).

[0047] In other embodiments, in the direction in which the first groove 230 points to the second groove 240, the depth of the first groove 230 is greater than the depth of the second groove 240, the area of ​​the first groove 230 can be a test area for WAT test, and the area outside the first groove 230 can be an isolation area for WAT test, and the height difference between the surface of the substrate 200 at the bottom of the first groove 230 and the surface of the substrate 200 at the bottom of the second groove 240 is small, and the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201 will be reduced, which can lessen the impact on the movement trajectory of the test probe from the isolation area to the test area, so that it is easier for the test probe to enter the redistribution layer 210 connected to the pad 201; the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201 is reduced, and the height of the redistribution layer 210 is also reduced, which can improve the problem of test probe contamination or even test probe damage.

[0048] In some embodiments, the semiconductor structure includes: at least two first grooves 230 arranged in a direction perpendicular to the surface of the substrate 200; and along the arrangement direction of the first grooves 230 pointing to the second grooves 230, the orthographic projection of any first groove 230 on the substrate 200 is located within the orthographic projection of the first groove 230 adjacent to and away from the second groove 240 on the substrate 200, and at least one first step is formed between adjacent first grooves 230, so that more redistribution layers 210 can be accommodated in the first grooves 230, reducing the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201, making it easier for the test probe to enter the redistribution layer 210 connected to the pad 201, and the height of the redistribution layer 210 is reduced, and the movement path of the test probe sliding over the side wall and contacting the bottom is also reduced, which can improve the problem of test probe contamination or even test probe damage.

[0049] In some embodiments, the redistribution layer 210 is located on the top surface and sidewalls of the second passivation layer 204 and the sidewalls of the dielectric layer 203 and the first passivation layer 202, and the bottom of the redistribution layer 210 is connected to the pad 201; the thickness of the redistribution layer 210 located at the bottom of the second groove 240 is greater than 1um, and the thickness range of the redistribution layer 210 can not only ensure that the cross-sectional area of ​​the redistribution layer 210 is large, but also reduce the square resistance of the redistribution layer 210, which is beneficial to reduce the total output loss of the semiconductor structure. The thickness range of the redistribution layer 210 can ensure that the redistribution layer 210 is sufficient to withstand the stress generated by the test equipment detecting the redistribution layer in the post-packaging test process, or the stress generated in the bonding process of the re-formed pad and the packaging substrate or the pad and the pad in the chip packaging process, which is beneficial to avoid stress damage to the semiconductor structure. In other embodiments, the depth of the second groove 240 is less than or equal to 1um, the redistribution layer 210 is located on the inner wall and bottom of the first groove 230, and the redistribution layer 210 fills the second groove 240, so that the thickness of the redistribution layer 210 located at the bottom of the first groove 230 and the second groove 240 is greater than 1um.

[0050] In some embodiments, the material of the redistribution layer 210 may be any one or more of aluminum, titanium or titanium nitride. Aluminum, titanium or titanium nitride has low hardness and is easy to handle in subsequent packaging. Compared with using gold as the redistribution layer 210, it saves cost.

[0051] In some embodiments, in a direction perpendicular to the surface of the substrate 200, the cross-sectional shape of the opening 211 surrounded by the redistribution layer 210 is a trapezoid, that is, the inner wall surface of the opening 211 is a slope, and the extension direction of the slope can guide the test probe, thereby facilitating the test probe to enter the opening 211 to perform WAT testing on the pad 201, which is beneficial to improving the problem that the test probe cannot accurately align with the pad, and is beneficial to improving the accuracy of the test data.

[0052] In some embodiments, along the extension direction of the pad 201, the ratio of the width of the top of the opening 211 to the width of the pad 201 is in the range of 1.5 to 1. The width range of the opening 211 of the redistribution layer 210 can make the area at the top of the opening 211 larger, that is, the area above the pad 201 is larger, and the test probe can be more accurately aligned with the pad, which is beneficial to improve the accuracy of the test data; the larger area above the pad 201 is also beneficial for the test probe to enter the opening 211, that is, reduce contact with the side wall of the substrate 200, which is beneficial to improve the problem of test probe contamination or even test probe damage. The width range of the opening 211 of the redistribution layer 210 can also prevent the width of the top of the opening 211 from being too large, resulting in the conduction of the redistribution layer 210 in the adjacent test area, and the inability to achieve electrical isolation, thereby affecting the test accuracy of the adjacent test area.

[0053] In some embodiments, reference Figure 3 The semiconductor structure located in the chip area also includes: an oxide layer 220, which is located on the surface and side of the redistribution layer 210 away from the substrate 200, and is also located on the surface of the substrate 200 between adjacent redistribution layers 210; a polymer layer 250, which fills the opening 211 and is located on the oxide layer 220, and the polymer 250 has a first opening 251 that penetrates the thickness of the polymer 250, and the bottom of the first opening 251 exposes the redistribution layer 210, and the position is different from that of the opening 211.

[0054] The oxide layer 220 is an insulating material, and is used to isolate the alternately arranged redistribution layers 210. Specifically, in some embodiments, the material of the oxide layer 220 is silicon oxide. In other embodiments, the material of the oxide layer may also be silicon nitride or silicon carbide.

[0055] The polymer layer 250 is used to form a re-layout pad to meet the requirements of the new pad for the solder ball spacing; the polymer layer 250 can be used as a stress buffer medium in the packaging process. The material of the polymer layer 250 can be biphenyl cycloethylene (BCB) or polyimide (PI). The polymer layer 250 can be a single layer or a stacked structure. For example, the polymer layer 250 can include a stacked first polymer layer and a second polymer layer. The first polymer layer strengthens the passivation layer of the semiconductor structure (which can be the first passivation layer, the dielectric layer, and the second passivation layer in the substrate) and plays a role in stress buffering; the second polymer layer is used to flatten the surface of the semiconductor structure and protect the redistribution layer.

[0056] In the semiconductor structure provided by the embodiment of the present disclosure, the semiconductor structure includes: a first groove 230 and a second groove 240 that are connected to each other, the first groove 230 is located on a side of the second groove 240 away from the pad 201, the pad 201 is exposed at the bottom of the second groove 240, and the orthographic projection of the second groove 240 on the substrate 200 is located within the orthographic projection of the first groove 230 on the substrate 200, that is, in the direction perpendicular to the surface of the substrate 200, the width of the cross-sectional figure of the first groove 230 is greater than the width of the cross-sectional figure of the second groove 240, and a step is formed between the first groove 230 and the second groove 240, and the step can assist the first groove 230 to accommodate more redistribution layers 210, thereby reducing The height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201 can be reduced, which can lessen the impact on the movement trajectory of the test probe from the area without the redistribution layer 210 to the area where the redistribution layer 210 is located, and it is easier for the test probe to enter the opening 211 of the redistribution layer 210 connected to the pad 201; the height difference between the top surface of the redistribution layer 210 and the top surface of the pad 201 is reduced, that is, the height of the redistribution layer 210 on the side wall of the substrate 200 is reduced, which can reduce the contact area between the test probe and the redistribution layer 210 on the side wall, and can avoid the problem of the test probe being contaminated or even damaged due to the difficulty of needle insertion, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0057] Correspondingly, another aspect of the embodiments of the present disclosure further provides a method for preparing a semiconductor structure, and the semiconductor structure provided by the above embodiments can be prepared by using the preparation method.

[0058] Figures 4 to 19 A schematic diagram of the structures corresponding to each step in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0059] refer to Figure 4 and Figure 5 , providing a substrate 200, in which solder pads 201 distributed at intervals are disposed.

[0060] The substrate 200 can be a stacked structure, and the substrate 200 can have electrical devices such as transistors, resistors or capacitors. The pad 201 can be electrically connected to the port of the electrical device through a variety of conductive structures (not shown in the figure) to apply an operating voltage / current to the electrical device and derive a test voltage / current of the electrical device.

[0061] The wafer includes a chip area and a cutting road area. The chip area and the cutting road area have specific circuits composed of various semiconductor devices, such as transistors, resistors, and triodes. The cutting road area is used for subsequent cutting to be divided into individual independent chips. The semiconductor devices in the chip area have the same structure as the semiconductor devices in the cutting road area. The semiconductor devices in the cutting road area can be subjected to WAT testing to simulate and characterize the performance of the semiconductor devices in the chip area, thereby helping to improve the yield of the wafer. Exemplarily, the method for preparing a semiconductor structure provided in an embodiment of the present application can form a semiconductor structure in the cutting road area, including a substrate 200 and a pad 201, wherein various types of semiconductor devices are formed in the substrate 200.

[0062] refer to Figure 4 , providing an initial substrate 209, on the surface of which a plurality of pads 201 distributed at intervals are formed.

[0063] In some embodiments, the initial substrate 209 may be located in the cutting path area, and the pad 201 may be used as a pad for WAT testing. The material of the pad 201 may be aluminum, tungsten, and copper. Aluminum, tungsten, and copper have low resistance, which is beneficial to improving the conductivity of the pad 201, thereby improving the conductivity of the pad 201 and the subsequently formed redistribution layer.

[0064] refer to Figure 5 A first passivation layer 202, a dielectric layer 203 and a second passivation layer 204 are sequentially formed on an initial substrate 209, the first passivation layer 202 covers the surface of the pad 201, and the top surface of the first passivation layer 202 is higher than the top surface of the pad 201, and the initial substrate 209, the first passivation layer 202, the dielectric layer 203 and the second passivation layer 204 together serve as a substrate 200.

[0065] The material of the first passivation layer 202 is an insulating material, which is used to isolate the spaced pads 201. Specifically, in some embodiments, the material of the first passivation layer 202 is silicon oxide. In other embodiments, the material of the first passivation layer 202 may also be silicon nitride or silicon carbide.

[0066] In some embodiments, the material of the dielectric layer 203 is silicon nitride, which is used as an etching stop to prevent subsequent etching from being too deep and affecting the reliability of the semiconductor structure; the material of the second passivation layer 204 can be the same as that of the first passivation layer 202. In other embodiments, the material of the dielectric layer 203 can also be an insulating material such as silicon oxide, silicon carbide, or other high dielectric constant materials. The material of the second passivation layer 204 can be different from that of the first passivation layer 202.

[0067] It should be noted that the embodiment of the present disclosure does not limit the specific film layers of the substrate 200 (such as the initial substrate 209, the first passivation layer 202, the dielectric layer 203 and the second passivation layer 204). For example, the initial substrate 209 may only have a first passivation layer covering the pad 201.

[0068] refer to Figures 6 to 13 , a patterned substrate 200 is formed to form a first groove 230 and a second groove 240 that are connected in the substrate 200, the first groove 230 is formed on the side of the second groove 240 away from the pad 201, the pad 201 is exposed at the bottom of the second groove 240, and the orthographic projection of the second groove 240 on the substrate 200 is located within the orthographic projection of the first groove 230 on the substrate 200.

[0069] The first groove 230 and the second groove 240 serve as a process basis for subsequently forming a redistribution layer. Subsequently, a redistribution layer is formed on the inner wall of the first groove 230 , the inner wall of the second groove 240 and the surface of the exposed pad 201 .

[0070] In some embodiments, the first groove 230 is connected to the second groove 240, and the orthographic projection of the second groove 240 on the substrate 200 is located within the orthographic projection of the first groove 230 on the substrate 200, and a step is formed between the first groove 230 and the second groove 240. The step can help the first groove 230 to accommodate more redistribution layers, reduce the height difference between the top surface of the redistribution layer and the top surface of the pad 201, and can lessen the impact on the movement trajectory of the test probe from the non-redistribution layer area to the area where the redistribution layer is located, so that it is easier for the test probe to enter the redistribution layer connected to the pad 201. The height difference between the top surface of the redistribution layer and the top surface of the pad 201 is reduced, and the height of the redistribution layer is also reduced. The movement path of the test probe in contact with the side wall and the bottom is also reduced, which can improve the problem of test probe contamination or even test probe damage.

[0071] In some embodiments, the central axis of the first groove 230 coincides with the central axis of the second groove 240 and the central axis of the pad 201; in the direction from the first groove 230 to the second groove 240, the depth of the first groove 230 is equal to the depth of the second groove 240, such as Fig. 9 or Fig.13 As shown, the width of the first groove 230 is d1=d0+2*h / tan(a)+2x, where d0 is the width of the first opening 206 of the first mask layer 205 (refer to Figure 6 ) or the width of the third opening 226 of the third mask layer 225 (reference Fig.10) is the width of the bottom of the second groove 240, h is the depth of the second groove 240, a is the minimum angle formed by the inner wall surface of the second groove 240 and the bottom of the second groove 240, and x is the width of the step formed between the first groove 230 and the second groove 240. It can be understood that due to the isotropic etching, the sidewalls of the first groove 230 and the sidewalls of the second groove 240 are also etched, thereby forming a trapezoid. Therefore, d0 corresponds to the minimum width of the second groove 240, and d1 corresponds to the minimum width of the first groove 230, that is, the actual width of the first groove 230 can be greater than or equal to d1.

[0072] In some embodiments, reference Figures 6 to 9 The process steps of forming the first groove 230 and the second groove 240 include: patterning the substrate 200 to form the first groove 230; etching the exposed portion of the substrate 200 at the bottom of the first groove 230 to form the second groove 240.

[0073] The steps of forming the first groove 230 and the second groove 240 will be described in detail below with reference to the accompanying drawings.

[0074] refer to Figure 6 , a first mask layer 205 is formed on the top surface of the substrate 200 .

[0075] In some embodiments, a first mask layer 205 is formed on the top surface of the second passivation layer 204, and the first mask layer 205 has a first opening 206 penetrating the first mask layer 205; the first mask layer 205 can be a photoresist or a hard mask layer; the material of the hard mask layer can be silicon nitride, titanium nitride or silicon oxide.

[0076] refer to Figure 7 , with the first mask layer 205 (reference Figure 6 ) is used as a mask, and the substrate 200 is etched to form a first groove 230.

[0077] In some embodiments, the first mask layer 205 is used as a mask to etch a portion of the second passivation layer 204 along the sidewall of the first opening 206 to form a first groove 230 ; and the first mask layer 205 is removed.

[0078] In some other embodiments, the first groove is formed by etching the second passivation layer and a portion of the dielectric layer. In some further embodiments, the first groove is formed by etching the second passivation layer, the dielectric layer, and a portion of the first passivation layer.

[0079] refer to Figure 8 , a second mask layer 215 is formed on the top surface of the substrate 200 .

[0080] The second mask layer 215 has a second opening 216 penetrating the second mask layer 215. The second opening 216 is used to define the position of a second groove to be formed subsequently. The second opening 216 is located in the first groove 230 (refer to Figure 7 ), and the orthographic projection of the second opening 216 on the surface of the substrate 200 is located within the orthographic projection of the first groove 230 on the surface of the substrate 200.

[0081] In order to improve the position accuracy of the second opening 216 in the second mask layer 215, before forming the second mask layer 215, it can also include: forming a first filling layer 207 in the first groove 230, the first filling layer 207 fills the first groove 230 and is also located on the surface of the substrate 200. In this way, the first filling layer 207 provides a relatively flat interface contact for forming the second mask layer 215, and there is no need to form the second mask layer 215 in the first groove 230, so that the thickness of the second mask layer 215 is relatively thin, which is conducive to saving process costs. In some embodiments, the material of the second mask layer 215 can be a hard mask material or a photoresist material. The first filling layer 207 can be a bottom anti-reflective coating (Bottom Anti-Reflective Coating, BARC). It can be understood that in other embodiments, the second mask layer 215 can also be directly formed on the surface of the substrate 200.

[0082] refer to Fig. 9 , with the second mask layer 215 (reference Figure 8 ) is used as a mask, and the substrate 200 is etched to form a second groove 240.

[0083] In some embodiments, the second mask layer 215 is used as a mask to etch the filling layer 207 , the first passivation layer 202 , the dielectric layer 203 and the second passivation layer 204 along the sidewall of the second opening 216 to form a second groove 240 ; the second mask layer 215 and the first filling layer 207 are removed.

[0084] In some embodiments, reference Figures 6 to 9 The size of the first opening 206 is consistent with the size of the second opening 216, that is, the first mask layer 205 and the second mask layer 215 can be the same. When the substrate 200 is etched for the second time, due to the isotropy of the etching, the side wall of the first groove 230 will be etched, and the width of the first groove 230 finally formed is greater than the width of the second groove 240.

[0085] It should be noted that the above is an example of first forming the first groove 230 and then forming the second groove 240. In the embodiment of the present disclosure, the second groove 240 can also be formed first and then the first groove 230. Figures 10 to 13 To explain in detail:

[0086] refer to Figures 10 to 13 The process steps for forming the first groove 230 and the second groove 240 include: patterning the substrate 200 to form the first groove 260, and exposing the pad 201 at the bottom of the first groove 260; etching the substrate 200 with a partial thickness located outside the first groove 260, increasing the size of a portion of the first groove 260 to form the first groove 230, and the remaining first groove 260 serves as the second groove 240.

[0087] refer to Fig.10 , a third mask layer 225 is formed on the top surface of the substrate 200 .

[0088] In some embodiments, a third mask layer 225 is formed on the top surface of the second passivation layer 204, and the third mask layer 225 has a third opening 226 penetrating the third mask layer 225. The third mask layer 225 may be a photoresist or a hard mask layer; the material of the hard mask layer may be silicon nitride, titanium nitride or silicon oxide.

[0089] refer to Fig.11 , with the third mask layer 225 (reference Fig.10 ) is used as a mask, and the substrate 200 is etched to form a first trench 260.

[0090] In some embodiments, the third mask layer 225 is used as a mask to etch the second passivation layer 204 , the dielectric layer 203 and a portion of the first passivation layer 202 along the sidewall of the third opening 226 to form a first trench 260 ; and the third mask layer 225 is removed.

[0091] refer to Fig.12 , a fourth mask layer 235 is formed on the top surface of the substrate 200 .

[0092] In some embodiments, the fourth mask layer 235 has a fourth opening 236 penetrating the fourth mask layer 235. The fourth opening 236 is used to define the position of the first recess to be formed subsequently. The fourth opening 236 is located in the first groove 260 (refer to Fig.11 ), and the orthographic projection of the first groove 260 on the surface of the substrate 200 is located within the orthographic projection of the fourth opening 236 on the surface of the substrate 200.

[0093] In order to improve the position accuracy of the fourth opening 236 in the fourth mask layer 235, before forming the fourth mask layer 235, the process may further include: forming a second filling layer 217 in the first groove 260, the second filling layer 217 completely filling the first groove 260 and being located on the surface of the substrate 200. In this way, the second filling layer 217 provides a relatively flat interface contact for forming the fourth mask layer 235, and there is no need to form the fourth mask layer 235 in the first groove 260, so that the thickness of the fourth mask layer 235 is relatively thin, which is conducive to saving process costs.

[0094] In some embodiments, the material of the fourth mask layer 235 may be a hard mask material or a photoresist material. The second filling layer 217 may be a bottom anti-reflection layer.

[0095] It is understandable that, in other embodiments, the fourth mask layer 235 may also be directly formed on the surface of the substrate 200 .

[0096] refer to Fig.13 , with the fourth mask layer 235 (reference Fig.12 ) is used as a mask to etch a portion of the thickness of the substrate 200 located at the periphery of the first trench 260 to form a first recess 230.

[0097] In some embodiments, the fourth mask layer 235 is used as a mask to etch a portion of the first passivation layer 202 along the sidewall of the fourth opening 236 to form a first groove 230, and the remaining first groove 260 serves as the second groove 240; the fourth mask layer 235 and the second filling layer 217 are removed.

[0098] In some embodiments, reference Figures 10 to 13 The size of the third opening 226 is consistent with the size of the fourth opening 236, that is, the third mask layer 225 and the fourth mask layer 235 can be the same. When the substrate 200 is etched for the second time, due to the isotropy of the etching, the side wall of the first groove 260 will be etched, and the width of the first groove 230 finally formed is greater than the width of the second groove 240.

[0099] In some other embodiments, the method for preparing a semiconductor structure may further include: repeating Figure 6 and Figure 7 or Fig.12 and Fig.13 The steps form a plurality of interconnected first grooves 230, and along the arrangement direction of the first grooves 230 pointing to the second grooves 230, the orthographic projection of any first groove 230 on the substrate 200 is located within the orthographic projection of the first groove 230 adjacent to and away from the second groove 240 on the substrate 200.

[0100] refer to Figures 14 to 16 , a redistribution layer 210 is formed. The redistribution layer 210 is formed on the surface of the pad 201 and is also formed on the inner wall of the first groove 230 and the inner wall and bottom of the second groove 240 .

[0101] In some embodiments, the thickness of the redistribution layer 210 formed at the bottom of the second groove 240 is greater than 1um. The thickness range of the redistribution layer 210 can ensure that the cross-sectional area of ​​the redistribution layer 210 is large, reduce the square resistance of the redistribution layer 210, and help reduce the total output loss of the semiconductor structure. The thickness range of the redistribution layer 210 can also ensure that the redistribution layer 210 is sufficient to withstand the stress generated by the test equipment detecting the redistribution layer 210 in the post-packaging test process, or the stress generated in the bonding process between the pad and the packaging substrate or between the pads in the chip packaging process, which helps to avoid stress damage to the semiconductor structure. In other embodiments, the depth of the second groove 240 is less than or equal to 1um, and the redistribution layer 210 can also be formed on the inner wall and bottom of the first groove 230, and the redistribution layer 210 fills the second groove 240, so that the thickness of the redistribution layer 210 formed at the bottom of the first groove 230 and the second groove 240 is greater than 1um.

[0102] The process steps of forming the redistribution layer 210 will be described in detail below with reference to the accompanying drawings.

[0103] refer to Fig.14 , forming a continuous conductive film 208 , the conductive film 208 is located on the inner wall of the first groove 230 , the inner wall and bottom of the second groove 240 , and the top surface of the substrate 200 .

[0104] A continuous conductive film 208 is formed by a vapor deposition process. The conductive film 208 is located on the top surface and side walls of the second passivation layer 204, and the side walls of the dielectric layer 203 and the first passivation layer 202. The bottom of the conductive film 208 is connected to the pad 201. The material of the conductive film 208 can be any one or more of aluminum, titanium or titanium nitride.

[0105] refer to Fig.15 , forming an alternately arranged fifth mask layer 245, the fifth mask layer 245 is located on the top surface of the conductive film 208 away from the second passivation layer 204, and a portion of the top surface of the conductive film 208 is exposed between adjacent fifth mask layers 245; the material of the fifth mask layer 245 can be the same as that of the first mask layer 205.

[0106] refer to Fig.16 , the conductive film 208 located on the top surface of the substrate 200 is etched, and the remaining conductive film 208 serves as a redistribution layer 210 .

[0107] Using the fifth mask layer 235 as a mask, the conductive film 208 in a partial area is etched until the top surface of the second passivation layer 204 is exposed to form a redistribution layer 210 arranged at intervals; and the fifth mask layer 235 is removed.

[0108] The method for preparing the semiconductor structure provided in the embodiment of the present application can also prepare the semiconductor structure of the chip area, and the method for forming the first groove, the second groove and the redistribution layer is the same as the above embodiment ( Figures 4 to 16 ) is the same or similar to the preparation method of the semiconductor structure provided, and will not be described in detail here.

[0109] It can be understood that the structure of the fifth mask layer 245 located in the chip area (eg Fig.17 ) and the structure of the fifth mask layer 245 located in the cutting street area (such as Fig.14 ) is different, that is, the redistribution layer 210 (such as Fig.18 ) structure and the redistribution layer 210 (such as Fig.16 ) is also different. Fig.18 , the redistribution layer 210 in the semiconductor structure of the chip region is also located on the surface of the substrate 200 .

[0110] refer to Fig.19 , an oxide layer 220 is formed. The oxide layer 220 is located on the surface and side of the redistribution layer 210 away from the substrate 200.

[0111] The oxide layer 220 may also be located on the surface of the substrate 200 between adjacent redistribution layers 210. The oxide layer 220 is an insulating material and is used to isolate the spaced redistribution layers 210. Specifically, in some embodiments, the material of the oxide layer 220 is silicon oxide. In other embodiments, the material of the oxide layer may also be silicon nitride or silicon carbide.

[0112] Continue to refer Fig.19 , forming a polymer layer 250, the polymer layer 250 fills the opening 211 and is located on the oxide layer 220, the polymer 250 has a first opening 251 that penetrates the thickness of the polymer 250 and the thickness of the oxide layer 220, the bottom of the first opening 251 exposes the redistribution layer 210, and the position is different from that of the opening 211.

[0113] The polymer layer 250 is used to form a re-layout pad to meet the requirements of the new pad for the solder ball spacing; the polymer layer 250 can be used as a stress buffer medium in the packaging process. The material of the polymer layer 250 can be biphenyl cycloethylene (BCB) or polyimide (PI). The polymer layer 250 can be a single layer or a stacked structure. For example, the polymer layer 250 can include a stacked first polymer layer and a second polymer layer. The first polymer layer strengthens the passivation layer of the semiconductor structure (which can be the first passivation layer, the dielectric layer, and the second passivation layer in the substrate) and plays a role in stress buffering; the second polymer layer is used to flatten the surface of the semiconductor structure and protect the redistribution layer 210.

[0114] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein solder pads are arranged at intervals; A first groove and a second groove are connected, the first groove and the second groove are located in the substrate, the first groove is located on a side of the second groove away from the pad, the pad is exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate; a redistribution layer, the redistribution layer being located on the surface of the pad and also being located on the inner wall of the first groove and the inner wall and bottom of the second groove; Wherein, the redistribution layer is used for testing.

2. The semiconductor structure according to claim 1, characterized in that: In a cross section perpendicular to the surface direction of the substrate, the cross-sectional shape of the first groove and / or the cross-sectional shape of the second groove is one of the shapes of circle, square, rectangle, trapezoid and the like.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The central axis of the first groove coincides with the central axis of the second groove and the central axis of the pad.

4. The semiconductor structure according to claim 1 or 2, characterized in that: In a direction from the first groove to the second groove, a depth of the first groove is greater than or equal to a depth of the second groove.

5. The semiconductor structure according to claim 4, characterized in that: The depth of the first groove is equal to the depth of the second groove. Along the arrangement direction of the pad, the width of the first groove is d1=d0+2*h / tan(a)+2x, wherein d0 is the minimum width of the second groove, h is the depth of the second groove, a is the minimum angle formed by the inner wall surface of the second groove and the bottom of the second groove, and x is the width of the step formed between the first groove and the second groove.

6. The semiconductor structure according to claim 1, characterized in that include: At least two of the first grooves are arranged in a direction perpendicular to the surface of the substrate; and along the arrangement direction of the first grooves pointing to the second grooves, the orthographic projection of any of the first grooves on the substrate is located within the orthographic projection of the first groove on the substrate that is adjacent and far away from the second groove.

7. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the surface of the substrate, a cross-sectional shape of the opening surrounded by the redistribution layer is a trapezoid.

8. The semiconductor structure according to claim 7, characterized in that: Along the arrangement direction of the pads, the ratio of the width of the top of the opening to the width of the pads is in the range of 1.5 to 1.

9. The semiconductor structure according to claim 1, characterized in that: The thickness of the redistribution layer located at the bottom of the second groove is greater than 1 um.

10. The semiconductor structure according to claim 1, wherein: The material of the redistribution layer is aluminum, titanium or titanium nitride.

11. The semiconductor structure according to claim 1, characterized in that: The substrate comprises an initial substrate, a first passivation layer, a dielectric layer and a second passivation layer stacked in sequence, the pad is located on the initial substrate, the first passivation layer covers the pad surface, and the top surface of the first passivation layer is higher than the top surface of the pad.

12. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein solder pads distributed at intervals are formed in the substrate; Patterning the substrate to form a first groove and a second groove connected to each other in the substrate, wherein the first groove is formed on a side of the second groove away from the pad, the pad is exposed at the bottom of the second groove, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate; forming a redistribution layer, wherein the redistribution layer is formed on the surface of the pad and is also formed on the inner wall of the first groove and the inner wall and bottom of the second groove; Wherein, the redistribution layer is used for testing.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The process steps of forming the first groove and the second groove connected to each other include: Patterning the substrate to form the first groove; The exposed portion of the substrate at the bottom of the first groove is etched to form the second groove.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: Before forming the first groove, a first mask layer is formed on the top surface of the substrate, and the substrate is etched using the first mask layer as a mask to form the first groove; before forming the second groove, a second mask layer is formed on the top surface of the substrate, and the substrate is etched using the second mask layer as a mask to form the second groove.

15. The method for preparing a semiconductor structure according to claim 12, characterized in that: The process steps of forming the first groove and the second groove connected to each other include: Patterning the substrate to form a first groove, wherein the pad is exposed at the bottom of the first groove; A portion of the substrate thickness located at the periphery of the first groove is etched to increase the size of a portion of the first groove to form the first recess, and the remaining first groove serves as the second recess.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that: Before forming the first groove, forming a third mask layer on the top surface of the substrate; using the third mask layer as a mask, etching the substrate to form the first groove; Before forming the first groove, forming a fourth mask layer on the top surface of the substrate; Using the fourth mask layer as a mask, a portion of the thickness of the substrate located at the periphery of the first trench is etched to form the first recess.

17. The method for preparing a semiconductor structure according to claim 12, characterized in that: The process steps of forming the redistribution layer include: forming a continuous conductive film, wherein the conductive film is located on the inner wall of the first groove, the inner wall and the bottom of the second groove, and the top surface of the substrate; The conductive film on the top surface of the substrate is etched, and the remaining conductive film serves as the redistribution layer.

18. The method for preparing a semiconductor structure according to claim 12, characterized in that: The process step of providing a substrate comprises: Providing an initial substrate, wherein a plurality of pads distributed at intervals are formed on the surface of the initial substrate; A first passivation layer, a dielectric layer and a second passivation layer are stacked in sequence on the initial substrate, the first passivation layer covers the surface of the pad, and the top surface of the first passivation layer is higher than the top surface of the pad, and the initial substrate, the first passivation layer, the dielectric layer and the second passivation layer together serve as the substrate.

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