Optical sensor and method of forming the same, and electronic device

Abstract

An optoelectronic sensor and a method of forming the same, and an electronic device, the optoelectronic sensor comprising: a first opening through a dielectric layer over a pixel substrate and an interconnect layer of a lead region; a first pad layer at a bottom of the first opening and in contact with the interconnect layer; a passivation layer filling the first opening and on a first surface, covering the first pad layer and a conductive layer; a second opening in the passivation layer and exposing the first surface of the pixel substrate and a top surface of an isolation structure, the second opening being in a grid pattern; a metal layer filling the second opening and in contact with the conductive layer; and a second pad layer on the passivation layer of the first surface and connected to the metal layer. By applying a negative potential to the second pad layer, the conductive layer of the isolation structure is connected to the negative potential through the metal layer, which is conducive to adsorbing positive charges on the sidewall of the isolation structure, thereby improving the interface state of the sidewall of the isolation structure and reducing the dark current of the pixel unit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a photoelectric sensor and a method for forming the same, as well as an electronic device. Background Technology

[0002] A photoelectric sensor is a device that converts light signals into electrical signals. Its working principle is based on the photoelectric effect, which refers to the phenomenon where electrons in a substance absorb the energy of photons and produce corresponding electrical effects when light shines on them.

[0003] For example, CCD (Charge Coupled Device) image sensors and CMOS image sensors, widely used in digital cameras and other electro-optical devices, both utilize photoelectric conversion to convert optical images into electrical signals and output digital images. ToF (Time of Flight) distance sensors, such as DTOF (Direct Time of Flight) sensors, record the time between the emission and detection of a light pulse, converting the time difference into distance information. This technology can be used in various ranging scenarios, including autonomous driving, robotic vacuum cleaners, and VR (Virtual Reality) / AR (Augmented Reality) modeling.

[0004] However, the performance of photoelectric sensors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a photoelectric sensor, a method for forming the same, and an electronic device, thereby improving the performance of the photoelectric sensor.

[0006] To address the aforementioned problems, embodiments of the present invention provide a photoelectric sensor, comprising: a pixel substrate including opposing first and second surfaces, the pixel substrate including a photosensitive region and a lead region surrounding the photosensitive region, the photosensitive region including an array of pixel unit regions; an isolation structure located within the pixel substrate between the pixel unit regions, the isolation structure including a conductive layer, the top surface of the conductive layer exposed on the first surface, the isolation structure located within the photosensitive region; a dielectric layer located on the second surface of the pixel substrate, the dielectric layer being located on a logic substrate; an interconnect layer located within the dielectric layer of the lead region; and a first opening penetrating the pixel substrate and the interconnect region. A dielectric layer above the interconnect layer has a first opening that exposes a portion of the top of the interconnect layer facing the first surface; a first pad layer located at the bottom of the first opening and in contact with the interconnect layer; a passivation layer filling the first opening and located on the first surface, covering the first pad layer and the conductive layer; a second opening located within the passivation layer and exposing the first surface of the pixel substrate and the top surface of the isolation structure, the second opening being in a grid pattern; a metal layer filling the grid-like second opening and in contact with the conductive layer; and a second pad layer located on the passivation layer of the first surface and connected to the metal layer, the second pad layer being located between the isolation structure and the first pad layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a photoelectric sensor, comprising: providing a pixel substrate, including a first surface and a second surface opposite to each other, the pixel substrate including a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area including an array of pixel unit areas, an isolation structure being formed within the pixel substrate between the pixel unit areas, the isolation structure including a conductive layer, the top surface of the conductive layer being exposed on the first surface; a dielectric layer being formed on the second surface, an interconnect layer being formed within the dielectric layer of the lead area; forming a first opening penetrating the pixel substrate above the lead area and the dielectric layer above the interconnect layer, the first opening exposing a portion of the top of the interconnect layer facing the first surface; forming a first pad layer contacting the interconnect layer at the bottom of the first opening; forming a passivation layer filling the first opening and located on the first surface, the passivation layer covering the first pad layer and the conductive layer; forming a metal layer penetrating the passivation layer above the isolation structure and contacting the conductive layer, and a second pad layer located on the passivation layer of the first surface and connected to the metal layer, the metal layer being in a mesh shape.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the photoelectric sensor provided by this embodiment of the invention, a metal layer fills the grid-like second opening and is in contact with the conductive layer; a second pad layer is located on the passivation layer of the first surface and is connected to the metal layer. Accordingly, when the photoelectric sensor is working, it is easy to apply a negative potential to the second pad layer, so that the conductive layer of the isolation structure is connected to a negative potential through the metal layer. This facilitates the adsorption of positive charges on the sidewalls of the isolation structure, thereby improving the interface state of the sidewalls of the isolation structure and reducing the dark current of the pixel unit. In addition, compared with improving the interface state of the sidewalls of the isolation structure by doping the pixel substrate with P-type ions, this embodiment of the invention also helps to avoid the limitation of ion implantation depth. Accordingly, it is easy to increase the light absorption thickness and optical path by increasing the thickness of the pixel substrate, thereby improving the photon detection efficiency of the photosensitive area and improving the photon detection sensitivity performance of the photoelectric sensor. In summary, this embodiment of the invention optimizes the performance of the photoelectric sensor.

[0010] In the photoelectric sensor formation method provided by the embodiments of the present invention, a second pad layer is formed that penetrates the passivation layer above the isolation structure and is in contact with the conductive layer, and a second pad layer is located on the passivation layer of the first surface and is connected to the metal layer. Accordingly, when the photoelectric sensor is working, by applying a negative potential to the second pad layer, the conductive layer of the isolation structure is connected to a negative potential through the metal layer. This is beneficial for adsorbing positive charges on the sidewalls of the isolation structure, thereby improving the interface state of the sidewalls of the isolation structure and reducing the dark current of the pixel unit. In addition, compared with improving the interface state of the sidewalls of the isolation structure by doping the pixel substrate with P-type ions, the embodiments of the present invention are also beneficial for avoiding the limitation of the ion doping depth. Accordingly, it is easier to increase the light absorption thickness and optical path by increasing the thickness of the pixel substrate, thereby improving the photon detection efficiency of the photosensitive area and improving the photon detection sensitivity performance of the photoelectric sensor. In summary, the embodiments of the present invention optimize the performance of the photoelectric sensor. Attached Figure Description

[0011] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a photoelectric sensor;

[0012] Figure 7 and Figure 8 This is a schematic diagram of the structure of an embodiment of the photoelectric sensor of the present invention;

[0013] Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the photoelectric sensor of the present invention. Detailed Implementation

[0014] As the background technology shows, the performance of current photoelectric sensors needs improvement. This paper analyzes the reasons why the performance of photoelectric sensors needs improvement, using a method for forming a photoelectric sensor as an example. Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in the formation method of a photoelectric sensor.

[0015] refer to Figure 1 A pixel substrate 10 is provided, including a first surface 11 and a second surface 12 opposite to each other. The pixel substrate includes a photosensitive region 10P and a lead region 10N surrounding the photosensitive region 10P. The photosensitive region 10P includes an array of pixel unit regions (not shown). An isolation structure 13 is formed in the pixel substrate 10 between the pixel unit regions. The top surface of the isolation structure 13 is exposed on the first surface 11. A dielectric layer 14 is formed on the second surface 12. An interconnect layer 15 is formed in the dielectric layer 14 of the lead region 10N. A logic substrate (not shown) is also bonded on the dielectric layer 14 of the second surface 12.

[0016] refer to Figure 2 An opening 16 is formed in the pixel substrate 10 that extends through the lead area 10N and the dielectric layer 14 above the interconnect layer 15, the opening 16 exposing a portion of the top of the interconnect layer 15 facing the first surface 11.

[0017] refer to Figure 3 A pad layer 17 is formed at the bottom of the opening 16 to contact the interconnect layer 15.

[0018] refer to Figure 4 This forms a filling opening 16 and a passivation layer 18 located on the first surface 11, the passivation layer 18 covering the pad layer 17 and the top surface of the isolation structure 13.

[0019] refer to Figure 5 A mesh-like metal layer 19 is formed on the passivation layer 18 at the top of the isolation structure 13.

[0020] refer to Figure 6 After the metal layer 19 is formed, an interconnect trench 20 is formed that penetrates the passivation layer 18 above the pad layer 17, exposing the pad layer 17.

[0021] In the above-described formation method, the step of forming the isolation structure typically includes: forming an isolation trench within the pixel substrate 10 between adjacent pixel unit regions; and forming an isolation structure within the isolation trench. Typically, an etching process is used to form the isolation trench, and a filling process is used to form the isolation structure within the isolation trench. After the etching and filling processes, some interface states are usually generated on the sidewalls of the isolation structure. The surfaces of these interface states adsorb inverted negatively charged electron layers, and the presence of these interface states increases the dark current of the pixel unit.

[0022] To prevent dark current caused by interface states, p-type ion implantation is typically performed on the pixel substrate before bonding it to the logic substrate. P-type ion implantation neutralizes the negatively charged electron layer of the interface states, thus mitigating the dark current problem caused by these states.

[0023] However, in the field of photoelectric sensors, the absorption thickness and optical path are usually increased by increasing the thickness of the pixel substrate, thereby increasing the photon detection efficiency and thus improving the photon detection sensitivity.

[0024] As the pixel substrate thickness gradually increases, when the thickness exceeds the maximum ion implantation depth, the sidewalls of the isolation structure cannot be completely surrounded by P-type ions. During photoelectric sensor operation, the sidewalls of the isolation structure not surrounded by P-type ions will increase the dark current of the pixel. Furthermore, when the first surface is the back side of the pixel substrate, since the front-end device has already been fabricated during ion implantation, to prevent adverse effects on the electrical performance of the front-end device, even if ion implantation can be performed, the implanted ions cannot undergo a high-temperature activation process. Unactivated ion implantation cannot play its corresponding role.

[0025] To address the technical problem, this invention provides a photoelectric sensor in which a metal layer fills a grid-like second opening and contacts a conductive layer; a second pad layer is located on the passivation layer of the first surface and connected to the metal layer. Accordingly, when the photoelectric sensor is operating, applying a negative potential to the second pad layer allows the conductive layer of the isolation structure to access a negative potential through the metal layer, which facilitates the adsorption of positive charges on the sidewalls of the isolation structure. This improves the interface state of the isolation structure sidewalls and reduces the dark current of the pixel unit. Furthermore, compared to improving the interface state of the isolation structure sidewalls by doping the pixel substrate with P-type ions, this invention also avoids the limitation of ion implantation depth. Consequently, increasing the pixel substrate thickness increases the light absorption thickness and optical path, thereby improving the photon detection efficiency of the photosensitive area and enhancing the photon detection sensitivity of the photoelectric sensor. In summary, this invention optimizes the performance of the photoelectric sensor.

[0026] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 7 and Figure 8 The diagram shows a structural schematic of an embodiment of the photoelectric sensor of the present invention.

[0027] As an example, this embodiment uses a TOF (Time of Flight) sensor as the photoelectric sensor for illustration. More specifically, the photoelectric sensor can be a DTOF (Direct Time of Flight) sensor. In other embodiments, the photoelectric sensor can also be an iTOF (Indirect Time of Flight) sensor.

[0028] In other embodiments, the photoelectric sensor may also be other types of photoelectric sensors such as CCD (Charge Coupled Device) image sensors and CMOS image sensors.

[0029] like Figure 7 and Figure 8 As shown, in this embodiment, the photoelectric sensor includes: a pixel substrate 100, including a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 including a photosensitive area 100P and a lead area 100N surrounding the photosensitive area 100P, the photosensitive area 100P including an array of pixel unit areas (not shown); an isolation structure located within the pixel substrate 100 between the pixel unit areas, the isolation structure including a conductive layer 110, the top surface of the conductive layer 110 exposed on the first surface 101, the isolation structure located within the photosensitive area 100P; a dielectric layer 120 located on the second surface 102 of the pixel substrate 100, the dielectric layer 120 located on a logic substrate; an interconnect layer 130 located within the dielectric layer 120 of the lead area 100N; and a first opening 140 (referring to a reference). Figure 10 The first opening 140 exposes a portion of the top of the interconnect layer 130 facing the first surface 101; a first pad layer 150 is located at the bottom of the first opening 140 and contacts the interconnect layer 130; a passivation layer 160 fills the first opening 140 and is located on the first surface 101, covering the first pad layer 150 and the conductive layer 110; a second opening 170 (refer to reference) Figure 14 The second opening is located within the passivation layer 160 and exposes the first surface 101 of the pixel substrate 100 and the top surface of the isolation structure. The second opening is in the form of a mesh. The metal layer 210 fills the mesh-shaped second opening and is in contact with the conductive layer 110. The second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected to the metal layer 210.

[0030] The pixel substrate 100 provides an operating platform for the formation of a photoelectric sensor. In this embodiment, the pixel substrate 100 includes a substrate. Specifically, the substrate material may include one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0031] In this embodiment, the first surface 101 is the back surface of the pixel substrate 100, and the second surface 102 is the front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a backside illumination (BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is the light-receiving surface.

[0032] The pixel substrate 100 includes a photosensitive area 100P, which is used to receive optical signals and convert them into electrical signals. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed. The pixel units are used to receive optical signals and convert them into electrical signals.

[0033] The lead area 100N is used for wiring and forming leads to achieve electrical connection between pixel units or other device structures and external circuits.

[0034] The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel units. In this embodiment, the isolation structure is a deep trench isolation (DTI) structure. In this embodiment, the isolation structure includes a conductive layer 110 so that a voltage can be applied to the conductive layer 110 to adsorb positive charges on the sidewalls of the isolation structure, thereby improving the interface state of the sidewalls of the isolation structure and reducing the dark current of the pixel unit.

[0035] The end of the conductive layer 110 is exposed on the first surface 101 so that the metal layer 210 can contact the conductive layer 110, thereby allowing the electrical properties of the conductive layer 110 to be conducted through the metal layer 210. In this embodiment, the conductive layer 110 is made of a metallic material. Metallic materials have good electrical conductivity, and since they are typically opaque, they can also act as light-blocking materials between adjacent pixel units.

[0036] In this embodiment, the conductive layer 110 is made of one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride, and copper. As one embodiment, the conductive layer 110 is made of tungsten. Tungsten is not easily diffused and has excellent hole-filling ability, thereby improving the filling effect of the conductive layer 110 in deep trenches. Furthermore, tungsten is an opaque metal material, which can act as a light barrier, making the reduction effect of the isolation structure 110 on optical crosstalk between adjacent pixel units more significant.

[0037] In this embodiment, the isolation structure further includes an insulating layer (not shown) located between the conductive layer 110 and the pixel substrate 100. The insulating layer is used to achieve insulation between the conductive layer 110 and the pixel substrate 100. In this embodiment, the material of the insulating layer includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0038] In this embodiment, an insulating layer is also formed on the first surface 101 of the conductive layer 110. In this embodiment, the insulating layer includes a negatively charged dielectric layer (not shown). The negatively charged dielectric layer has a more comprehensive negative charge than a conventional dielectric layer. The negative charge can increase the accumulation of holes at the interface of the negatively charged dielectric layer, and correspondingly, holes can accumulate at the bottom and sidewalls of the isolation structure to form a P-type protective structure, which is beneficial to improving the leakage problem of the sidewalls of the isolation structure.

[0039] More specifically, the material of the negatively charged dielectric layer includes high-k dielectric materials. As one embodiment, the high-k dielectric material includes any one or more of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0040] Pixel interconnects are formed within the dielectric layer 120, which is used to achieve isolation between the pixel interconnects. The material of the dielectric layer 120 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0041] Pixel interconnects are used to establish electrical connections between pixel units and external circuitry or other interconnect structures. Specifically, pixel interconnects comprise one or more layers of interconnects.

[0042] In this embodiment, the pixel interconnect includes an interconnect layer 130 located within the dielectric layer 120 of the lead region 100N. The interconnect layer 130 is used to realize circuit connections between pixel units and electrical connections between pixel units and subsequent first bonding pad layers, thereby realizing electrical connections between pixel units and external circuits. The material of the interconnect layer 130 is a metal, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0043] In this embodiment, the photoelectric sensor further includes a logic substrate 200, bonded to the dielectric layer 120 of the second surface 102 of the pixel substrate 100. The logic substrate 200 serves as a logic wafer, used to analyze and process the electrical signals provided by the pixel substrate 100. Specifically, logic devices are formed within the logic substrate 200, and these logic devices are used to analyze and process the electrical signals provided by the pixel substrate 100.

[0044] By setting the pixel area (i.e., the photosensitive area) and the logic area on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, it is beneficial to increase the pixel area, shorten the path of light to the photoelectric element, reduce light scattering, and make the light more focused, thereby improving the photoelectric sensor's light-sensing ability in low-light environments and reducing system noise and crosstalk.

[0045] As one embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by hybrid bonding.

[0046] The bottom of the first opening 140 is used to provide space for forming the first pad layer 150, and the first opening 140 exposes a portion of the top of the interconnect layer 130 so that the first pad layer 150 can contact the interconnect layer 130, thereby achieving an electrical connection between the first pad layer 150 and the interconnect layer 130.

[0047] The first pad layer 150 is used to contact the interconnect layer 130 to achieve electrical connection between the interconnect layer 130 and external circuits or other interconnect structures. The material of the first pad layer 150 is a conductive material. In this embodiment, the material of the first pad layer 150 includes one or more of aluminum, titanium, gold, and indium tin oxide. As an embodiment, the material of the first pad layer 150 is aluminum. Aluminum has good electrical conductivity and is an easily etchable material, thus making it easy to form the first pad layer 150 in a patterned manner.

[0048] The first solder pad 150 is located inside the first opening 140, and the top surface of the first solder pad 150 is lower than the first surface 101.

[0049] The passivation layer 160 is used to fill the first opening 140 to provide a flat surface for the process. The first passivation layer 160 also serves to protect the first pad layer 150. In this embodiment, the material of the passivation layer 160 is an insulating material, including one or more of silicon oxide, silicon oxynitride, and silicon nitride. As one embodiment, the material of the passivation layer 160 is silicon oxide.

[0050] The second opening 170 provides space for the formation of the metal layer 210 and exposes the top surface of the conductive layer 110 so that the metal layer 210 can contact the conductive layer 110.

[0051] The metal layer 210 corresponds to the position and shape of the isolation structure, and the area enclosed by the metal layer 210 corresponds to each pixel unit area, thereby preventing optical crosstalk between adjacent pixel units.

[0052] Specifically, the metal layer 210 fills the grid-like second opening 170, the metal layer 210 is a grid-like structure, and the metal layer 210 is located on the first surface 101 of the pixel substrate 100, that is, the metal layer 210 is located on the back side of the pixel substrate 100, and the metal layer 210 is a back metal layer.

[0053] The metal layer 210 penetrates the passivation layer 160 above the isolation structure and is in contact with the conductive layer 110, thereby enabling the electrical connection between the conductive layer 110 and the second pad layer 220.

[0054] In this embodiment, the metal layer 210 is in contact with a portion of the top surface of the conductive layer 110, or the metal layer 210 is in contact with the top surface of all the conductive layers 110. Since the conductive layers 110 in each isolation structure are interconnected, even if the metal layer 210 only contacts the top surface of a portion of the conductive layers 110, electrical connection between all the conductive layers 110 and the external circuit can be achieved through the metal layer 210.

[0055] In this embodiment, the material of the metal layer 210 is a metallic material, including one or both of aluminum and tungsten. As an example, the material of the metal layer 210 is aluminum. Aluminum is an easily etchable material, which facilitates the patterning process for forming the metal layer 210. Furthermore, aluminum has good electrical conductivity, which helps improve the electrical connectivity of the metal layer 210. In addition, aluminum is an opaque material, thus ensuring that the metal layer 210 reduces optical crosstalk between adjacent pixel units.

[0056] The second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected to the metal layer 210. It is used to realize the electrical connection between the metal layer 210 and the external circuit. So when the photoelectric sensor is working, by applying a negative potential to the second pad layer 220, the conductive layer 110 of the isolation structure can be connected to a negative potential through the metal layer 210. This is beneficial to adsorb positive charges on the sidewall of the isolation structure, thereby improving the interface state of the sidewall of the isolation structure and reducing the dark current of the pixel unit.

[0057] Furthermore, compared to improving the interface states of the isolation structure sidewalls by doping the pixel substrate with P-type ions, this embodiment also helps to avoid being limited by the depth of ion doping. Accordingly, it is easier to increase the light absorption thickness and optical path by increasing the thickness of the pixel substrate by 100, thereby improving the photon detection efficiency of the photosensitive area and improving the photon detection sensitivity performance of the photoelectric sensor.

[0058] In summary, this embodiment optimizes the performance of the photoelectric sensor.

[0059] In this embodiment, the material of the second solder pad layer 220 is a metallic material. As one embodiment, the material of the second solder pad layer 220 includes one or more of aluminum, titanium, gold, and indium tin-doped oxide. In this embodiment, the material of the second solder pad layer 220 is the same as the material of the metal layer 210.

[0060] More specifically, in this embodiment, the second solder pad layer 220 and the metal layer 210 are an integral structure because the second solder pad layer 220 and the metal layer 210 are formed in the same step, which not only simplifies the process flow, but also improves the electrical connection performance between the second solder pad layer 220 and the metal layer 210.

[0061] In this embodiment, the photoelectric sensor further includes a ground wire 230 that penetrates a portion of the passivation layer 160 and is in contact with the pixel substrate 100. The ground wire 230 is spaced from the metal layer 210 and the second bonding pad layer 220. In this embodiment, the ground wire 230 also penetrates a portion of the thickness of the pixel substrate 100.

[0062] During the formation of the second pad layer 220 and the metal layer 210, a large amount of charge is usually generated. The ground wire 230 is in contact with the pixel substrate 100 to release the charge through the pixel substrate 100 during the formation of the second pad layer 220 and the metal layer 210, preventing the charge from accumulating on the first surface 101 of the pixel substrate 100, thereby preventing the arcing phenomenon from occurring during the formation of the second pad layer 220 and the metal layer 210.

[0063] In this embodiment, the material of the grounding wire 230 is the same as that of the metal layer 210. Specifically, in this embodiment, the grounding wire 230, the metal layer 210, and the second solder pad layer 220 are formed in the same step, and the top surface of the grounding wire 230 is flush with the top surfaces of the metal layer 210 and the second solder pad layer 220.

[0064] To address this problem, the present invention also provides a method for forming a photoelectric sensor. Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the photoelectric sensor of the present invention.

[0065] As an example, this embodiment uses a TOF (Time of Flight) sensor as the photoelectric sensor for illustration. More specifically, the photoelectric sensor can be a DTOF (Direct Time of Flight) sensor. In other embodiments, the photoelectric sensor can also be an iTOF (Indirect Time of Flight) sensor.

[0066] In other embodiments, the photoelectric sensor may also be other types of photoelectric sensors such as CCD (Charge Coupled Device) image sensors and CMOS image sensors.

[0067] The method for forming the photoelectric sensor in this embodiment will be described in detail below with reference to the accompanying drawings.

[0068] refer to Figure 9 A pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other. The pixel substrate 100 includes a photosensitive area 100P and a lead area 100N surrounding the photosensitive area 100P. The photosensitive area 100P includes an array of pixel unit areas (not shown). An isolation structure is formed in the pixel substrate 100 between the pixel unit areas. The isolation structure includes a conductive layer 110. The top surface of the conductive layer 110 is exposed on the first surface 101. A dielectric layer 120 is formed on the second surface 102. An interconnect layer 130 is formed in the dielectric layer 120 of the lead area 100N.

[0069] The pixel substrate 100 provides an operating platform for subsequent process technology. In this embodiment, the pixel substrate 100 includes a substrate. Specifically, the substrate material may include one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0070] In this embodiment, the first surface 101 is the back surface of the pixel substrate 100, and the second surface 102 is the front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a back-illuminated (BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is the light-receiving surface.

[0071] The pixel substrate 100 includes a photosensitive area 100P, which is used to receive optical signals and convert them into electrical signals. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed. The pixel units are used to receive optical signals and convert them into electrical signals.

[0072] The lead area 100N is used for wiring and forming leads to achieve electrical connection between pixel units or other device structures and external circuits.

[0073] The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel units. In this embodiment, the isolation structure is a deep trench isolation (DTI) structure. In this embodiment, the isolation structure includes a conductive layer 110 so that a voltage can be applied to the conductive layer 110 to adsorb positive charges on the sidewalls of the isolation structure, thereby improving the interface state of the sidewalls of the isolation structure and reducing the dark current of the pixel unit.

[0074] The end of the conductive layer 110 is exposed on the first surface 101 so that a metal layer in contact with the conductive layer 110 can be formed on the first surface 101, thereby bringing out the electrical properties of the conductive layer 110 through the metal layer.

[0075] In this embodiment, the conductive layer 110 is made of a metallic material. Metallic materials have good electrical conductivity, and since they are typically opaque, they can also act as light-blocking agents between adjacent pixel units.

[0076] In this embodiment, the conductive layer 110 is made of one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride, and copper. As one embodiment, the conductive layer 110 is made of tungsten. Tungsten is not easily diffused and has excellent hole-filling ability, thereby improving the filling effect of the conductive layer 110 in deep trenches. Furthermore, tungsten is an opaque metal material, which can act as a light barrier, making the reduction effect of the isolation structure 110 on optical crosstalk between adjacent pixel units more significant.

[0077] In this embodiment, the isolation structure further includes an insulating layer (not shown) located between the conductive layer 110 and the pixel substrate 100. The insulating layer is used to achieve insulation between the conductive layer 110 and the pixel substrate 100. The material of the insulating layer includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0078] In this embodiment, an insulating layer is also formed on the first surface 101 of the conductive layer 110.

[0079] In this embodiment, the insulating layer includes a negatively charged dielectric layer (not shown). This negatively charged dielectric layer has a more comprehensive negative charge than a conventional dielectric layer. This negative charge increases hole accumulation at the interface of the negatively charged dielectric layer, allowing holes to accumulate at the bottom and sidewalls of the isolation structure, forming a P-type protective structure. This helps improve the leakage problem on the sidewalls of the isolation structure. More specifically, the material of the negatively charged dielectric layer includes a high-k dielectric material. As one embodiment, the high-k dielectric material includes any one or more of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0080] In this embodiment, the step of forming the isolation structure includes: forming an isolation trench (not shown) in the pixel substrate 100 between adjacent pixel unit areas; forming an insulating layer on the sidewalls and bottom of the isolation trench, and a conductive layer 110 on the insulating layer and filling the isolation trench.

[0081] Pixel interconnects are formed within the dielectric layer 120, which is used to achieve isolation between the pixel interconnects. The material of the dielectric layer 120 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0082] Pixel interconnects are used to achieve electrical connections between pixel units and external circuits or other interconnect structures. Specifically, a pixel interconnect includes one or more interconnect layers. In this embodiment, the pixel interconnect includes an interconnect layer 130 located within the dielectric layer 120 of the lead region 100N. The interconnect layer 130 is used to achieve circuit connections between pixel units and also to achieve electrical connections between pixel units and subsequent first pad layers, thereby achieving electrical connections between pixel units and external circuits. The material of the interconnect layer 130 is a metal, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0083] In this embodiment, a logic substrate 200 is further bonded to the dielectric layer 120 of the second surface 102 of the pixel substrate 100. The logic substrate 200 serves as a logic wafer and is used to analyze and process the electrical signals provided by the pixel substrate 100. Specifically, logic devices are formed within the logic substrate 200, and these logic devices are used to analyze and process the electrical signals provided by the pixel substrate 100.

[0084] By setting the pixel area and logic area on different substrates and bonding the pixel substrate 100 and logic substrate 200 together, it is beneficial to increase the pixel area, shorten the path of light to the photoelectric element, reduce light scattering, and make the light more focused, thereby improving the photoelectric sensor's light-sensing ability in low-light environments and reducing system noise and crosstalk.

[0085] As one embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by hybrid bonding.

[0086] As an example, the steps of providing a pixel substrate 100 bonded with a logic substrate include: providing a pixel substrate 100; providing a logic substrate 200; implementing a bonding between a dielectric layer 120 of the second surface 102 of the pixel substrate 100 and the logic substrate 200; after implementing the bonding, thinning a first surface 101 of the pixel substrate 100; and after thinning, forming an isolation structure within the pixel substrate 100 between adjacent pixel unit regions.

[0087] refer to Figure 10 A first opening 140 is formed, extending through the pixel substrate 100 of the lead region 100N and the dielectric layer 120 above the interconnect layer 130. The first opening 140 exposes a portion of the top of the interconnect layer 130 facing the first surface 101. The bottom of the first opening 140 provides space for the formation of a first solder pad layer, and the first opening 140 exposes a portion of the top of the interconnect layer 130 so that the first solder pad layer subsequently formed at the bottom of the first opening 140 can contact the interconnect layer 130, thereby achieving an electrical connection between the first solder pad layer and the interconnect layer 130.

[0088] As an embodiment, the step of forming the first opening 140 includes: forming a top opening 141 through the pixel substrate 100 of the lead area 100N, the top opening exposing the dielectric layer 120; forming a bottom opening 142 through the dielectric layer 120 below the top opening 141, exposing a portion of the top of the interconnect layer 130 facing the first surface 101, the bottom opening 142 and the top opening 141 constituting the first opening 140.

[0089] As an example, an anisotropic dry etching process is used to form a top opening 141 in the pixel substrate 100 that penetrates the lead region 100N. The anisotropic dry etching process has high control over the etching profile, which is beneficial for precise control of the profile morphology of the top opening 141.

[0090] As an example, an anisotropic dry etching process is used to form a bottom opening 142 that penetrates the dielectric layer 120 below the top opening 141. The anisotropic dry etching process has high control over the etching profile, which is beneficial for precise control of the profile morphology of the bottom opening 142 and reduces the probability of accidental etching of the interconnect layer 130.

[0091] It should be noted that, in this embodiment, after forming the top opening 141 and before forming the bottom opening 142, the method for forming the photoelectric sensor further includes: forming an isolation layer (not shown) on the sidewall and bottom of the top opening 141 and on the first surface 101, the isolation layer also covering the conductive layer 110.

[0092] The isolation layer serves to protect the pixel substrate 100 and also isolates the pixel substrate 100 from the subsequent first bonding pad layer. In this embodiment, the isolation layer is made of silicon oxide.

[0093] refer to Figure 11 A first solder pad layer 150 is formed at the bottom of the first opening 140, contacting the interconnect layer 130. The first solder pad layer 150 contacts the interconnect layer 130 to provide electrical connection between the interconnect layer 130 and external circuits or other interconnect structures. The first solder pad layer 150 is located within the first opening 140, and the top surface of the first solder pad layer 150 is lower than the first surface 101.

[0094] The first pad layer 150 is made of a conductive material. In this embodiment, the material of the first pad layer 150 includes one or more of aluminum, titanium, gold, and indium tin oxide. As an example, the material of the first pad layer 150 is aluminum. Aluminum has good electrical conductivity and is an easily etchable material, thus making it easy to form the first pad layer 150 in a patterned manner.

[0095] In this embodiment, the step of forming the first pad layer 150 includes: forming a first pad material layer (not shown) on the bottom and sidewall of the first opening 140 and on the first surface 101; removing a portion of the first pad material layer located on the first surface 101 and at the bottom of the first opening 140, and using the remaining first pad material layer at the bottom of the first opening 140 as the first pad layer 150.

[0096] refer to Figure 12 and Figure 13 This forms a filling layer 140 and a passivation layer 160 located on the first surface 101 (e.g., ...). Figure 13 As shown, passivation layer 160 covers first pad layer 150 and conductive layer 110. Passivation layer 160 is used to fill first opening 140 to provide a flat surface for subsequent process steps. Passivation layer 160 also protects first pad layer 150 from the effects of subsequent process steps.

[0097] In this embodiment, the passivation layer 160 is made of an insulating material, including one or more of silicon oxide, silicon oxynitride, and silicon nitride. As one embodiment, the passivation layer 160 is made of silicon oxide.

[0098] In this embodiment, the step of forming the passivation layer 160 includes: as follows Figure 12 As shown, a passivation material layer 155 is formed to fill the first opening 140 and is also located on the first surface 101. The passivation material layer 155 covers the first pad layer 150 and the conductive layer 110. A groove (not shown) corresponding to the first opening 140 is formed in the passivation material layer 155; as Figure 12 As shown, a graphic layer 145 is formed within the groove; as Figure 13 As shown, the passivation material layer 155 exposed by the pattern layer 145 is thinned; as Figure 13 As shown, remove graphics layer 145; Figure 13 As shown, after removing the pattern layer 145, the passivation material layer 155 is planarized, and the remaining passivation material layer 155 is used as the passivation layer 160.

[0099] The passivation material layer 155 is used to form the passivation layer. As one embodiment, the passivation material layer 155 is formed using a chemical vapor deposition process.

[0100] The pattern layer 145 is used as a mask for thinning the passivation material layer 155. In this embodiment, the material of the pattern layer 145 is photoresist.

[0101] By thinning the passivation material layer 155 exposed on the graphics layer 145, the thickness difference between the passivation material layer 155 on the top surface of the pixel substrate 100 and the passivation material layer 155 in the first opening 140 is reduced, thereby improving the top surface height consistency of the passivation material layer 155, which is beneficial for subsequent planarization of the passivation material layer 155.

[0102] Specifically, an etching process is used to thin the passivation material layer 155 exposed on the pattern layer 145. The etching process allows for precise control over the thinning thickness of the passivation material layer 155.

[0103] The passivation material layer 155 is planarized to improve the flatness of its top surface, thus providing a flat surface for subsequent processing. As one embodiment, a chemical mechanical polishing process is used to planarize the passivation material layer 155.

[0104] In this embodiment, during the planarization process of the passivation material layer 155, a portion of the thickness of the passivation material layer 155 located on the top surface of the pixel substrate 100 is retained to prevent the planarization process from damaging the conductive layer 110.

[0105] refer to Figures 14 to 16 A passivation layer 160 is formed that penetrates the top of the isolation structure and is in contact with the conductive layer 110, and a second pad layer 220 is located on the passivation layer 160 on the first surface 101 and connected to the metal layer 210, wherein the metal layer is in the form of a mesh.

[0106] In this embodiment, the second pad layer 220 is used to connect to a negative potential. When the photoelectric sensor is working, it is easy to apply a negative potential to the second pad layer 220 so that the conductive layer 110 of the isolation structure can be connected to a negative potential through the metal layer 210. This is beneficial for adsorbing positive charges on the sidewall of the isolation structure, thereby improving the interface state of the sidewall of the isolation structure and reducing the dark current of the pixel unit.

[0107] Furthermore, compared to improving the interface states of the isolation structure sidewalls by doping the pixel substrate with P-type ions, this embodiment also helps to avoid being limited by the depth of ion doping. Accordingly, it is easier to increase the light absorption thickness and optical path by increasing the thickness of the pixel substrate by 100, thereby improving the photon detection efficiency of the photosensitive area and improving the photon detection sensitivity performance of the photoelectric sensor.

[0108] In summary, this embodiment optimizes the performance of the photoelectric sensor.

[0109] The metal layer 210 corresponds to the position and shape of the isolation structure, and the area enclosed by the metal layer 210 corresponds to each pixel unit area, thereby preventing optical crosstalk between adjacent pixel units. Specifically, the metal layer 210 is a mesh structure, and the metal layer 210 is located on the first surface 101 of the pixel substrate 100, that is, the metal layer 210 is located on the back side of the pixel substrate 100, and the metal layer 210 is a back metal mesh.

[0110] The metal layer 210 penetrates the passivation layer 160 above the isolation structure and is in contact with the conductive layer 110, thereby enabling the electrical connection between the conductive layer 110 and the second pad layer 220.

[0111] In this embodiment, the metal layer 210 is in contact with a portion of the top surface of the conductive layer 110, or the metal layer 210 is in contact with the top surface of all the conductive layers 110. Since the conductive layers 110 in each isolation structure are interconnected, even if the metal layer 210 only contacts the top surface of a portion of the conductive layers 110, electrical connection between all the conductive layers 110 and the external circuit can be achieved through the metal layer 210.

[0112] In this embodiment, the material of the metal layer 210 is a metallic material, including one or both of aluminum and tungsten. As an example, the material of the metal layer 210 is aluminum. Aluminum is an easily etchable material, which facilitates the patterning process for forming the metal layer 210. Furthermore, aluminum has good electrical conductivity, which helps improve the electrical connectivity of the metal layer 210. In addition, aluminum is an opaque material, thus ensuring that the metal layer 210 reduces optical crosstalk between adjacent pixel units.

[0113] The second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected to the metal layer 210. It is used to realize the electrical connection between the metal layer 210 and the external circuit. Thus, when the photoelectric sensor is working, the conductive layer 110 can be connected to a negative potential by applying a negative potential to the second pad layer 220.

[0114] In this embodiment, the material of the second solder pad layer 220 is a metallic material. As one embodiment, the material of the second solder pad layer 220 includes one or more of aluminum, titanium, gold, and indium tin-doped oxide.

[0115] In this embodiment, the material of the second pad layer 220 is the same as the material of the metal layer 210.

[0116] More specifically, in this embodiment, the second pad layer 220 and the metal layer 210 are formed in the same step, and the second pad layer 220 and the metal layer 210 are an integral structure, which not only helps to simplify the process flow, but also reduces resistance and improves the electrical connection performance between the second pad layer 220 and the metal layer 210.

[0117] It should be noted that the formation method further includes: in the step of forming the metal layer 210, a ground line 230 with a partial width of passivation layer 160 is also formed through the pixel substrate 100, and the ground line 230 is in contact with the pixel substrate 100. There is a gap between the ground line 230 and the metal layer 210 and the second pad layer 220.

[0118] During the formation of the second pad layer 220 and the metal layer 210, a significant amount of charge is typically generated. The grounding wire 230, which contacts the pixel substrate 100, is used to release the charge through the pixel substrate 100 during the formation of the second pad layer 220 and the metal layer 210, preventing charge accumulation on the first surface 101 of the pixel substrate 100 and thus preventing arcing during the formation of the second pad layer 220 and the metal layer 210. In this embodiment, the grounding wire 230 also penetrates a portion of the thickness of the pixel substrate 100.

[0119] In this embodiment, the material of the grounding wire 230 is the same as the material of the metal layer 210.

[0120] The specific steps for forming the metal layer 210, the second solder pad layer 220, and the grounding wire 230 in this embodiment will be described below with reference to the accompanying drawings.

[0121] like Figure 14 As shown, a second opening 170 is formed in the passivation layer 160 that extends through the isolation structure, exposing the top surface of the conductive layer 110. The second opening 170 provides space for the formation of a metal layer, exposing the conductive layer 110 so that the metal layer can contact the conductive layer 110.

[0122] In this embodiment, the second opening 170 exposes a portion of the top surface of the conductive layer 110, or the second opening 170 exposes the entire top surface of the conductive layer 110.

[0123] In this embodiment, the process for forming the second opening 170 includes a dry etching process. The dry etching process has high process controllability, which is beneficial for improving the controllability of the cross-section of the second opening 170, and also helps to reduce the probability of damage to the conductive layer 110.

[0124] In this embodiment, the forming method further includes: after forming the passivation layer 160, and before forming the metal layer 210 located in the second opening 170 and in contact with the conductive layer 110, and the second pad layer 220 located on the passivation layer 160 on the first surface 101 and connected to the metal layer 210, forming a ground trench 180 that penetrates a portion of the passivation layer 160 on the pixel substrate 100, the ground trench 180 exposing the pixel substrate 100.

[0125] The grounding trench 180 is used to provide space for forming the grounding wire.

[0126] In this embodiment, during the formation of the ground trench 180, an etching process is also performed. Therefore, the ground trench 180 also penetrates a portion of the pixel substrate 100. In other embodiments, the ground trench may penetrate only the passivation layer.

[0127] In this embodiment, the formation of the second opening 170 after the formation of the grounding trench 180 is used as an example for illustration. In other embodiments, the grounding trench may be formed after the formation of the second opening, or the second opening and the grounding trench may be formed in the same step.

[0128] like Figures 15 to 16 As shown, a metal layer 210 is formed in the second opening 170 and in contact with the conductive layer 110, and a second pad layer 220 is formed on the passivation layer 160 of the first surface 101 and connected to the metal layer 210. The forming method further includes forming a grounding wire 230 located in a grounding trench 180, the grounding wire 230 being spaced apart from the metal layer 210 and the second pad layer 220.

[0129] Specifically, such as Figure 15 As shown, a metal material layer 190 is formed on the passivation layer 160, and the metal material layer 190 fills the second opening 170 and the grounding trench 180; as Figure 16As shown, a patterned metal material layer 190 is reserved within the second opening 170 and in contact with the conductive layer 110 for use as a metal layer 210. A portion of the metal material layer 190 on the passivation layer 160 above the pixel substrate 100 adjacent to the isolation structure is reserved for use as a second solder pad layer 220. The second solder pad layer 220 is electrically connected to the metal layer 210. A portion of the metal material layer 190 within the ground trench 180 is reserved for use as a ground wire 230.

[0130] In this embodiment, a physical vapor deposition (PVD) process is used to form a metal material layer 190.

[0131] The first surface 101 of the pixel substrate 100 is an insulating surface composed of a passivation layer 160. Before the metal material layer 190 is formed, the conductive layer 110 is electrically isolated from the pixel substrate 100. During the formation of the metal material layer 190 using a physical vapor deposition process, a large amount of charge can easily accumulate on the first surface 101. The metal material layer 190 is also formed in the grounding trench 180 and is in contact with the pixel substrate 100, thereby releasing the charge through the pixel substrate 100 to prevent arc discharge problems caused by charge accumulation on the first surface 101.

[0132] In this embodiment, an etching process is used to pattern the metal material layer 190. Specifically, an anisotropic dry etching process is used to pattern the metal material layer 190.

[0133] refer to Figure 17 and Figure 18 , Figure 17 This is a cross-sectional view. Figure 18 for Figure 17 In the corresponding top view, in this embodiment, the forming method further includes: after forming the metal layer 210, forming an interconnect trench 240 that penetrates the passivation layer 160 above the first pad layer 150, exposing the first pad layer 150.

[0134] Interconnect trenches 240 are formed to expose the first solder pad layer 150, enabling subsequent electrical connections between the first solder pad layer 150 and external circuitry. This facilitates subsequent packaging and testing processes.

[0135] It should be noted that, in this embodiment, before forming the interconnect trench 240, the method for forming the photoelectric sensor further includes forming a protective layer 250 on the top surface and sidewalls of the metal layer 210 and the second pad layer 220. The protective layer 250 is also formed on the top surface and sidewalls of the ground wire 230.

[0136] The protective layer 250 serves to protect the metal layer 210, the second solder pad layer 220, and the grounding wire 230. In this embodiment, the material of the protective layer 250 is silicon oxide. In other embodiments, the material of the protective layer may also be silicon nitride or silicon oxynitride.

[0137] In addition, during the formation of the interconnect trench 240, the protective layer 250 on the top surface of the second pad layer 220 is removed to expose the second pad layer 220, thereby enabling subsequent electrical connection between the second pad layer 220 and the external circuit, allowing the second pad layer 220 to be connected to a negative potential.

[0138] Accordingly, embodiments of the present invention also provide an electronic device, including the photoelectric sensor provided in embodiments of the present invention.

[0139] The electronic device in this embodiment can be any electronic product or device with photoelectric sensing function, such as a mobile phone, tablet computer, laptop computer, navigator, camera, camcorder, robot vacuum cleaner, virtual reality device, augmented reality device, etc., or any intermediate product including the aforementioned photoelectric sensor.

[0140] As can be seen from the foregoing description, the photoelectric sensor provided in this embodiment has excellent performance. By using the photoelectric sensor provided in this embodiment, it is beneficial to improve the performance of electronic devices and enhance the user experience.

[0141] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photoelectric sensor, characterized in that, include: A pixel substrate includes opposing first and second surfaces, the pixel substrate including a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area including an array of pixel units; An isolation structure is located within the pixel substrate between the pixel unit regions. The isolation structure includes a conductive layer, the top surface of which is exposed on the first surface. The isolation structure is located in the photosensitive area. A dielectric layer is located on the second surface of the pixel substrate, and the dielectric layer is located on a logic substrate; An interconnect layer is located within the dielectric layer of the lead region; A first opening extends through the pixel substrate of the lead area and the dielectric layer above the interconnect layer, and the first opening exposes the top portion of the interconnect layer facing the first surface; The first pad layer is located at the bottom of the first opening and is in contact with the interconnect layer; A passivation layer fills the first opening and is located on the first surface, the passivation layer covering the first pad layer and the conductive layer; The second opening is located within the passivation layer and exposes the first surface of the pixel substrate and the top surface of the isolation structure; the second opening is in the form of a mesh. A metal layer fills the grid-like second opening and is in contact with the conductive layer; The metal layer corresponds to the position and shape of the isolation structure, and the area enclosed by the metal layer corresponds to each pixel unit area; The second solder pad layer is located on the passivation layer of the first surface and is connected to the metal layer. The second solder pad layer is located between the isolation structure and the first solder pad layer. The second solder pad layer is used to connect to a negative potential.

2. The photoelectric sensor as described in claim 1, characterized in that, The photoelectric sensor further includes: a ground wire, a passivation layer extending through a portion of its width and in contact with the pixel substrate.

3. The photoelectric sensor as described in claim 2, characterized in that, The top surface of the grounding wire is flush with the top surface of the metal layer and the second solder pad layer.

4. The photoelectric sensor as described in claim 1, characterized in that, The metal layer and the second pad layer are an integral structure.

5. The photoelectric sensor as described in claim 1, characterized in that, The metal layer is in contact with a portion of the top surface of the conductive layer, or the metal layer is in contact with the top surface of all the conductive layers.

6. The photoelectric sensor as described in claim 1, characterized in that, The photoelectric sensor further includes: a logic substrate, which is bonded to a dielectric layer on the second surface of the pixel substrate.

7. The photoelectric sensor as described in claim 1 or 6, characterized in that, The first surface is the back side of the pixel substrate, and the second surface is the front side of the pixel substrate.

8. The photoelectric sensor as described in claim 1, characterized in that, The isolation structure further includes an insulating layer located between the conductive layer and the pixel substrate.

9. The photoelectric sensor as described in claim 8, characterized in that, The conductive layer is made of one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride, and copper; the insulating layer is made of any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

10. The photoelectric sensor as described in claim 1, characterized in that, The pixel substrate is made of one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium nitride; the interconnect layer is made of one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride; the first pad layer is made of one or more of aluminum, titanium, gold, and tin-doped indium oxide; the passivation layer is made of one or more of silicon oxide, silicon oxynitride, and silicon nitride; the metal layer is made of one or two of aluminum and tungsten; and the second pad layer is made of one or more of aluminum, titanium, gold, and tin-doped indium oxide.

11. A method for forming a photoelectric sensor, characterized in that, include: A pixel substrate is provided, including a first surface and a second surface opposite to each other. The pixel substrate includes a photosensitive area and a lead area surrounding the photosensitive area. The photosensitive area includes an array of pixel unit areas. An isolation structure is formed in the pixel substrate between the pixel unit areas. The isolation structure includes a conductive layer. The top surface of the conductive layer is exposed on the first surface. A dielectric layer is formed on the second surface, and an interconnect layer is formed within the dielectric layer of the lead region; A first opening is formed through the pixel substrate and the dielectric layer above the interconnect layer in the lead area, the first opening exposing a portion of the top of the interconnect layer facing the first surface; A first pad layer in contact with the interconnect layer is formed at the bottom of the first opening; A passivation layer is formed to fill the first opening and on the first surface, the passivation layer covering the first pad layer and the conductive layer; A passivation layer is formed that extends through the top of the isolation structure and is in contact with the conductive layer, and a second pad layer is formed on the passivation layer of the first surface and connected to the metal layer. The metal layer is in the form of a grid, and the position and shape of the metal layer correspond to the isolation structure. The area enclosed by the metal layer corresponds to each pixel unit area. The second pad layer is used to connect to a negative potential.

12. The method for forming a photoelectric sensor as described in claim 11, characterized in that, The steps of forming the metal layer and the second pad layer include: forming a second opening through a passivation layer above the isolation structure, the second opening exposing the top surface of the conductive layer; forming a metal layer located in the second opening and in contact with the conductive layer, and a second pad layer located on the passivation layer of the first surface and connected to the metal layer.

13. The method for forming a photoelectric sensor as described in claim 12, characterized in that, The steps of forming the metal layer and the second pad layer include: forming a metal material layer on the passivation layer, the metal material layer filling the second opening; patterning the metal material layer, reserving a portion of the metal material layer located within the second opening and in contact with the conductive layer for use as the metal layer, reserving a portion of the metal material layer on the passivation layer above the pixel substrate adjacent to the isolation structure for use as the second pad layer, the second pad layer being electrically connected to the metal layer.

14. The method for forming a photoelectric sensor as described in claim 12, characterized in that, The process for forming the second opening includes a dry etching process.

15. The method for forming a photoelectric sensor as described in claim 11, characterized in that, The metal layer is in contact with a portion of the top surface of the conductive layer, or the metal layer is in contact with the entire top surface of the conductive layer.

16. The method for forming a photoelectric sensor as described in claim 11, characterized in that, The method for forming the photoelectric sensor further includes: after forming the metal layer, forming an interconnect trench that penetrates the passivation layer above the first pad layer to expose the first pad layer.

17. The method for forming a photoelectric sensor as described in claim 11, characterized in that, In the step of providing the pixel substrate, a logic substrate is also bonded to the dielectric layer of the second surface of the pixel substrate.

18. The method for forming a photoelectric sensor as described in claim 11 or 17, characterized in that, The first surface is the back side of the pixel substrate, and the second surface is the front side of the pixel substrate.

19. The method for forming a photoelectric sensor as described in claim 11, characterized in that, The method for forming the photoelectric sensor further includes: in the step of forming the metal layer, a grounding wire is also formed that penetrates a passivation layer of a portion width on the pixel substrate, and the grounding wire is in contact with the pixel substrate.

20. An electronic device, characterized in that, include: The photoelectric sensor as described in any one of claims 1 to 11.

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