Gallium oxide rectifier and fabrication process, gallium oxide rectifier structure and fabrication process

Abstract

The application discloses a gallium oxide rectifier and a manufacturing process and a gallium oxide rectifier structure and a manufacturing process, and relates to the technical field of semiconductors. The gallium oxide rectifier comprises the following structures: a gallium oxide substrate layer, a gallium oxide epitaxial layer arranged on the upper surface of the gallium oxide substrate layer, a cathode arranged on the upper surface of one side of the gallium oxide channel layer, a p-type semiconductor layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, a first anode layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, arranged close to the p-type semiconductor layer, and having a gap between the p-type semiconductor layer, a second anode layer arranged on the upper surface of the p-type semiconductor layer, and a third anode layer electrically connected with the first anode layer and the second anode layer. The application utilizes the accumulation and depletion of channel carriers to realize the rectification characteristic, and therefore does not depend on the barrier height, and can break the trade-off between the turn-on voltage and the off-state leakage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor structure, and particularly to a gallium oxide rectifier and a manufacturing process, a gallium oxide rectifier structure and a manufacturing process. BACKGROUND

[0002] Ideally, the smaller the opening voltage of the diode is, the smaller the reverse leakage is. The existing diode of gallium oxide has two structures, including a Schottky diode and a heterojunction pn junction diode. Their rectification characteristics depend on the height of the potential barrier. The higher the potential barrier is, the greater the opening voltage is, and the smaller the reverse leakage is. Conversely, the smaller the opening voltage is, the greater the reverse leakage is. The rectification characteristic of the Schottky diode is dominated by the thermionic emission model of the Schottky junction. The PN junction is dominated by the minority carrier diffusion model. Regardless of which structure, the rectification characteristic thereof depends on the height of the junction potential barrier. According to the thermionic emission model, there is an incompatibility between the low opening voltage and the low off-state leakage. SUMMARY

[0003] The present application is directed to the shortcomings in the prior art. In order to solve the problem of incompatibility between the low opening voltage and the low off-state leakage in the prior art, the present application proposes a gallium oxide field effect rectifier structure.

[0004] In order to solve the above technical problems, the present application solves the problems through the following technical solutions:

[0005] A gallium oxide rectifier, comprising the following structures:

[0006] A gallium oxide substrate layer,

[0007] A gallium oxide epitaxial layer arranged on the upper surface of the gallium oxide substrate layer;

[0008] A cathode arranged on the upper surface of one side of the gallium oxide channel layer;

[0009] A p-type semiconductor layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode;

[0010] A first anode layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, close to the p-type semiconductor layer, and having a gap between the p-type semiconductor layer;

[0011] A second anode layer arranged on the upper surface of the p-type semiconductor layer;

[0012] A third anode layer electrically connected to the first anode layer and the second anode layer.

[0013] As one of the real-time modes, the p-type semiconductor layer is made of any one of Si, NiO, GaN, MgO and Cu2O.

[0014] As one of the real-time ways, the gallium oxide substrate layer is a Fe or Mg doped semi-insulating single crystal gallium oxide single crystal substrate.

[0015] As one of the real-time ways, the upper surface part of the p-type semiconductor layer is covered by the second metal electrode, and the other part is an extension part not covered by the second metal electrode.

[0016] As one of the real-time ways, the doping ion concentration of the gallium oxide epitaxial layer ranges from 1e16 cm -3 to 1e18 cm -3 , and the thickness ranges from 50 nm to 1500 nm.

[0017] As one of the real-time ways, the thickness of the p-type semiconductor layer is 10 nm-100 nm;

[0018] As one of the real-time ways, the doping ion concentration of the gallium oxide epitaxial layer is 1e18 cm -3 , and the thickness of the gallium oxide epitaxial layer is 200 nm.

[0019] Further, a gallium oxide rectifier structure is provided, which includes two or more gallium oxide rectifiers as described above, and a groove is arranged between adjacent two gallium oxide rectifiers, and the depth of the groove is greater than or equal to the thickness of the gallium oxide epitaxial layer.

[0020] Further, a gallium oxide rectifier manufacturing process is provided, which is used to manufacture the gallium oxide rectifier as described above, and includes the following steps:

[0021] A semi-insulating single crystal gallium oxide single crystal is selected as the gallium oxide substrate layer, and a gallium oxide epitaxial layer is grown on the gallium oxide substrate layer;

[0022] A photolithography method is used for patterning, and an ohmic electrode is formed on the upper surface of the gallium oxide epitaxial layer to form an ohmic contact, and a cathode and a first anode are formed;

[0023] A photolithography method is used for patterning, a p-type semiconductor layer is grown on the upper surface of the gallium oxide epitaxial layer, and a second anode is grown on the upper surface of the p-type semiconductor layer, and the second anode forms an ohmic contact with the p-type semiconductor;

[0024] A photolithography method is used for patterning, and a third anode is grown above the first anode and the second anode, and the third anode connects the first anode and the second anode in contact with the p-type semiconductor.

[0025] Further, a gallium oxide rectifier structure manufacturing process is provided, which is used to manufacture the gallium oxide rectifier structure as described above, and includes the following steps:

[0026] A semi-insulating single crystal gallium oxide single crystal is selected as the gallium oxide substrate layer, and a gallium oxide epitaxial layer is grown on the gallium oxide substrate layer;

[0027] Etching grooves between two adjacent gallium oxide rectifiers;

[0028] Using photolithography to pattern, making ohmic electrode on the surface of gallium oxide epitaxial layer to form ohmic contact, cathode and first anode;

[0029] Using photolithography to pattern, growing p-type semiconductor layer on the surface of gallium oxide epitaxial layer, and then growing second anode on the surface of p-type semiconductor layer, the second anode forms ohmic contact with the p-type semiconductor;

[0030] Using photolithography to pattern, growing third anode above the first anode and the second anode, the third anode connects the first anode and the second anode which is in contact with the p-type.

[0031] Advantages of the present invention:

[0032] The gallium oxide field effect rectifier structure is proposed, which realizes the rectification characteristic by using the accumulation and depletion of channel carriers, and thus does not depend on the barrier height, and can break the trade-off between the turn-on voltage and the off-state leakage. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0034] Figure 1 It is a schematic diagram of a gallium oxide rectifier;

[0035] Figure 2 It is a schematic diagram of the conduction of a gallium oxide rectifier after applying a reverse voltage;

[0036] Figure 3 It is a schematic diagram of the conduction of a gallium oxide rectifier after applying a small forward voltage;

[0037] Figure 4 It is a schematic diagram of the conduction of a gallium oxide rectifier after applying a large forward voltage;

[0038] Figure 5 It is a schematic diagram of the conduction of a gallium oxide rectifier with grooves;

[0039] Figure 6 It is a schematic diagram of another gallium oxide rectifier disclosed in embodiment 3;

[0040] Figure 7 It is a schematic diagram of a gallium oxide rectifier structure;

[0041] Figure 8 is a flow chart of a gallium oxide rectifier manufacturing process. DETAILED DESCRIPTION

[0042] Exemplary embodiments of the present disclosure are described herein below with reference to the accompanying drawings, in which various details of embodiments of the present disclosure are set forth to facilitate an understanding, and should be considered as merely exemplary. Thus, it will be appreciated that various modifications and changes can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the purpose of clarity and the brevity, the description below omits the description of well-known functions and structures.

[0043] Example 1

[0044] A gallium oxide rectifier, such as Figure 1 , includes the following structure:

[0045] a gallium oxide substrate layer,

[0046] a gallium oxide epitaxial layer disposed on the upper surface of the gallium oxide substrate layer, i.e., a gallium oxide channel;

[0047] a cathode disposed on the upper surface of one side of the gallium oxide channel layer, which can be made of Ti / Au;

[0048] a p-type semiconductor layer disposed on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, and the p-type semiconductor layer can be made of NiO, Si, GaN, MgO, or Cu2O;

[0049] a first anode layer disposed on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, close to the p-type semiconductor layer, and having a gap between the p-type semiconductor layer;

[0050] a second anode layer disposed on the upper surface of the p-type semiconductor layer, which can be made of Ni / Au, Pt / Au, or the like;

[0051] a third anode layer electrically connected to the first anode layer and the second anode layer, which can be made of Au.

[0052] The third anode layer can be made of any conductive metal, and the p-type semiconductor layer, the first anode layer, the second anode layer, and the third anode layer are collectively regarded as an anode. When a negative voltage is applied to the cathode of the rectifier, the channel below the transistor gate is depleted of low-potential electrons, so no current can pass through. When a positive voltage is applied to the cathode of the rectifier, the channel below the transistor gate is accumulated with high-potential electrons, so current can pass through. Thus, unidirectional conductivity is achieved. The rectifier structure realized by this principle only needs to control the channel to achieve an opening voltage close to 0 volts, and can have a lower reverse leakage current.

[0053] The rectification characteristic principle diagram of the device is shown in Figures 2 to 4 When a reverse voltage is applied to the anode, a depletion region is formed under the p-type semiconductor, and the device is in an off state, as shown in Figure 2 When a small forward voltage is applied to the anode, that is, the voltage applied to the anode is greater than 0V and less than the opening voltage of the pn junction, the depletion region under the p-type semiconductor decreases, the device is in an on state but the current is small, as shown in Figure 3 When a large forward voltage is applied to the anode, that is, the voltage applied is greater than the opening voltage of the pn junction, the depletion region under the p-type semiconductor disappears, the device is in an on state and the pn junction is turned on, the two currents are combined, and the overall current is large, as shown in Figure 4 .

[0054] The gallium oxide substrate layer is a Mg-doped semi-insulating single-crystal gallium oxide single-crystal substrate. As another implementation, the gallium oxide substrate layer can also be a Fe-doped semi-insulating single-crystal gallium oxide single-crystal substrate.

[0055] As a preferred solution, the gallium oxide epitaxial layer outside the cathode and the anode of the gallium oxide rectifier is provided with a groove, and the groove depth is greater than or equal to the thickness of the gallium oxide epitaxial layer. As shown in Figure 5 The gallium oxide epitaxial layer outside the cathode and the anode is provided with a groove to ensure that the current flows from the opposite sides of the cathode and the anode, and the product has higher performance.

[0056] As a preferred solution, the doping ion concentration of the gallium oxide epitaxial layer ranges from 1e16 cm -3 to 1e18 cm -3 , and the thickness ranges from 50 nm to 1500 nm, and further preferably, the thickness can be 100-600 nm, and the doping ion concentration of the gallium oxide epitaxial layer ranges from 1e16 cm -3 to 1e18 cm -3 .

[0057] As a preferred solution, the thickness of the p-type semiconductor layer is 10 nm-100 nm.

[0058] Example 2

[0059] Based on the technology of Embodiment 1, a gallium oxide rectifier structure is further disclosed, which includes two or more gallium oxide rectifiers as described in Embodiment 1, and a groove is provided between adjacent two gallium oxide rectifiers, and the groove depth is greater than or equal to the thickness of the gallium oxide epitaxial layer.

[0060] In order to isolate two or more devices on the same wafer from each other and prevent crosstalk between them, some gallium oxide rectifier products need to be isolated between devices, as shown in Figure 1 The groove depth is greater than or equal to the thickness of the gallium oxide epitaxial layer, as shown in Figure 7As shown, if the groove depth is less than the thickness of the gallium oxide epitaxial layer, the crosstalk between multiple devices cannot be completely avoided.

[0061] Example 3

[0062] On the basis of Embodiment 1 or Embodiment 2, further disclosed is still another gallium oxide rectifier, comprising the following structure: Figure 6 , which comprises the following structure:

[0063] a gallium oxide substrate layer,

[0064] a gallium oxide epitaxial layer arranged on the upper surface of the gallium oxide substrate layer, i.e. a gallium oxide channel;

[0065] a cathode arranged on the upper surface of one side of the gallium oxide channel layer;

[0066] a p-type semiconductor layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode;

[0067] a first anode layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, close to the p-type semiconductor layer, and having a gap between the p-type semiconductor layer, and being a Ti / Au layer;

[0068] a second anode layer arranged on the upper surface of the p-type semiconductor layer, being a Ni / Au layer;

[0069] a third anode layer electrically connected to the first anode layer and the second anode layer.

[0070] In the structure, the upper surface of the p-type semiconductor layer is partially covered by the second metal electrode, and the other part is an extension part not covered by the second metal electrode. The structure design, i.e. the extension of the p-type semiconductor layer, can effectively improve the breakdown voltage of the device.

[0071] Example 4

[0072] The embodiment discloses a gallium oxide rectifier manufacturing process for manufacturing the gallium oxide rectifier disclosed above, comprising the following steps:

[0073] a semi-insulating single-crystal gallium oxide single crystal is selected as the gallium oxide substrate layer, and a gallium oxide epitaxial layer is grown thereon;

[0074] photolithography is adopted to patternize, and an ohmic electrode is formed on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;

[0075] photolithography is adopted to patternize, and a p-type semiconductor layer is grown on the upper surface of the gallium oxide epitaxial layer, and a second anode is grown on the upper surface of the p-type semiconductor layer, and the second anode forms ohmic contact with the p-type semiconductor;

[0076] Growth of a third anode above the first anode and the second anode by means of photolithography, the third anode connects the first anode and the second anode in contact with the p-type.

[0077] (I) The embodiment provides a more specific scheme, and discloses relevant parameters as references.

[0078] Step 1, Fe-doped semi-insulating single-crystal gallium oxide single-crystal substrate layer is selected, a 200-nm gallium oxide epitaxial layer is grown, and the concentration is 1e18 cm -3 .

[0079] Step 2, photolithography is adopted to form patterns, 20-nm Ti and 200-nm Au ohmic electrodes are evaporated by means of electron beam evaporation to form ohmic contact, at this time, the cathode and the first anode are prepared, and the cathode and the first anode are both Ti / Au layers.

[0080] Step 3, photolithography is adopted to form patterns, 50-nm p-type NiO is grown by means of magnetron sputtering or pulsed laser deposition, a p-type semiconductor layer is obtained, 20-nm Ni and 200-nm Au metal electrodes are grown by means of electron beam evaporation, and the second anode is obtained, and the second anode forms ohmic contact with the p-type semiconductor layer.

[0081] Step 4, photolithography is adopted to form patterns, 20-nm Ni and 200-nm Au metal are evaporated by means of electron beam evaporation, and the third anode is obtained, and the third anode connects the ohmic electrode and the electrode in contact with the p-type.

[0082] (II) The embodiment provides another scheme, and discloses relevant parameters as references.

[0083] Step 10, Mg-doped semi-insulating single-crystal gallium oxide single-crystal substrate is selected, a 400-nm epitaxial layer is grown, and the concentration is 5e17 cm -3 .

[0084] Step 20, photolithography is adopted to form patterns, 20-nm Ti and 200-nm Au ohmic electrodes are evaporated by means of electron beam evaporation to form ohmic contact, at this time, the cathode and the first anode are prepared.

[0085] Step 30, photolithography is adopted to form patterns, 50-nm p-type Cu2O is grown by means of magnetron sputtering or pulsed laser deposition, a p-type semiconductor layer is obtained, 20-nm Pt and 200-nm Au metal electrodes are grown by means of electron beam evaporation, and the second anode is obtained, and the second anode forms ohmic contact with the p-type semiconductor.

[0086] Step 40, photolithography is adopted to form patterns, 200-nm Au metal is evaporated by means of electron beam evaporation, and the third anode is obtained, and the third anode connects the ohmic electrode and the electrode in contact with the p-type.

[0087] Example 5

[0088] In some preparation processes, a plurality of series-connected gallium oxide rectifiers are prepared on the same wafer, referring to Figure 8 , comprising the following steps:

[0089] Selecting a semi-insulating single-crystal gallium oxide single crystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer thereon;

[0090] Etching a groove between two adjacent gallium oxide rectifiers;

[0091] Using photolithography to pattern, an ohmic electrode is made on the surface of the gallium oxide epitaxial layer to form an ohmic contact, a cathode and a first anode;

[0092] Using photolithography to pattern, a p-type semiconductor layer is grown on the surface of the gallium oxide epitaxial layer, and a second anode is grown on the surface of the p-type semiconductor layer, the second anode forming an ohmic contact with the p-type semiconductor;

[0093] Using photolithography to pattern, a third anode is grown above the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.

[0094] The present embodiment proposes a more specific scheme, and discloses relevant parameters as a reference:

[0095] Step 100, selecting a Fe-doped semi-insulating single-crystal gallium oxide single crystal substrate, growing a 200nm epitaxial layer, the concentration is 1e18 cm -3 ;

[0096] Step 200, device isolation: using BCl3 and Ar or Cl2 as etching gas, inductively coupled plasma etching, etching depth is 400nm, forming a groove between two adjacent anodes or cathodes, to avoid series interference;

[0097] Step 300, using photolithography to pattern, using electron beam evaporation to deposit 20nm Ti and 200nm Au ohmic electrode to form ohmic contact, at this time, the cathode and the first anode are prepared, that is, the cathode and the first anode are both Ti / Au layers;

[0098] Step 400, using photolithography to pattern, using magnetron sputtering or pulsed laser deposition method to grow 50nm p-type NiO to obtain a p-type semiconductor layer, and then using electron beam evaporation method to grow 20nm Ni and 200nm Au metal electrode to obtain a second anode, the second anode forming an ohmic contact with the p-type semiconductor;

[0099] Step 500, using photolithography means patterning, using electron beam evaporation method to evaporate 20nm Ni and 200nm Au metal, to obtain the third anode, the third anode connects the ohmic electrode and the electrode contacting the p-type.

[0100] The embodiment proposes another scheme, and discloses relevant parameters as references:

[0101] Step a, selecting a Mg-doped semi-insulating single crystal gallium oxide single crystal substrate, growing a 400nm epitaxial layer, and the concentration is 5e17cm -3 ;

[0102] Step b, device isolation production: using BCl3 and Ar or Cl2 as etching gas, inductively coupled plasma etching is carried out, the etching depth is 600nm, a groove is formed between two adjacent anodes or cathodes, to avoid series interference;

[0103] Step c, using photolithography means patterning, using electron beam evaporation to evaporate 20nm Ti and 200nm Au ohmic electrode to form ohmic contact, at this time, the prepared is a cathode and a first anode;

[0104] Step d, using photolithography means patterning, using magnetron sputtering or pulsed laser deposition method to grow 50nm p-type Cu2O, and then using electron beam evaporation method to grow 20nm Pt and 200nm Au metal electrode, to obtain a second anode, the second anode forms ohmic contact with the p-type semiconductor;

[0105] Step e, using photolithography means patterning, using electron beam evaporation method to evaporate 200nm Au metal to obtain a third anode, the third anode connects the ohmic electrode and the electrode contacting the p-type.

[0106] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited to this, any change or replacement within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Meanwhile, the technical solutions of the above embodiments and the embodiments can be combined arbitrarily. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A gallium oxide rectifier, characterized in that, Includes the following structure: gallium oxide substrate, A gallium oxide epitaxial layer is disposed on the upper surface of a gallium oxide substrate layer; The cathode is located on the upper surface of one side of the gallium oxide channel layer; A p-type semiconductor layer is disposed on the upper surface of the gallium oxide channel layer opposite to the cathode. The first anode layer is disposed on the upper surface of the gallium oxide channel layer opposite to the cathode, close to the p semiconductor layer, and has a gap between it and the p-type semiconductor layer. The second anode layer is disposed on the upper surface of the p-type semiconductor layer; The third anode layer is electrically connected to the first and second anode layers; The p-type semiconductor layer is made of any one of the following materials: Si, NiO, GaN, MgO, and Cu2O.

2. The gallium oxide rectifier according to claim 1, characterized in that, The gallium oxide substrate is a semi-insulating single-crystal gallium oxide substrate doped with Fe or Mg.

3. The gallium oxide rectifier according to claim 1, characterized in that, The upper surface of the p-type semiconductor layer is partially covered by the second metal electrode, and the other part is an extension that is not covered by the second metal electrode.

4. The gallium oxide rectifier according to claim 1 or 2, characterized in that, The doping ion concentration of the gallium oxide epitaxial layer ranges from 1e16 cm⁻³ to 1e18 cm⁻³, and the thickness ranges from 50 nm to 1500 nm.

5. The gallium oxide rectifier according to claim 1 or 2, characterized in that, The thickness of the p-type semiconductor layer is 10nm-100nm.

6. The gallium oxide rectifier according to claim 1, characterized in that, The gallium oxide epitaxial layer has a doping ion concentration of 1e18 cm-3 and a thickness of 200 nm.

7. A gallium oxide rectifier structure, characterized in that, The invention includes two or more gallium oxide rectifiers as described in any one of claims 1-6, wherein a groove is provided between two adjacent gallium oxide rectifiers, and the groove depth is greater than or equal to the thickness of the gallium oxide epitaxial layer.

8. A manufacturing process for a gallium oxide rectifier, characterized in that, To manufacture the gallium oxide rectifier according to any one of claims 1-6, the following steps are included: A semi-insulating single-crystal gallium oxide was selected as the gallium oxide substrate, and a gallium oxide epitaxial layer was grown on it. The cathode and the first anode are fabricated by patterning the gallium oxide epitaxial layer using photolithography to form an ohmic contact. A p-type semiconductor layer is grown on the upper surface of a gallium oxide epitaxial layer using photolithography, and then a second anode is grown on the upper surface of the p-type semiconductor layer. The second anode forms an ohmic contact with the p-type semiconductor. A third anode is grown above the first and second anodes using photolithography to pattern the anode. The third anode connects the first anode and the second electrode that is in p-type contact.

9. A fabrication process for a gallium oxide rectifier structure, characterized in that, To fabricate the gallium oxide rectifier structure of claim 7, the following steps are included: A semi-insulating single-crystal gallium oxide was selected as the gallium oxide substrate, and a gallium oxide epitaxial layer was grown on it. A groove is etched between two adjacent gallium oxide rectifiers; The cathode and the first anode are fabricated by patterning the gallium oxide epitaxial layer using photolithography to form an ohmic contact. A p-type semiconductor layer is grown on the upper surface of a gallium oxide epitaxial layer using photolithography, and then a second anode is grown on the upper surface of the p-type semiconductor layer. The second anode forms an ohmic contact with the p-type semiconductor. A third anode is grown above the first and second anodes using photolithography to pattern the anode. The third anode connects the first anode and the second electrode that is in p-type contact.

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