Wafer bonding ohmic contact electrode annealing method

Abstract

The application provides a wafer bonding ohmic contact electrode annealing method, which comprises the following steps: aligning and attaching a bonding surface of a III-V epitaxial wafer with a bonding surface of a Si wafer to form a pre-bonding wafer; applying a first preset pressure on the pre-bonding wafer at a first preset temperature and keeping the first preset pressure for a first preset time period to form a bonding wafer; forming a first metal electrode on the outer surface of the III-V epitaxial wafer and forming a second metal electrode on the outer surface of the Si wafer to form a pre-annealing bonding wafer; applying a second preset pressure on the pre-annealing bonding wafer at a second preset temperature and keeping the second preset pressure for a second preset time period to perform annealing and form a bonding wafer with an ohmic contact electrode. The wafer bonding ohmic contact electrode annealing method provided by the application can adapt the annealing temperature to the wafer bonding temperature, can obtain a bonding wafer with stable process and an ohmic contact electrode with low contact resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processes, and in particular to an annealing method for ohmic contact electrodes in wafer bonding. Background Technology

[0002] As the efficiency of single-junction Si solar cells approaches their theoretical limit, Si-based III-V multi-junction solar cells are considered an effective solution to further improve the efficiency of Si solar cells. Due to the difference in lattice constants between III-V compounds and Si, epitaxial growth of III-V compounds on Si substrates results in defects such as dislocations at the growth interface. Wafer bonding technology, which does not require consideration of lattice mismatch between materials, is an effective method for bonding III-V compounds to Si. However, due to the difference in thermal expansion coefficients between III-V compounds and Si, achieving low-temperature (bonding temperature below 500°C) wafer bonding is crucial for the successful bonding of III-V compounds to Si.

[0003] Studies have found that as the bonding temperature increases (>300℃), the resistivity of GaAs / Si bonded wafers increases with temperature due to the difference in thermal expansion coefficients between GaAs and Si. In recent years, a surface-active bonding method has become the main method for fabricating III-V / Si multi-junction solar cells. The minimum interfacial resistivity between GaAs and Si can reach 3.6 mΩ·cm. -2 The highest efficiency of III-V / Si multijunction solar cells prepared using this method can reach 34.1%. However, this method undoubtedly increases the cost and difficulty of preparation due to the use of special equipment for wafer surface activation and the need for bonding under ultra-high vacuum. Plasma activation provides a new solution for developing GaAs-Si low-temperature wafer bonding technology. Plasma activation refers to treating the wafer surface with argon, oxygen, and nitrogen plasma before wafer bonding to increase the density of surface functional groups (-OH). After plasma activation, the wafers are bonded face-to-face to form a pre-bonded wafer, which still needs to be heated to 200-300°C to improve the bonding strength. In the process of fabricating devices using bonded wafers, the thermal annealing of the ohmic contact electrodes is the core factor affecting device performance. However, the temperature of the alloy formed between GaAs and the metal electrode is usually greater than 300°C. High-temperature annealing leads to an increase in the number of defects at the GaAs-Si bonding interface, thus affecting the electrical performance of III-V / Si multijunction solar cell devices.

[0004] Therefore, the annealing temperature of the ohmic contact electrode and the bonding annealing are key issues that must be considered when preparing III-V / Si multijunction solar cells with excellent electrical properties. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] In view of this, the present invention provides an annealing method for ohmic contact electrodes of wafer bonding to solve or partially solve the above problems.

[0007] (II) Technical Solution

[0008] This invention provides an annealing method for ohmic contact electrodes in wafer bonding, comprising: aligning and bonding the bonding surfaces of a III-V epitaxial wafer and a Si wafer to form a pre-bonded wafer; applying a first preset pressure to the pre-bonded wafer at a first preset temperature and maintaining it for a first preset time period to form a bonded wafer; forming a first metal electrode on the outer surface of the III-V epitaxial wafer and a second metal electrode on the outer surface of the Si wafer to form a pre-annealed bonded wafer; applying a second preset pressure to the pre-annealed bonded wafer at a second preset temperature and maintaining it for a second preset time period to perform annealing, thereby forming a bonded wafer with ohmic contact electrodes.

[0009] In one embodiment of the present invention, before the bonding surfaces of the III-V epitaxial wafer and the Si wafer are fully aligned to form a pre-bonded wafer, the annealing method further includes: cleaning the III-V epitaxial wafer; cleaning the Si wafer; using the polished surfaces of the cleaned III-V epitaxial wafer and the Si wafer as bonding surfaces, and performing surface activation treatment on the bonding surfaces of the cleaned III-V epitaxial wafer and the Si wafer.

[0010] In one embodiment of the present invention, the step of applying a first preset pressure to the pre-bonded wafer at a first preset temperature and maintaining it for a first preset time period to form a bonded wafer includes: applying the first preset pressure to the pre-bonded wafer using a bonding machine at the first preset temperature, wherein the first preset pressure is 500-3000 mbar and the first preset temperature is 200-300°C; and maintaining it for a first preset time period to form the bonded wafer, wherein the first preset time period is 1-3 hours.

[0011] In one embodiment of the present invention, forming a first metal electrode on the outer surface of the III-V epitaxial wafer includes: forming a first Ni layer on the outer surface of the III-V epitaxial wafer, the first Ni layer having a thickness of 20-30 nm; forming a first Au layer on the first Ni layer, the first Au layer having a thickness of 80-100 nm; forming a Ge layer on the first Au layer, the Ge layer having a thickness of 10-20 nm; forming a second Ni layer on the Ge layer, the second Ni layer having a thickness of 100-120 nm; and forming a second Au layer on the second Ni layer, the second Au layer having a thickness of 40-60 nm, thereby obtaining a multilayered first metal electrode.

[0012] In one embodiment of the present invention, forming a second metal electrode on the outer surface of the Si wafer includes: forming a Ti layer on the outer surface of the Si wafer, the Ti layer having a thickness of 30-80 nm; forming a Pt layer on the Ti layer, the Pt layer having a thickness of 30-80 nm; and forming an Au layer on the Pt layer, the Au layer having a thickness of 250-320 nm, thereby obtaining a multilayer second metal electrode.

[0013] In one embodiment of the present invention, applying a second preset pressure to the pre-annealed wafer at a second preset temperature and maintaining it for a second preset time period for annealing includes: applying the second preset pressure to the pre-annealed bonded wafer using a bonding machine at the second preset temperature, wherein the second preset pressure is 500-3000 mbar, the second preset temperature is 200-300°C, and the heating rate of the second preset temperature is 5-10°C per minute; maintaining it for a second preset time period, wherein the second preset time period is 1-3 hours; and continuously cooling the pre-annealed wafer to room temperature at a cooling rate of 5-10°C per minute to complete the annealing operation.

[0014] In one embodiment of the present invention, the cleaning of the III-V epitaxial wafer includes: boiling the III-V epitaxial wafer sequentially with acetone and anhydrous ethanol; rinsing the boiled III-V epitaxial wafer repeatedly with deionized water at least 3 times; and immersing the rinsed III-V epitaxial wafer in a 10% hydrofluoric acid solution for 30 to 60 seconds to complete the cleaning of the III-V epitaxial wafer.

[0015] In one embodiment of the present invention, the cleaning of the Si wafer includes: boiling the Si wafer in a mixed solution of concentrated sulfuric acid and hydrogen peroxide with a volume ratio of 3:1; heating the boiled Si wafer in a water bath at 75-85°C in a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water with a volume ratio of 1:1:6 for 10-15 minutes; and immersing the water-bath-heated Si wafer in a 10% hydrofluoric acid solution for 10-60 seconds to complete the cleaning of the Si wafer.

[0016] In one embodiment of the present invention, the surface activation treatment of the bonding surfaces of the cleaned III-V epitaxial wafer and Si wafer includes: placing the bonding surfaces of the cleaned III-V epitaxial wafer and Si wafer upward in a reactive ion etching machine and introducing argon gas to perform surface activation treatment.

[0017] In one embodiment of the present invention, the step of placing the cleaned III-V epitaxial wafer and the Si wafer with the bonding surface facing upward in a reactive ion etching machine and introducing argon gas includes: setting the flow rate of the argon gas introduced into the reactive ion etching machine to be 20-80 sccm and the pressure to be 30-50 mTorr, and processing it in the reactive ion etching machine for 30-300 seconds.

[0018] (III) Beneficial Effects

[0019] (1) The annealing method provided by the present invention applies a certain pressure to the bonded wafer at a lower temperature for annealing treatment, thereby achieving the adaptation of the annealing temperature to the wafer bonding temperature, and finally obtaining a bonded wafer with stable process and an ohmic contact electrode with low contact resistance.

[0020] (2) The annealing method provided by the present invention mainly anneals the bonded wafer and contact electrode by bonding machine, which can effectively reduce the polishing cost and annealing cost in the wafer bonding process, thereby reducing the device manufacturing cost.

[0021] (3) The annealing method provided by the present invention is applicable to III-V epitaxial wafers and Si wafers, and has a wide range of applications. Attached Figure Description

[0022] Figure 1 The flowchart illustrates an annealing method for wafer-bonded ohmic contact electrodes provided by an embodiment of the present invention.

[0023] Figure 2 The diagram schematically illustrates the test results of a circular transmission line model (CTLM) for the ohmic contact resistance values ​​between Ni / Au / Ge / Ni / Au multilayer elemental metals and GaAs obtained according to an embodiment of the present invention.

[0024] Figure 3The diagram illustrates the test results of a circular transmission line model (CTLM) of the ohmic contact resistance values ​​between Ti / Pt / Au multilayer elemental metals and Si, obtained according to an embodiment of the present invention.

[0025] Figure 4 The diagram schematically illustrates the voltage and current curves of the bonded wafer after the annealing method of the ohmic contact electrode of wafer bonding according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] This invention provides an annealing method for wafer-bonded ohmic contact electrodes, a crucial step in the fabrication of Si-based III-V multijunction solar cells. Since the efficiency of single-junction Si solar cells approaches their theoretical limit, Si-based III-V multijunction solar cells represent the next step in solar cell development. Compared to single-junction Si solar cells, Si-based III-V multijunction solar cells utilize a variety of semiconductor materials with different band gaps. However, the significant difference in lattice constant between III-V compounds and Si leads to defects such as dislocations at the growth interface when growing III-V compounds on Si substrates using epitaxial processes. The wafer-bonded ohmic contact electrode annealing method proposed in this invention is a key step in solving these problems.

[0029] This invention provides an annealing method for ohmic contact electrodes in wafer bonding, see [link to relevant documentation]. Figure 1 This includes steps S101 to S104:

[0030] Step S101: Align and bond the bonding surface of the III-V epitaxial wafer with the bonding surface of the Si wafer to form a pre-bonded wafer.

[0031] Step S102: At a first preset temperature, apply a first preset pressure to the pre-bonded wafer and maintain it for a first preset time period to form a bonded wafer.

[0032] Step S103: A first metal electrode is formed on the outer surface of a III-V epitaxial wafer, and a second metal electrode is formed on the outer surface of a Si wafer to form a pre-annealed bonded wafer.

[0033] Step S104: At a second preset temperature, a second preset pressure is applied to the pre-annealed bonding wafer and maintained for a second preset time period to perform annealing, thereby forming a bonding wafer with ohmic contact electrodes.

[0034] In the annealing method for ohmic contact electrodes in wafer bonding provided by this invention, a III-V epitaxial wafer and a Si wafer can be cut into the same shape. The bonding surfaces of the III-V epitaxial wafer and the Si wafer are selected, and the two bonding surfaces are aligned and bonded to form a pre-bonded wafer. The pre-bonded wafer is then bonded. At a first preset temperature, a first preset pressure is applied to the pre-bonded wafer and maintained for a first preset time period, causing the pre-bonded wafer to form a bonded wafer. Both the bonding surfaces of the III-V epitaxial wafer and the Si wafer in the pre-bonded wafer have clean, atomically flat surfaces. During the bonding process, the III-V epitaxial wafer and the Si wafer are bonded together through van der Waals forces, molecular forces, and even atomic forces. After bonding, a first metal electrode is formed on the outer surface of the III-V epitaxial wafer, and a second metal electrode is formed on the outer surface of the Si wafer. A final annealing process is then performed. At a second preset temperature, a second preset pressure is applied to the pre-annealed wafer and maintained for a second preset time period to anneal, forming a bonded wafer with ohmic contact electrodes. The number of defects at the bonding interface decreases during annealing, and the first and second metal electrodes form alloyed electrodes with ohmic contacts during annealing, ultimately improving the efficiency and fabrication process stability of Si-based III-V multijunction solar cells. The wafer bonding ohmic contact electrode annealing method provided by this invention is applicable to various Si-based III-V multijunction solar cells and has a wide range of applications. The low-temperature wafer bonding technology used in this application is mainly for bonding two materials with different coefficients of thermal expansion. Applying excessively high temperatures can increase the number of growth defects at the wafer bonding interface, or even cause wafer warping and cracking. Simultaneously, electrode thermal annealing is also a crucial process step in the fabrication of heterogeneous material devices, directly affecting the electrical performance of the devices.

[0035] In one embodiment of the present invention, before step S101, the method further includes: cleaning the III-V epitaxial wafer; cleaning the Si wafer; taking any side of the cleaned III-V epitaxial wafer and the Si wafer as the bonding surface, and performing surface activation treatment on the bonding surface of the cleaned III-V epitaxial wafer and the Si wafer.

[0036] The cleaning process for III-V epitaxial wafers includes: boiling the III-V epitaxial wafers sequentially with acetone and anhydrous ethanol; rinsing the boiled III-V epitaxial wafers repeatedly with deionized water at least 3 times; and immersing the rinsed III-V epitaxial wafers in a 10% hydrofluoric acid solution for 30–60 seconds to complete the cleaning of the III-V epitaxial wafers.

[0037] The cleaning process for Si wafers includes: boiling the Si wafers in a mixed solution of concentrated sulfuric acid and hydrogen peroxide at a volume ratio of 3:1; heating the boiled Si wafers in a water bath at 75–85°C for 10–15 minutes in a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water at a volume ratio of 1:1:6; and immersing the water-bath-heated Si wafers in a 10% hydrofluoric acid solution for 10–60 seconds to complete the cleaning of the Si wafers.

[0038] The surface activation process includes placing the cleaned III-V epitaxial wafer and the Si wafer with the bonding surfaces facing upwards in a reactive ion etching machine and introducing argon gas for surface activation. Optionally, the flow rate of the argon gas introduced into the reactive ion etching machine can be set to 20–80 sccm, the pressure to 30–50 mTorr, and the treatment time in the reactive ion etching machine can be 30–300 seconds.

[0039] In one embodiment of the present invention, step S102 includes: applying a first preset pressure to the pre-bonded wafer using a bonding machine at a first preset temperature, wherein the first preset pressure is 500–3000 mbar and the first preset temperature is 200–300°C; maintaining the bonding for a first preset time period to form a bonded wafer, wherein the first preset time period is 1–3 hours. The present invention employs a low-temperature (bonding temperature below 500°C) bonding method, performing bonding at a first preset temperature of 200–300°C and using a first preset pressure of 500–3000 mbar, which can accommodate the bonding of various III-V epitaxial wafers and Si wafers, and has a wide range of applications.

[0040] In one embodiment of the present invention, step S103, forming a first metal electrode on the outer surface of a III-V epitaxial wafer, includes: forming a first Ni layer on the outer surface of the III-V epitaxial wafer, the thickness of the first Ni layer being 20-30 nm; forming a first Au layer on the first Ni layer, the thickness of the first Au layer being 80-100 nm; forming a Ge layer on the first Au layer, the thickness of the Ge layer being 10-20 nm; forming a second Ni layer on the Ge layer, the thickness of the second Ni layer being 100-120 nm; and forming a second Au layer on the second Ni layer, the thickness of the second Au layer being 40-60 nm, thereby obtaining a multilayered first metal electrode. Step S103, forming a second metal electrode on the outer surface of a Si wafer, includes: forming a Ti layer on the outer surface of the Si wafer, the thickness of the Ti layer being 30-80 nm; forming a Pt layer on the Ti layer, the thickness of the Pt layer being 30-80 nm; and forming an Au layer on the Pt layer, the thickness of the Au layer being 250-320 nm, thereby obtaining a multilayered second metal electrode. The metal electrodes selected in this application, due to their multilayer structure and thickness, will form alloyed metal electrodes during the subsequent annealing process, achieving good ohmic contact with the III-V epitaxial wafer and the Si wafer. See [link to application]. Figure 2 and Figure 3 , Figure 2 The diagram schematically illustrates the circular transmission line model (CTLM) test results of the ohmic contact resistance values ​​between a Ni / Au / Ge / Ni / Au multilayer elemental metal and GaAs obtained according to an embodiment of the present invention. It shows that the specific contact resistivity of the first metal electrode is 1.81 × 10⁻⁶. -4 Ωcm 2 . Figure 3 The diagram schematically illustrates the circular transmission line model (CTLM) test results of the ohmic contact resistance between Ti / Pt / Au multilayer elemental metals and Si, obtained according to an embodiment of the present invention. It shows that the specific contact resistivity of the second metal electrode is 2.76 × 10⁻⁶. -6 Ω·cm 2 The test results indicate that both the first and second metal electrodes formed good linear ohmic contacts with the portions they were connected to.

[0041] In one embodiment of the present invention, step S104 includes: applying a second preset pressure to the pre-annealed bonded wafer using a bonding machine at a second preset temperature, wherein the second preset pressure is 500-3000 mbar, the second preset temperature is 200-300°C, and the heating rate of the second preset temperature is 5-10°C per minute; maintaining the temperature for a second preset time period, wherein the second preset time period is 1-3 hours; and continuously cooling the pre-annealed wafer to room temperature at a cooling rate of 5-10°C per minute to complete the annealing operation. The present invention uses a bonding machine to anneal the metal electrodes, employing a gradual temperature increase and decrease, and maintaining the temperature consistent with the first preset temperature set for low-temperature bonding, ensuring that the formation of ohmic contacts does not affect the quality of the low-temperature bonded wafer. The second preset temperature is lower than the metal alloying temperature; simply increasing the annealing time cannot form ohmic contacts. Setting a second preset pressure during annealing accelerates metal alloying, ensuring that ohmic contacts are formed at a lower temperature during annealing. Furthermore, annealing the metal-containing bonded wafer reduces thermal stress at the bonding interface, preventing warping and cracking. The second preset time period facilitates the formation of a sufficient ohmic contact between the metal and semiconductor, thereby improving device performance. The gradual annealing process further reduces thermal stress at the bonding interface. See also Figure 4 , Figure 4 The diagram schematically illustrates the voltage-current curves of the bonded wafer after annealing using the ohmic contact electrode method of wafer bonding according to an embodiment of the present invention. The III-V group epitaxial wafer is a GaAs epitaxial wafer. The voltage-current relationship shows that the GaAs / Si bonded wafer prepared using the present invention exhibits linear ohmic contact characteristics, and the resistivity of the bonded wafer is <0.4 Ω·cm. 2 It possesses excellent electrical properties.

[0042] The annealing method provided by this invention mainly anneals the bonded wafer and contact electrodes using a bonding machine. It can also effectively reduce the polishing cost and annealing cost in the wafer bonding process, thereby reducing the device fabrication cost.

[0043] Throughout the accompanying drawings, identical elements are represented by the same or similar reference numerals. Conventional structures or constructions have been omitted where they may cause confusion in understanding this disclosure. Furthermore, the shapes, dimensions, and positional relationships of the components in the drawings do not reflect actual size, scale, or actual positional relationships. Additionally, any reference numerals placed between parentheses in the claims should not be construed as limiting the claims.

[0044] Similarly, to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0046] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An annealing method for ohmic contact electrodes bonded to wafers, comprising: The bonding surfaces of the III-V epitaxial wafers are aligned and bonded to the bonding surfaces of the Si wafers to form a pre-bonded wafer. At a first preset temperature, a first preset pressure is applied to the pre-bonded wafer using a bonding machine, wherein the first preset pressure is 500~3000 mbar and the first preset temperature is 200~300°C; the bonding wafer is maintained for a first preset time period to form a bonded wafer, wherein the first preset time period is 1~3 hours; A first metal electrode is formed on the outer surface of the III-V epitaxial wafer, and a second metal electrode is formed on the outer surface of the Si wafer to form a pre-annealed bonded wafer. At a second preset temperature, a second preset pressure is applied to the pre-annealed bonded wafer using a bonding machine, wherein the second preset pressure is 500~3000 mbar, the second preset temperature is 200~300℃, and the heating rate of the second preset temperature is 5~10℃ per minute; the temperature is maintained for a second preset time period, wherein the second preset time period is 1~3 hours; the pre-annealed bonded wafer is continuously cooled to room temperature at a cooling rate of 5~10℃ per minute to complete the annealing operation and form a bonded wafer with ohmic contact electrodes.

2. The annealing method according to claim 1, wherein before fully aligning the bonding surface of the III-V epitaxial wafer with the bonding surface of the Si wafer to form a pre-bonded wafer, the annealing method further comprises: The III-V epitaxial wafer was cleaned; The Si wafer is cleaned; The polished surfaces of the cleaned III-V epitaxial wafer and Si wafer are used as bonding surfaces, and surface activation treatment is performed on the bonding surfaces of the cleaned III-V epitaxial wafer and Si wafer.

3. The annealing method according to claim 1, wherein forming a first metal electrode on the outer surface of the III-V epitaxial wafer comprises: A first Ni layer is formed on the outer surface of the III-V epitaxial wafer, and the thickness of the first Ni layer is 20~30 nm. A first Au layer is formed on the first Ni layer, and the thickness of the first Au layer is 80~100nm; A Ge layer is formed on the first Au layer, and the thickness of the Ge layer is 10~20nm; A second Ni layer is formed on the Ge layer, and the thickness of the second Ni layer is 100~120nm; A second Au layer is formed on the second Ni layer, the thickness of the second Au layer being 40~60nm, to obtain a multilayer first metal electrode.

4. The annealing method according to claim 1, wherein forming a second metal electrode on the outer surface of the Si wafer comprises: A Ti layer is formed on the outer surface of the Si wafer, and the thickness of the Ti layer is 30~80nm. A Pt layer is formed on the Ti layer, and the thickness of the Pt layer is 30~80nm; An Au layer with a thickness of 250-320 nm is formed on the Pt layer to obtain a multilayer second metal electrode.

5. The annealing method according to claim 2, wherein cleaning the III-V epitaxial wafer comprises: The III-V epitaxial wafer was boiled sequentially with acetone and anhydrous ethanol. The boiled III-V epitaxial wafer was rinsed repeatedly with deionized water at least 3 times. The rinsed III-V epitaxial wafer is immersed in a 10% hydrofluoric acid solution for 30-60 seconds to complete the cleaning of the III-V epitaxial wafer.

6. The annealing method according to claim 2, wherein cleaning the Si wafer comprises: The Si wafer was boiled in a mixed solution of concentrated sulfuric acid and hydrogen peroxide with a volume ratio of 3:

1. The boiled Si wafer was heated in a water bath at 75-85°C for 10-15 minutes in a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water with a volume ratio of 1:1:

6. The Si wafer, after being heated in a water bath, is immersed in a 10% hydrofluoric acid solution for 10-60 seconds to complete the cleaning of the Si wafer.

7. The annealing method according to claim 2, wherein the surface activation treatment of the bonding surfaces of the cleaned III-V epitaxial wafer and Si wafer comprises: The cleaned III-V epitaxial wafer and Si wafer, with the bonding surfaces facing upwards, are placed in a reactive ion etching machine and argon gas is introduced to perform surface activation treatment.

8. The annealing method according to claim 7, wherein placing the cleaned III-V epitaxial wafer and the Si wafer with the bonding surfaces facing upwards in a reactive ion etching machine and introducing argon gas comprises: The flow rate of argon gas introduced into the reactive ion etching machine is set to 20~80 sccm, and the pressure is set to 30~50 mTorr. The process is carried out in the reactive ion etching machine for 30~300 seconds.

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