Power converter with smooth transition control mechanism

Abstract

A power converter with a smooth transition control mechanism is disclosed. An oscillator circuit outputs a clock signal. A control circuit receives the clock signal from the oscillator circuit and outputs a control signal based on the clock signal. A driver circuit outputs an upper bridge gate signal and a lower bridge gate signal in accordance with the control signal. An upper bridge switch is turned on or off in accordance with the upper bridge gate signal received from the driver circuit. A lower bridge switch is turned on or off in accordance with the lower bridge gate signal received from the driver circuit. The oscillator circuit receives the upper bridge gate signal from the driver circuit and determines whether to adjust the clock signal output to the control circuit based on the upper bridge gate signal.

Description

Technical Field

[0001] This invention relates to a power converter, and more particularly to a power converter with a smooth transition control mechanism. Background Technology

[0002] Power converters are used to convert voltage and provide the converted voltage to other electronic devices as the power required for their operation. The conduction time of the upper and lower bridge switches of a power converter affects the magnitude of its output current. However, traditional control circuits for power converters cannot effectively control the operation of the drive circuit to operate the upper and lower bridge switches, resulting in excessively high or low output current, which can damage the load through which the output current flows and the circuit components of the power converter. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a power converter with a smooth transition control mechanism, addressing the shortcomings of existing technologies. The converter includes an oscillation circuit, a control circuit, a drive circuit, an upper bridge switch, and a lower bridge switch. The oscillation circuit is configured to output a clock signal. The control circuit is connected to the oscillation circuit. The control circuit is configured to receive the clock signal from the oscillation circuit and output a control signal based on the clock signal. The drive circuit is connected to the control circuit and the oscillation circuit. The drive circuit is configured to output an upper bridge turn-on signal and a lower bridge turn-on signal according to the control signal. A first terminal of the upper bridge switch is coupled to a shared voltage. The control terminal of the upper bridge switch is connected to the drive circuit. The upper bridge switch turns on or off according to the upper bridge turn-on signal received from the drive circuit. A first terminal of the lower bridge switch is connected to a second terminal of the upper bridge switch. The second terminal of the lower bridge switch is grounded. The node between the first terminal of the lower bridge switch and the second terminal of the upper bridge switch is connected to a first terminal of an inductor. The second terminal of the inductor is connected to a first terminal of an output capacitor. The second terminal of the output capacitor is grounded. The control terminal of the lower bridge switch is connected to the drive circuit. The lower bridge switch turns on or off according to the lower bridge turn-on signal received from the drive circuit. The oscillation circuit receives the upper bridge conduction signal from the drive circuit and determines whether to adjust the clock signal output to the control circuit based on the upper bridge conduction signal.

[0004] In an embodiment, when the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit modulates the frequency of the clock signal.

[0005] In this embodiment, when the time point at which the upper bridge conduction signal transitions from a high level to a low level is no later than the time point at which the clock signal transitions, the oscillation circuit does not modulate the clock signal.

[0006] In an embodiment, when the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit reduces the frequency of the clock signal.

[0007] In an embodiment, when the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit delays the time point at which the clock signal pulse appears until after the time point at which the upper bridge conduction signal transitions from a high level to a low level.

[0008] In this embodiment, the transition time point is the falling edge of the clock signal.

[0009] In this embodiment, the oscillation circuit includes a comparator. The first input of the comparator is connected to the first terminal of an input capacitor. The first terminal of the input capacitor is connected to a current source. The second terminal of the input capacitor is grounded. The second input of the comparator is coupled to a reference voltage. The third input of the comparator is connected to the output of a drive circuit to receive an upper bridge turn-on signal. The output of the comparator is connected to the input of a control circuit and outputs a clock signal to the control circuit.

[0010] In this embodiment, the oscillation circuit further includes a voltage divider circuit. The input terminal of the voltage divider circuit is coupled to the input voltage. The output terminal of the voltage divider circuit is connected to the second input terminal of the comparator.

[0011] In this embodiment, the voltage divider circuit includes a first resistor and a second resistor. A first terminal of the first resistor is coupled to the input voltage. A second terminal of the first resistor is connected to the first terminal of the second resistor. A second terminal of the second resistor is grounded. The node between the second terminal of the first resistor and the first terminal of the second resistor is connected to the second input terminal of a comparator.

[0012] In one embodiment, the power converter with a smooth transition control mechanism further includes an error amplifier. The first input terminal of the error amplifier is connected to the node between the second terminal of the inductor and the first terminal of the output capacitor. The second input terminal of the error amplifier is coupled to a reference voltage. The output terminal of the error amplifier is connected to a control circuit, which outputs a control signal based on an error amplification signal output by the error amplifier.

[0013] As described above, the present invention provides a power converter with a smooth transition control mechanism, which can appropriately modulate the frequency of the clock signal according to the amount of energy required by the power supply. The control circuit controls the drive circuit to open or close the upper bridge switch and the lower bridge switch in real time based on the frequency of the modulated clock signal, so as to effectively prevent large ripples in the output signal of the power converter, thereby keeping the output voltage of the power converter stable and preventing it from dropping to a low value.

[0014] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0015] Figure 1This is a block diagram of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0016] Figure 2 This is a block diagram of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0017] Figure 3 This is a flowchart illustrating the steps of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0018] Figure 4 The waveform diagram shows the signal of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0019] Figure 5 This is a waveform diagram of the signal from a traditional power converter. Detailed Implementation

[0020] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0021] Please see Figure 1 and Figure 3 ,in Figure 1 This is a block diagram of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0022] The power converter with a smooth transition control mechanism in this embodiment may include, for example: Figure 1 The diagram shows an oscillation circuit 100, a control circuit 200, a drive circuit 300, an upper bridge switch UG, and a lower bridge switch LG. The control circuit 200 can be connected to the oscillation circuit 100 and the drive circuit 300. The drive circuit 300 can be connected to the control terminals of the upper bridge switch UG, the lower bridge switch LG, and the oscillation circuit 100.

[0023] The first terminal of the upper bridge switch UG is coupled to the shared voltage VCC. The first terminal of the lower bridge switch LG can be connected to the second terminal of the upper bridge switch UG. The second terminal of the lower bridge switch LG can be grounded. The node LX between the first terminal of the lower bridge switch LG and the second terminal of the upper bridge switch UG can be connected to the first terminal of the inductor L. The second terminal of the inductor L can be connected to the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout can be grounded. The node between the second terminal of the inductor L and the first terminal of the output capacitor Cout can be the output terminal of the power converter and supply the output voltage VOUT.

[0024] like Figure 3 The steps S101 to S111 shown can be applied to the smooth transition control mechanism of the power converter in this embodiment, as explained in detail below.

[0025] In step S101, the power converter is powered on.

[0026] In step S103, the oscillation circuit 100 outputs a clock signal CLK to the control circuit 200.

[0027] In step S105, the control circuit 200 outputs a control signal to the drive circuit 300 based on the clock signal CLK. The drive circuit 300 outputs a first-level (e.g., high-level) upper bridge turn-on signal UGS to the upper bridge switch UG to turn on the upper bridge switch UG, and outputs a second-level (e.g., low-level) lower bridge turn-on signal LGS to the lower bridge switch LG to turn off the lower bridge switch LG.

[0028] In step S107, it is determined whether the energy supplied by the power converter is sufficient for the operation of the electronic device connected to the power converter. If the energy supplied by the power converter is insufficient, step S105 is executed, the upper bridge switch UG is turned on, and the lower bridge switch LG is turned off. Conversely, if the energy supplied by the power converter is sufficient, step S109 is executed.

[0029] In step S109, the drive circuit 300 outputs a second-level (e.g., low-level) upper bridge turn-on signal UGS to the upper bridge switch UG to turn off the upper bridge switch UG, and outputs a first-level (e.g., high-level) lower bridge turn-on signal LG to the lower bridge switch LG to turn on the lower bridge switch LG.

[0030] It is worth noting that the oscillation circuit 100 can receive the upper bridge turn-on signal UGS from the drive circuit 300, and can determine whether to modulate the clock signal CLK output to the control circuit based on the upper bridge turn-on signal UGS, so as to change the on-time length of the upper bridge switch UG and the lower bridge switch LG. For example, the oscillation circuit 100 can adjust the frequency of the clock signal CLK, or adjust the timing of one or more pulses of the clock signal CLK.

[0031] For example, in step S111, the oscillation circuit 100 can determine whether the time point Tosc, when the upper bridge conduction signal UGS transitions from a high level to a low level, is later than the transition time point Tclk of the clock signal CLK pulse. In this embodiment, the transition time point Tclk of the clock signal CLK pulse can be the falling edge of the clock signal CLK, or in practice, the rising edge of the clock signal CLK.

[0032] If the oscillation circuit 100 determines that the time point Tosc of the upper bridge conduction signal UGS transitioning from the high level to the low level is not later than the transition time point Tclk of the pulse of the clock signal CLK, the oscillation circuit 100 will not adjust the frequency of the clock signal CLK.

[0033] Conversely, if the oscillation circuit 100 determines that the time point Tosc of the upper bridge conduction signal UGS transitioning from the high level to the low level is later than the time point Tclk of the pulse of the clock signal CLK, the oscillation circuit 100 can adjust the frequency of the clock signal CLK, for example, the oscillation circuit 100 can reduce the frequency of the clock signal CLK.

[0034] When the oscillation circuit 100 determines that the time point Tosc of the upper bridge conduction signal UGS transitioning from a high level to a low level is later than the time point Tclk of the pulse of the clock signal CLK, the oscillation circuit 100 can delay the time point of this pulse of the clock signal CLK until after the time point when the upper bridge conduction signal UGS transitions from a high level to a low level.

[0035] Please see Figure 2 This is a block diagram of a power converter with a smooth transition control mechanism according to an embodiment of the present invention.

[0036] The oscillation circuit 100 included in the power converter of this embodiment may include a comparator CMP, a current source SC, and an input capacitor Cin.

[0037] The first input terminal of comparator CMP, such as the non-inverting input terminal, can be connected to the first terminal of input capacitor Cin. The first terminal of input capacitor Cin can be connected to current source SC. The second terminal of input capacitor Cin can be grounded. The second input terminal of comparator CMP, such as the inverting input terminal, can be coupled to a reference voltage.

[0038] If necessary, the oscillator circuit 100 may also include a voltage divider circuit DVR. The input terminal of the voltage divider circuit DVR is coupled to the input voltage VIN. The output terminal of the voltage divider circuit DVR is connected to the second input terminal of the comparator CMP. The voltage divider circuit DVR can output the aforementioned reference voltage to the second input terminal of the comparator CMP, such as the inverting input terminal.

[0039] For example, a voltage divider circuit DVR may include a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 is coupled to the input voltage VIN. The second terminal of the first resistor R1 can be connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 can be grounded. The node between the second terminal of the first resistor R1 and the first terminal of the second resistor R2 can be connected to the second input terminal of a comparator CMP. The voltage at the node between the second terminal of the first resistor R1 and the first terminal of the second resistor R2 can be a reference voltage coupled to the second input terminal of the aforementioned comparator CMP, such as the inverting input terminal.

[0040] It is worth noting that the third input terminal of the comparator CMP can be connected to the output terminal of the driver circuit 300 to receive the upper bridge conduction signal UGS. The output terminal of the comparator CMP can be connected to the input terminal of the control circuit 200. The comparator CMP can output a clock signal CLK to the control circuit 200 based on the voltage at the first input terminal of the comparator CMP, the voltage at the second input terminal of the comparator CMP, and the upper bridge conduction signal UGS.

[0041] The power converter in this embodiment may include a feedback circuit to feed back the output voltage Vout of the power converter (or other relevant data such as a voltage divider of the output voltage Vout) to the control circuit 200. For example, the feedback circuit may include an error amplifier ER. The first input terminal of the error amplifier ER (e.g., a non-inverting input terminal) may be connected to the node between the second terminal of the inductor L and the first terminal of the output capacitor Cout. The second input terminal of the error amplifier ER (e.g., an inverting input terminal) may be coupled to a reference voltage Vref. The output terminal of the error amplifier ER may be connected to an input terminal of the control circuit 200.

[0042] Error amplifier ER amplifies the difference between the voltage at its first input terminal and the voltage at its second input terminal to output an amplified error signal to control circuit 200. Control circuit 200 outputs a control signal to drive circuit 300 based on the amplified error signal received from error amplifier ER and the clock signal CLK received from comparator CMP of oscillation circuit 100.

[0043] Please see Figure 1 , Figure 4 and Figure 5 ,in Figure 4 The waveform diagram is shown for the power converter with a smooth transition control mechanism according to an embodiment of the present invention. Figure 5 This is a waveform diagram of the signal from a traditional power converter.

[0044] like Figure 5As shown, VIN represents the input voltage of the conventional power converter, VOUT0 represents the output voltage of the conventional power converter, IL0 represents the current of the inductor of the conventional power converter, LXS0 represents the node signal between the second terminal of the upper bridge switch and the first terminal of the lower bridge switch of the conventional power converter, CLK0 represents the clock signal of the conventional power converter, ES0 represents the error amplification signal of the error amplifier of the conventional power converter, and LFS0 represents the energy signal of the node between the second terminal of the upper bridge switch and the first terminal of the lower bridge switch of the conventional power converter.

[0045] like Figure 5 As shown, the clock signal CLK0 of the traditional power converter has a fixed frequency, which causes the turn-off time of the signal LFS0 of the traditional power converter to vary randomly with energy, resulting in a large ripple in the output voltage VOUT0 of the traditional power converter.

[0046] like Figure 4 As shown, VIN represents the input voltage of the power converter of the present invention, VOUT represents the output voltage of the power converter of the present invention, IL represents the current of the inductor L of the power converter of the present invention, LXS represents the node signal of node LX between the second terminal of the upper bridge switch UG and the first terminal of the lower bridge switch LG of the power converter of the present invention, CLK represents the clock signal received by the control circuit 200 of the power converter of the present invention from the oscillation circuit 100, ES represents the error amplification signal of the error amplifier ER of the power converter of the present invention, and LFS represents the energy signal of node LX between the second terminal of the upper bridge switch UG and the first terminal of the lower bridge switch LG of the power converter of the present invention.

[0047] like Figure 4 As shown, when the time required for the node signal LXS of the power converter to supply sufficient energy (i.e., the time the upper bridge switch UG needs to remain on) is greater than the interval between the two pulses of the clock signal CLK, the oscillation circuit 100 reduces the frequency of the clock signal CLK supplied to the control circuit 200. That is, the frequency of the clock signal CLK is no longer a constant value, making the off-time of the energy signal LFS a constant value. As a result, the output voltage VOUT of the power converter is stable and has low ripple.

[0048] In summary, the present invention provides a power converter with a smooth transition control mechanism, which can appropriately modulate the frequency of the clock signal according to the amount of energy required by the power supply. The control circuit controls the drive circuit to open or close the upper bridge switch and the lower bridge switch in real time based on the frequency of the modulated clock signal, so as to effectively prevent large ripples in the output signal of the power converter, thereby keeping the output voltage of the power converter stable and preventing it from dropping to a low value.

[0049] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0050] The above-disclosed content is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power converter with a smooth transition control mechanism, characterized in that, The power converter with a smooth transition control mechanism includes: An oscillating circuit configured to output a clock signal; A control circuit, connected to the oscillation circuit, configured to receive the clock signal from the oscillation circuit and output a control signal based on the clock signal; A driving circuit, connected to the control circuit and the oscillation circuit, is configured to output an upper bridge conduction signal and a lower bridge conduction signal according to the control signal; An upper bridge switch, the first terminal of which is coupled to a shared voltage, the control terminal of which is connected to the drive circuit, and the upper bridge switch is turned on or off according to the upper bridge conduction signal received from the drive circuit; as well as A lower bridge switch is provided, wherein the first end of the lower bridge switch is connected to the second end of the upper bridge switch, the second end of the lower bridge switch is grounded, the node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor, the second end of the inductor is connected to the first end of an output capacitor, the second end of the output capacitor is grounded, the control terminal of the lower bridge switch is connected to the drive circuit, and the lower bridge switch is turned on or off according to the lower bridge conduction signal received from the drive circuit. The oscillation circuit receives the upper bridge conduction signal from the driving circuit and determines whether to adjust the clock signal output to the control circuit based on the upper bridge conduction signal. The oscillation circuit includes a comparator. The first input terminal of the comparator is connected to the first terminal of an input capacitor, the first terminal of the input capacitor is connected to a current source, the second terminal of the input capacitor is grounded, the second input terminal of the comparator is coupled to a reference voltage, the third input terminal of the comparator is connected to the output terminal of the drive circuit to receive the upper bridge conduction signal, and the output terminal of the comparator is connected to the input terminal of the control circuit and outputs the clock signal to the control circuit.

2. The power converter with a smooth transition control mechanism according to claim 1, characterized in that, When the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit modulates the frequency of the clock signal.

3. The power converter with a smooth transition control mechanism according to claim 2, characterized in that, When the time point at which the upper bridge conduction signal transitions from a high level to a low level is no later than the transition time point of the clock signal, the oscillation circuit does not modulate the clock signal.

4. The power converter with a smooth transition control mechanism according to claim 2, characterized in that, When the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit reduces the frequency of the clock signal.

5. The power converter with a smooth transition control mechanism according to claim 2, characterized in that, When the time point at which the upper bridge conduction signal transitions from a high level to a low level is later than the time point at which the clock signal transitions, the oscillation circuit delays the time point at which the pulse of the clock signal appears until after the time point at which the upper bridge conduction signal transitions from a high level to a low level.

6. The power converter with a smooth transition control mechanism according to claim 2, characterized in that, The transition time point is the falling edge of the clock signal.

7. The power converter with a smooth transition control mechanism according to claim 1, characterized in that, The oscillation circuit also includes a voltage divider circuit, the input of which is coupled to an input voltage, and the output of which is connected to the second input of the comparator.

8. The power converter with a smooth transition control mechanism according to claim 7, characterized in that, The voltage divider circuit includes a first resistor and a second resistor. A first end of the first resistor is coupled to the input voltage. A second end of the first resistor is connected to the first end of the second resistor. A second end of the second resistor is grounded. The node between the second end of the first resistor and the first end of the second resistor is connected to the second input terminal of the comparator.

9. The power converter with a smooth transition control mechanism according to claim 1, characterized in that, The power converter with a smooth transition control mechanism also includes an error amplifier. The first input terminal of the error amplifier is connected to the node between the second terminal of the inductor and the first terminal of the output capacitor. The second input terminal of the error amplifier is coupled to the reference voltage. The output terminal of the error amplifier is connected to the control circuit. The control circuit outputs the control signal based on the error amplification signal output by the error amplifier.

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