An anti-interference one-line communication receiving method and system based on Schmitt trigger

Abstract

The present invention provides an anti-interference one-line communication receiving method and system based on a Schmitt trigger, which belongs to the field of electric vehicle charging information communication technology. It solves the problem of high difficulty in identifying low-level logic 0 in existing communication receiving systems. The communication receiving method includes S1, real-time acquisition of the logic level of the square wave signal of the IO port on the MCU equipped with a Schmitt trigger, while the timer counts and records it as time T0; S2, when the rising edge or falling edge of the square wave signal is acquired, the logic level on the IO port and the time T0 are first acquired and saved as the cycle time T, and a delay interrupt of a fixed time Ts is executed, and the IO port is no longer acquired, and the timing is continued; S3, after a fixed time Ts delay, acquisition is performed again, and it is determined whether the logic level acquired again is valid. The communication receiving method has the advantages of being able to identify the difficulty of low-level logic 0 and having good anti-interference ability against noise.

Description

Technical Field

[0001] The present invention belongs to the technical field of electric vehicle charging information communication, and relates to an anti-interference one-line communication receiving method based on a Schmitt trigger. Background Art

[0002] Currently, in the electric vehicle industry, hardware designs include designs where the transmitter and receiver circuits use two IO ports, one for input and one for output. Alternatively, a single IO port is multiplexed, with the transmit and receive functions time-shared by switching the IO port's input and output settings. To save costs, a single IO port is often used in practice for both the transmit and receive ends of a single-line communication signal. This bidirectional, simplex communication method meets communication requirements while also saving costs. In practical applications, this method is often used for information communication between the charger, battery management system (BMS), and controller. This single-line communication utilizes the internationally standard SIF communication protocol, with logic levels conforming to TTL specifications.

[0003] TTL (Transistor-Transistor Logic) structure mostly uses Vcc 5V. Taking Vcc 5V as an example, the port input level logic is: 0V≤VL≤0.8V, 2V≤VH≤5V; that is, the input signal is greater than 2V as a high level representing logic 1, and less than 0.8V as a low level representing logic 0. When the level is between 0.8V and 2V, the logic cannot be determined, such as Figure 2 shown.

[0004] In a one-line communication application, a communication line is used to transmit square wave signals, and the information unit carried is expressed by pulse time width (hereinafter referred to as width) or width ratio, such as Figure 1 As shown in the figure, by using the time width or width ratio of T1 and T2, plus the pre-agreed definition (protocol), information such as start, stop, bit information 1, bit information 0, etc. can be interpreted, thereby achieving the purpose of transmitting communication. Its typical simplified circuit is as follows Figure 3 As shown in FIG, when there is only one fixed connection communication between sending and receiving, the isolation diode D1 is not designed into the circuit. The isolation diode D1 is designed into the circuit only when multiple independent nodes are connected and communicated, such as Figure 4As shown, one node transmits and two nodes receive. If, in a connected state, receiving node 1 (without isolation diode D1) is unpowered (5V not working), the circuit in node 1 will pull the voltage level on the one-line bus down, preventing receiving node 2 on the bus from receiving the communication data. Therefore, isolation diode D1 is necessary to isolate the unpowered device from affecting the bus, while capacitor C1 filters out noise on the communication signal line. However, in actual operation, the following problem still exists: when using isolation diode D1, due to the voltage difference between the diodes (minimum 0.4V), a logic 0 signal sent on the external one-line signal, such as a signal with a minimum voltage level of 0V, will be transmitted to the MCU's IO pin at a minimum level of 0.4V when transmitted through the above circuit. This reduces the recognizable low-level range from 0V≤VL≤0.8V to 0.4V≤VL≤0.8V. Moreover, as a sending node, there is always a hardware circuit to implement the transmission of high and low level logic. The low level controlled by the circuit is no longer an absolute 0V, and there will be a voltage of several tenths of a volt, generally 0.2V-0.4V. Taking the minimum 0.2V, plus the voltage difference of 0.4V of the isolation diode D1, the low level space that the receiver can recognize as logic 0 is compressed to 0.6V≤VL≤0.8V, and the recognition space becomes narrower; if there is noise interference on the one-line communication bus causing level fluctuations, it will also increase the difficulty of recognizing the low-level logic 0, or even make it impossible to recognize it. At the same time, different capacitance values ​​of capacitor C1 have applicable filtering frequency bands, such as: 0.1uf is suitable for 10K-100K Hz frequency band, 10nf is suitable for 100K-1M Hz frequency band, 1nf is suitable for 1M-10M Hz frequency band. The filtering frequency band bandwidth of capacitor C1 in the circuit is limited, so it is bound to be unable to completely filter out the clutter on the one-line communication bus, and it will receive certain clutter interference, which will cause the level fluctuations mentioned above, and will increase the difficulty of identifying low-level logic 0, or even make it impossible to identify it. In order to achieve wider frequency band filtering, it is necessary to increase the filtering circuit and printed circuit board space, causing the product cost to rise, and it is also impossible to completely eliminate clutter. At the same time, if the capacitance value of capacitor C1 increases, it will cause the rising edge clipping of the communication signal square wave to be too large (such as Figure 5 This delay delays the reception of high-level signals, affecting the acquisition and measurement of the high-level width T2. Therefore, specific communication protocols often impose maximum time requirements for this rise delay based on the duration of T2. This requirement places a maximum value constraint on filter capacitor C1 in circuit design, making it impossible to achieve unlimited wideband filtering through hardware design. Summary of the Invention

[0005] The purpose of the present invention is to solve the above technical problems and propose an anti-interference one-line communication receiving method based on Schmitt trigger.

[0006] The object of the present invention can be achieved by the following technical solution: A Schmitt trigger-based anti-interference one-line communication receiving method, characterized in that it includes the following steps:

[0007] S1, collect the logic level of the square wave signal of the IO port on the MCU equipped with a Schmitt trigger in real time, and at the same time, the timer counts and records it as time T0;

[0008] S2. When the rising edge or falling edge of the square wave signal is collected, the logic level on the IO port and the time T0 are collected and saved as the cycle time T. Then, the external delay interrupt program is executed to perform a delay interrupt of a fixed time Ts. During the delay interrupt, the logic level of the IO port is no longer collected, and the timer continues to count.

[0009] S3, after a fixed time delay Ts, the logic level of the IO port is collected again, and it is determined whether the re-collected logic level is valid;

[0010] If the judgment is invalid, the cycle time T saved in step S2 is automatically abandoned, and the external delay interrupt program is exited, and then the communication work is continued according to step S1;

[0011] If the judgment is valid, the logic level, cycle time T1 and current timer time T collected and saved in step S2 are normally saved and interpreted, the timer continues to count and the communication work continues according to step S1;

[0012] Among them, judging whether the logic level collected again is valid is specifically as follows: if the collected logic level is consistent with the logic level saved in step S2, it is determined to be valid; otherwise, it is determined to be invalid; the normal storage and interpretation of the time T of the current timer is specifically as follows: the time value after subtracting the cycle time T in step S2 from the time T0 of the current timer is assigned to the time T0 of the current timer and the timing is continued on this basis.

[0013] In the above-mentioned anti-interference one-line communication receiving method based on a Schmitt trigger, the timer is configured as a timer for performing frequency division counting on a system clock.

[0014] In the above-mentioned anti-interference one-line communication receiving method based on Schmitt trigger, the fixed time period Ts in step S2 can be adjusted according to actual conditions.

[0015] In the above-mentioned anti-interference one-line communication receiving method based on Schmitt trigger, the logic level is a high level or a low level.

[0016] In the above-mentioned anti-interference one-line communication receiving method based on Schmitt trigger, the step S1 is preceded by a setting step, specifically: setting the port corresponding to the one-line transmitting and receiving to the digital signal receiving mode, and setting the IO port to the external interrupt receiving port, and the interrupt mode to the rising edge and falling edge trigger mode.

[0017] An anti-interference one-line communication receiving system based on a Schmitt trigger, including an MCU on a charger and a battery, characterized in that: it also includes a Schmitt trigger, the Schmitt trigger is connected between the charger and the IO port on the MCU, the MCU includes a timer, a timer, a collection unit, a storage unit and a processing unit, the collection unit is used to collect the logic level signal of the IO port on the MCU and feed the logic level signal back to the processing unit; the timer is used to count and record it as time T0; the timer is used to time the time TS; the storage unit is used to store the above-mentioned logic level, the timing time T0 and the delay interrupt program; the processing unit is used to control the storage unit when receiving the rising edge or falling edge of the square wave signal fed back by the collection unit The element stores the currently collected IO port logic level and the above-mentioned timing time T0. At this time, the timing time T0 is stored as the cycle time T, and then the delayed interrupt program is executed to perform a delayed interrupt of a fixed time Ts. During the delayed interrupt, the control acquisition unit does not work, and after the delayed interrupt ends, the control acquisition unit collects the logic level of the IO port again, and makes a judgment on whether the validity is made according to the IO port logic level collected again. If it is judged to be invalid, the control storage unit automatically abandons the saved cycle time T, and exits the external delay interrupt program, and then controls to continue communication. If it is judged to be valid, the collected and saved logic level, cycle time T1 and the current timer timing time T are normally saved and interpreted, and the control timer continues timing and communication.

[0018] In the above-mentioned anti-interference one-line communication receiving system based on Schmitt trigger, the Schmitt trigger is an external Schmitt trigger circuit, or is integrated on an IO port.

[0019] In the above-mentioned anti-interference one-line communication receiving system based on the Schmitt trigger, the judgment of whether the IO port logic level collected again is valid is specifically: if the collected logic level is consistent with the logic level saved in the previous storage unit, it is judged to be valid; otherwise, it is judged to be invalid.

[0020] In the above-mentioned anti-interference one-line communication receiving system based on Schmitt trigger, the normal storage and interpretation of the time T of the current timer is specifically: the time value after subtracting the cycle time T from the time T0 of the current timer is assigned to the time T0 of the current timer and the timing is continued on this basis.

[0021] In the above-mentioned anti-interference one-line communication receiving system based on a Schmitt trigger, the timer is configured as a timer for performing frequency division counting on the system clock.

[0022] Compared with the existing technology, the anti-interference first-line communication receiving system and method has the following advantages:

[0023] 1. Using a Schmitt trigger for triggering can increase the low-level logic threshold that can be recognized by the MCU's IO terminal logic 0. For example, at a voltage of 5V, its low-level logic threshold can be increased to 1.5V, which greatly broadens the recognition space and reduces the difficulty of recognition. At the same time, the Schmitt trigger also has a certain ability to resist clutter interference, which also reduces clutter interference to a certain extent, thereby reducing the difficulty of identifying low-level logic levels.

[0024] 2. When a trigger signal (rising edge or falling edge) is detected, the delayed interrupt program is executed. At this time, the acquisition unit no longer collects the logic level of the I0 port, which means that the noise interference on the IO port during this period will not be read. Since the noise interference on the IO port will not be interrupted in the interrupt response program, the effect of software filtering is achieved. By performing noise filtering through software filtering, there is no need to increase the capacitance value of capacitor C1 to avoid excessive clipping on the rising edge of the communication signal square wave; at the same time, there is no need to add capacitor circuits and printed circuit boards, thereby reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the time width or width ratio of square wave signals T1 and T2 transmitted using a communication line.

[0026] Figure 2 This is the TTL (Transistor-Transisitor Logic) structure diagram.

[0027] Figure 3 This is a simplified circuit diagram that uses a communication line to transmit a square wave signal.

[0028] Figure 4 This is a circuit diagram with two nodes that uses a communication line to transmit a square wave signal.

[0029] Figure 5 yes Figure 1 The waveform diagram shows that the rising edge of the communication signal square wave is clipped too much.

[0030] Figure 6 This is a flow chart of the anti-interference one-line communication receiving method based on Schmitt trigger.

[0031] Figure 7This is the principle block diagram of the anti-interference first-line communication receiving system based on Schmitt trigger.

[0032] Figure 8 yes Figure 2 Schematic diagram of the waveform after level logic improvement. DETAILED DESCRIPTION

[0033] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solutions of the present invention, but the present invention is not limited to these embodiments.

[0034] Example 1

[0035] like Figure 6 As shown, the anti-interference one-line communication receiving method based on the Schmitt trigger includes the following steps:

[0036] S1, collect the logic level of the square wave signal of the IO port on the MCU equipped with a Schmitt trigger in real time, and at the same time, the timer counts and records it as time T0;

[0037] S2. When the rising edge or falling edge of the square wave signal is collected, the logic level on the IO port and the time T0 are collected and saved as the cycle time T. Then, the external delay interrupt program is executed to perform a delay interrupt of a fixed time Ts. During the delay interrupt, the logic level of the IO port is no longer collected, and the timer continues to count.

[0038] S3, after a fixed time delay Ts, the logic level of the IO port is collected again, and it is determined whether the re-collected logic level is valid;

[0039] If the judgment is invalid, the cycle time T saved in step S2 is automatically abandoned, and the external delay interrupt program is exited, and then the communication work is continued according to step S1;

[0040] If the judgment is valid, the logic level, cycle time T1 and current timer time T collected and saved in step S2 are normally saved and interpreted, the timer continues to count and the communication work continues according to step S1;

[0041] Among them, judging whether the logic level collected again is valid is specifically as follows: if the collected logic level is consistent with the logic level saved in step S2, it means that the logic levels of the IO ports before and after a fixed time Ts are the same, indicating that what is collected in step S2 is indeed the rising edge or falling edge of the square wave signal rather than the interference triggered by the noise, then it is determined to be valid, and the logic level is high or low. For example, after step S2 collects the rising edge, the high level detected at this time is stored. After a fixed time Ts, if the IO port is still high when it is collected again, it is determined to be valid and it is indeed a rising edge. Then the square wave crosses from a low level. If the current timer reaches a high level, the previously measured time T0 is the low level width T1 in the entire square wave cycle. Otherwise, it is a level jump caused by noise, not a true rising or falling edge, and is judged invalid. The current timer time T is normally saved and interpreted as follows: the time value after subtracting the cycle time T in step S2 from the current timer time T0 is assigned to the current timer time T0 and continues timing based on this. Since timers are all timing continuously, when accurately calculating the high and low level widths in a square wave cycle, it is necessary to subtract the time T of the previous cycle to obtain the cumulative timing time of the current cycle. The fixed time Ts can be adjusted according to actual conditions.

[0042] The Schmitt trigger is an external Schmitt trigger circuit or integrated on an IO port.

[0043] In electronics, a Schmitt trigger is a comparator circuit with positive feedback. Unlike ordinary gate circuits, a Schmitt trigger has two threshold voltages: a positive threshold voltage and a negative threshold voltage. The positive threshold voltage is the input voltage that causes the circuit to change state when the input signal rises from a low level to a high level, while the negative threshold voltage is the input voltage that causes the circuit to change state when the input signal falls from a high level to a low level. The difference between the positive and negative threshold voltages is called the hysteresis voltage.

[0044] For a standard Schmitt trigger, the output is high when the input voltage is above the positive-going threshold voltage; low when the input voltage is below the negative-going threshold voltage; and the output remains unchanged when the input is between the positive and negative threshold voltages. In other words, the threshold voltages corresponding to the output switching from a high-level to a low-level, or vice versa, are different. The output changes only when the input voltage changes sufficiently, hence the name trigger. This dual-threshold behavior is known as hysteresis, indicating that the Schmitt trigger has memory. Essentially, the Schmitt trigger is a bistable multivibrator. The Schmitt trigger can be used as a waveform shaping circuit, shaping analog signal waveforms into square waves that digital circuits can process. Furthermore, due to its hysteresis characteristic, the Schmitt trigger can be used for interference suppression, reducing noise interference to a certain extent and making it easier to identify low-level logic levels.

[0045] By properly configuring the resistance value in the Schmitt trigger application, the level logic under 5V power supply is improved as follows Figure 8 As shown, when the input voltage of the Schmitt trigger is above 3.5V, the output logic is high; when the input voltage is below 1.5V, the output logic becomes low; and when the input voltage is between 1.5V and 3.5V, the output logic remains unchanged. In other words, the output logic changes only when the input voltage changes sufficiently. This allows communication signals to transmit data at a reasonable level within the 5V voltage range. Raising the low-level logic threshold voltage to 1.5V opens up new possibilities for circuit design at each node in the communication. This significantly broadens the recognition range and reduces the difficulty compared to existing technologies.

[0046] Furthermore, step S1 includes a setting step before it, specifically: setting the port corresponding to the one-line transmission and reception to digital signal receiving mode, and setting the IO port to an external interrupt receiving port, and the interrupt mode to rising edge and falling edge trigger mode. The timer is configured as a timer that divides and counts the system clock, which is used to measure the width of the square wave pulse in the one-line communication. Usually, the counting period after frequency division is set to 1 microsecond, and the timer is selected to be 16 bits, so that the square wave pulse width between 1 microsecond and 65.5ms can be measured. The timing accuracy and length are specifically adjusted according to the definition of the communication protocol. The operation of the timer is controlled by the IO port edge trigger interrupt program. After the MCU port (represented by IO) and the timer (TIM0 is used as an example of the timer) are configured, the external interrupt enable bit of the IO is turned on, the timer TIM0 is cleared, the status word is cleared, and the one-line communication is waited for.

[0047] This method designs a set of software and hardware combination methods, using software delay filtering to prevent the influence of interference signals; based on the former, the real-time pulse width measurement method is used to collect pulse widths and calculate width ratios, so that data can be interpreted efficiently and reliably. The specific method is as follows:

[0048] In terms of system design, the MCU uses external interrupts to collect square wave signals from the communication IO port. The interrupt is set to edge trigger mode (rising and falling edges). When a trigger signal (rising or falling edge) is detected, the delayed interrupt program is executed. At this time, the acquisition unit no longer collects the logic level of the I0 port, which means that the noise interference on the IO port during this period will not be read. Since the interrupt response program is also within the interrupt response, the noise interference on the IO port will not be interrupted, thus achieving the effect of software filtering. By performing noise filtering through software filtering, the capacitance value of capacitor C1 is not increased to avoid excessive clipping on the rising edge of the communication signal square wave. At the same time, there is no need to add capacitor circuits and printed circuit boards, thus reducing product costs. Through this method, the T1 / T2 phase period of the square wave can be accurately collected, laying a good foundation for subsequent data interpretation.

[0049] At the same time, existing Figure 3 In streamlined circuits, MCUs often use a method of querying IO port level logic to collect communication signals in their on-line communication software design. System time allocation involves either scheduled or off-time query collection. To improve accuracy, this query collection calculates a collection period based on the minimum width of the transmitted signal. Multiple sampling cycles and algorithms are then combined to interpret the correct communication data. Since data is transmitted continuously, clock deviations between the transmitting MPU and receiving MCU systems, as well as physical effects during transmission, can cause errors in data pulse width. This pre-planned time-based collection method, coupled with continuous sampling and interpretation of continuous data, can easily lead to excessive error accumulation, resulting in high bit error rates. Some on-line communication systems also use ratios for transmission, such as T2 / T1 or T2 / (T1+T2). In these systems, the requirements for the T1 and T2 pulse widths at each node are less stringent, allowing for a wider error range. Deciphering systems that transmit information using ratios poses significant challenges for algorithms using simple query collection methods. However, this method starts measuring the period of the square wave T1 / T2 phase from the level jump, without the error accumulation caused by the clock asynchrony between the sending end and the receiving end, so that accurate acquisition can be achieved to overcome the above-mentioned problems.

[0050] In the electric bicycle industry, lithium-ion battery chargers using this technology save space on the PCB layout, use minimal peripheral components, and save costs. Regarding MCU selection, the timing acquisition method requires a high-speed single-chip microcomputer to implement. However, using this method, an inexpensive, cost-effective 8-bit single-chip microcomputer can be selected, thereby reducing hardware costs and increasing the product's industry competitiveness. Compared with existing products, it is more compatible. For example, if a communication system contains two or more proportional pulse widths, it is difficult to implement them through hardware and it is difficult to achieve compatibility. However, this method uses a set of algorithms to basically cover all aspects (calculating time length or ratio), saving code space. Not only does it provide adaptive data interpretation, but it can also interpret other constraints in the communication definition, enhancing the reliability of communication data interpretation.

[0051] Example 2

[0052] like Figure 7 As shown, the anti-interference one-line communication receiving system based on the Schmitt trigger includes an MCU on the charger and the battery, and also includes a Schmitt trigger. The Schmitt trigger is connected between the charger and the IO port on the MCU. The Schmitt trigger of this embodiment is an external Schmitt trigger circuit. Of course, in order to save the printed circuit board space brought by the external Schmitt trigger circuit, the Schmitt trigger can also be integrated on the IO port.

[0053] The MCU includes a timer, a timer, a collection unit, a storage unit, and a processing unit. The collection unit is used to collect the logic level signal of the IO port on the MCU and feed the logic level signal back to the processing unit; the timer is used to count and record it as time T0; the timer is used to time the fixed time TS and is configured as a timer for dividing and counting the system clock; the storage unit is used to store the above-mentioned logic level, timing time T0, and delay interrupt program; the processing unit is used to control the storage unit to store the currently collected IO port logic level and the above-mentioned timing time T0 when receiving the rising or falling edge of the square wave signal fed back by the collection unit. At this time, the timing time T0 is stored as the cycle time T, and then Execute the delay interrupt program to perform a delay interrupt of a fixed time Ts. During the delay interrupt, the control acquisition unit does not work, and after the delay interrupt ends, the control acquisition unit collects the logic level of the IO port again, and makes a judgment on whether it is valid based on the logic level of the IO port collected again. If it is judged to be invalid, the control storage unit automatically abandons the saved cycle time T, and exits the external delay interrupt program, and then controls to continue communication. If it is judged to be valid, the collected and saved logic level, cycle time T1 and the current timer timing time T are normally saved and interpreted, and the timer is controlled to continue timing and continue communication.

[0054] Among them, the judgment of whether the IO port logic level collected again is valid is specifically as follows: if the collected logic level is consistent with the logic level saved in the previous storage unit, it is judged to be valid; otherwise, it is judged to be invalid; the normal storage and interpretation of the time T of the current timer is specifically as follows: the time value after subtracting the cycle time T from the time T0 of the current timer is assigned to the time T0 of the current timer and the timing is continued on this basis.

[0055] The other working principles are the same as those in the first embodiment and will not be described again.

[0056] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described specific embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A Schmitt trigger-based anti-interference one-line communication receiving method, characterized in that: The steps include: S1, collect the logic level of the square wave signal of the IO port on the MCU equipped with a Schmitt trigger in real time, and at the same time, the timer counts and records it as time T0; S2. When the rising edge or falling edge of the square wave signal is collected, the logic level on the IO port and the time T0 are collected and saved as the cycle time T. Then, the external delay interrupt program is executed to perform a delay interrupt of a fixed time Ts. During the delay interrupt, the logic level of the IO port is no longer collected, and the timer continues to count. S3, after a fixed time delay Ts, the logic level of the IO port is collected again, and it is determined whether the re-collected logic level is valid; If the judgment is invalid, the cycle time T saved in step S2 is automatically abandoned, and the external delay interrupt program is exited, and then the communication work is continued according to step S1; If the judgment is valid, the logic level, cycle time T1 and current timer time T collected and saved in step S2 are normally saved and interpreted, the timer continues to count and the communication work continues according to step S1; Among them, judging whether the logic level collected again is valid is specifically as follows: if the collected logic level is consistent with the logic level saved in step S2, it is judged to be valid; otherwise, it is judged to be invalid; the normal storage and interpretation of the time T of the current timer is specifically as follows: the time value after subtracting the cycle time T in step S2 from the time T0 of the current timer is assigned to the time T0 of the current timer and the timing is continued on this basis.

2. The anti-interference one-line communication receiving method based on Schmitt trigger according to claim 1, characterized in that: The timer is configured as a timer for dividing and counting the system clock.

3. The anti-interference one-line communication receiving method based on Schmitt trigger according to claim 1 or 2, characterized in that: The fixed time period Ts in step S2 can be adjusted according to actual conditions.

4. The anti-interference one-line communication receiving method based on Schmitt trigger according to claim 3, characterized in that: The logic level is a high level or a low level.

5. The anti-interference one-line communication receiving method based on Schmitt trigger according to claim 4, characterized in that: The step S1 is preceded by a setting step, specifically: setting the port corresponding to the transceiver to a digital signal receiving mode, and setting the IO port to an external interrupt receiving port, with the interrupt mode being a rising edge and falling edge trigger mode.

6. An anti-interference one-line communication receiving system based on a Schmitt trigger, including an MCU on a charger and a battery, characterized by: The device further includes a Schmitt trigger connected between the charger and an IO port on the MCU. The MCU includes a timer, a timer, a collection unit, a storage unit, and a processing unit. The collection unit is used to collect a logic level signal from the IO port on the MCU and feed the logic level signal back to the processing unit. The timer is used to measure time and record it as time T0. The timer is used for timing the fixed time TS; the storage unit is used to store the above-mentioned logic level, timing time T0 and delay interrupt program; the processing unit is used to control the storage unit to store the currently collected IO port logic level and the above-mentioned timing time T0 when receiving the rising edge or falling edge of the square wave signal feedback from the acquisition unit. At this time, the timing time T0 is stored as the cycle time T, and then the delay interrupt program is executed to perform a delayed interrupt for the fixed time Ts. During the delay interrupt, the acquisition unit is controlled not to work, and after the delay interrupt ends, the acquisition unit is controlled to collect the logic level of the IO port again, and a judgment is made on whether the validity is made based on the IO port logic level collected again. If the judgment is invalid, the storage unit is controlled to automatically abandon the saved cycle time T and exit the external delay interrupt program, and then the communication work is controlled to continue. If the judgment is valid, the collected and saved logic level, cycle time T1 and the current timer timing time T are normally saved and interpreted, and the timer is controlled to continue timing and communication work.

7. The anti-interference one-line communication receiving system based on Schmitt trigger according to claim 6, characterized in that: The Schmitt trigger is an external Schmitt trigger circuit or is integrated on an IO port.

8. The anti-interference one-line communication receiving system based on Schmitt trigger according to claim 6 or 7, characterized in that: The determination of validity based on the re-collected IO port logic level is specifically: if the collected logic level is consistent with the logic level previously stored in the storage unit, it is determined to be valid; otherwise, it is determined to be invalid.

9. The anti-interference one-line communication receiving system based on Schmitt trigger according to claim 8, characterized in that: Normally saving and interpreting the time T counted by the current timer is as follows: assigning the time value obtained by subtracting the cycle time T from the time T0 counted by the current timer to the time T0 counted by the current timer and continuing to count on this basis.

10. The anti-interference one-line communication receiving system based on Schmitt trigger according to claim 9, characterized in that: The timer is configured as a timer for dividing and counting the system clock.

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