A full-duplex transceiving system and method based on latency configuration and self-interference mitigation

Abstract

The application discloses a full-duplex transceiving system and method based on time delay configuration and self-interference suppression, and the system comprises a transmitting device, a receiving device, an analog self-interference cancellation module, a clock module, a time delay parameter configuration module and a self-interference suppression module. First, the delay parameter is configured, the phase noise contained in the multipath self-interference component is partially compensated by making the receiving oscillator signal be emitted after the transmitting oscillator signal passes through a specific delay, then the phase noise coefficient is extracted, the self-interference channel response is estimated by using the extracted coefficient and the transmitting signal, and the self-interference suppression is carried out to compensate the residual phase noise. The self-interference suppression method has higher self-interference suppression capacity compared with the traditional self-interference suppression algorithm.

Description

Technical Field

[0001] This invention relates to self-interference suppression in full-duplex communication, and particularly to a full-duplex transceiver system and method based on delay configuration and self-interference suppression. Background Technology

[0002] To achieve high spectral efficiency, full-duplex (FD) technology has attracted research interest from both academia and industry. Employing full-duplex technology allows transceivers to simultaneously transmit and receive signals at the same carrier frequency, potentially doubling spectral efficiency. Furthermore, the advantages of full-duplex communication include lower feedback delay, lower end-to-end delay, and more flexible spectrum planning. However, the transmitted signal from a full-duplex transceiver will reach its local receiving antenna, where it will form a self-interference (SI) signal. If the SI signal and the desired signal (SOI) cannot be separated in the time or frequency domain, the SI signal will cause a sharp deterioration in the demodulation performance of the desired signal.

[0003] To mitigate this degradation, self-interference cancellation schemes can be employed in the spatial, analog, and digital domains. However, at higher transmission power levels, such as exceeding 40 dBm, considering a receiver noise floor of -90 dBm, self-interference can be 130 dB higher than the noise floor. In this case, the non-ideal characteristics of the hardware become more pronounced, and the self-interference components caused by these non-ideal characteristics increase. Since the traditional cancellation schemes mentioned above are not designed to suppress these self-interference components, they typically fail to achieve satisfactory results at high transmission power. As a typical non-ideal characteristic defect, the phase noise introduced by the local oscillator limits the maximum self-interference cancellation capability and becomes a major bottleneck in full-duplex communication. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a full-duplex transceiver system and method based on delay configuration and self-interference suppression.

[0005] The objective of this invention is achieved through the following technical solution: a full-duplex transceiver system based on delay configuration and self-interference suppression, comprising a transmitter, a receiver, a clock module, a delay parameter configuration module, and a self-interference suppression module;

[0006] The transmitter is used to convert the baseband digital transmission signal into an analog signal and then up-convert it to obtain a radio frequency signal for transmission.

[0007] The receiver includes a receiving antenna and N receiving channels. When the full-duplex transceiver system is operating in the delay parameter configuration phase, the receiver receives the signal transmitted by the transmitter through the receiving antenna, transmits the received signal to the first receiving channel for down-conversion and analog-to-digital conversion, and then transmits it to the delay parameter configuration module. When the full-duplex transceiver system is operating in the signal transmission and reception phase, the receiver receives the working signal through the receiving antenna and transmits it to each of the N receiving channels. After down-conversion and analog-to-digital conversion in each receiving channel, N baseband digital received signals are obtained and transmitted to the self-interference suppression module.

[0008] The delay parameter configuration module is used to calculate the delay parameter based on the signal output by the first receiving channel in the receiver during the delay parameter configuration stage, and to configure the clock module.

[0009] The clock module is used to provide an up-conversion signal to the transmitter, and during the delay parameter configuration phase, to provide a down-conversion signal to the first receiving channel of the receiver, and during the signal transmission and reception phase, to provide down-conversion signals to all receiving channels of the receiving device.

[0010] The self-interference suppression module is used to suppress self-interference using the signals from N receiving channels during the signal transmission and reception phase, thereby obtaining the self-interference suppressed received signal.

[0011] A full-duplex transceiver method based on delay configuration and self-interference suppression includes the following steps:

[0012] S1. When the full-duplex transceiver system is operating in the delay parameter configuration phase, the transmitter transmits a signal, and then the delay parameters are calculated based on the signal output from the first receiving channel in the receiver to configure the delay of each delay unit in the clock module:

[0013] S101. In the transmitter, the baseband digital transmission signal is converted from digital to analog and then transmitted to the upconversion module. In the upconversion module, the signal is mixed with the upconversion signal from the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna.

[0014] S102. The receiver receives the signal transmitted by the transmitter through the receiving antenna, sends the received signal into the first receiving channel, and mixes it with the down-conversion signal provided by the clock module in the down-conversion module of the receiving channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the delay parameter configuration module.

[0015] S103. The delay parameter configuration module estimates the self-interference channel response based on the baseband digital received signal, constructs a cancellation signal to cancel the self-interference signal, and then determines the delay parameter to configure the clock module based on the residual self-interference power and the self-interference channel response after self-interference signal cancellation.

[0016] S2. During the signal transmission and reception phase, based on the configured delay parameters, signal reception is performed and self-interference suppression is completed:

[0017] S201. In the transmitter, the baseband digital transmission signal is converted from digital to analog, and then the obtained signal is transmitted to the upconversion module. In the upconversion module, it is mixed with the upconversion signal provided by the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna.

[0018] S202. In the receiver, the working signal is received through the receiving antenna, and then the received signal is transmitted to each receiving channel of the receiver;

[0019] In the downconversion module of each receiving channel, the received signal is mixed with the downconversion signal provided by the clock module for that channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the self-interference suppression module.

[0020] S203. The self-interference suppression module uses the digital self-interference signal output from the receiving channel to suppress self-interference.

[0021] The beneficial effects of this invention are as follows: By delaying the transmission oscillator signal after a specific delay, this invention partially compensates for the phase noise contained in multipath self-interference components, thus achieving phase noise compensation during the transmission stage. Then, in signal processing, phase noise parameters are extracted, and the extracted coefficients and the transmitted signal are used to estimate the self-interference channel response, thereby suppressing the remaining phase noise. This self-interference suppression method, by utilizing phase noise parameters, can obtain an almost accurate self-interference channel response, reduce self-interference channel estimation errors, and thus improve self-interference suppression capabilities, enabling full-duplex transceivers to operate in high-power application scenarios. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the system principle of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0024] like Figure 1As shown, a full-duplex transceiver system based on delay configuration and self-interference suppression includes a transmitter, a receiver, a clock module, a delay parameter configuration module, and a self-interference suppression module.

[0025] The transmitter is used to convert the baseband digital transmission signal into an analog signal and then up-convert it to obtain a radio frequency signal for transmission.

[0026] The receiver includes a receiving antenna and N receiving channels. When the full-duplex transceiver system is operating in the delay parameter configuration phase, the receiver receives the signal transmitted by the transmitter through the receiving antenna, transmits the received signal to the first receiving channel for down-conversion and analog-to-digital conversion, and then transmits it to the delay parameter configuration module. When the full-duplex transceiver system is operating in the signal transmission and reception phase, the receiver receives the working signal through the receiving antenna and transmits it to each of the N receiving channels. After down-conversion and analog-to-digital conversion in each receiving channel, N baseband digital received signals are obtained and transmitted to the self-interference suppression module.

[0027] The delay parameter configuration module is used to calculate the delay parameter based on the signal output by the first receiving channel in the receiver during the delay parameter configuration stage, and to configure the clock module.

[0028] The clock module is used to provide an up-conversion signal to the transmitter, and during the delay parameter configuration phase, to provide a down-conversion signal to the first receiving channel of the receiver, and during the signal transmission and reception phase, to provide down-conversion signals to all receiving channels of the receiving device.

[0029] The self-interference suppression module is used to suppress self-interference using the signals from N receiving channels during the signal transmission and reception phase, thereby obtaining the self-interference suppressed received signal.

[0030] Furthermore, the transmitter includes a DAC module, an up-conversion module, and a transmitting antenna;

[0031] The input terminal of the DAC module is connected to the baseband digital transmission signal, the output terminal of the DAC module is connected to the first input terminal of the upconversion module, the second input terminal of the upconversion module is connected to the clock module that provides the upconversion signal, and the output terminal of the upconversion module is connected to the transmitting antenna, which transmits the signal output by the upconversion module to the outside.

[0032] Furthermore, each of the receiving channels includes a down-conversion module and an ADC module. The first input terminal of the down-conversion module is connected to the receiving antenna, the second output terminal of the down-conversion module is connected to the clock module that provides the down-conversion signal, the output terminal of the down-conversion module is connected to the ADC module, and the output terminal of the ADC module is connected to the self-interference suppression module.

[0033] In the first receiving channel of the receiver, the output of the ADC module is also connected to the delay parameter configuration module.

[0034] Furthermore, the clock module includes a local oscillator, delay unit d1 to delay unit d2. N The output of the local oscillator is connected to the up-conversion module of the transmitter to provide an up-converted signal to the transmitter.

[0035] The output of the local oscillator is also connected to delay unit d1, and delay unit d1 is also connected to delay units d2 through d3 respectively. N Connection, where delay d i The output terminal is used to provide the down-conversion signal for the i-th receiving channel in the receiver, i = 1, 2, ..., N; delay d2 ~ delay d N A switch is installed on the connection path between each delay unit and delay unit d1;

[0036] The delay parameter configuration module configures the clock module, that is, it configures the delay of each delay unit in the clock module.

[0037] In the embodiments of this application, during the delay parameter configuration stage, the delay devices d2 to d3 are... N All switches on the path connected to delay d1 are disconnected; during the signal transmission and reception phase, delay d2 to delay d... N All switches on the path connected to delayer d1 are closed.

[0038] A full-duplex transceiver method based on delay configuration and self-interference suppression includes the following steps:

[0039] S1. When the full-duplex transceiver system is operating in the delay parameter configuration phase, the transmitter transmits a signal, and then the delay parameters are calculated based on the signal output from the first receiving channel in the receiver to configure the delay of each delay unit in the clock module:

[0040] S101. In the transmitter, the baseband digital transmission signal is converted from digital to analog and then transmitted to the upconversion module. In the upconversion module, the signal is mixed with the upconversion signal from the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna.

[0041] S102. The receiver receives the signal transmitted by the transmitter through the receiving antenna, sends the received signal into the first receiving channel, and mixes it with the down-conversion signal provided by the clock module in the down-conversion module of the receiving channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the delay parameter configuration module.

[0042] S103. The delay parameter configuration module estimates the self-interference channel response based on the baseband digital received signal, constructs a cancellation signal to cancel the self-interference signal, and then determines the delay parameter to configure the clock module based on the residual self-interference power and the self-interference channel response after self-interference signal cancellation.

[0043] S2. During the signal transmission and reception phase, based on the configured delay parameters, signal reception is performed and self-interference suppression is completed:

[0044] S201. In the transmitter, the baseband digital transmission signal is converted from digital to analog, and then the obtained signal is transmitted to the upconversion module. In the upconversion module, it is mixed with the upconversion signal provided by the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna.

[0045] S202. In the receiver, the working signal is received through the receiving antenna, and then the received signal is transmitted to each receiving channel of the receiver;

[0046] In the downconversion module of each receiving channel, the received signal is mixed with the downconversion signal provided by the clock module for that channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the self-interference suppression module.

[0047] S203. The self-interference suppression module uses the digital self-interference signal output from the receiving channel to suppress self-interference.

[0048] In step S101, the up-conversion signal provided by the clock module is:

[0049] a T =exp{-j[2πf c [(t)+θ(t)]},

[0050] Where f c θ(t) and θ(t) are the carrier frequency and transmitter phase noise, respectively;

[0051] The radio frequency transmission signal obtained by upconversion is:

[0052]

[0053] Where x(t) is the baseband transmitted signal;

[0054] The radio frequency transmission signal is transmitted to the remote node via the antenna, and at the same time After passing through the self-interference channel h I (t) reaches the local receiver and becomes a self-interference signal. Therefore, the received signal at the antenna includes both the self-interference signal and the receiver noise, denoted as:

[0055]

[0056] Where n(t) is the receiver noise, L is the number of self-interference channel multipaths, and h i τ i These are the gain and delay of the i-th self-interference channel multipath component, respectively;

[0057] In step S102, the down-conversion signal provided by the clock module to the first receiving channel in the receiver is:

[0058] a Ri =exp{-j[2πf c (t-τ1)+θ(t-τ1)]}

[0059] Where τ1 represents the delay of delayer d1 in the clock module;

[0060] After downconversion, the received signal of the first channel is:

[0061]

[0062] m represents the multipath number of the self-interference channel, x(t) represents the transmitted signal, L represents the total number of multipaths in the self-interference channel, and h1 and τ1 represent the gain and propagation delay of the first path of the multipath channel, where A i =exp{j2πf c τ i} is the phase change caused by transmission delay, B i (t)=exp{jθ(t-τ i )} represents the phase change caused by phase noise, and * represents the conjugate function.

[0063] In step S103, the self-interference channel response is first estimated based on the baseband digital received signal. Then, based on the self-interference channel response, a cancellation signal is constructed to cancel the self-interference signal, resulting in the residual self-interference signal;

[0064] In the embodiments of this application, the above-mentioned self-interference channel response estimation, cancellation signal construction, and self-interference signal cancellation can be performed based on the time domain or the frequency domain:

[0065] (1) The process based on time-domain signals is as follows:

[0066] A1. Estimating the self-interference channel response:

[0067] Suppose that the frequency-converted received signal r1(t) passes through an ADC to obtain a sequence r1[n]. The sequence can be expressed as a vector as follows:

[0068] r D =X D h D +n

[0069] r D ={r1[n],r1[n+1]...,r1[n+M-1]} T It is an M×1 receive vector, where M is the signal processing length and X is the signal length. D It is an M×P transmitted signal matrix, where n is a vector composed of noise, and X D Represented as

[0070] X D =(x0,x1,...,x P-1 )

[0071] Where, x i The transmitted signal vector is defined as follows:

[0072] x i ={x[i],x[i+1]...,x[i+M-1]} T

[0073] x[n] is the digital sequence obtained after x(t) is processed by the ADC, h D ={β0,β1,...,β P-1} T It is a P×1 digital SI channel response vector;

[0074] Where P satisfies P≥(τ) L -τ1) / Ts is a constant, where Ts is the sampling interval, and

[0075]

[0076] The SI channel is obtained using an LS estimator, and the estimated SI channel is expressed as follows:

[0077]

[0078] A2. Constructing the cancellation signal:

[0079] Using the estimated channel response and transmitted signal X D The self-interference cancellation signal is reconstructed as follows:

[0080]

[0081] A3. Self-interference signal cancellation

[0082] Subtracting the self-interference cancellation signal from the received signal yields the following residual self-interference signal:

[0083]

[0084] (2) The process based on frequency domain signals is as follows:

[0085] Full-duplex transceivers use OFDM modulation, i.e., frequency domain transmission sequence {X}. n The sequence |0≤n≤K-1}, after OFDM modulation and analog-to-digital conversion, yields a time-domain transmitted signal x(t). This signal is then up-converted, transmitted through the channel, and reaches the receiver. The received signal at the antenna undergoes down-conversion, analog-to-digital conversion, and OFDM demodulation to obtain a digital-domain received signal. The frequency-domain transmitted sequence can be represented as a matrix, X, denoted as...

[0086] X = diag{X0,X1,...,X} K-1}

[0087] Where K represents the number of subcarriers, and the frequency domain received signal is represented as...

[0088] r = XFh D +n

[0089] Where F is a K×P matrix, denoted as

[0090] [F] n,k =e -j2πkn / K 0≤n≤K-1, 0≤k≤P-1

[0091] h D It is the discrete time-domain SI channel impulse response vector of P×1, where n represents the noise vector, and the received signal r is a K×1 sequence, represented as {r n |0≤n≤K-1}.

[0092] A1. Estimating the self-interference channel response:

[0093] Given the known subcarrier {i} of the transmitted signal X n Place the known signal a in |0≤n≤G-1} i As pilot signals, pilot signals are used for self-interference channel estimation. Where, {i n |0≤n≤G-1} represents the position where the pilot signal is inserted, G is the number of pilot signals to be inserted, and the pilot transmission signal matrix A is represented as follows.

[0094] A = diag{a0, a1, ..., a G-1}

[0095] Where {a n |0≤n≤G-1} represents the transmitted signal at the pilot subcarrier.

[0096] The pilot received signal y in the frequency domain is represented as

[0097] y = ABh D +n

[0098] Where B is a G×P Fourier transform matrix, denoted as...

[0099]

[0100] The channel impulse response estimation result is

[0101]

[0102] The channel estimation results will be used to calculate the delay configuration parameters.

[0103] A2. Constructing the cancellation signal:

[0104] Using the estimated channel impulse response The self-interference cancellation signal, reconstructed in the frequency domain from the transmitted signal X, is as follows:

[0105]

[0106] A3. Self-interference signal cancellation

[0107] The self-interference cancellation signal is subtracted from the received signal in the frequency domain to complete the self-interference cancellation.

[0108] y c =rc.

[0109] Further, in step S103, determining the delay parameters based on the residual self-interference power after self-interference signal cancellation and the self-interference channel response includes:

[0110] 1. Determine the delay parameters of delayer d1 based on the residual self-interference power after self-interference signal cancellation, and configure the delay parameters of delayer d1:

[0111] Adjust the delay parameter of delayer d1. Repeat steps A1 to A3 after each adjustment and measure the self-interference power to obtain the residual self-interference power until the residual self-interference power reaches the minimum value. Record the delay parameter at this time as D and configure the delay parameter of delayer d1 as D.

[0112] II. Determine the delay timer d2~d based on the self-interference signal response. N The relative delay parameters, and the delay timers d2 to d3. N Configure the delay parameters:

[0113] For delay d i The delay parameters are determined using the following method;

[0114] (1) Set the threshold value λ;

[0115] (2) Assume that the self-interference channel response is estimated. Where P represents the length of the self-interference channel response, and the position index u[i] is defined, with initial values ​​k=0 and i=1.

[0116] (a) Connect λ with Comparison:

[0117] If index k satisfies Let u[i] = k, and then let k = k + 1, i = i + 1;

[0118] If index k does not satisfy Let k = k + 1;

[0119] (b) Proceed to step (a) until k = P-1;

[0120] (3) Let L = i, that is, the value of i at the end of step (2), and construct the position index vector u = (u[1], u[2], ..., u[L]), where L is the length of the position index vector u;

[0121] Let Q = min{L,N}, and then calculate the delay parameter D when i = 2,...,Q. i = (u[i]-u[1])Ts, then configure the delay d i The delay parameter is set to D. i .

[0122] In other words, when L is greater than or equal to N, Q = N. At this time, the delays of all receiving channels can be configured. During the signal transmission and reception phase, each receiving channel participates in the self-interference suppression process (subsequent steps B1 to B4).

[0123] If Q = L when L is less than N, then the delay of the (L+1)th to (N)th receiving channels is configured to 0 or a random initial value. In the actual signal transmission and reception phase, only the down-converted signals of the 1st to Qth receiving channels will be used for self-interference suppression (subsequent steps B1 to B4). The signals of the (L+1)th to (N)th receiving channels will not be used for self-interference suppression. The signals of these channels can be directly discarded or transmitted to the baseband as a reference for the signal reception process.

[0124] Furthermore, in step S201, the up-conversion signal provided by the clock module is...

[0125] a T =exp{-j[2πf c [(t)+θ(t)]},

[0126] Where f c θ(t) represents the carrier frequency and the transmitter phase noise, thus yielding the radio frequency transmitted signal.

[0127]

[0128] Where x(t) is the baseband transmitted signal, f c θ(t) and θ(t) are the carrier frequency and transmitter phase noise, respectively;

[0129] The radio frequency transmission signal is transmitted to the remote node via the antenna, and at the same time After passing through the self-interference channel h I (t) reaches the local receiver and becomes a self-interference signal. Therefore, the received signal at the antenna includes the self-interference signal, the useful signal, and the receiver noise, denoted as:

[0130]

[0131] Where s(t) and n(t) are the received useful signal and receiver noise, respectively, L is the number of self-interference channel multipaths, and h i τ i These are the gain and delay of the i-th self-interference channel multipath component, respectively;

[0132] In step S202, the time delay signal provided by the clock module for the i-th receiving channel is:

[0133] a Ri =exp{-j[2πf c (t-τ i )+θ(t-τ i )]}

[0134] Where τ i Indicates clock module delay;

[0135] After down-conversion, the received signal of the i-th receiving channel is represented as:

[0136]

[0137] m represents the self-interference multipath number, x(t) represents the transmitted signal, L represents the total number of multipaths in the self-interference channel, and h m and τ m This represents the channel gain and propagation delay for each multipath. Where A... i =exp{j2πf c τ i} is the phase change caused by transmission delay, B i (t)=exp{jθ(t-τ i )} represents the phase change caused by phase noise.

[0138] Further, step S203 includes:

[0139] B1. Extracting Phase Noise Figures

[0140] Divide the received signals from the first channel and the i-th channel to obtain the phase noise figure, i.e.

[0141]

[0142] B2. Estimating the self-interference channel

[0143] To perform signal processing, the signal is represented as

[0144] r i =(X⊙Γ)h+z

[0145] Where r i ={r i [n],r i [n+1]...,r i [n+M-1]} T It is an M×1 receive vector, where M is the signal processing length and r is the received vector. i [n] represents the digital received signal, h = {h1, h2, ..., h...} L} T Z is an L×1 channel vector, where z is a vector composed of useful signal and noise; X is an M×L matrix, defined as...

[0146] X = (x1, x2, ..., x L )

[0147] Where x i 1≤i≤L is the transmitted signal vector, defined as

[0148] x i ={x[n-μ i ],...,x[n+M-1-μ i ]} T

[0149] Where μ i =u[i]-u[1] is the number of delayed samples for the i-th multipath component, u[i] is the channel location index obtained in step 103, and Γ is also an M×L matrix, defined as

[0150] Γ=(γ1,γ2,...,γ L )

[0151] Where γ i ={γ i [n],γ i [n+1]...,γ i [n+M-1]} T It is a digitized vector of phase noise parameters.

[0152] Using the phase noise estimate extracted in step B1, construct the measurement matrix.

[0153]

[0154] Using the estimation results, according to the formula r i Using the formula, least squares channel estimation is performed to obtain the estimated channel.

[0155]

[0156] B3. Reconstructing the self-interference cancellation signal

[0157] After estimating the phase noise parameters and channel response, the estimated phase noise figures and channel response are used to reconstruct the self-interference cancellation signal, which is then reconstructed as follows:

[0158]

[0159] B4. Perform self-interference elimination

[0160] Subtracting the reconstructed self-interference signal from the received signal in the first receiving channel, the residual signal is expressed as:

[0161]

[0162] y r The received signal is obtained after self-interference suppression.

[0163] Although exemplary embodiments of the invention have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions in form and detail may be made without departing from the scope and spirit of the invention disclosed in the appended claims, and all such modifications and substitutions should fall within the protection scope of the appended claims. Furthermore, the various steps in the method claimed by this invention can be combined in any combination. Therefore, the description of the embodiments disclosed in this invention is not intended to limit the scope of the invention, but rather to describe the invention. Accordingly, the scope of the invention is not limited by the above embodiments, but is defined by the claims or their equivalents.

Claims

1. A full-duplex transceiver system based on delay configuration and self-interference suppression, characterized in that: It includes a transmitter, a receiver, a clock module, a delay parameter configuration module, and a self-interference suppression module; The transmitter is used to convert the baseband digital transmission signal into an analog signal and then up-convert it to obtain a radio frequency signal for transmission. The receiver includes a receiving antenna and N receiving channels. When the full-duplex transceiver system is working in the delay parameter configuration stage, the receiver receives the signal transmitted by the transmitter through the receiving antenna, transmits the received signal to the first receiving channel for down-conversion and analog-to-digital conversion, and then transmits it to the delay parameter configuration module. When the full-duplex transceiver system is working in the signal transmission and reception phase, the receiver receives the working signal through the receiving antenna and transmits it to N receiving channels respectively. After down-conversion and analog-to-digital conversion in each receiving channel, N baseband digital received signals are obtained and transmitted to the self-interference suppression module. The delay parameter configuration module is used to calculate the delay parameter based on the signal output by the first receiving channel in the receiver during the delay parameter configuration stage, and to configure the clock module. The clock module is used to provide an up-conversion signal to the transmitter, and during the delay parameter configuration phase, to provide a down-conversion signal to the first receiving channel of the receiver, and during the signal transmission and reception phase, to provide down-conversion signals to all receiving channels of the receiving device. The self-interference suppression module is used to suppress self-interference using the signals from N receiving channels during the signal transmission and reception phase, thereby obtaining the self-interference suppressed received signal.

2. The full-duplex transceiver system based on delay configuration and self-interference suppression according to claim 1, characterized in that: The transmitter includes a DAC module, an up-conversion module, and a transmitting antenna; The input terminal of the DAC module is connected to the baseband digital transmission signal, the output terminal of the DAC module is connected to the first input terminal of the upconversion module, the second input terminal of the upconversion module is connected to the clock module that provides the upconversion signal, and the output terminal of the upconversion module is connected to the transmitting antenna, which transmits the signal output by the upconversion module to the outside.

3. A full-duplex transceiver system based on delay configuration and self-interference suppression according to claim 1, characterized in that: Each of the receiving channels includes a down-conversion module and an ADC module. The first input terminal of the down-conversion module is connected to the receiving antenna, the second output terminal of the down-conversion module is connected to the clock module that provides the down-conversion signal, the output terminal of the down-conversion module is connected to the ADC module, and the output terminal of the ADC module is connected to the self-interference suppression module. In the first receiving channel of the receiver, the output of the ADC module is also connected to the delay parameter configuration module.

4. A full-duplex transceiver system based on delay configuration and self-interference suppression according to claim 1, characterized in that: The clock module includes a local oscillator and delay units d1 to d2. N The output of the local oscillator is connected to the up-conversion module of the transmitter to provide an up-converted signal to the transmitter. The output of the local oscillator is also connected to delay unit d1, and delay unit d1 is also connected to delay units d2 through d3 respectively. N Connection, where delay d i The output terminal is used to provide the down-conversion signal for the i-th receiving channel in the receiver, i = 1, 2, ..., N; delay d2 ~ delay d N A switch is installed on the connection path between each delay unit and delay unit d1; The delay parameter configuration module configures the clock module, that is, it configures the delay of each delay unit in the clock module.

5. A full-duplex transceiver method based on delay configuration and self-interference suppression, employing the system described in any one of claims 1 to 4, characterized in that: Includes the following steps: S1. When the full-duplex transceiver system is operating in the delay parameter configuration phase, the transmitter transmits a signal, and then the delay parameters are calculated based on the signal output from the first receiving channel in the receiver to configure the delay of each delay unit in the clock module: S101. In the transmitter, the baseband digital transmission signal is converted from digital to analog and then transmitted to the upconversion module. In the upconversion module, the signal is mixed with the upconversion signal from the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna. S102. The receiver receives the signal transmitted by the transmitter through the receiving antenna, sends the received signal into the first receiving channel, and mixes it with the down-conversion signal provided by the clock module in the down-conversion module of the receiving channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the delay parameter configuration module. S103. The delay parameter configuration module estimates the self-interference channel response based on the baseband digital received signal, constructs a cancellation signal to cancel the self-interference signal, and then determines the delay parameter to configure the clock module based on the residual self-interference power and the self-interference channel response after self-interference signal cancellation. S2. During the signal transmission and reception phase, based on the configured delay parameters, signal reception is performed and self-interference suppression is completed: S201. In the transmitter, the baseband digital transmission signal is converted from digital to analog, and then the obtained signal is transmitted to the upconversion module. In the upconversion module, it is mixed with the upconversion signal provided by the clock module to obtain the radio frequency transmission signal, which is then transmitted through the transmitting antenna. S202. In the receiver, the working signal is received through the receiving antenna, and then the received signal is transmitted to each receiving channel of the receiver; In the downconversion module of each receiving channel, the received signal is mixed with the downconversion signal provided by the clock module for that channel. After analog-to-digital conversion of the mixed signal, the resulting baseband digital received signal is transmitted to the self-interference suppression module. S203. The self-interference suppression module uses the digital self-interference signal output from the receiving channel to suppress self-interference.

6. The full-duplex transceiver method based on delay configuration and self-interference suppression according to claim 5, characterized in that: In step S101, the up-conversion signal provided by the clock module is: a T =exp{-j[2πf c (t)+θ(t)]}, Where f c θ(t) and θ(t) are the carrier frequency and transmitter phase noise, respectively; The radio frequency transmission signal obtained by upconversion is: Where x(t) is the baseband transmitted signal; The radio frequency transmission signal is transmitted to the remote node via the antenna, and at the same time After passing through the self-interference channel h I (t) reaches the local receiver and becomes a self-interference signal. Therefore, the received signal at the antenna includes both the self-interference signal and the receiver noise, denoted as: Where n(t) is the receiver noise, L is the number of self-interference channel multipaths, and h i τ i These are the gain and delay of the i-th self-interference channel multipath component, respectively; In step S102, the down-conversion signal provided by the clock module to the first receiving channel in the receiver is: a Ri =exp{-j[2πf c (t-τ1)+θ(t-τ1)]} Where τ1 represents the delay of delayer d1 in the clock module; After downconversion, the received signal of the first channel is: m represents the multipath number of the self-interference channel, x(t) represents the transmitted signal, L represents the total number of multipaths in the self-interference channel, and h1 and τ1 represent the gain and propagation delay of the first path of the multipath channel, where A i =exp{j2πf c τ i } is the phase change caused by transmission delay, B i (t)=exp{jθ(t-τ i )} represents the phase change caused by phase noise, and * represents the conjugate function.

7. A full-duplex transceiver method based on delay configuration and self-interference suppression according to claim 6, characterized in that: In step S103, the self-interference channel response is first estimated based on the baseband digital received signal. Then, a cancellation signal is constructed based on the self-interference channel response to cancel the self-interference signal and obtain the residual self-interference signal.

8. A full-duplex transceiver method based on delay configuration and self-interference suppression according to claim 7, characterized in that: In step S103, determining the delay parameters based on the residual self-interference power after self-interference signal cancellation and the self-interference channel response includes:

1. Determine the delay parameters of delayer d1 based on the residual self-interference power after self-interference signal cancellation, and configure the delay parameters of delayer d1: Adjust the delay parameters of delayer d1, and repeat the self-interference channel response estimation, cancellation signal construction and self-interference signal cancellation after each adjustment. Then, measure the power of the self-interference signal involved to obtain the residual self-interference power. Until the residual self-interference power reaches its minimum value, the delay parameter at this time is recorded as D, and the delay parameter of delayer d1 is configured as D; II. Determine the delay timer d2~d based on the self-interference signal response. N The delay parameters, and the delay timers d2 to d3. N Configure the delay parameters: For delay d i The delay parameters are determined using the following method; (1) Set the threshold value λ; (2) Assume that the self-interference channel response is estimated. Where P represents the length of the self-interference channel response, and the position index u[i] is defined, with initial values ​​k=0 and i=1. (a) Connect λ with Comparison: If index k satisfies Let u[i] = k, and then let k = k + 1, i = i + 1; If index k does not satisfy Let k = k + 1; (b) Proceed to step (a) until k = P-1; (3) Let L = i, that is, the value of i at the end of step (2), and construct the position index vector u = (u[1], u[2], ..., u[L]), where L is the length of the position index vector u; Let Q = min{L,N}, and then calculate the delay parameter D when i = 2,…,Q. i = (u[i]-u[1])Ts, then configure the delay d i The delay parameter is set to D. i .

9. A full-duplex transceiver method based on delay configuration and self-interference suppression according to claim 5, characterized in that: In step S201, the up-conversion signal provided by the clock module is a T =exp{-j[2πf c (t)+θ(t)]}, Where f c θ(t) represents the carrier frequency and the transmitter phase noise, thus yielding the radio frequency transmitted signal. Where x(t) is the baseband transmitted signal, f c θ(t) and θ(t) are the carrier frequency and transmitter phase noise, respectively; The radio frequency transmission signal is transmitted to the remote node via the antenna, and at the same time After passing through the self-interference channel h I (t) reaches the local receiver and becomes a self-interference signal. Therefore, the received signal at the antenna includes the self-interference signal, the useful signal, and the receiver noise, denoted as: Where s(t) and n(t) are the received useful signal and receiver noise, respectively, L is the number of self-interference channel multipaths, and h i τ i These are the gain and delay of the i-th self-interference channel multipath component, respectively; In step S202, the time delay signal provided by the clock module for the i-th receiving channel is: a Ri =exp{-j[2πf c (t-t i )+θ(t-τ i )]} Where τ i Indicates clock module delay; After down-conversion, the received signal of the i-th receiving channel is represented as: m represents the self-interference multipath number, x(t) represents the transmitted signal, L represents the total number of multipaths in the self-interference channel, and h m and τ m Represents the channel gain and propagation delay for each multipath, where A i =exp{j2πf c τ i } is the phase change caused by transmission delay, B i (t)=exp{jθ(t-τ i )} represents the phase change caused by phase noise.

10. A full-duplex transceiver method based on delay configuration and self-interference suppression according to claim 9, characterized in that: Step S203 includes: B1. Extracting Phase Noise Figures Divide the received signals from the first channel and the i-th channel to obtain the phase noise figure, i.e. B2. Estimating the self-interference channel To perform signal processing, the signal is represented as r i =(X⊙Γ)h+z Where r i ={r i [n],r i [n+1]···,r i [n+M-1]} T It is an M×1 receive vector, where M is the signal processing length and r is the received vector. i [n] represents the digital received signal, h = {h1, h2, ..., h...} L } T It is an L×1 channel vector, where z is a vector composed of useful signal and noise; X is an M×L matrix, defined as X=(x1,x2,···,x L ) Where x i 1≤i≤L is the transmitted signal vector, defined as x i ={x[n-μ i ],···,x[n+M-1-μ i ]} T Where μ i =u[i]-u[1] is the number of delayed samples for the i-th multipath component, u[i] is the channel location index obtained in step 103, and Γ is also an M×L matrix, defined as C=(c1,c2,…,c Γ ) Where γ i ={γ i [n],γ i [n+1]···,γ i [n+M-1]} T It is a digitized vector of phase noise parameters. Using the phase noise estimate extracted in step B1, construct the measurement matrix. Using the estimation results, according to the formula r i Using the formula, least squares channel estimation is performed to obtain the estimated channel. B3. Reconstructing the self-interference cancellation signal After estimating the phase noise parameters and channel response, the estimated phase noise figures and channel response are used to reconstruct the self-interference cancellation signal, which is then reconstructed as follows: B4. Perform self-interference elimination Subtracting the reconstructed self-interference signal from the received signal in the first receiving channel, the residual signal is expressed as: y r The received signal is obtained after self-interference suppression.

Images