Deep trench silicon capacitor and method of making same
By designing the interconnection path of the upper and lower electrode terminals and the multilayer stacked array structure of the deep trench silicon capacitor, the problems of dielectric material and thickness limitations were solved, enabling the high-performance application of high-density silicon capacitors and reducing the equivalent series resistance and equivalent series inductance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XWAVE TECH (SHANGHAI) CO LTD
- Filing Date
- 2023-03-03
- Publication Date
- 2026-06-09
AI Technical Summary
Traditional deep trench silicon capacitors are limited by dielectric materials, dielectric layer area and thickness, making it difficult to meet high-performance requirements. There is room for improvement, especially in increasing silicon capacitor density and reducing equivalent series resistance and equivalent series inductance.
The interconnection path between the upper and lower electrode terminals of the deep trench silicon capacitor is designed so that current is introduced into the electrode points from different directions. The dielectric layer area is increased by using a multi-layer stacked array structure to achieve the interactive flow of current to counteract the magnetic field and reduce parasitic parameters.
The performance of deep trench silicon capacitors has been improved by increasing the dielectric layer area and reducing the equivalent series resistance and equivalent series inductance, thus enabling high-performance applications of high-density silicon capacitors.
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Figure CN116347972B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of silicon capacitor technology, and in particular to a deep trench silicon capacitor and its fabrication method. Background Technology
[0002] With the consensus that the post-Moore's Law era has arrived, heterogeneous integration (HCI) technology has become a crucial technological route for integrated circuit development. HCI typically uses a silicon interposer as a substrate to achieve power supply between chips and handle high-speed interconnects. This integration technology significantly reduces interconnect latency and power consumption, and to some extent improves integration density and functionality. Therefore, with the increasing high-performance demands of HCI applications, the need for larger silicon interposers and finer, more complex wiring is required. However, larger silicon interposers and finer wiring often lead to more severe power integrity issues.
[0003] More severe coupling and crosstalk problems arise between interconnect signal lines, and the stacking along the z-axis further exacerbates the chaotic electromagnetic environment of the entire package system. Therefore, the power supply network and interconnect signals require more stringent power integrity and signal integrity design. Both signal integrity and power integrity issues can be effectively improved by using appropriate decoupling capacitors, whether on the stack, the interposer, or the PCB (printed circuit board). However, each decoupling capacitor has its maximum effective decoupling radius, which depends on the capacitor's capacitance, equivalent series resistance (ESR), equivalent series inductance (ESL), and the inherent characteristics of the load circuit.
[0004] In traditional silicon capacitor technology, deep trench silicon capacitors (DTC) are well-suited for silicon interposer integration in applications requiring AC coupling and DC decoupling due to their low equivalent series resistance (ESR), low-profile power inductance, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) processes. Metal-insulator-metal (MIM) and metal-oxide-semiconductor (MOS) capacitor technologies are widely used for on-chip decoupling; however, both MIM and MOS technologies struggle to achieve high capacitance densities, resulting in larger on-chip areas in practical applications. In contrast, deep trench silicon capacitors offer higher capacitance density and greater on-chip area savings. However, existing deep trench capacitors are limited by their dielectric materials, dielectric layer area, and thickness, making it difficult to meet higher performance and application requirements. Significant room for improvement remains in increasing silicon capacitor density and reducing ESR and ESR.
[0005] In summary, traditional deep trench silicon capacitors suffer from poor performance due to limitations in dielectric materials, dielectric layer area, and thickness. Summary of the Invention
[0006] Therefore, it is necessary to provide a high-performance deep trench silicon capacitor and its manufacturing method to address the aforementioned technical problems.
[0007] In a first aspect, this application provides a deep trench silicon capacitor, comprising: a first metal layer;
[0008] The upper electrode terminals, including a first upper electrode terminal and a second upper electrode terminal, are diagonally distributed on one side of the first metal layer;
[0009] The lower electrode terminals include a first lower electrode terminal and a second lower electrode terminal, which are diagonally distributed on one side of the first metal layer, located on the same side of the first metal layer as the upper electrode terminals but at a diagonal position different from the distribution of the upper electrode terminals.
[0010] The second metal layer is fixedly installed on the other side of the first metal layer;
[0011] The base includes a silicon substrate and a plurality of trenches formed on the silicon substrate. The base is disposed on the side of the second metal layer away from the first metal layer, and the openings of the trenches face the second metal layer.
[0012] A stack array is disposed inside the trench;
[0013] The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal are interconnected to introduce current into the electrode points of the deep trench silicon capacitor from different directions, thereby achieving the interactive flow of current and canceling the magnetic field generated when the current flows in.
[0014] In one embodiment, the multilayer stack array is arranged within the trench, and the electrode layer of the stack array is connected to the second metal layer and interconnected with the first metal layer through the second metal layer.
[0015] In one embodiment, the first metal layer is rectangular, and the top of the first metal layer has a first mounting portion, a second mounting portion, a third mounting portion and a fourth mounting portion, wherein the first mounting portion and the third mounting portion are located at both ends of one diagonal of the first metal layer, and the second mounting portion is located at both ends of the other diagonal of the first metal layer.
[0016] In one embodiment, a first wire is embedded on the first metal layer, and the first mounting portion, the second mounting portion, the third mounting portion and the fourth mounting portion are connected to each other through the first wire.
[0017] In one embodiment, the first upper electrode terminal is disposed on the first mounting portion, the second upper electrode terminal is disposed on the third mounting portion, the first lower electrode terminal is disposed on the second mounting portion, and the second lower electrode terminal is disposed on the fourth mounting portion;
[0018] The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal achieve the interactive flow of current through the first wire.
[0019] In one embodiment, the second metal layer is configured as a rectangle with the same size as the first metal layer.
[0020] In one embodiment, a second wire is embedded on the second metal layer, wherein the second wire is parallel to the diagonal of the second metal layer, and the first wire is perpendicular to the second wire.
[0021] Secondly, this application provides a method for manufacturing a deep trench silicon capacitor, used to realize the deep trench silicon capacitor as described in any one of the first aspects of this application, the method comprising:
[0022] A first upper electrode terminal, a second upper electrode terminal, a first lower electrode terminal, and a second lower electrode terminal are disposed on one side of the first metal layer;
[0023] A first wire is embedded on the first metal layer, so that the first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal and the second lower electrode terminal can achieve current interaction through the first wire;
[0024] A second metal layer is disposed on the other side of the first metal layer, and a silicon substrate is disposed at the bottom of the second metal layer;
[0025] Multiple trenches are formed on the silicon substrate such that the openings of the trenches on the silicon substrate face the second metal layer;
[0026] A multilayer stack array is disposed in a silicon substrate trench, and the electrode layer of the multilayer stack array is connected to the second metal layer;
[0027] The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal are interconnected to introduce current into the electrode points of the deep trench silicon capacitor from different directions, thereby achieving the interactive flow of current and canceling the magnetic field generated when the current flows in.
[0028] In one embodiment, both the first metal layer and the second metal layer are rectangular of the same size, and a second wire is embedded in the second metal layer, the second wire being perpendicular to the first wire.
[0029] In one embodiment, a first mounting portion, a second mounting portion, a third mounting portion and a fourth mounting portion are provided on the top of the first metal layer, wherein the first mounting portion and the third mounting portion are located at both ends of one diagonal of the first metal layer, the second mounting portion is located at both ends of the other diagonal of the first metal layer, and they are connected to each other through the first wire.
[0030] The first upper electrode terminal is disposed on the first mounting part, the second upper electrode terminal is disposed on the third mounting part, the first lower electrode terminal is disposed on the second mounting part, and the second lower electrode terminal is disposed on the fourth mounting part. The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal achieve the interactive flow of current through the first wire.
[0031] The aforementioned deep trench silicon capacitor and its fabrication method, through the design of the interconnection path between the upper and lower electrode terminals of the deep trench silicon capacitor, enable the signal from the upper electrode terminal to reach the lower electrode terminal via the shortest path. Furthermore, it introduces current into the electrode points of the silicon capacitor from different directions, achieving interactive current flow. This counteracts the magnetic field generated when current flows in, thereby reducing the parasitic parameters of the high-density silicon capacitor, namely the equivalent series resistance and equivalent series inductance. The deep trench capacitor technology and stacked array structure effectively increase the dielectric layer area of the silicon capacitor, allowing for a higher unfolded area with the same projected area. The multi-layer stacked array structure can further multiply the unfolded area, further increasing the dielectric layer area to achieve high-density silicon capacitors. Therefore, this deep trench silicon capacitor, by reducing the equivalent series resistance and equivalent series inductance and increasing the dielectric layer area, improves the performance of the deep trench silicon capacitor to a certain extent. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the overall structure of a deep trench silicon capacitor according to an embodiment of this application;
[0033] Figure 2 This is a schematic diagram of the distribution structure of the upper and lower electrode terminals of the deep trench silicon capacitor in this embodiment;
[0034] Figure 3 This is a schematic diagram showing the relative positions of the wiring on the two metal layers in this embodiment;
[0035] Figure 4 This is a schematic diagram of the overall structure of the deep trench silicon capacitor in Example 2 of this embodiment;
[0036] Figure 5 This is a schematic diagram of the metal layer wiring structure in Example 2 of this embodiment;
[0037] Figure 6 This is a schematic diagram showing the relative position structure of the wiring on the two metal layers in Example 2 of this embodiment;
[0038] Figure 7 This is a comparison chart of the equivalent series resistance (ESR) parameter curves in this embodiment;
[0039] Figure 8 This is a comparison chart of the equivalent series inductance (ESL) parameter curves in this embodiment;
[0040] Figure 9 A flowchart of a method for manufacturing a deep trench silicon capacitor according to one embodiment of this application.
[0041] In the figure: 100, first metal layer; 110, first mounting part; 120, second mounting part; 130, third mounting part; 140, fourth mounting part; 150, first wire; 200, first upper electrode terminal; 300, second upper electrode terminal; 400, first lower electrode terminal; 500, second lower electrode terminal; 600, second metal layer; 610, second wire; 700, base; 710, silicon substrate; 720, trench; 800, stack array. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on the other component or there may be an intermediate component. When a component is considered to be "connected to" another component, it can be directly connected to the other component or there may be an intermediate component present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application's specification are for illustrative purposes only and do not represent the only possible implementation.
[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0045] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature and the second feature are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0046] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.
[0047] See Figure 1 and Figure 2 As shown, in one embodiment, a deep trench silicon capacitor includes:
[0048] A first metal layer 100 is square in shape, with mounting portions at both ends of its two top diagonals: a first mounting portion 110, a second mounting portion 120, a third mounting portion 130, and a fourth mounting portion 140. A first conductive wire 150 is embedded in the first metal layer 100, interconnecting the first mounting portions 110, 120, 130, and 140. Specifically, the first mounting portion 110 and the third mounting portion 130 are located at opposite ends of the same diagonal, while the second mounting portion 120 and the third mounting portion 140 are located at opposite ends of the other diagonal.
[0049] The upper electrode terminal includes a first upper electrode terminal 200 and a second upper electrode terminal 300. Both the first upper electrode terminal 200 and the second upper electrode terminal 300 are disposed on the top of the first metal layer 100. The first upper electrode terminal 200 is disposed on the first mounting portion 110, and the second upper electrode terminal 200 is disposed on the third mounting portion 130. The first upper electrode terminal 200 and the second upper electrode terminal 300 are diagonally distributed on the first metal layer 100.
[0050] The lower electrode terminals include a first lower electrode terminal 400 and a second lower electrode terminal 500. The first lower electrode terminal 400 is disposed on the second mounting portion 120, and the second lower electrode terminal 500 is disposed on the fourth mounting portion 140. They are diagonally distributed on the top of the first metal layer 100.
[0051] It should be noted that since the first mounting part 110, the second mounting part 120, the third mounting part 130 and the fourth mounting part 140 are interconnected on the first metal layer 100 through the first wire 150, the first upper electrode terminal 200, the first lower electrode terminal 400, the second upper electrode terminal 300 and the second lower electrode terminal 500 mounted on the first mounting part 110, the second mounting part 120, the third mounting part 130 and the fourth mounting part 140 are interconnected with each other through the first wire 150, so that the current is introduced into the electrode points of the deep trench silicon capacitor from different directions, realizing the interactive flow of current, thereby canceling the magnetic field generated when the current flows in.
[0052] The second metal layer 600 is a square with the same size as the first metal layer 100 and is fixedly installed at the bottom of the first metal layer 100. A second wire 610 is embedded in the second metal layer 600. The second wire 610 is parallel to one of the diagonals of the second metal layer 600 and perpendicular to the first wire 150.
[0053] Combination Figure 3 The figure shows the relative positional relationship between the first conductor 150 on the first metal layer 100 and the second conductor 610 on the second metal layer 600.
[0054] The base 700 is composed of a silicon substrate 710 and a plurality of trenches 720 formed on the silicon substrate 710. The silicon substrate 710 is made of polycrystalline silicon. The trenches 720 are formed on the silicon substrate 710. The base 700 is disposed on the side of the second metal layer 600 away from the first metal layer 100, and the openings of the trenches 720 face the second metal layer 600.
[0055] A stacked array 800 is disposed inside the trench 720. Since the opening of the trench 720 faces the second metal layer 600, the electrode layer of the stacked array 800 disposed inside the trench 720 can be connected to the bottom of the second metal layer 600, and interconnected with the first metal layer 100 using the second metal layer 600 as a conductor. By setting a multi-layer stacked array 800 inside the trench 720, deep trench capacitor technology can obtain a higher unfolded area with the same projected area. The structure of the multi-layer stacked array 800 can double the unfolded area of the trench 720, thereby increasing the dielectric layer area and realizing high-density silicon capacitors.
[0056] The aforementioned deep trench silicon capacitor, through the design of the interconnection path between the upper and lower electrode terminals, allows the signal from the upper electrode terminal to reach the lower electrode terminal via the shortest path. It also introduces current into the electrode points of the silicon capacitor from different directions, achieving interactive current flow. This counteracts the magnetic field generated when current flows in, thereby reducing the parasitic parameters of the high-density silicon capacitor, namely the equivalent series resistance and equivalent series inductance. Deep trench capacitor technology and the stacked array structure effectively increase the dielectric layer area of the silicon capacitor, enabling a higher unfolded area for the same projected area. The multi-layer stacked array structure can further multiply the unfolded area, further increasing the dielectric layer area to achieve high-density silicon capacitors. Therefore, this deep trench silicon capacitor improves its performance to a certain extent by reducing the equivalent series resistance and equivalent series inductance and increasing the dielectric layer area.
[0057] Next, the deep trench silicon capacitor provided in this application will be further illustrated through Examples 1 and 2.
[0058] Example 1: Combining Figures 1 to 3 As shown, the first metal layer 100 is configured as a square metal layer. Two upper electrode terminals (Signal 1 and Signal 2) are respectively provided at both ends of one diagonal of the top of the square metal layer, and two lower electrode terminals (GND 1 and GND 2) are respectively provided at both ends of the other diagonal of the top of the square metal layer, so that the upper and lower electrode terminals of the deep trench silicon capacitor have a symmetrical structure, and the upper and lower electrode terminals can be reversed in actual application.
[0059] In Example 1, by increasing the number of upper electrode (Signal) and lower electrode (GND) terminals to form a four-terminal silicon capacitor and mounting it on a substrate, the number of current inflow points for the silicon capacitor to be damaged by electric shock is increased. The upper electrode terminals (Signal 1 and Signal 2) and the lower electrode terminals (GND 1 and GND 2) are arranged diagonally. In other words, Signal 1 and Signal 2 are the first upper electrode terminal 200 and the second upper electrode terminal 300, respectively, and GND 1 and GND 2 are the first lower electrode terminal 400 and the second lower electrode terminal 500. This allows current to flow into the silicon capacitor electrode points from different directions. The current flowing into the upper and lower electrode terminals of the silicon capacitor interacts, ultimately canceling out the magnetic field introduced by the current, thereby reducing mutual inductance. Furthermore, since parasitic parameters (ESR and ESL) increase with the increase of the flow path length of the current flowing into the silicon capacitor and decrease with the increase of the flow path linewidth, the parasitic parameters (ESR and ESL) of the silicon capacitor can be reduced by interconnecting the first metal layer 100 and the second metal layer 600 (interconnecting metal 1 layer and interconnecting metal 2 layer) to reduce the trace length from the upper electrode terminal to the lower electrode terminal and increase the trace width.
[0060] In Example 1, since the ESL of a silicon capacitor increases with the length of the current flow path and decreases with the width of the flow path, the current flow path to the silicon capacitor can be reduced by increasing the number of upper and lower electrode terminals. Furthermore, in practical applications of silicon capacitors, mounting them on a substrate with a four-terminal structure can result in lower parasitic inductance. The electrode layers of the stack array 800 below the second metal layer 600 are connected via interconnect metal layers. The two upper electrode terminals and two lower electrode terminals are designed diagonally and routed at a 45° angle on the square second metal layer 600. That is, the second conductor 610 forms a 45° angle with the boundary of the second metal layer 600, and the first conductor 150 on the first metal layer 100 is perpendicular to the second conductor 610 on the second metal layer 600. This routing method on the first metal layer 100 and the second metal layer 600 allows the current entering the upper electrode of the silicon capacitor to flow out along the shortest path, thereby shortening the current flow path from the upper electrode terminal to the lower electrode terminal and increasing the width of the current flow path on the interconnect second metal layer 600.
[0061] Example 2: Combining Figures 4 to 6 As shown, by changing the wiring direction of the first conductor 150 and the second conductor 610 on the first metal layer 100 and the second metal layer 600, the current flow path into the silicon capacitor is changed. When changing the wiring direction of the first conductor 150 and the second conductor 610 on the metal layer, the first conductor 150 is arranged parallel to the boundary of the second metal layer 600, and the second conductor 610 starts from the center point of the first metal layer 100 and extends towards the boundary of the first metal layer 100 at a right angle, so that the upper and lower electrode terminals are interconnected with each other and the first metal layer 100 and the second metal layer 600 are interconnected, so that the current flows through each other in a shorter path during the mutual current flow.
[0062] This application also performs parasitic parameter (ESR and ESL) testing on existing two-terminal silicon capacitors, comparing the results with those of Examples 1 and 2 of this application. See 7 and Figure 8 The figures show comparisons of the equivalent series resistance (ESR) and equivalent series inductance (ESL) curves for two terminals, four terminals in Example 1, and four terminals in Example 2. It can be seen that when the deep trench silicon capacitor has only two terminals, its ESR and ESL parameters are higher than the other two curves. When using the routing method of Example 1, its ESR and ESL parameters are the lowest compared to the other two curves. The ESR and ESL parameters of the four-terminal deep trench silicon capacitor using the routing method of Example 2 are between those of the two-terminal silicon capacitor and the four-terminal deep trench silicon capacitor in Example 1. Therefore, combining... Figure 3 and Figure 6 It can be seen that the arrangement of the first conductor 150 on the first metal layer 100 and the arrangement of the second conductor 610 on the second metal layer 600 have changed in Examples 1 and 2. Since the first conductor 150 and the second conductor 610 partially overlap in their relative positions in Example 2, the wiring method on the two metal layers in Example 2 results in a longer current flow distance between the upper and lower electrode terminals compared to Example 1. In summary, the shorter the current flow distance between the upper and lower electrode terminals due to the wiring on the metal layer of the deep trench four-terminal silicon capacitor, the smaller its equivalent series resistance and equivalent series inductance parameters. Furthermore, the four-terminal silicon capacitor also has smaller equivalent series resistance and equivalent series inductance parameters compared to the traditional two-terminal silicon capacitor.
[0063] like Figure 9 As shown, in one embodiment, a method for fabricating a deep trench silicon capacitor includes the following steps:
[0064] Step S910: A first upper electrode terminal, a second upper electrode terminal, a first lower electrode terminal, and a second lower electrode terminal are disposed on one side of the first metal layer.
[0065] Specifically, a first upper electrode terminal, a second upper electrode terminal, a first lower electrode terminal, and a second lower electrode terminal are respectively disposed on the upper surface of the first metal layer, such that the line connecting the first upper electrode terminal and the second upper electrode terminal intersects with the line connecting the first lower electrode terminal and the second lower electrode terminal, that is, the first upper electrode terminal and the second upper electrode terminal are located at the two ends of one diagonal of the first metal layer, and the first lower electrode terminal and the second lower electrode terminal are located at the two ends of the other diagonal of the first metal layer.
[0066] In step S920, a first wire is embedded in the first metal layer, so that the first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal and the second lower electrode terminal can achieve current interaction through the first wire.
[0067] In step S930, a second metal layer is disposed on the other side of the first metal layer, and a silicon substrate is disposed at the bottom of the second metal layer.
[0068] Specifically, a second metal layer is disposed at the bottom of the first metal layer to interconnect the first metal layer and a polycrystalline silicon substrate is disposed at the bottom of the second metal layer.
[0069] In step S940, multiple trenches are formed on the silicon substrate such that the openings of the trenches on the silicon substrate face the second metal layer.
[0070] Specifically, in step S930, multiple trenches are formed on the polycrystalline silicon substrate, and the openings of the formed silicon substrate trenches face the bottom of the second metal layer.
[0071] Step S950: A multilayer stack array is formed in the silicon substrate trench, and the electrode layer of the multilayer stack array is connected to the second metal layer.
[0072] Specifically, a multilayer stack array is formed in the silicon substrate trench opened in step S940, and the electrode layer of the multilayer stack array is interconnected with the bottom of the second metal layer.
[0073] The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal are interconnected to introduce current into the electrode points of the deep trench silicon capacitor from different directions, thereby achieving the interactive flow of current and canceling the magnetic field generated when the current flows in.
[0074] In this embodiment, both the first and second metal layers are rectangular of the same size, and a second wire is embedded in the second metal layer, perpendicular to the first wire. The top of the first metal layer has a first mounting portion, a second mounting portion, a third mounting portion, and a fourth mounting portion. The first and third mounting portions are located at opposite ends of one diagonal of the first metal layer, and the second mounting portion is located at opposite ends of the other diagonal of the first metal layer, and they are connected to each other via the first wire. A first upper electrode terminal is disposed in the first mounting portion, a second upper electrode terminal in the third mounting portion, a first lower electrode terminal in the second mounting portion, and a second lower electrode terminal in the fourth mounting portion. Current flows interactively between the first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal via the first wire.
[0075] The aforementioned deep trench silicon capacitor fabrication method, by designing the interconnection path between the upper and lower electrode terminals of the deep trench silicon capacitor, allows the signal from the upper electrode terminal to reach the lower electrode terminal via the shortest path. It also introduces current into the electrode points of the silicon capacitor from different directions, achieving interactive current flow. This counteracts the magnetic field generated when current flows in, thereby reducing the parasitic parameters of the high-density silicon capacitor, namely the equivalent series resistance and equivalent series inductance. Deep trench capacitor technology and the stacked array structure effectively increase the dielectric layer area of the silicon capacitor, enabling a higher unfolded area for the same projected area. The multi-layer stacked array structure can double the unfolded area, further increasing the dielectric layer area to achieve high-density silicon capacitors. Therefore, this deep trench silicon capacitor, by reducing the equivalent series resistance and equivalent series inductance and increasing the dielectric layer area, improves the performance of the deep trench silicon capacitor to a certain extent.
[0076] It should be noted that the electrode layer of the multilayer stacked array is interconnected with the second metal layer, and interconnected with the first metal layer through the second metal layer. The first and second metal layers are two rectangular metal layers of equal size, each with four corners. The first and second upper electrode terminals are located at two opposite corners of the upper surface of the first metal layer, and the first and second lower electrode terminals are located at the other two opposite corners of the upper surface of the first metal layer. The conductors that enable current exchange are divided into a first conductor and a second conductor. The first conductor is located in the second metal layer and forms a 45° angle with the boundary of the second metal layer, while the second conductor is located in the first metal layer and forms a 90° angle with the first conductor.
[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A deep trench silicon capacitor, characterized in that, include: First metal layer; The upper electrode terminals, including a first upper electrode terminal and a second upper electrode terminal, are diagonally distributed on one side of the first metal layer; The lower electrode terminals include a first lower electrode terminal and a second lower electrode terminal, which are diagonally distributed on one side of the first metal layer, located on the same side of the first metal layer as the upper electrode terminals but at a diagonal position different from the distribution of the upper electrode terminals. The second metal layer is fixedly installed on the other side of the first metal layer; The base includes a silicon substrate and a plurality of trenches formed on the silicon substrate. The silicon substrate is disposed on the side of the second metal layer away from the first metal layer, and the openings of the trenches face the second metal layer. A stack array is disposed inside the trench; The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal are interconnected to introduce current into the electrode points of the deep trench silicon capacitor from different directions, thereby realizing the interactive flow of current and canceling the magnetic field generated when the current flows in. The first metal layer is rectangular, and the top of the first metal layer has a first mounting portion, a second mounting portion, a third mounting portion and a fourth mounting portion, wherein the first mounting portion and the third mounting portion are located at both ends of one diagonal of the first metal layer, and the second mounting portion is located at both ends of the other diagonal of the first metal layer; A first wire is embedded in the first metal layer, and the first mounting part, the second mounting part, the third mounting part and the fourth mounting part are connected to each other through the first wire; The first upper electrode terminal is disposed on the first mounting portion, the second upper electrode terminal is disposed on the third mounting portion, the first lower electrode terminal is disposed on the second mounting portion, and the second lower electrode terminal is disposed on the fourth mounting portion; The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal achieve the interactive flow of current through the first wire; The second metal layer is configured as a rectangle with the same size as the first metal layer; A second wire is embedded in the second metal layer, wherein the second wire is parallel to the diagonal of the second metal layer, and the first wire is perpendicular to the second wire.
2. The deep trench silicon capacitor according to claim 1, characterized in that, The multilayer stack array is arranged in the trench, and the electrode layer of the stack array is connected to the second metal layer and interconnected with the first metal layer through the second metal layer.
3. A method for manufacturing a deep trench silicon capacitor, used to realize the deep trench silicon capacitor according to any one of claims 1 to 2, characterized in that, The method includes: A first upper electrode terminal, a second upper electrode terminal, a first lower electrode terminal, and a second lower electrode terminal are disposed on one side of the first metal layer; A first wire is embedded on the first metal layer, so that the first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal and the second lower electrode terminal can achieve current interaction through the first wire; A second metal layer is disposed on the other side of the first metal layer, and a silicon substrate is disposed at the bottom of the second metal layer; Multiple trenches are formed on the silicon substrate such that the openings of the trenches on the silicon substrate face the second metal layer; A multilayer stack array is disposed in a silicon substrate trench, and the electrode layer of the multilayer stack array is connected to the second metal layer; The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal are interconnected to introduce current into the electrode points of the deep trench silicon capacitor from different directions, thereby realizing the interactive flow of current and canceling the magnetic field generated when the current flows in. The first metal layer and the second metal layer are both rectangular in shape and the second metal layer is embedded with a second wire, which is perpendicular to the first wire.
4. The method for fabricating a deep trench silicon capacitor according to claim 3, characterized in that, The top of the first metal layer is provided with a first mounting part, a second mounting part, a third mounting part and a fourth mounting part, wherein the first mounting part and the third mounting part are located at both ends of one diagonal of the first metal layer, the second mounting part is located at both ends of the other diagonal of the first metal layer, and they are connected to each other through the first wire. The first upper electrode terminal is disposed on the first mounting part, the second upper electrode terminal is disposed on the third mounting part, the first lower electrode terminal is disposed on the second mounting part, and the second lower electrode terminal is disposed on the fourth mounting part. The first upper electrode terminal, the second upper electrode terminal, the first lower electrode terminal, and the second lower electrode terminal achieve the interactive flow of current through the first wire.