Low power consumption optimization method and device for recursive FFT processor

Abstract

This paper proposes a low-power optimization method for a recursive FFT processor. The twiddle factor generation unit, based on a lookup table search method, not only adopts the existing operational architecture but also adds additional judgment and control logic to reduce the number of memory accesses and complex multiplications during the twiddle factor generation process, effectively reducing power consumption. Furthermore, the twiddle factor calculation unit is responsible for performing complex multiplications on the twiddle factors and the butterfly operation results to obtain the final result. For large-scale two-dimensional FFT algorithms, the phase factor replaces the twiddle factor in the last column transform stage. This method uses look-ahead calculation to reduce additional memory read and write accesses at the first stage, thereby reducing power consumption and the computation time of the first-stage FFT.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and more particularly to a low-power consumption optimization method for a twiddle factor generating unit and a twiddle factor calculating unit of a recursive FFT processor. Background Art

[0002] The Fast Fourier Transform (FFT) is a fast calculation method for the Discrete Fourier Transform (DFT) algorithm. FFT and its inverse transform (IFFT) are among the most commonly used algorithms in modern signal processing and communications, and are widely used in digital image processing, radar signal processing, mobile communications, and other fields.

[0003] FFT processors implemented using ASICs can meet the performance and power requirements of specific application scenarios. Several different architectures have been proposed for FFT ASIC implementations, both domestically and internationally. Recursive FFT processors, among others, utilize fewer resources to achieve pipelining and parallelism within each level of computation. For moderate performance requirements, they can flexibly implement FFT operations with varying number of points. Specifically, they can perform not only one-dimensional FFTs with small number of points, but also two-dimensional FFTs with large number of points. However, recursive architectures have complex memory access rules and consume significant power during computation.

[0004] The prior art discloses a twiddle factor generation unit based on a lookup table search method, which has the characteristics of low latency, low power consumption, high precision, and ease of pipeline processing, and is very suitable as a twiddle factor generation unit of a recursive FFT processor.

[0005] However, the lookup table search method requires additional memory access and multiplication operations, and a large number of rotation factors with a value of 1 are also involved in the calculation process. This ineffective operation increases a lot of power consumption. Summary of the Invention

[0006] Purpose of the Invention: To address the problem of excessive power consumption in the prior art due to redundant memory access and redundant multiplication operations, the present invention proposes a low-power optimization method for the twiddle factor generation unit and the twiddle factor calculation unit based on the operational characteristics of the small-scale one-dimensional FFT algorithm and the large-scale two-dimensional FFT algorithm in a recursive FFT processor.

[0007] Technical Solution: First, a twiddle factor generation unit based on a lookup table search method is proposed. It mainly includes an index generation module, an address generation module, a multiplier control module, and a low-power control module. This unit is connected to two constant twiddle factor memories and a complex multiplier. The real-time twiddle factor results are sent to the twiddle factor calculation unit for complex multiplication with the butterfly operation results. This unit also adds additional judgment logic and control logic to reduce the number of memory accesses and multiplications during the twiddle factor generation process, thereby reducing power consumption.

[0008] In some implementations of the first aspect, the index generation module can generate rotation factor indexes for a radix-2, radix-4, radix-8, or two-dimensional FFT algorithm based on the number of points and levels of the current butterfly operation. The four algorithms share the logic for generating the rotation factor indexes, thereby reducing the area of ​​the rotation factor generation unit to a certain extent.

[0009] Furthermore, the address generation module obtains the access offset address based on the generated index and adds additional judgment logic to determine whether the constant rotation factor is 1 through the access offset address. If it is not 1, the constant rotation factor 1 or constant rotation factor 2 is taken from the corresponding addresses of the two constant rotation factor memories. The following four situations may occur:

[0010] The constant rotation factor 1 and the constant rotation factor 2 are both 1;

[0011] The constant rotation factor 1 is 1 and the constant rotation factor 2 is not 1;

[0012] The constant rotation factor 2 is 1 and the constant rotation factor 1 is not 1;

[0013] The constant rotation factor 1 and the constant rotation factor 2 are both not 1;

[0014] The calculation process of these four cases requires different processing.

[0015] Furthermore, the multiplier control module sends the constant rotation factor 1 and the constant rotation factor 2 to the complex multiplier for operation, and the complex multiplier returns the result to the rotation factor generation unit after the operation is completed; if it is the first case, the complex multiplication operation is performed normally; and for the second, third and fourth cases, the two constant rotation factors are no longer sent to the complex multiplier, and are processed by direct registration. Specifically, the control signal needs to be tapped in all three cases, and then the constant rotation factor 2 is registered in the second case, the constant rotation factor 1 is registered in the third case, and no data is registered in the fourth case.

[0016] Furthermore, when the constant rotation factor 1 and the constant rotation factor 2 are both 1, an additional butterfly multiplication enable signal is generated. At this time, the result of the butterfly unit is stored in the register in the rotation factor calculation unit to avoid complex multiplication operations with the rotation factors.

[0017] Secondly, the calculation process of the two-dimensional algorithm under large number of points is optimized.

[0018] First, the operation process of the two-dimensional FFT algorithm is explained. The two-dimensional FFT algorithm divides the input sequence of length N into an N1×N2 matrix. The operation process is divided into three steps:

[0019] Column transformation: perform FFT operation on each column of the matrix;

[0020] Multiply each element of the matrix by the intermediate rotation factor (phase factor);

[0021] Row transformation: perform FFT operation on each row of the matrix.

[0022] Because the twiddle factors in the last butterfly stage of the recursive FFT processor are all 1, they are not multiplied by the twiddle factors during the final butterfly operation, and the result is returned to the source data memory at the original address. The second phase factor multiplication step of the 2D FFT algorithm occurs after the last butterfly stage of the column transform FFT. Therefore, the phase factor is directly used to replace the twiddle factors in the last column transform stage when processing the phase factor. This method of look-ahead calculation reduces the number of additional read and write memory accesses by one level. Beneficial effects

[0023] The twiddle factor generation unit used in the recursive FFT processor of the present invention not only has the operational characteristics of the prior art, but also shares the same calculation logic with radix-2, radix-4, radix-8 and two-dimensional FFT algorithms, thereby reducing the area to a certain extent. At the same time, additional judgment logic and control logic are added, reducing the number of memory accesses and multiplications of the twiddle factor generation unit, thereby greatly reducing power consumption.

[0024] In the second step of the two-dimensional FFT algorithm, the operation process of multiplying the phase factor is advanced by one level, which reduces the power consumption of memory access and also shortens the operation time of the first-level FFT. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the overall framework of the rotation factor generation unit of the present invention.

[0026] Figure 2 FIG. 1 is a schematic diagram of the overall framework of another embodiment of the rotation factor generation unit of the present invention.

[0027] Figure 3It is a low-power optimization logic diagram of the rotation factor generation unit of the present invention.

[0028] Figure 4 Schematic diagram of the operation logic of the rotation factor calculation unit of the present invention. Implementation Method

[0029] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0030] The overall framework of the rotation factor generation unit of the present invention is as follows Figure 1 As shown, compared with the prior art, the rotation factor index of the radix 2, radix 4, radix 8 or two-dimensional FFT algorithm can be generated under the same logic, which reduces the area to a certain extent. At the same time, the judgment logic and control logic are increased, thereby reducing the number of memory accesses and multiplications of the rotation factor generation unit, greatly reducing power consumption. The rotation factor generation unit can not only output the rotation factor result, but also output the butterfly multiplication flag. When the butterfly multiplication flag is valid, the butterfly operation result will not be complex multiplied with the rotation factor. The butterfly operation result is output in the rotation factor calculation unit by registering, effectively reducing power consumption.

[0031] If the twiddle factor generation unit operates as follows: First, it generates a corresponding access offset address sequence based on the length of the current input sequence and retrieves the corresponding constants from two constant memories according to this address sequence; then, these two constants are returned to the generation unit and multiplied by a complex multiplier. The resulting product is processed according to symmetry requirements; finally, the generation unit outputs the twiddle factor sequence. As described in the background, a large number of twiddle factors with a value of 1 are also involved in the calculation process, and this inefficient calculation increases power consumption.

[0032] Among them, the entire low power optimization logic is as follows Figure 2 The specific steps are as follows:

[0033] (1) Generate an index based on the number of points and levels currently calculated, and convert the index into the access offset address of the two constant rotation factor memories. At this time, determine whether the offset address of the constant rotation factor 1 is 0. If the offset address is 0, the constant rotation factor flag bit 1 is valid, and the rotation factor generation unit no longer accesses the constant rotation factor 1 memory; if the offset address is not 0, the constant rotation factor 1 memory is accessed.

[0034] Similarly, the process of determining whether the offset address of the constant rotation factor 2 is 0 is the same as the above process. Figure 2 There are four cases shown in total.

[0035] (2) If both the constant rotation factor flag 1 and the constant rotation factor flag 2 are valid, the butterfly multiplication flag is valid. This flag is used as the output of the rotation factor generation unit to control the operation of the complex multiplier of the butterfly operation unit.

[0036] If the constant twiddle factor flag bit 1 is valid and the constant twiddle factor flag bit 2 is invalid, the constant twiddle factor memory 2 is accessed, the constant twiddle factor 2 is stored, and is output as the twiddle factor result.

[0037] If the constant twiddle factor flag bit 2 is valid and the constant twiddle factor flag bit 1 is invalid, the constant twiddle factor memory 1 is accessed, the constant twiddle factor 1 is stored, and is output as the twiddle factor result.

[0038] If both the constant rotation factor flag bit 1 and the constant rotation factor flag bit 2 are invalid, the constant rotation factor 1 and the constant rotation factor 2 are sent to the complex multiplier for operation, and the result is output as the rotation factor result.

[0039] (3) After outputting the twiddle factor result and the butterfly multiplication flag, the twiddle factor calculation unit determines whether the butterfly multiplication flag is valid. If valid, the butterfly operation result is stored and sent back to the original address as the final result. If invalid, the butterfly operation result is complex multiplied with the twiddle factor, and the result is sent back to the original address as the final result.

[0040] In the prior art, during each butterfly operation in a recursive FFT processor, the result is returned to the source address of the source data memory. The next operation is then re-read from the memory and fed to the butterfly unit to begin the operation. Therefore, after the final operation in a two-dimensional FFT algorithm, the result is returned to the source data memory. The subsequent multiplication by the phase factor involves re-reading the data from the memory for the operation. Because the two-dimensional FFT algorithm in a recursive FFT processor is used to process large numbers of points, multiplying by the phase factor not only consumes a lot of power, but also requires the same amount of time as the first FFT butterfly operation.

[0041] like Figure 2As shown, in a further embodiment, the rotation factor generation unit is composed of an index generation module, an address generation module, a low-power control module and a multiplier control module. The index generation module generates a rotation factor index based on parameters such as the number of points and the number of operation levels input externally, and converts the index into the access address of two constant rotation factor memories in the address generation module. At the same time, the address generation module is also responsible for the read and write control of the memory. The multiplication control module sends the two constant rotation factors read from the memory into the complex multiplier for multiplication, and the result is processed to obtain the rotation factor W. The low-power control module determines the current low-power mode based on the address generated by the address generation module, controls the read and write of the memory and the complex multiplier. The rotation factor calculation unit multiplies the rotation factor W and the butterfly operation result to obtain the final result, and the butterfly multiplication flag controls the multiplication process.

[0042] The present invention advances the operation of multiplying the phase factor by one level, replacing the rotation factor of the last level of the butterfly operation, effectively reducing power consumption. The specific implementation process is as follows:

[0043] Since the twiddle factors in the last stage of the butterfly operation are all 1, the twiddle factor generation unit does not work during the last stage of the butterfly operation. When a phase factor multiplication is required, the twiddle factor generation unit receives a signal from the upper-layer module and starts calculating and generating the phase factor. It then sends the generated phase factor and the butterfly multiplication flag to the twiddle factor calculation unit.

[0044] like Figure 3 As shown, in the twiddle factor calculation unit, a selector is used to determine the current operation process. If the current operation process is not the second step of the two-dimensional FFT algorithm or the last stage of the butterfly operation, the selector MUX0 outputs 0, which is then phase-ORed with the butterfly multiplication flag to obtain the first signal mul_en. The first signal mul_en serves as the selection signal of MUX1 and the drive signal of the complex multiplier request signal mul_req. When the first signal mul_en is 1, the butterfly unit operation result after complex addition / complex subtraction is stored and output and directly sent to the original address of the memory. When the first signal mul_en is 0, the butterfly unit operation result after complex addition / complex subtraction is complex multiplied with the twiddle factor W, and the obtained result is sent to the original address of the memory.

[0045] If the current operation process is not the second step of the two-dimensional FFT algorithm, but the last stage of the butterfly operation, the selector MUX1 outputs 1, so the value of the first signal mul_en is always 1, and all butterfly unit operation results are directly stored and sent to the original address of the memory.

[0046] If the current calculation is the second step of the 2D FFT algorithm, which is also the final stage of the butterfly operation, MUX0 outputs 0, and the rotation factor generation unit generates a phase factor that is sent to the rotation factor calculation unit. This phase factor is multiplied by the butterfly operation result one step earlier. This calculation of the phase factor one step earlier reduces the memory access power consumption and memory access time of the first-stage FFT butterfly operation, thus achieving the goal of reducing power consumption.

[0047] This example uses a 14nm SMIC process library and PTPX to analyze power consumption in a 4-way parallel computing scenario. The analysis of a 1024-point FFT operation at 1GHz reveals that dynamic power consumption was 183.7mW before optimization and 138.1mW after implementing this optimization solution, a reduction of approximately 24%. Furthermore, the calculation cycle for 1024 points was reduced from 1062 to 814 cycles, a reduction of approximately 23%. The reduction in calculation cycles increases with the number of points.

[0048] In summary, this invention primarily addresses the high power consumption issues associated with the operation of the twiddle factor generation unit and the twiddle factor calculation unit. Based on the operational characteristics of small-scale one-dimensional FFT algorithms and large-scale two-dimensional FFT algorithms in recursive FFT processors, this invention proposes a method for optimizing the twiddle factor generation unit and the twiddle factor calculation unit for low power consumption.

[0049] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes may be made to it in form and detail without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A low-power optimization device for a recursive FFT processor, characterized in that: The invention comprises a rotation factor generation unit based on a lookup table search method: the rotation factor generation unit comprises an index generation module, an address generation module, a multiplier control module and a low power consumption control module; The rotation factor generation unit is connected to two constant rotation factor memories and a complex multiplier, and the rotation factor results generated in real time are sent to the rotation factor calculation unit for operation; The rotation factor generation unit adds additional judgment logic and control logic to reduce the number of memory accesses and multiplications during the rotation factor generation process. For the second step of the large-point two-dimensional FFT algorithm multiplying the phase factor by one level, the phase factor is advanced by one level and complex multiplied with the butterfly operation result. The index generation module generates the rotation factor index of the radix 2, radix 4, radix 8 or 2D FFT algorithm according to the number of points and levels of the current butterfly operation. The four algorithms share the logic of rotation factor index generation; The address generation module obtains the data access offset address based on the generated index, and adds additional judgment logic to determine whether the constant rotation factor is 1 through the data access offset address. If it is not 1, the constant rotation factor 1 or constant rotation factor 2 is obtained from the corresponding addresses of the two constant rotation factor memories; The low power control module determines the current low power mode according to the address generated by the address generation module, and controls the reading and writing of the memory and the complex multiplier; The multiplier control module sends the constant rotation factor 1 and the constant rotation factor 2 to the complex multiplier for operation. After the complex multiplier operation is completed, the result is returned to the rotation factor generation unit; If one of the constant rotation factor 1 and the constant rotation factor 2 has a value of 1, the constant rotation factor that is not 1 is output as the result of the rotation factor generation unit; When the constant rotation factor 1 and the constant rotation factor 2 are both 1, an additional butterfly multiplication enable signal is generated. At this time, the butterfly unit operation result is stored in the register in the rotation factor calculation unit to avoid complex multiplication operation with the rotation factor.

2. A low power consumption optimization method for a recursive FFT processor, characterized in that: The steps include: Step S1: Generate an index based on the number of points and levels currently calculated, and convert the index into an access offset address for two constant twiddle factor memories. For constant twiddle factor 1 and constant twiddle factor 2, respectively, perform the following process: determine whether the offset address is 0; if the offset address is 0, the constant twiddle factor flag is valid, and the twiddle factor generation unit no longer accesses the constant twiddle factor memory; if the offset address is not 0, access the constant twiddle factor memory; Step S2: If both the constant twiddle factor flag 1 and the constant twiddle factor flag 2 are valid, the butterfly multiplication flag is valid. This flag is used as the output of the twiddle factor generation unit to control the operation of the complex multiplier of the butterfly operation unit. If the constant twiddle factor flag bit 1 is valid and the constant twiddle factor flag bit 2 is invalid, the constant twiddle factor memory 2 is accessed and the constant twiddle factor 2 is stored and output as the twiddle factor result. If the constant twiddle factor flag bit 2 is valid and the constant twiddle factor flag bit 1 is invalid, the constant twiddle factor memory 1 is accessed and the constant twiddle factor 1 is stored and output as the twiddle factor result. If both the constant rotation factor flag bit 1 and the constant rotation factor flag bit 2 are invalid, the constant rotation factor 1 and the constant rotation factor 2 are sent to the complex multiplier to participate in the operation, and the result is output as the rotation factor result; In step S3, after outputting the twiddle factor result and the butterfly multiplication flag, the twiddle factor calculation unit determines whether the butterfly multiplication flag is valid. If valid, the butterfly operation result is stored and sent back to the original address as the final result. If invalid, the butterfly operation result is complex multiplied by the twiddle factor, and the result is sent back to the original address as the final result.

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