Sub-pixel circuit, display panel and display device

Abstract

Sub-pixel circuits, display panels, and display devices are disclosed. A sub-pixel circuit for operating a sub-pixel of a display panel can include a reference circuit configured to receive a high potential voltage and output a control voltage for controlling a driving current flowing through a light emitting element, a light emitting circuit including the light emitting element, the light emitting circuit configured to receive the control voltage and a low potential voltage and control the light emitting element based on a driving voltage, an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit, and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0182406, filed on December 20, 2021, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a sub-pixel circuit, a display panel, and a display device. Background Art

[0004] Representative display devices that display images based on digital data include liquid crystal display (LCD) devices using liquid crystals and organic light emitting display devices using organic light emitting diodes (OLEDs).

[0005] Among these display devices, organic light emitting diode displays use organic light emitting diodes (OLEDs), which have a fast response capability and various advantages in terms of contrast, luminous efficiency, brightness, and viewing angle. In this case, the LEDs can be implemented using inorganic or organic materials.

[0006] An organic light emitting diode display includes light emitting diodes arranged in sub-pixels on a display panel, and controls the brightness represented by each sub-pixel when displaying an image by controlling current flowing to the light emitting diodes to emit light.

[0007] Such a display device may include a sub-pixel circuit disposed on a display panel to drive a light-emitting element. For example, the sub-pixel circuit includes a drive transistor for controlling a drive current flowing through the light-emitting element, and at least one scan transistor for controlling a gate-source voltage of the drive transistor in response to a scan signal. The scan transistor of the sub-pixel circuit may be controlled by a scan signal output from a gate drive circuit disposed on the substrate of the display panel.

[0008] In this case, characteristic values ​​such as the threshold voltage or mobility of the driving transistor constituting each sub-pixel may vary depending on the driving time, or the characteristic value of each transistor may deviate due to the difference in the driving time of each sub-pixel. This may cause a deviation in brightness between sub-pixels (brightness unevenness), thereby degrading image quality.

[0009] To address the deviation in luminance between sub-pixels, display devices have adopted a technique for sensing characteristic values ​​of sub-pixels (eg, threshold voltage or mobility of a driving transistor) and compensating for the characteristic values ​​of the sub-pixels.

[0010] However, since the light emitting elements constituting the sub-pixels may also degrade according to the usage time of the display device, it is difficult to simultaneously compensate for the degradation of the light emitting elements and the characteristic value of the driving transistor. Summary of the Invention

[0011] The inventors of the present disclosure have invented a sub-pixel circuit, a display panel, and a display device that can simultaneously compensate for degradation of a driving transistor and degradation of a light-emitting element. Therefore, embodiments of the present disclosure relate to a sub-pixel circuit, a display panel, and a display device that substantially eliminate one or more problems due to limitations and disadvantages of the related art.

[0012] Embodiments of the present disclosure may provide a sub-pixel circuit, a display panel, and a display device capable of compensating for degradation of a driving transistor and degradation of a light emitting element simultaneously.

[0013] Embodiments of the present disclosure may provide a sub-pixel circuit, a display panel, and a display device capable of simultaneously compensating for degradation of a driving transistor and degradation of a light emitting element by controlling a driving current flowing through the light emitting element in proportion to a data voltage.

[0014] Embodiments of the present disclosure can provide a sub-pixel circuit, a display panel, and a display device in which a driving current flowing through a light emitting element is controlled to be proportional to a data voltage regardless of changes in a characteristic value of a driving transistor.

[0015] Additional features and aspects will be explained in part in the following description and in part will become apparent from the description, or may be learned by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and obtained through structures specifically pointed out or deducible in the written description, its claims, and the accompanying drawings.

[0016] To achieve these and other aspects of the present inventive concept, as implemented and broadly described herein, a sub-pixel circuit for operating at least one sub-pixel of a plurality of sub-pixels disposed on a display panel may include: a reference circuit configured to receive a high potential voltage and output a control voltage for controlling a driving current flowing through a light-emitting element; a light-emitting circuit including a light-emitting element, the light-emitting circuit configured to receive the control voltage and a low potential voltage, and to control the light-emitting element based on the driving voltage; an amplification circuit configured to compare the control voltage with a data voltage to generate a driving voltage for controlling the light-emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal, and to control a timing for applying the data voltage to the amplification circuit based on the first scan signal.

[0017] In another aspect, a display panel may include a plurality of sub-pixels and the sub-pixel circuitry described in detail above.

[0018] In another aspect, a display device may include: a display panel including a plurality of sub-pixels and a sub-pixel circuit for operating at least one of the plurality of sub-pixels; a gate driver circuit configured to supply a plurality of scan signals to the display panel via a plurality of gate lines; a data driver circuit configured to supply a plurality of data voltages to the display panel via a plurality of data lines; and a timing controller configured to drive the gate driver circuit and the data driver circuit. The sub-pixel circuit may include: a reference circuit configured to receive a high-potential voltage and output a control voltage for controlling a drive current flowing through a light-emitting element; a light-emitting circuit including a light-emitting element, the light-emitting circuit configured to receive the control voltage and a low-potential voltage and control the light-emitting element based on the drive voltage; an amplifier circuit configured to compare the control voltage with a data voltage to generate a drive voltage for controlling the light-emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal and control the timing of applying the data voltage to the amplifier circuit based on the first scan signal.

[0019] According to the embodiments of the present disclosure, a sub-pixel circuit, a display panel, and a display device capable of compensating for degradation of a driving transistor and degradation of a light emitting element at the same time can be provided.

[0020] According to the embodiments of the present disclosure, a sub-pixel circuit, a display panel, and a display device capable of simultaneously compensating for degradation of a driving transistor and a light emitting element by controlling a driving current flowing through the light emitting element in proportion to a data voltage can be provided.

[0021] According to the embodiments of the present disclosure, a sub-pixel circuit, a display panel, and a display device in which a driving current flowing through a light emitting element is controlled to be proportional to a data voltage regardless of changes in a characteristic value of a driving transistor can be provided.

[0022] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the inventive concept as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0024] Figure 1 is a diagram schematically illustrating a configuration of a display device according to various example embodiments of the present disclosure;

[0025] Figure 2 is a diagram illustrating an example of a system of a display device according to an example embodiment of the present disclosure;

[0026] Figure 3 is a diagram illustrating an example of a sub-pixel circuit of a display device.

[0027] Figure 4 is a signal timing diagram illustrating an example of externally compensating the threshold voltage of a driving transistor in a display device;

[0028] Figure 5 is a signal timing diagram illustrating an example of externally compensating the mobility of a drive transistor in a display device;

[0029] Figure 6 is a signal timing diagram illustrating an example of internal compensation for the threshold voltage and mobility of a drive transistor in a display device;

[0030] Figure 7 is a block diagram illustrating a sub-pixel circuit according to an example embodiment of the present disclosure;

[0031] Figure 8 is a diagram illustrating a detailed configuration of a sub-pixel circuit according to an example embodiment of the present disclosure;

[0032] Figure 9 is an example signal waveform diagram illustrating the operation of a sub-pixel circuit according to an example embodiment of the present disclosure;

[0033] Figure 10 is a signal waveform diagram showing that a current flowing through a reference circuit varies according to a data voltage in a sub-pixel circuit according to an example embodiment of the present disclosure;

[0034] Figure 11A 、 Figure 11B and Figure 11C is a signal waveform diagram illustrating changes in current and voltage of a sub-pixel circuit when a driving transistor has different threshold voltages in the sub-pixel circuit according to an example embodiment of the present disclosure;

[0035] Figure 12 is a diagram illustrating a detailed configuration of another sub-pixel circuit according to an example embodiment of the present disclosure; and

[0036] Figure 13 is an example signal waveform diagram illustrating the operation of another sub-pixel circuit according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following example embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided to make the present disclosure sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents.

[0038] Unless otherwise specified, the same reference numerals always refer to the same elements. The names of the various elements used in the following description are selected only for the convenience of writing the specification and may therefore be different from the names used in the actual product.

[0039] In the following description, where a detailed description of related known functions or configurations may unnecessarily obscure one aspect of the example embodiments of the present disclosure, a detailed description of such known configuration functions may be omitted.

[0040] Where the terms “comprise,” “have,” “include,” “contain,” “compose,” “consist of,” “formed of,” etc. are used, one or more other elements may be added unless these terms are used with a more restrictive term, such as “only.” Elements described in the singular are intended to include the plural, and conversely, elements described in the plural are intended to include the singular unless the context clearly indicates otherwise.

[0041] Although the terms "first," "second," A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as these terms are not used to define a particular order or priority. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0042] When expressions are used where an element or layer is “connected to,” “coupled to,” “adhered to,” or “in contact with,” or “overlaps” another element or layer, unless otherwise specified, the element or layer can not only be directly connected, coupled or adhered to, or directly “in contact with,” or “overlap” another element or layer, but can also be indirectly connected, coupled or adhered to, or indirectly “in contact with,” or “overlap” another element or layer with one or more intermediate elements or layers being “disposed” or “interposed” between the elements or layers.

[0043] When a temporal relationship between processes, operations, procedures, steps, events, etc. is described as, for example, "after," "subsequently," "next," or "before," such a relationship not only encompasses a continuous or sequential order, but may also encompass non-continuous or non-sequential relationships, unless more restrictive terms, such as "just," "immediately," or "directly" are used.

[0044] The shapes, sizes, ratios, angles, numbers, etc. of various exemplary embodiments shown in the drawings to describe the present disclosure are given only as examples. Therefore, the present disclosure is not limited to the descriptions in the drawings.

[0045] When explaining an element, even if no explicit description of such an error or tolerance range is provided, the element (including its size and relative size) will be interpreted as including a normal error or tolerance range. The tolerance or error range may be caused by various factors, such as process factors, internal or external influences, noise, etc. In addition, the term "may" fully includes all meanings of the term "can".

[0046] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

[0047] Figure 1 is a diagram schematically illustrating a configuration of a display device according to various example embodiments of the present disclosure.

[0048] like Figure 1 As shown, a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110, in which a plurality of gate lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix. The display device 100 may further include a gate driving circuit 120 for driving the plurality of gate lines GL, a data driving circuit 130 for supplying data voltages through the plurality of data lines DL, a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130, and a power management circuit 150.

[0049] The display panel 110 displays an image based on a scan signal transferred from the gate driving circuit 120 through a plurality of gate lines GL and a data voltage transferred from the data driving circuit 130 through a plurality of data lines DL.

[0050] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. In the case of an organic light emitting display, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a dual emission scheme.

[0051] In the display panel 110, a plurality of pixels may be arranged in a matrix. Each pixel may include sub-pixels SP having different colors, such as white, red, green, and blue sub-pixels. The sub-pixels SP may be defined by a plurality of data lines DL and a plurality of gate lines GL, respectively.

[0052] One subpixel SP may include, for example, a thin film transistor (TFT) formed at a cross point between one data line DL and one gate line GL, a light emitting element such as an organic light emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain a voltage.

[0053] For example, if the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, respectively. Therefore, 3840×4=15360 data lines DL can be provided in the display device 100. Each sub-pixel SP can be provided at the intersection between the corresponding gate line GL and the corresponding data line DL.

[0054] The gate driving circuit 120 may be controlled by the timing controller 140 to sequentially output scan signals to a plurality of gate lines GL disposed in the display panel 110 , thereby controlling a driving timing of the plurality of sub-pixels SP.

[0055] In a display device 100 having a resolution of, for example, 2160×3840, sequentially outputting scan signals to 2160 gate lines GL from the first gate line to the 2160th gate line can be referred to as 2160-phase driving. Sequentially outputting scan signals to each unit of four gate lines GL, for example, sequentially outputting scan signals to the fifth to eighth gate lines after sequentially outputting scan signals to the first to fourth gate lines, is referred to as a 4-phase driving method. In other words, sequentially outputting scan signals to every N gate lines GL can be referred to as N-phase driving.

[0056] The gate driver circuit 120 may include one or more gate driver integrated circuits (GDICs). Depending on the driving scheme to be implemented, the gate driver circuit 120 may be located on only one side of the display panel 110 or on each of two opposing sides. The gate driver circuit 120 may be implemented in the form of a gate-in-panel (GIP) embedded in the bezel area of ​​the display panel 110.

[0057] The data driving circuit 130 may receive image data DATA from the timing controller 140 and convert the received image data DATA into an analog data voltage. Then, as the data voltage may be output to each data line DL according to the timing of the scan signal applied to the corresponding gate line GL, each sub-pixel SP connected to the data line DL may display a light emitting signal having a brightness corresponding to the data voltage.

[0058] Likewise, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs). The source driver integrated circuits (SDICs) may be connected to bonding pads of the display panel 110 using a tape automated bonding (TAB) or chip on glass (COG) method, or may be directly disposed on the display panel 110.

[0059] In some cases, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit SDIC may be implemented in a chip-on-film (COF) type. In this case, each source driver integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to a corresponding data line DL of the display panel 110 through the circuit film.

[0060] The timing controller 140 may provide various control signals to the gate driving circuit 120 and the data driving circuit 130, and may control the operations of the gate driving circuit 120 and the data driving circuit 130. In other words, the timing controller 140 may control the gate driving circuit 120 to output a scan signal according to a timing implemented in each frame, and on the other hand, may transfer image data DATA received from an external device (e.g., via the host system 200) to the data driving circuit 130.

[0061] In this case, the timing controller 140 receives several timing signals including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK, along with the image data DATA from the external host system 200 .

[0062] The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device, but the present invention is not limited thereto.

[0063] Therefore, the timing controller 140 may generate control signals according to various timing signals received from the host system 200 and may transfer the control signals to the gate driving circuit 120 and the data driving circuit 130 .

[0064] For example, the timing controller 140 can output several gate control signals, including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE, to control the gate driver circuit 120. The gate start pulse GSP can control the timing at which one or more gate driver integrated circuits GDIC constituting the gate driver circuit 120 start operating. The gate clock GCLK is a clock signal commonly input to one or more gate driver integrated circuits GDIC and can control the shift timing of the scan signal. The gate output enable signal GOE can specify timing information about the one or more gate driver integrated circuits GDIC.

[0065] The timing controller 140 can output various data control signals, including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE, to control the data driver circuit 130. The source start pulse SSP can control the timing at which one or more source driver integrated circuits (SDICs) constituting the data driver circuit 130 begin data sampling. The source sampling clock SCLK is a clock signal that can control the timing of data sampling in the source driver integrated circuits (SDICs). The source output enable signal SOE can control the output timing of the data driver circuit 130.

[0066] The display device 100 may further include a power management circuit 150 that supplies various voltages or currents to, for example, the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 or controls the various voltages or currents to be supplied.

[0067] The power management circuit 150 may adjust a direct current (DC) input voltage Vin provided from the host system 200 to generate power required to drive the display panel 100 , the gate driving circuit 120 , and the data driving circuit 130 .

[0068] The sub-pixel SP may be positioned at an intersection between a corresponding gate line GL and a corresponding data line DL, and a light-emitting element may be provided in each sub-pixel SP. For example, an organic light-emitting diode display may include a light-emitting element such as an organic light-emitting diode in each sub-pixel SP, and may display an image by controlling a current flowing to the light-emitting element according to a data voltage.

[0069] The display device 100 may be one of various types of devices such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0070] Figure 2 is a diagram illustrating an example of a system of a display device according to an example embodiment of the present disclosure.

[0071] like Figure 2As shown, in the display device 100 according to an example embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 can be implemented in a chip-on-film (COF) type among various types (e.g., TAB, COG, or COF), and the gate driver circuit 120 can be implemented in a gate-in-panel (GIP) type among various types (e.g., TAB, COG, COF, or GIP).

[0072] When the gate driving circuit 120 is implemented as a GIP type, a plurality of gate driving integrated circuits GDIC included in the gate driving circuit 120 may be directly formed in the bezel region of the display panel 110. In this case, the gate driving integrated circuits GDIC may receive various signals (e.g., a clock signal, a gate high signal, a gate low signal, etc.) for generating a scan signal through gate driving-related signal lines provided in the bezel region.

[0073] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be mounted on the source film SF, and one side of the source film SF may be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits SDIC and the display panel 110 may be provided on the source film SF.

[0074] The display device 100 may include at least one source printed circuit board SPCB for making circuit connections between a plurality of source driving integrated circuits SDIC and other devices, and may include a control printed circuit board CPCB for mounting control components and various electronic devices.

[0075] The other side of the source film SF on which the source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. In other words, the side of the source film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, while the other side thereof can be electrically connected to the source printed circuit board SPCB.

[0076] The timing controller 140 and the power management circuit (power management IC) 150 may be mounted on the control printed circuit board (CPCB). The timing controller 140 may control the operation of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may supply power voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120 and may control the supplied voltage or current.

[0077] The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be electrically connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0078] The display device 100 may also include a setup board 170 electrically connected to the control printed circuit board (CPCB). In this case, the setup board 170 may also be referred to as a power board. A main power management circuit 160 for managing the overall power of the display device 100 may be provided on the setup board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0079] In the example display device 100 configured in this manner, a power voltage may be generated in the setup board 170 and transmitted to the power management circuit 150 in the control printed circuit board (CPCB). The power management circuit 150 may transmit the power voltage for display driving or characteristic value sensing to the source printed circuit board (SPCB) via a flexible printed circuit (FPC) or a flexible flat cable (FFC). The power voltage transmitted to the source printed circuit board (SPCB) may be supplied by a source driver integrated circuit (SDIC) to emit light or sense specific sub-pixels (SP) in the display panel 110.

[0080] Each sub-pixel SP arranged in the display panel 110 in the display device 100 may include a light emitting element and a circuit element for driving the light emitting element, such as an organic light emitting diode, such as a driving transistor.

[0081] The type and number of circuit elements constituting each sub-pixel SP may vary depending on the functions to be provided and the design scheme.

[0082] Figure 3 is a diagram illustrating an example of a sub-pixel circuit of a display device.

[0083] like Figure 3 As shown, an example sub-pixel circuit may include one or more transistors and capacitors and may have a light emitting element disposed therein.

[0084] For example, the sub-pixel circuit may include a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, and a light emitting element ED.

[0085] The driving transistor DRT may include a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node to which the data voltage Vdata is applied from the data driving circuit 130 through the corresponding data line DL when the scan transistor SCT is turned on.

[0086] The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting diode ED and may be one of a source node or a drain node.

[0087] The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL to which the high potential voltage EVDD is applied and may be the other of the drain node and the source node.

[0088] In this case, during the display driving period, a high potential voltage EVDD required for displaying an image may be supplied to the driving voltage line DVL. For example, the high potential voltage EVDD for displaying an image may be 27V.

[0089] The scan transistor SCT may be electrically connected between the first node N1 of the drive transistor DRT and the data line DL, and the corresponding gate line GL may be connected to the gate node of the scan transistor SCT. Therefore, the scan transistor SCT may operate according to the first scan signal SCAN1 supplied through the gate line GL. When turned on, the scan transistor SCT may transfer the data voltage Vdata supplied through the data line DL to the gate node (i.e., the first node N1) of the drive transistor DRT, thereby controlling the operation of the drive transistor DRT.

[0090] The sensing transistor SENT may be electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and a corresponding gate line GL may be connected to the gate node of the sensing transistor SENT. The sensing transistor SENT may operate according to a second scan signal SCAN2 supplied via the gate line GL. When the sensing transistor SENT is turned on, a reference voltage Vref supplied via the reference voltage line RVL may be transmitted to the second node N2 of the driving transistor DRT.

[0091] In other words, when the scan transistor SCT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the second node N2 of the driving transistor DRT may be controlled so that current for driving the light emitting diode ED may be supplied.

[0092] The gate nodes of the scanning transistor SCT and the sensing transistor SENT may be commonly connected to one gate line GL, or may be connected to different gate lines GL. FIG. 2 shows an example in which the scanning transistor SCT and the sensing transistor SENT are connected to different gate lines GL. In this example, the scanning transistor SCT and the sensing transistor SENT may be independently controlled by a first scanning signal SCAN1 and a second scanning signal SCAN2 transmitted through different gate lines GL, respectively.

[0093] On the other hand, if the scanning transistor SCT and the sensing transistor SENT are commonly connected to one gate line GL, the scanning transistor SCT and the sensing transistor SENT can be simultaneously controlled by the first scan signal SCAN1 or the second scan signal SCAN2 transmitted through one gate line GL, and the aperture ratio of the subpixel SP can be increased.

[0094] Each transistor provided in the sub-pixel circuit may be an N-type transistor or a P-type transistor. Figure 3 In the example shown, the transistors are N-type transistors.

[0095] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and may maintain the data voltage Vdata during one frame.

[0096] Depending on the type of the driving transistor DRT, a storage capacitor Cst may also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the light emitting diode ED may be electrically connected to the second node N2 of the driving transistor DRT, and the low potential voltage EVSS may be applied to the cathode electrode of the light emitting diode ED.

[0097] The low potential voltage EVSS may be a ground voltage or a voltage higher or lower than the ground voltage. The low potential voltage EVSS may vary depending on the driving state. For example, the low potential voltage EVSS during display driving and the low potential voltage EVSS during sensing driving may be set to be different from each other.

[0098] The scan transistor SCT and the sense transistor SENT may be referred to as switching transistors that are controlled by scan signals SCAN1 and SCAN2 , respectively.

[0099] The structure of the sub-pixel SP may also include one or more additional transistors, or in some cases, one or more additional capacitors.

[0100] In this case, in order to effectively sense the characteristic value (e.g., threshold voltage or mobility) of the driving transistor DRT, the display device 100 may use a method for measuring the current flowing due to the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT. This is called current sensing.

[0101] In other words, the characteristic value or change in the characteristic value of the driving transistor DRT in the subpixel SP may be derived by measuring the current flow caused by the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT.

[0102] In this case, the reference voltage line RVL can not only be used to transmit the reference voltage Vref, but also be used as a sensing line for sensing the characteristic value of the driving transistor DRT in the sub-pixel. Therefore, the reference voltage line RVL can also be called a sensing line or a sensing channel.

[0103] More specifically, the characteristic value of the driving transistor DRT or the change in the characteristic value may correspond to a difference between a gate node voltage and a source node voltage of the driving transistor DRT.

[0104] Compensation for the characteristic value of the driving transistor DRT can be performed by external compensation using an external compensation circuit to sense and compensate for the characteristic value of the driving transistor DRT. Alternatively, compensation can be performed by internal compensation that senses and compensates for the characteristic value of the driving transistor DRT inside the sub-pixel SP, rather than using an additional external configuration.

[0105] In this case, external compensation may be performed before the display apparatus 100 is shipped, and internal compensation may be performed after the display apparatus 100 is shipped. However, even after the display apparatus 100 is shipped, internal compensation and external compensation may be performed together.

[0106] Figure 4 is a signal timing diagram illustrating an example of externally compensating the threshold voltage of a driving transistor in a display device.

[0107] like Figure 4 As shown, sensing of the threshold voltage Vth of the driving transistor DRT in the exemplary display device 100 may be performed in an initialization phase INITIAL, a tracking phase TRACKING, and a sampling phase SAMPLING.

[0108] In this case, since the scanning transistor SCT and the sensing transistor SENT are simultaneously turned on and off for sensing the threshold voltage Vth of the driving transistor DRT, the first scanning signal SCAN1 and the second scanning signal SCAN2 can be applied together through one gate line GL, or the first scanning signal SCAN1 and the second scanning signal SCAN2 can be applied simultaneously through different gate lines GL, respectively.

[0109] The initialization phase INITIAL is a period during which the second node N2 of the driving transistor DRT may be charged with the reference voltage Vref to sense the threshold voltage Vth of the driving transistor DRT, and the first and second scan signals SCAN1 and SCAN2 having a high level may be applied through the gate line GL.

[0110] The tracking phase TRACKING is a period in which charges may be stored in the storage capacitor Cst after charging of the second node N2 of the driving transistor DRT is completed.

[0111] The sampling phase SAMPLING is a period in which a current flow from charges stored in the storage capacitor Cst is detected after the storage capacitor Cst of the driving transistor DRT is charged.

[0112] If the first and second scan signals SCAN1 and SCAN2 are simultaneously applied in the initialization phase INITIAL, the scan transistor SCT may be turned on. Therefore, the first node N1 of the driving transistor DRT may be initialized to a sensing data voltage Vdata_sen for sensing a threshold voltage Vth.

[0113] The sensing transistor SENT may also be turned on by the first and second scan signals SCAN1 and SCAN2 at an on level, and a reference voltage Vref may be applied through the reference voltage line RVL. Therefore, the second node N2 of the driving transistor DRT may be initialized to the reference voltage Vref.

[0114] In the tracking phase TRACKING, the voltage of the second node N2 of the driving transistor DRT reflecting the threshold voltage Vth of the driving transistor DRT may be tracked. To this end, in the tracking phase TRACKING, the scanning transistor SCT and the sensing transistor SENT may remain in the on state, and the reference voltage Vref applied through the reference voltage line RVL may be cut off.

[0115] Therefore, the second node N2 of the driving transistor DRT may float, and the voltage at the second node N2 of the driving transistor DRT may begin to rise from the reference voltage Vref. In this case, since the sensing transistor SENT is turned on, the increase in the voltage at the second node N2 of the driving transistor DRT may cause the voltage on the reference voltage line RVL to increase.

[0116] In this process, the voltage at the second node N2 of the driving transistor DRT may increase and then saturate. The saturation voltage when the second node N2 of the driving transistor DRT reaches the saturation state may correspond to the difference (Vdata_sen-Vth) between the sensing data voltage Vdata_sen for sensing the threshold voltage Vth and the threshold voltage Vth of the driving transistor DRT.

[0117] In the sampling phase SAMPLING, the first and second scan signals SCAN1 and SCAN2 of a high level may be maintained to the gate line GL, and charges stored in the storage capacitor Cst of the driving transistor DRT may be detected by the characteristic value detection circuit included in the data driving circuit 130 .

[0118] Figure 5 is a signal timing diagram illustrating an example of externally compensating the mobility of a drive transistor in a display device.

[0119] like Figure 5 As shown, like the sensing of the threshold voltage Vth, the sensing of the mobility of the driving transistor DRT in the exemplary display device 100 may be performed in the initialization phase INITIAL, the tracking phase TRACKING, and the sampling phase SAMPLING.

[0120] In the initialization phase INITIAL, the scanning transistor SCT may be turned on by the first scanning signal SCAN1 at an on-level, so that the first node N1 of the driving transistor DRT may be initialized to the data voltage Vdata_sen for mobility sensing. In addition, the sensing transistor SENT may be turned on by the second scanning signal SCAN2 at an on-level, and in this state, the second node N2 of the driving transistor DRT may be initialized to the reference voltage Vref.

[0121] The tracking phase TRACKING is a phase for tracking the mobility of the driving transistor DRT. The mobility of the driving transistor DRT may indicate the current driving capability of the driving transistor DRT and may be calculated by tracking the voltage of the second node N2 of the driving transistor DRT throughout the tracking phase TRACKING.

[0122] In the tracking phase TRACKING, the scanning transistor SCT may be turned off by the first scanning signal SCAN1 at an off level, and the switch through which the reference voltage Vref is applied to the reference voltage line RVL may be turned off. Therefore, the first node N1 and the second node N2 of the driving transistor DRT may both be floated, and the voltages of both the first node N1 and the second node N2 of the driving transistor DRT may increase.

[0123] In particular, since the voltage at the second node N2 of the driving transistor DRT can be initialized to the reference voltage Vref, it can increase from the reference voltage Vref. In this case, since the sensing transistor SENT is turned on, the increase in the voltage at the second node N2 of the driving transistor DRT causes the voltage on the reference voltage line RVL to increase.

[0124] In the sampling phase SAMPLING, the characteristic value sensing circuit can detect the voltage of the second node N2 of the drive transistor DRT at a predetermined amount of time Δt after the voltage at the second node N2 starts to increase.

[0125] In this case, the sensing voltage detected by the characteristic value sensing circuit can indicate the voltage Vref+ΔV, i.e., the reference voltage Vref plus the predetermined voltage ΔV. The mobility of the drive transistor DRT can be calculated based on the thus-detected sensing voltage Vref+ΔV, the known reference voltage Vref, and the amount of time Δt of the voltage increase ΔV of the second node N2.

[0126] In other words, the mobility of the drive transistor DRT is proportional to the voltage change ΔV / Δt per unit time on the reference voltage line RVL throughout the tracking phase TRACKING and the sampling phase SAMPLING. Thus, the mobility of the drive transistor DRT can be proportional to the slope of the voltage waveform on the reference voltage line RVL.

[0127] Figure 6 is a signal timing diagram illustrating an example of internal compensation of a threshold voltage and a mobility of a drive transistor in a display device.

[0128] As Figure 6 indicated, the internal compensation of the characteristic values of the drive transistor DRT in the display device 100 can be performed in the initialization phase INITIAL, the threshold voltage sensing phase Vth SENSING, the mobility compensation phase μCOMPENSATION, and the emission phase EMISSION.

[0129] In the initialization phase INITIAL, a second scan signal SCAN2 of a high level can be input to turn on the sensing transistor SENT, thereby initializing the voltage of the second node N2 (i.e., the source node voltage of the drive transistor DRT) to the reference voltage Vref.

[0130] Thereafter, a first scan signal SCAN1 of a high level can be provided to turn on the scan transistor SCT, and a data voltage Vdata can be provided to the first node N1 (i.e., the gate node of the drive transistor DRT) to turn on the drive transistor DRT. Subsequently, if the data voltage Vdata decreases to the level of the bias voltage Vos, the voltage of the first node N1 can become the level of the bias voltage Vos.

[0131] If a low level of the second scan signal SCAN2 is applied to turn off the sensing transistor SENT in the threshold voltage sensing phase Vth SENSING, the voltage of the second node N2 can rise to a voltage that is the difference between the bias voltage Vos of the driving transistor DRT and the threshold voltage Vth, such that the storage capacitor Cst is charged with a voltage of the threshold voltage Vth level.

[0132] In the mobility compensation phase μCOMPENSATION, the voltage of the first node N1 can be increased to the level of the data voltage Vdata by applying the gray scale to be displayed through the display panel 110, i.e., the corresponding data voltage Vdata. Accordingly, the second node N2 can be gradually charged according to the mobility (μ) characteristics of the driving transistor DRT. Accordingly, the storage capacitor Cst can store the difference voltage, i.e., the sum of the data voltage Vdata and the threshold voltage Vth minus the voltage variation ΔV according to the bias voltage Vos and the mobility μ.

[0133] In the emission phase EMISSION, a low level of the first scan signal SCAN1 can be applied to turn off the scan transistor SCT, such that the driving transistor DRT applies a current whose threshold voltage Vth and mobility μ have been corrected through the voltage level stored in the storage capacitor Cst to the light emitting diode EL.

[0134] Such internal compensation or external compensation can be performed after a power-on signal is generated in the display device 100 and before display driving starts. For example, if the power-on signal is applied to the display device 100, the timing controller 140 can load various parameters for driving the display panel 110, and then can drive the display.

[0135] In this case, the parameters for driving the display panel 110 can include information about sensing and compensation of the characteristic values previously performed on the display panel 110. In the parameter loading process, sensing and compensation of the characteristic values (threshold voltage and mobility) of the driving transistor DRT can be performed. As described above, the process of sensing the characteristic values in the parameter loading process after the power-on signal is generated can be referred to as a power-on sensing process.

[0136] Alternatively, a period in which the characteristic values of the driving transistor DRT are sensed and compensated can be made after a power-off signal of the display device 100 is generated. For example, when the power-off signal is generated in the display device 100, the timing controller 140 can cut off the data voltage supplied to the display panel 110, and can sense the characteristic values of the driving transistor DRT for a predetermined time. As such, the sensing process for sensing the characteristic values in a state in which the data voltage is cut off when the power-off signal is generated can be referred to as a power-off sensing process.

[0137] In addition, sensing and compensation of the characteristic value of the driving transistor DRT can be performed in real time while driving the display. This sensing process is called a real-time (RT) sensing process. In the real-time sensing process, the sensing process can be performed on one or more sub-pixels SP in one or more sub-pixel SP rows during each blank period during the display driving period.

[0138] In other words, during a display driving period in which an image is displayed on the display panel 110, a blank period in which no data voltage is supplied to the subpixels SP may exist within a frame or between one frame and the next frame. During the blank period, characteristic value sensing and compensation of one or more subpixels SP may be performed.

[0139] In this way, when performing sensing during the blanking period, a row of sub-pixels SP for which sensing is performed can be randomly selected. Therefore, after performing the sensing process during the blanking period, abnormalities that may occur during the display driving period can be mitigated. During the display driving period following the sensing process performed during the blanking period, a restored data voltage can be supplied to the sub-pixels SP for which sensing has already been performed. Therefore, during the display driving period following the sensing process during the blanking period, abnormalities in the row of sub-pixels SP for which sensing has already been performed can be further mitigated.

[0140] In this case, since saturation of the voltage at the second node N2 of the drive transistor DRT may take a relatively long time, threshold voltage sensing of the drive transistor DRT may take a long time, and thus sensing and compensation of the drive transistor DRT may be primarily performed as a power-off sensing process. In contrast, since mobility sensing of the drive transistor DRT may take a relatively short time compared to the threshold voltage sensing process, mobility sensing and compensation may be performed as a real-time sensing process.

[0141] However, in the display device 100, the light emitting element ED constituting the sub-pixel may also degrade according to driving time. The above internal compensation and external compensation may not be able to compensate for the degradation of the light emitting element ED and the characteristic value of the driving transistor DRT at the same time.

[0142] Therefore, the embodiments of the present disclosure provide a sub-pixel circuit, a display panel, and a display device that can simultaneously compensate for the degradation of the light-emitting element ED and the degradation of the driving transistor DRT by presenting a new sub-pixel circuit that is controlled so that the driving current flowing through the light-emitting element ED can be proportional to the data voltage Vdata.

[0143] Therefore, a sub-pixel circuit, a display panel, and a display device can be provided in which the driving current flowing through the light emitting element ED can be kept constant despite the variation in the characteristic value of the driving transistor DRT.

[0144] Figure 7 is a block diagram illustrating a sub-pixel circuit according to an example embodiment of the present disclosure.

[0145] As Figure 7 indicated, the sub-pixel circuit 300 according to an example embodiment of the present disclosure can include a reference circuit 310, a light emitting circuit 320, an amplification circuit 330, and an input circuit 340.

[0146] The reference circuit 310 can receive a high potential voltage EVDD and can control a change in a driving current Id flowing through the light emitting circuit 320. For example, when a control voltage Vc at an input node of the light emitting circuit 320 has the same potential as a data voltage Vdata, a current I3 applied to the amplification circuit 330 becomes 0, so that a reference current Iref flowing through the reference circuit 310 has the same value as the driving current Id flowing through the light emitting circuit 320.

[0147] During a display driving period, the high potential voltage EVDD can have a level required to display an image. For example, the high potential voltage EVDD to display an image can be 27 V, but the present disclosure is not limited thereto.

[0148] The light emitting circuit 320 can be positioned between the control voltage Vc and a low potential voltage EVSS and can control an operation of the light emitting element ED according to a driving voltage Vd at an output node of the amplification circuit 330. When the light emitting element ED is turned on, the driving current Id can flow through the light emitting circuit 320.

[0149] The low potential voltage EVSS can be a ground voltage or a voltage higher or lower than the ground voltage. The low potential voltage EVSS can vary according to a driving state. For example, the low potential voltage EVSS during display driving and the low potential voltage EVSS during sensing driving can be set to be different from each other.

[0150] The amplification circuit 330 can compare the control voltage Vc with the data voltage Vdata to generate the driving voltage Vd for controlling an operation of the light emitting circuit 320. For example, the amplification circuit 330 can be formed of an operational amplifier having an inverting input terminal to which the control voltage Vc is applied and a non-inverting input terminal (+) to which an output voltage from the input circuit 340 is applied.

[0151] A resistance value of the light emitting circuit 320 can decrease in inverse proportion to the driving voltage Vd of the amplification circuit 330. When the control voltage Vc is greater than the data voltage Vdata, the driving voltage Vd corresponding to the output node of the amplification circuit 330 can decrease.

[0152] Therefore, when the control voltage Vc and the data voltage Vdata have the same level, the operation of the amplification circuit 330 may be stopped, and the control voltage Vc may maintain the same level as the data voltage Vdata.

[0153] The input circuit 340 may determine a time when the data voltage Vdata is applied to the non-inverting input terminal (+) of the amplification circuit 330 through the scan signal SCAN.

[0154] In other words, the exemplary sub-pixel circuit 300 of the present disclosure can be controlled to allow the control voltage Vc to maintain a level proportional to the data voltage Vdata, so that the driving current Id flowing through the light-emitting element ED is proportional to the level of the data voltage Vdata. Therefore, regardless of the degradation of the light-emitting element ED or the characteristic value of the driving transistor, a current proportional to the data voltage Vdata can flow through the light-emitting element ED, thereby maintaining the brightness of the display device 100.

[0155] Figure 8 is a diagram illustrating a detailed configuration of a sub-pixel circuit according to an example embodiment of the present disclosure.

[0156] like Figure 8 As shown, the sub-pixel circuit 300 according to an exemplary embodiment of the present disclosure may include a reference circuit 310, a light emitting circuit 320, an amplifying circuit 330, and an input circuit 340. The following describes an exemplary sub-pixel circuit 300 to which an n-th scan signal SCAN(n) is applied, for example, among a plurality of sub-pixels constituting the display panel 110.

[0157] The reference circuit 310 may include a reference transistor Tref having a drain node and a gate node to which a control voltage Vc may be supplied, and a source node to which a high potential voltage EVDD may be applied.

[0158] The light-emitting circuit 320 may include a light-emitting element ED and a driving transistor Td, wherein the light-emitting element ED has a cathode electrode to which a low potential voltage EVSS can be applied, and the driving transistor Td has a drain node connected to the anode electrode of the light-emitting element, a source node to which a control voltage Vc can be applied, and a gate node to which a driving voltage Vd of the amplifier circuit 330 can be applied.

[0159] The reference transistor Tref may be turned on while the high potential voltage EVDD is applied to the source node, and when the driving transistor Td is turned on by the driving voltage Vd of the amplification circuit 330 , the driving current Id may flow through the light emitting circuit 320 .

[0160] In this case, when the control voltage Vc and the data voltage Vdata have the same level of potential, the entire reference current Iref flowing through the reference circuit 310 may flow through the light emitting circuit 320 , and the driving current Id may have the same value as the reference current Iref.

[0161] The amplifier circuit 330 may include a control transistor Tc, a reset transistor Trst, and a first capacitor C1. The control transistor Tc may have a gate node to which a control voltage Vc may be applied and a drain node connected to the gate node of the drive transistor Td. The reset transistor Trst may have a source node to which a reset voltage Vrst may be applied, a gate node to which an (n-1)th scan signal SCAN(n-1) may be applied, and a drain node shared with the control transistor Tc. The first capacitor C1 may be connected to the drain node of the control transistor Tc to transfer a power voltage Vp for driving the drive transistor Td.

[0162] The reset voltage Vrst may be applied at a voltage level configured to turn off the driving transistor Td.

[0163] The power voltage Vp may be applied at a level capable of driving the driving transistor Td at a certain point in time, and the level may be changed by the charge stored in the first capacitor C1. In other words, the power voltage Vp may not continuously maintain a constant voltage level.

[0164] The input circuit 340 may include a switching transistor Tsw and a second capacitor C2. The switching transistor Tsw may have a gate node to which the nth scan signal SCAN(n) may be applied, a source node to which the data voltage Vdata may be applied, and a drain node connected to the source node of the control transistor Tc. The second capacitor C2 may be connected between the drain node of the switching transistor Tsw and the low potential voltage EVSS.

[0165] Therefore, the input circuit 340 may supply the data voltage Vdata to the amplifying circuit 330 through the n-th scan signal SCAN(n). The second capacitor C2 may be used to stably transfer the data voltage Vdata.

[0166] The transistors Td, Tref, Tc, Trst, and Tsw constituting the example sub-pixel circuit 300 may be P-type transistors or N-type transistors.

[0167] P-type transistors are relatively more reliable than N-type transistors. In the case of a P-type transistor, since the driving transistor Td can be fixed to the high potential voltage EVDD during the period when the light-emitting element ED emits light, the current flowing through the light-emitting element ED can be stably supplied without significant fluctuations.

[0168] When operating in the saturation region, the P-type transistor can flow a constant current regardless of a change in threshold voltage, thereby providing relatively high reliability.

[0169] On the other hand, since the N-type transistor uses electrons rather than holes as carriers, the N-type transistor has a higher mobility than the P-type transistor, thereby enabling an increase in switching speed.

[0170] The N-type transistor can be an oxide transistor formed of an oxide semiconductor (e.g., a transistor having a channel formed of an oxide semiconductor such as indium, gallium, zinc oxide, or IGZO). The P-type transistor can be a silicon transistor formed of a semiconductor such as silicon (e.g., a transistor having a polysilicon channel formed by a low-temperature process called LTPS or low-temperature polysilicon).

[0171] Described herein is an example in which the transistors Td, Tref, Tc, Trst, and Tsw constituting the sub-pixel circuit 300 are P-type transistors.

[0172] The terms "source node" and "drain node" of a transistor can be used interchangeably depending on the input voltage.

[0173] Figure 9 FIG. 7 is an example signal waveform diagram illustrating an operation of the sub-pixel circuit according to an example embodiment of the present disclosure.

[0174] Referring to Figure 9 , the operation of the sub-pixel circuit 300 driven by the nth scan signal SCAN(n) in the display device 100 according to an example embodiment of the present disclosure is described below.

[0175] If the reset transistor Trst is turned on by the (n-1)th scan signal SCAN(n-1) before the nth scan signal SCAN(n), the reset voltage Vrst can be applied to the gate node of the driving transistor Td to turn off the driving transistor Td. The power voltage Vp can increase to the level of the reset voltage Vrst.

[0176] Thereafter, if the nth scan signal SCAN(n) is applied to turn on the switch transistor Tsw, the data voltage Vdata can be applied to the second capacitor C2. In this case, the power voltage Vp can decrease at a constant slope. If the power voltage Vp reaches the threshold voltage level of the driving transistor Td, the driving transistor Td can be turned on, and the reference current Iref flowing through the reference circuit 310 can be transferred to the light emitting circuit 320 through the driving transistor Td.

[0177] The control voltage Vc corresponding to the output voltage of the reference circuit 310 can be reduced by the reference current Iref and the drive current Id flowing from the reference circuit 310 through the light emitting circuit 320.

[0178] If the control voltage Vc is reduced and reaches the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc, the control transistor Tc can be turned on. If the control transistor Tc is turned on, the charge stored in the first capacitor C1 can be moved to the second capacitor C2, so that the drive current Id flowing through the drive transistor Td can be reduced. Accordingly, the control voltage Vc can be increased, and the control transistor Tc can be turned off.

[0179] As the control transistor Tc is repeatedly turned on and off for a short period, the control voltage Vc can maintain the level of the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc.

[0180] In this state, the reference current Iref flowing through the reference transistor Tref in the saturation region can be expressed as follows:

[0181] Iref = K * [(Vc - Vth(Tref)] 2 = K * [(Vdata + Vth(Tc) - Vth(Tref)] 2

[0182] Here, K = Cox * (W / L) * μ, W and L respectively denote the channel width and length of the reference transistor Tref, Cox denotes the capacitance of the gate insulating film, and μ denotes the mobility of the reference transistor Tref.

[0183] In this case, if the deposition conditions of the control transistor Tc and the reference transistor Tref positioned adjacent to each other are maintained to be the same, the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref can have the same value. In other words, the control transistor Tc and the reference transistor Tref can be formed to have the same threshold voltage Vth by maintaining the thickness and composition ratio of the gate node, the source node, the drain node, and the insulating film located therebetween under the same conditions in the process of depositing the control transistor Tc and the reference transistor Tref.

[0184] If the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref have the same value, the reference current Iref flowing through the reference transistor Tref can be expressed as:

[0185] Iref = K * Vdata2

[0186] In other words, since both the drive current Id flowing through the light emitting element ED and the reference current Iref flowing through the reference transistor Tref are proportional to the data voltage Vdata, the drive current Id for driving the light emitting element ED can be adjusted by the data voltage Vdata regardless of the characteristic value of the light emitting element ED or the characteristic value of the drive transistor Td.

[0187] On the other hand, if the drive transistor Td is an oxide transistor, the threshold voltage Vth can be shifted due to positive bias temperature stress (PBTS). However, in this case, the shift of the threshold voltage Vth can be minimized by increasing the amplitude of the high potential voltage EVDD to increase the drive current Id flowing through the light emitting element ED and to lower the gate-source node voltage of the drive transistor Td.

[0188] For example, the high potential voltage EVDD can be set to 28 V or more to reduce the shift of the threshold voltage Vth of the drive transistor Td due to positive bias temperature stress (PBTS).

[0189] Accordingly, the example pixel circuit 300 of the present disclosure can control by allowing the control voltage Vc corresponding to the output voltage of the reference circuit 310 to maintain a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata to allow the drive current Id flowing through the light emitting element ED to be proportional to the level of the data voltage Vdata. Accordingly, in the example pixel circuit 300 of the present disclosure, regardless of the deterioration of the light emitting element ED or the characteristic value of the drive transistor Td, a current proportional to the data voltage Vdata can flow through the light emitting element ED. Therefore, it is possible to provide a display panel 110 and a display device 100 having uniform brightness.

[0190] Figure 10 is a signal waveform diagram illustrating that the current flowing through the reference circuit according to the example embodiment of the present disclosure varies according to the data voltage in the sub-pixel circuit.

[0191] As Figure 10 illustrated, the sub-pixel circuit 300 according to the example embodiment of the present disclosure can be controlled to allow the drive current Id flowing through the light emitting circuit 320 and the reference current Iref flowing through the reference circuit 310 to be proportional to the level of the data voltage Vdata by allowing the control voltage Vc of the output node of the reference circuit 310 to maintain a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata.

[0192] For example, when the control voltage Vc is maintained at a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata, the driving current Id flowing through the light emitting circuit 320 and the reference current Iref flowing through the reference circuit 310 can maintain the same value. In this case, it can be identified that, when the data voltage Vdata is sequentially changed to levels of 22 V, 21 V, 20 V, 19 V, and 18 V, the driving current Id flowing through the light emitting circuit 320 and the reference current Iref flowing through the reference circuit 310 each have a value substantially proportional to the data voltage Vdata.

[0193] Figure 11A 、 Figure 11B and Figure 11C are signal waveform diagrams illustrating changes in current and voltage of a sub-pixel circuit when a driving transistor has different threshold voltages in the sub-pixel circuit according to an example embodiment of the present disclosure.

[0194] As shown in Figure 11A 、 Figure 11B and Figure 11C , in the sub-pixel circuit 300 according to an example embodiment of the present disclosure, a characteristic value such as a threshold voltage of the driving transistor Td can change as a driving time increases.

[0195] In consideration of this, in a case where the threshold voltage of the driving transistor Td has a reference voltage and increases by 1 V from the reference voltage, changes in a driving voltage Vd corresponding to an output voltage of the amplification circuit 330, a control voltage Vc corresponding to an output voltage of the reference circuit 310, and a driving current Id flowing through the light emitting circuit 320 are measured.

[0196] It can be determined that, when the threshold voltage of the driving transistor Td increases, a level of the driving voltage Vd corresponding to the output voltage of the amplification circuit 330 changes Figure 11A .

[0197] However, although the threshold voltage of the driving transistor Td increases, the control voltage Vc corresponding to the output voltage of the reference circuit 310 is always maintained at a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata Figure 11B .

[0198] Therefore, although the threshold voltage of the driving transistor Td changes, the driving current Id flowing through the light emitting circuit 320 and the reference current Iref flowing through the reference circuit 310 can maintain constant values Figure 11C .

[0199] Thus, since the drive current Id flowing through the light emitting element ED has a value proportional to the data voltage Vdata regardless of the deterioration of the light emitting element ED or the characteristic value of the drive transistor Td in the sub-pixel circuit 300, the display device 100 can maintain uniform luminance despite an increase in the drive time.

[0200] In the example sub-pixel circuit 300 of the present disclosure, the amplification circuit 330 can alternatively reset the drive transistor Td by controlling the power voltage Vp instead of implementing the reset transistor Trst.

[0201] Figure 12 is a view showing a detailed configuration of another sub-pixel circuit according to an example embodiment of the present disclosure.

[0202] As Figure 12 indicated, the sub-pixel circuit 300 according to an example embodiment of the present disclosure can include a reference circuit 310, a light emitting circuit 320, an amplification circuit 330, and an input circuit 340. An example in which an nth scan signal SCAN(n) is applied between a plurality of sub-pixels constituting the display panel 110 is described below.

[0203] The reference circuit 310 can include a reference transistor Tref having a drain node and a gate node to which a control voltage Vc can be supplied and a source node to which a high potential voltage EVDD can be applied.

[0204] The light emitting circuit 320 can include a light emitting element ED having a cathode electrode to which a low potential voltage EVSS can be applied and a drive transistor Td having a drain node connected to an anode electrode of the light emitting element ED, a source node to which a control voltage Vc can be applied, and a gate node to which a drive voltage Vd of the amplification circuit 330 can be applied.

[0205] The reference transistor Tref can be turned on by the high potential voltage EVDD, and when the drive transistor Td is turned on by the drive voltage Vd of the amplification circuit 330, a drive current Id can flow through the light emitting circuit 320.

[0206] In this case, when the control voltage Vc and the data voltage Vdata have the same level of potential, the entire reference current Iref flowing through the reference circuit 310 can flow through the light emitting circuit 320, and the drive current Id can have the same value as the reference current Iref.

[0207] The amplification circuit 330 can include a control transistor Tc and a first capacitor C1. The control transistor Tc can have a gate node to which a control voltage Vc can be applied and a drain node connected to a gate node of the drive transistor Td. The first capacitor C1 can be connected to the drain node of the control transistor Tc to transfer a power voltage Vp for driving the drive transistor Td. The power voltage Vp can have a level capable of driving the drive transistor Td.

[0208] The input circuit 340 can include a switching transistor Tsw and a second capacitor C2. The switching transistor Tsw can have a gate node to which an nth scan signal SCAN(n) can be applied, a source node to which a data voltage Vdata can be applied, and a drain node connected to a source node of the control transistor Tc. The second capacitor C2 can be connected between the drain node of the switching transistor Tsw and a low potential voltage EVSS.

[0209] Accordingly, the input circuit 340 can supply the data voltage Vdata to the amplification circuit 330 through the nth scan signal SCAN(n). The second capacitor C2 can be used to stably transfer the data voltage Vdata.

[0210] The transistors Td, Tref, Tc, and Tsw constituting the example sub-pixel circuit 300 can be P-type transistors or N-type transistors.

[0211] P-type transistors are relatively more reliable than N-type transistors. In the case of P-type transistors, since the drive transistor Td can be fixed to a high potential voltage EVDD during a period in which the light emitting element ED emits light, a current flowing through the light emitting element ED can be stably supplied without significant fluctuation.

[0212] When operated in the saturation region, P-type transistors can flow a constant current regardless of a change in threshold voltage, thereby providing relatively high reliability.

[0213] On the other hand, since N-type transistors use electrons rather than holes as carriers, N-type transistors have a higher mobility than P-type transistors, thereby enabling an increase in switching speed.

[0214] N-type transistors can be oxide transistors (e.g., transistors having a channel formed of an oxide semiconductor such as indium, gallium, zinc oxide, or IGZO) formed of an oxide semiconductor. P-type transistors can be silicon transistors (e.g., transistors having a polysilicon channel formed by a low-temperature process called LTPS or low-temperature polysilicon) formed of a semiconductor such as silicon.

[0215] Described herein is an example in which the transistors Td, Tref, Tc, and Tsw constituting the sub-pixel circuit 300 are P-type transistors.

[0216] The terms "source node" and "drain node" of the transistor can be used interchangeably according to the input voltage.

[0217] Figure 13 is an example signal waveform diagram illustrating an operation of another sub-pixel circuit according to an example embodiment of the present disclosure.

[0218] Referring to FIGS. 1 and 2, Figure 13 The operation of the sub-pixel circuit 300 according to an example embodiment of the present disclosure is described below.

[0219] The power voltage Vp can be applied in the form of a pulse from the power management circuit 150 according to one or more timing signals.

[0220] If the power voltage Vp is applied at a high level before the nth scan signal SCAN(n) is applied, the driving transistor Td can be turned off by the power voltage Vp.

[0221] Thereafter, if the nth scan signal SCAN(n) is applied to turn on the switching transistor Tsw, the data voltage Vdata can be applied to the second capacitor C2. After the nth scan signal SCAN(n) is applied, the power voltage Vp can be switched to a low level. If the power voltage Vp reaches a threshold voltage level of the driving transistor Td, the driving transistor Td can be turned on, and a reference current Iref flowing through the reference circuit 310 can be delivered to the light emitting circuit 320 through the driving transistor Td.

[0222] A control voltage Vc corresponding to the output voltage of the reference circuit 310 can be reduced by the reference current Iref and a driving current Id flowing from the reference circuit 310 through the light emitting circuit 320.

[0223] If the control voltage Vc reaches a level of a sum Vdata+Vth(Tc) of the data voltage Vdata and a threshold voltage Vth(Tc) of the control transistor Tc, the control transistor Tc can be turned on. If the control transistor Tc is turned on, the charge stored in the first capacitor C1 can move to the second capacitor C2, so that the driving current Id flowing through the driving transistor Td can decrease. Accordingly, the control voltage Vc can increase, and the control transistor Tc can be turned off.

[0224] As the control transistor Tc repeatedly turns on and off for a short period, the control voltage Vc can maintain a level of the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc.

[0225] In this case, if the deposition conditions of the control transistor Tc and the reference transistor Tref positioned adjacent to each other are the same, the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref can have the same value. In other words, the control transistor Tc and the reference transistor Tref can be formed to have the same threshold voltage Vth by maintaining the thickness and the composition ratio of the gate node, the source node, the drain node, and the insulating film positioned therebetween under the same conditions in a process of depositing the control transistor Tc and the reference transistor Tref.

[0226] If the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref have the same value, the reference current Iref flowing through the reference transistor Tref can be expressed as:

[0227] Iref = K * Vdata 2

[0228] In other words, since the driving current Id flowing through the light emitting element ED and the reference current Iref flowing through the reference transistor Tref are both proportional to the data voltage Vdata, the driving current Id for driving the light emitting element ED can be adjusted by the data voltage Vdata regardless of the characteristic value of the light emitting element ED or the driving transistor Td.

[0229] Therefore, the example pixel circuit 300 of the present disclosure can control by allowing the control voltage Vc corresponding to the output voltage of the reference circuit 310 to be maintained at a level corresponding to the sum Vdata + Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata, to allow the driving current Id flowing through the light emitting element ED to be proportional to the level of the data voltage Vdata.

[0230] Therefore, in the example pixel circuit 300 of the present disclosure, regardless of the degradation of the light emitting element ED or the characteristic value of the driving transistor Td, a current proportional to the data voltage Vdata can flow through the light emitting element ED. Therefore, it is possible to provide a display panel 110 and a display device 100 having uniform brightness.

[0231] The foregoing example embodiments are briefly described below.

[0232] A sub-pixel circuit for operating at least one sub-pixel of a plurality of sub-pixels disposed on a display panel can include a reference circuit configured to receive a high potential voltage and output a control voltage for controlling a driving current flowing through a light emitting element; a light emitting circuit including the light emitting element, the light emitting circuit configured to receive the control voltage and a low potential voltage and control the light emitting element based on a driving voltage; an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

[0233] In some embodiments, the reference circuit can include a reference transistor having a drain node and a gate node that provide the control voltage and a source node that receives the high potential voltage.

[0234] In some embodiments, the light emitting circuit can include a light emitting element having a cathode electrode that receives the low potential voltage and a driving transistor having a drain node connected to an anode electrode of the light emitting element and a gate node that receives the driving voltage.

[0235] In some embodiments, the amplification circuit can include an operational amplifier having an inverting input terminal that receives the control voltage, a non-inverting input terminal that receives an output voltage of the input circuit, and an output terminal that outputs the driving voltage.

[0236] In some embodiments, the amplification circuit can include a control transistor having a gate node that receives the control voltage and a drain node that provides the driving voltage to the light emitting circuit, and a first capacitor connected to the drain node of the control transistor to transfer the input power voltage.

[0237] In some embodiments, the reference circuit can include a reference transistor having a drain node and a gate node configured to provide the control voltage and a source node configured to receive the high potential voltage; and the control transistor and the reference transistor can have the same threshold voltage.

[0238] In some embodiments, the control transistor and the reference transistor can have at least one of the same thickness, the same composition ratio, and the same structure of the gate node, the source node, the drain node, and an insulating film located between the gate node and the source node and the drain node.

[0239] In some embodiments, the amplification circuit can further include a reset transistor having a source node that receives a reset voltage, a gate node that receives a second scan signal before the input circuit receives the first scan signal, and a drain node that is common with the control transistor.

[0240] In some embodiments, the driving transistor may be configured to be reset by the second scan signal and turned on by the first scan signal.

[0241] In some embodiments, at a control voltage having a level corresponding to the sum of the data voltage and the threshold voltage of the control transistor, a driving current flowing through the light emitting circuit and a reference current flowing through the reference circuit may have the same value.

[0242] In some embodiments, the input circuit may include: a switching transistor having a gate node for receiving a first scan signal, a source node for receiving a data voltage, and a drain node connected to the amplification circuit; and a second capacitor connected between the drain of the switching transistor and the low potential voltage.

[0243] In some embodiments, the light-emitting circuit may include a driving transistor having a drain node connected to an anode electrode of the light-emitting element and a gate node receiving a driving voltage; the driving transistor may be configured to be reset by an input power voltage and turned on by the first scanning signal before the input circuit receives the first scanning signal.

[0244] In some embodiments, the light emitting circuit, the reference circuit, the amplifying circuit, and the input circuit may include P-type transistors.

[0245] In some embodiments, the driving current may be proportional to the data voltage.

[0246] In some embodiments, a display panel may include a plurality of sub-pixels and the sub-pixel circuit of any of the above embodiments.

[0247] A display device may include: a display panel including a plurality of sub-pixels and a sub-pixel circuit for operating at least one of the plurality of sub-pixels; a gate driver circuit configured to supply a plurality of scan signals to the display panel via a plurality of gate lines; a data driver circuit configured to supply a plurality of data voltages to the display panel via a plurality of data lines; and a timing controller configured to drive the gate driver circuit and the data driver circuit. The sub-pixel circuit may include: a reference circuit configured to receive a high-potential voltage and output a control voltage for controlling a drive current flowing through a light-emitting element; a light-emitting circuit including a light-emitting element, the light-emitting circuit configured to receive the control voltage and a low-potential voltage and control the light-emitting element based on the drive voltage; an amplifier circuit configured to compare the control voltage with a data voltage to generate a drive voltage for controlling the light-emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal and control the timing of applying the data voltage to the amplifier circuit based on the first scan signal.

[0248] In some embodiments, the amplification circuit can include a control transistor having a gate node that receives the control voltage and a drain node that provides the drive voltage to the light-emitting circuit, and a first capacitor connected to the drain node of the control transistor to pass the input power voltage.

[0249] In some embodiments, the reference circuit can include a reference transistor having a drain node and a gate node configured to provide the control voltage and a source node configured to receive the high potential voltage; the control transistor and the reference transistor can have the same threshold voltage.

[0250] In some embodiments, the amplification circuit can further include a reset transistor having a source node that receives the reset voltage, a gate node that receives the second scan signal before the input circuit receives the first scan signal, and a drain node that is common with the control transistor; and the drive transistor can be configured to be reset by the second scan signal and turned on by the first scan signal.

[0251] In some embodiments, the drive current is proportional to the data voltage.

[0252] The above description has been presented to enable any person skilled in the art to make and use the various possible embodiments of the present disclosure. Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical idea of the present disclosure. Therefore, the example embodiments disclosed in the present disclosure are provided only for illustrative purposes, and are not intended to limit the technical idea of the present disclosure. It should be understood, therefore, that the above-described example embodiments are illustrative in all aspects and do not limit the present disclosure.

[0253] It will be obvious to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover the modifications and changes of the present disclosure, as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A sub-pixel circuit for operating at least one sub-pixel among a plurality of sub-pixels arranged on a display panel, the sub-pixel circuit comprising: a reference circuit configured to receive a high-potential voltage and output a control voltage for controlling a drive current flowing through the light-emitting element; a light emitting circuit including the light emitting element, the light emitting circuit being configured to receive the control voltage and the low potential voltage and to control the light emitting element based on a drive voltage; an amplifying circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit; as well as an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplifying circuit based on the first scan signal, Wherein, the amplifying circuit includes: a control transistor having a gate node for receiving the control voltage and a drain node for providing the driving voltage to the light emitting circuit; and A first capacitor is connected to the drain node of the control transistor to transfer an input power voltage.

2. The sub-pixel circuit according to claim 1, wherein: The reference circuit includes a reference transistor having a drain node and a gate node providing the control voltage and a source node receiving the high potential voltage.

3. The sub-pixel circuit according to claim 1 , wherein: The light emitting circuit comprises: The light emitting element has a cathode electrode receiving a voltage lower than the potential; and A driving transistor has a drain node connected to the anode electrode of the light emitting element and a gate node receiving the driving voltage.

4. The sub-pixel circuit according to claim 1 , wherein: The amplification circuit includes an operational amplifier having an inverting input terminal receiving the control voltage, a non-inverting input terminal receiving the output voltage of the input circuit, and an output terminal outputting the drive voltage.

5. The sub-pixel circuit according to claim 1 , wherein: The reference circuit includes a reference transistor having a drain node and a gate node configured to provide the control voltage and a source node configured to receive the high potential voltage; and The control transistor and the reference transistor have the same threshold voltage. The sub-pixel circuit according to claim 5 , wherein: The control transistor and the reference transistor have at least one of the following: the same thickness, the same composition ratio, and the same structure of a gate node, a source node, a drain node, and an insulating film located between the gate node and the source node and the drain node.

7. The sub-pixel circuit according to claim 1, wherein: The amplifying circuit further includes a reset transistor having a source node receiving a reset voltage, a gate node receiving a second scanning signal before the input circuit receives the first scanning signal, and a drain node shared with the control transistor.

8. The sub-pixel circuit according to claim 7, wherein: The driving transistor in the light emitting circuit is configured to be reset by the second scanning signal and turned on by the first scanning signal.

9. The sub-pixel circuit according to claim 1, wherein: At a control voltage having a level corresponding to a sum of the data voltage and a threshold voltage of the control transistor, a driving current flowing through the light emitting circuit and a reference current flowing through the reference circuit have the same value.

10. The sub-pixel circuit according to claim 1, wherein: The input circuit comprises: a switching transistor having a gate node receiving the first scan signal, a source node receiving the data voltage, and a drain node connected to the amplifying circuit; and A second capacitor is connected between the drain node of the switching transistor and the low potential voltage.

11. The sub-pixel circuit according to claim 10, wherein: The light emitting circuit includes a driving transistor having a drain node connected to an anode electrode of the light emitting element and a gate node receiving the driving voltage, and The driving transistor is configured to be reset by an input power voltage before the input circuit receives the first scan signal and to be turned on by the first scan signal.

12. The sub-pixel circuit according to claim 1, wherein: The light emitting circuit, the reference circuit, the amplifying circuit, and the input circuit include P-type transistors.

13. The sub-pixel circuit according to claim 1, wherein: The driving current is proportional to the data voltage.

14. A display panel comprising: multiple sub-pixels; as well as The sub-pixel circuit according to claim 1, which is used to operate at least one sub-pixel among the plurality of sub-pixels.

15. A display device comprising: A display panel comprising a plurality of sub-pixels and a sub-pixel circuit for operating at least one sub-pixel of the plurality of sub-pixels; a gate driving circuit configured to supply a plurality of scanning signals to the display panel through a plurality of gate lines; a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; as well as a timing controller configured to drive the gate driving circuit and the data driving circuit, Wherein, the sub-pixel circuit includes: a reference circuit configured to receive a high-potential voltage and output a control voltage for controlling a drive current flowing through the light-emitting element; a light emitting circuit including the light emitting element, the light emitting circuit being configured to receive the control voltage and the low potential voltage and to control the light emitting element based on a drive voltage; an amplifying circuit configured to compare the control voltage with a data voltage to generate a driving voltage for controlling the light emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplifying circuit based on the first scan signal, Wherein, the amplifying circuit includes: a control transistor having a gate node for receiving the control voltage and a drain node for providing the driving voltage to the light emitting circuit; and A first capacitor is connected to the drain node of the control transistor to transfer an input power voltage.

16. The display device according to claim 15, wherein: The reference circuit includes a reference transistor having a drain node and a gate node configured to provide the control voltage and a source node configured to receive the high potential voltage; and The control transistor and the reference transistor have the same threshold voltage.

17. The display device according to claim 15, wherein: The amplifier circuit further includes a reset transistor having a source node receiving a reset voltage, a gate node receiving a second scan signal before the input circuit receives the first scan signal, and a drain node shared with the control transistor; and The driving transistor in the light emitting circuit is configured to be reset by the second scanning signal and turned on by the first scanning signal.

18. The display device according to claim 15, wherein The driving current is proportional to the data voltage.

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