A method for improving edge collapse in a gallium arsenide via etch process
By combining a photoresist layer and a metal layer as a mask, and using polyimide to fill the holes, the edge chipping problem in the gallium arsenide through-hole etching process was solved, improving the high-frequency performance and lifespan of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN FULIAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-01-12
- Publication Date
- 2026-06-26
AI Technical Summary
In existing gallium arsenide through-hole etching processes, insufficient or excessive photoresist layer thickness can lead to edge chipping, affecting the high-frequency performance and lifespan of the device.
A combination of photoresist and metal layer is used as a mask. The chipped holes are filled by sputtering the metal layer, etching and coating polyimide to avoid morphology problems caused by insufficient or excessive photoresist thickness.
It effectively avoids abnormal morphology caused by chipped holes, optimizes metal etching time, and improves the high-frequency performance and lifespan of the device.
Smart Images
Figure CN116364649B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for improving edge chipping in gallium arsenide through-hole etching process. Background Technology
[0002] Current technology uses a photoresist layer as a mask, attaching a layer of photoresist to the wafer surface with a thickness of approximately 14 μm, which can etch depths of 75 μm to 100 μm. However, when etching gallium arsenide (GaAs) vias deeper than 100 μm, the photoresist layer thickness is insufficient to withstand inductively coupled plasma (ICP) etching. To address this issue, existing technologies mainly employ two approaches: one is to increase the photoresist thickness, which can lead to potential photoresist deformation, resulting in an etched contour that does not meet requirements; the other is to use a combination of a photoresist layer and a metal layer as a mask, which can cause edge chipping at the etched via edges, as shown in the attached image. Figure 1 As shown, during subsequent metal wiring processes such as sputtering and electroplating, the chipped edges will be filled, with the morphology as shown in the attached figure. Figure 2 As shown, this results in suboptimal high-frequency performance of the device and affects its lifespan. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a method to improve edge chipping in gallium arsenide via etching process, so as to solve the technical problem of how to avoid abnormal morphology caused by edge chipping during metal wiring.
[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0005] A method for improving edge chipping in gallium arsenide through-hole etching process includes the following steps: S1, sputtering a metal layer on the surface of the back side of the crystal after the front side process has been completed; S2, attaching a first photoresist layer on the metal layer, and removing the first photoresist layer at the through-hole to be etched after alignment and development; S3, etching the metal layer at the through-hole to be etched; S4, performing ICP etching on the through-hole to generate edge chipping; S5, removing the first photoresist layer and the metal layer; S6, coating polyimide on the surface of the back side of the crystal to fill the holes formed by edge chipping.
[0006] The beneficial effects of this invention are as follows: by using a combination of photoresist layer and metal layer as a mask, the morphology problems caused by insufficient or excessive photoresist thickness are avoided; by filling the holes formed by edge chipping with polyimide, abnormal morphology caused by edge chipping holes during metal wiring can be avoided. Attached Figure Description
[0007] Figure 1 Image showing the chipping morphology of a via etched by ICP;
[0008] Figure 2 Topographical image of metal filling chipped holes;
[0009] Figure 3 This is a flowchart illustrating the overall process of improving edge chipping in gallium arsenide via etching in a specific embodiment of the present invention.
[0010] Figure 4 This is a schematic diagram illustrating the process of edge chipping during the GaAs through-hole etching process in a specific embodiment of the present invention.
[0011] Figure 5 This is a schematic diagram illustrating the process of filling GaAs through-hole etching with PI in a specific embodiment of the present invention, where the hole is chipped.
[0012] Figure descriptions: 1. Wafer; 2. Metal layer; 3. First photoresist layer; 4. Metal on the front side of the wafer; 5. Polyimide; 6. Second photoresist layer; 7. Sputtered and electroplated metal. Detailed Implementation
[0013] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0014] Please refer to the appendix. Figure 3 This invention provides a method for improving edge chipping in gallium arsenide via etching processes, comprising the following steps:
[0015] S1. Sputter a metal layer onto the surface of the crystal back that has completed the front-side process;
[0016] S2. Attach a first photoresist layer onto the metal layer, and remove the first photoresist layer at the through hole to be etched by alignment and development.
[0017] S3. Etch the metal layer at the through-hole to be etched;
[0018] S4. Perform ICP etching on the through-holes to generate chipped edges;
[0019] S5. Remove the first photoresist layer and the metal layer;
[0020] S6. Coat the surface of the crystal back with polyimide to fill the holes formed by edge chipping.
[0021] As can be seen from the above description, the beneficial effects of the present invention are as follows: by using a combination of photoresist layer and metal layer as a mask, the morphology problems caused by insufficient or excessive photoresist thickness are avoided; by filling the holes formed by edge breakage with polyimide, abnormal morphology caused by edge breakage holes during metal wiring can be avoided.
[0022] Furthermore, the method further includes the step of:
[0023] S7. Attach a second photoresist layer to the surface of the crystal back, and remove the second photoresist layer at the through hole after alignment and development.
[0024] S8. Use ICP micro-etching to remove the polyimide that flowed into the bottom of the through hole in step S6, ensuring that the polyimide is completely removed.
[0025] S9. Remove the second photoresist layer and proceed with subsequent processes.
[0026] As described above, the present invention removes the polyimide at the bottom of the through-hole to avoid affecting the interconnection between the metals subsequently sputtered and electroplated and the metals on the front side of the wafer.
[0027] Furthermore, in step S2, the material of the metal layer is selected from one or more of tungsten, titanium, gold, and tungsten-titanium alloy.
[0028] As described above, these materials, in combination with the first photoresist layer, can resist ICP etching, ensuring that the etched via profile meets the requirements.
[0029] Furthermore, the thickness of the metal layer is 2000A-5000A.
[0030] As described above, a metal layer that is too thin cannot effectively block ICP etching, meaning it cannot protect GaAs from being etched by ICP. Conversely, a metal layer that is too thick requires a longer etching process to ensure no metal residue remains in the ICP etching area.
[0031] Furthermore, in step S3, the metal layer at the through hole to be etched is etched using a wet etching method.
[0032] As can be seen from the above description, wet etching is a simple process and can shorten the time of metal etching.
[0033] Furthermore, the etching time is 40s-80s.
[0034] As described above, optimizing the etching time can reduce the lateral etching of the metal and decrease the degree of edge chipping.
[0035] Furthermore, in step S2, the thickness of the first photoresist layer is 14μm-28μm;
[0036] As can be seen from the above description, due to the presence of the metal layer, the present invention can perform the IPC etching through-hole process using conventional photoresist thickness.
[0037] Furthermore, in step S4, the depth of the through hole is 120μm-250μm.
[0038] As described above, performing ICP etching on the wafer surface to create vias of this depth range will result in edge chipping.
[0039] Furthermore, in step S6, the coating thickness of polyimide on the surface of the crystal back is not less than 5 μm.
[0040] As described above, it is important to prevent the polyimide at the chipped edge from being lost in subsequent processes, which would affect the filling effect.
[0041] Furthermore, the second photoresist layer uses dry film photoresist.
[0042] As described above, using dry film photoresist can avoid the photoresist flowing into the vias due to coating, thus shortening the time of subsequent ICP micro-etching processes.
[0043] The above-mentioned method for improving edge chipping in gallium arsenide via etching process is illustrated through the following specific examples:
[0044] Example 1
[0045] The method described in this embodiment includes the following steps:
[0046] S1. Please refer to the appendix. Figure 4 (a) is a schematic diagram of the back of the wafer, where a metal layer is sputtered on the back surface (crystal back) of the wafer after the front-side process has been completed.
[0047] In this embodiment, the metal layer is made of gold (Au). The thickness of the metal layer is 4500 Å.
[0048] S2. Please refer to the appendix. Figure 4 (b) A first photoresist layer with a thickness of 14 μm is coated on the metal layer. After alignment and development, the first photoresist layer at the via to be etched is removed, exposing the metal layer at that location.
[0049] In other embodiments, the first photoresist layer may also be a dry film photoresist.
[0050] S3. Etch the metal layer at the through-hole to expose the surface of the crystal back.
[0051] The method used was wet etching, with an etching time of 60 seconds. The wet etching was isotropic, and the etch morphology is shown in the attached figure. Figure 4 As shown in (c).
[0052] Table 1 Comparison of the effects of different processing times in metal etching processes.
[0053]
[0054] By optimizing the parameters, the lateral etching of the metal can be reduced, thereby decreasing the degree of edge chipping that occurs in step S4.
[0055] S4. Please refer to the appendix. Figure 4 (d) The bottom is the metal on the front side of the wafer. ICP etching is performed from the back side of the wafer to create a through hole with an etching depth of 150μm, resulting in edge chipping.
[0056] S5. Remove the first photoresist layer and the metal layer. The edge morphology is shown in the attached figure. Figure 4 (e) and appendix Figure 5 As shown in (a).
[0057] The photoresist was removed by immersion in NMP (n-methylpyrrolidone) solution. The metal layer was removed by immersion in an etching solution; in this embodiment, potassium iodide solution was used.
[0058] S6. Coat the back surface of the crystal with polyimide (PI) to fill the chipped holes. This prevents sputtered and electroplated metal from filling these holes during subsequent metal wiring processes, which could lead to suboptimal high-frequency performance and affect the device's lifespan. The PI coating thickness on the back surface of the crystal is 5 μm.
[0059] At this point, some PI will flow to the bottom of the via. If not treated, this will affect the interconnection between the subsequent sputtered and electroplated metals and the metal on the front side of the wafer, as shown in the attached diagram. Figure 5 As shown in (b).
[0060] S7. Please refer to the appendix. Figure 5 (c) A second photoresist layer is attached to the surface of the crystal back. After alignment and development, the second photoresist layer at the via is removed, exposing the via. The photoresist material of the second photoresist layer can be either liquid photoresist or dry film photoresist. Because the via has already been etched at this point, applying liquid photoresist would cause a large amount of photoresist to flow into the via. To shorten the subsequent ICP micro-etching time, dry film photoresist is preferred. Dry film photoresist is generally thicker, with a thickness ranging from 14μm to 150μm being sufficient.
[0061] S8. Please refer to the appendix. Figure 5 (d) The polyimide at the bottom of the through hole is removed by ICP micro-etching. This step is over-etching to ensure that the polyimide is completely removed.
[0062] S9. Please refer to the appendix. Figure 5 (e) Remove the second photoresist layer and proceed with subsequent metal sputtering and electroplating processes. In this embodiment, sputtering involves seeding gold, and electroplating involves growing a thickness on the seed gold.
[0063] Example 2
[0064] The method described in this embodiment includes the following steps:
[0065] S1. Sputter a metal layer onto the surface of the back of the crystal after the front-side process has been completed.
[0066] In this embodiment, the metal layer is made of tungsten-titanium alloy (TiW). The thickness of the metal layer is 2000 Å.
[0067] S2. A first photoresist layer with a thickness of 28 μm is coated on the metal layer. After alignment and development, the first photoresist layer at the via to be etched is removed, exposing the metal layer at that location.
[0068] S3. Etch the metal layer at the through-hole to expose the surface of the crystal back.
[0069] The method used was wet etching, with an etching time of 40 seconds.
[0070] S4. ICP etching of vias is performed from the back of the crystal to a depth of 120μm, resulting in edge chipping.
[0071] S5. Remove the first photoresist layer and the metal layer.
[0072] S6. Coat the back surface of the crystal with PI to fill the chipped holes. This prevents sputtered and electroplated metal from filling these holes during subsequent metal wiring processes, which could lead to suboptimal high-frequency performance and affect the device's lifespan. The PI coating thickness on the back surface of the crystal is 7μm.
[0073] At this point, some PI will flow to the bottom of the via. If this is not treated, it will affect the interconnection between the metals sputtered and electroplated subsequently and the metals on the front side of the wafer.
[0074] S7. Attach a dry film photoresist layer to the surface of the crystal back, align and develop, remove the dry film photoresist layer at the through hole, and expose the through hole.
[0075] S8. Use ICP micro-etching to remove the polyimide at the bottom of the through-hole. This step is an over-etching process to ensure that the polyimide is completely removed.
[0076] S9. Remove the second photoresist layer and proceed with subsequent metal sputtering and electroplating processes.
[0077] Example 3
[0078] The method described in this embodiment includes the following steps:
[0079] S1. Sputter a metal layer onto the surface of the back of the crystal after the front-side process has been completed.
[0080] In this embodiment, the metal layer is a composite layer of tungsten (W) and titanium (Ti). The thickness of the composite metal layer is 5000 Å.
[0081] S2. A first photoresist layer with a thickness of 20 μm is coated on the metal layer. After alignment and development, the first photoresist layer at the via to be etched is removed, exposing the metal composite layer at that location.
[0082] S3. Etch the metal assembly at the through-hole to expose the surface of the crystal back.
[0083] The method used was wet etching, with an etching time of 80 seconds.
[0084] S4. ICP etching of vias is performed from the back of the crystal to a depth of 250μm, resulting in edge chipping.
[0085] S5. Remove the first photoresist layer and the metal layer.
[0086] S6. Coat the back surface of the crystal with PI to fill the chipped holes. This prevents sputtered and electroplated metal from filling these holes during subsequent metal wiring processes, which could lead to suboptimal high-frequency performance and affect the device's lifespan. The PI coating thickness on the back surface of the crystal is 5μm.
[0087] At this point, some PI will flow to the bottom of the via. If this is not treated, it will affect the interconnection between the metals sputtered and electroplated subsequently and the metals on the front side of the wafer.
[0088] S7. Attach a dry film photoresist layer to the surface of the crystal back, align and develop, remove the dry film photoresist layer at the through hole, and expose the through hole.
[0089] S8. Use ICP micro-etching to remove the polyimide at the bottom of the through-hole. This step is an over-etching process to ensure that the polyimide is completely removed.
[0090] S9. Remove the second photoresist layer and proceed with subsequent metal sputtering and electroplating processes.
[0091] Tests showed that the wafers obtained after using the methods described in Examples 1 to 3 did not exhibit any abnormal morphology, and the high-frequency performance and lifespan of the corresponding devices obtained after further processing met the product standards.
[0092] The present invention has the following advantages:
[0093] 1. By using a combination of photoresist and metal layers as a mask, the morphology problems caused by insufficient or excessive photoresist thickness are avoided, the metal etching time is optimized, the side etching is reduced, and the edge chipping is improved.
[0094] 2. Filling the holes formed by chipped edges with PI can prevent abnormal morphology caused by chipped holes during metal wiring.
[0095] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention's specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method for improving edge chipping in gallium arsenide through-hole etching process, characterized in that, Includes the following steps: S1. Sputter a metal layer onto the surface of the crystal back that has completed the front-side process; S2. Attach a first photoresist layer onto the metal layer, and remove the first photoresist layer at the through hole to be etched by alignment and development. S3. Etch the metal layer at the through-hole to be etched; S4. Perform ICP etching on the through-holes to create chipped edges; S5. Remove the first photoresist layer and the metal layer; S6. Coat the surface of the crystal back with polyimide to fill the holes formed by edge chipping.
2. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: It also includes the following steps: S7. Attach a second photoresist layer to the surface of the crystal back, and remove the second photoresist layer at the through hole after alignment and development. S8. Use ICP micro-etching to remove the polyimide that flowed into the bottom of the through hole in step S6, ensuring that the polyimide is completely removed. S9. Remove the second photoresist layer and proceed with subsequent processes.
3. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: In step S2, the material of the metal layer is selected from one or more of tungsten, titanium, gold, and tungsten-titanium alloy.
4. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 3, characterized in that: The thickness of the metal layer is 2000A-5000A.
5. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: In step S3, the metal layer at the through hole to be etched is etched using a wet etching method.
6. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 5, characterized in that: The etching time is 40s-80s.
7. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: In step S2, the thickness of the first photoresist layer is 14μm-28μm.
8. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: In step S4, the depth of the through hole is 120μm-250μm.
9. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 1, characterized in that: In step S6, the coating thickness of polyimide on the surface of the crystal back is not less than 5 μm.
10. The method for improving edge chipping in gallium arsenide through-hole etching process according to claim 2, characterized in that: The second photoresist layer uses dry film photoresist.