A 700℃ volatile gallium arsenide wafer anti-permeation protective layer and its preparation method

Abstract

This invention discloses a 700℃ volatile gallium arsenide wafer anti-permeation protective layer and its preparation method. The protective layer is formed by thermal curing of a metal-organic framework derived layer formed by the coordination of organic ligands with gallium atoms on the surface of gallium arsenide. The protective layer can spontaneously generate gaseous products in the temperature range of 680-720℃, achieving residue-free removal. It does not involve any acids, alkalis, or organic solvents, and completely eliminates the problems of surface damage, chemical residues, side etching, and waste liquid pollution caused by wet etching.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor materials and device manufacturing technology, specifically referring to a 700℃ volatile gallium arsenide wafer anti-permeation protective layer and its preparation method. Background Technology

[0002] Gallium arsenide (GaAs), as a second-generation compound semiconductor material, possesses excellent properties such as high electron mobility and a direct bandgap, and is widely used in radio frequency devices, optoelectronic devices, and high-speed digital circuits. However, at high temperatures (typically >600℃), the preferential volatilization of As leads to an imbalance in surface stoichiometry, generating a large number of arsenic vacancies and surface defects, which severely affects device performance and reliability. Therefore, a dense anti-permeation protective layer must be deposited before high-temperature processing to suppress As diffusion and block impurities such as oxygen and moisture in the ambient atmosphere.

[0003] Existing anti-permeability protective layer technologies can be mainly classified into the following categories: 1. Dielectric layer protection schemes: such as silicon dioxide (SiO2) and silicon nitride (SiN) prepared by plasma-enhanced chemical vapor deposition (PECVD). x Silicon oxynitride (SiON) and other similar protective layers are used. These layers exhibit good density and can withstand temperatures above 700°C. However, their removal requires wet etching solutions such as hydrofluoric acid (HF). The etching process not only easily damages the air-sensitive GaAs surface but also presents challenges such as side etching of fine lines, residue contamination, and waste liquid disposal. Furthermore, the surface after wet etching typically contains dangling bonds and residual oxides, requiring additional treatment before subsequent epitaxy or gate fabrication.

[0004] 2. Solid-state epitaxial capping: This involves lattice-matched or near-matched materials such as germanium (Ge), gallium arsenide (GaAs), and aluminum gallium arsenide (AlGaAs) grown in situ via molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). While this type of capping effectively protects the surface, its removal relies on selective wet etching (e.g., H₂O₂ solution for Ge, citric acid / H₂O₂ system for GaAs). This limited etching selectivity can easily erode the substrate or leave etching pits. Furthermore, epitaxial growth is costly and unsuitable for non-in-situ processes.

[0005] 3. Arsenic Cap (As-cap) Solution: This method involves depositing a metallic arsenic layer at low temperatures (<-20°C) within the MBE growth chamber, utilizing the significant sublimation of As in a vacuum (approximately 350°C) to achieve in-situ desorption. The advantage of this method is that the desorption process is entirely dry, resulting in a clean surface. However, the volatilization temperature of As-cap is far below 700°C. During the process of heating to the target process temperature of 700°C, the As layer completely volatilizes, losing its protective function. Even with thickened As layers, it is impossible to maintain a dense coverage at 700°C for an extended period. Furthermore, As-cap is extremely sensitive to the atmospheric environment, is highly susceptible to oxidation during the transfer process, and As is toxic, posing a high operational risk.

[0006] 4. Other exploratory solutions: Two-dimensional materials such as amorphous carbon and graphene, although they have a certain barrier ability, are prone to react with GaAs or have their structure destroyed at high temperatures, and are difficult to completely remove without damaging the surface.

[0007] In summary, no existing technology possesses a protective layer that maintains dense and stable anti-permeation performance throughout the entire high-temperature process at 700°C, and, after fulfilling its protective function, achieves spontaneous, residue-free volatilization through simple thermal triggering without any wet chemical steps, thus yielding an atomically clean surface. Therefore, developing a novel anti-permeation protective layer and supporting process that meets these requirements is of great significance for improving the performance of gallium arsenide devices, simplifying manufacturing processes, and reducing environmental impact. Summary of the Invention

[0008] To address the needs and problems mentioned in the background above, the present invention provides a 700°C volatile gallium arsenide wafer anti-permeation protective layer and its preparation method, so as to at least partially solve the above problems.

[0009] According to the technical solution of the present invention, a 700℃ volatile gallium arsenide wafer anti-permeation protective layer is provided. The protective layer is formed by thermal curing of a metal-organic framework derived layer formed by the coordination of organic ligands with gallium atoms on the surface of gallium arsenide. The protective layer can spontaneously generate gaseous products in the temperature range of 680 to 720℃, achieving residue-free removal.

[0010] Preferably, the organic ligand comprises a compound containing at least one functional group selected from phosphonic acid, carboxylic acid, sulfonic acid, or hydroxamic acid groups; The main molecular structure of the organic ligand includes at least one of a C4-C18 alkyl chain, phenyl, biphenyl, or naphthyl group.

[0011] Preferably, the thickness of the protective layer is 1–100 nm; the thermosetting is carried out in an inert atmosphere or in a vacuum, the curing temperature is 200–400 °C, and the curing time is 5–120 min.

[0012] Preferably, the self-emission is carried out in a low-pressure inert atmosphere or vacuum, with a pressure below 10 Torr; During the volatilization process, a carbothermic reduction reaction occurs, and the reaction products include at least one of gaseous Ga2O, CO, and CO2.

[0013] On the other hand, the present invention also provides a method for preparing a 700°C volatile gallium arsenide wafer anti-permeation protective layer, comprising the following steps: S1. Perform surface pretreatment on the gallium arsenide wafer to remove native oxides; S2. Apply organic ligands to the pretreated gallium arsenide surface and perform self-assembly deposition to form a metal-organic framework layer in which the organic ligands are coordinated with the surface gallium atoms; S3. Perform thermal curing in an inert atmosphere or vacuum to form a dense, impermeable protective layer.

[0014] Preferably, the surface pretreatment uses a 5-25% (w / w) ammonium sulfide solution or thioacetamide solution, and is immersed at 20-60°C for 5-30 minutes.

[0015] Preferably, the self-assembly deposition is performed by immersion; the concentration of organic ligands in the immersion solution is 0.1–100 mM, the self-assembly temperature is 0–100 °C, and the self-assembly time is 1–120 min; the self-assembly deposition is cycled 1–10 times.

[0016] Thirdly, the present invention also provides an application of a 700°C volatile gallium arsenide wafer anti-permeation protective layer, wherein the protective layer is applied in a gallium arsenide high-temperature process, the temperature of which is 680-720°C, and includes at least one of ion implantation activated annealing, ohmic contact alloying, or surface protection before epitaxial growth.

[0017] Preferably, the protective layer can also be applied to high-temperature processes of III-V compound semiconductor substrates, wherein the III-V compound semiconductor includes at least one of gallium arsenide, indium phosphide, or gallium antimonide.

[0018] Beneficial effects: Completely dry removal with zero wet contact: It does not involve any acids, alkalis, or organic solvents, completely eliminating problems such as surface damage, chemical residues, lateral corrosion, and waste liquid pollution caused by wet corrosion.

[0019] The evaporation temperature is precisely matched to the 700℃ process window: the protective layer remains stable below the target process temperature and is only triggered to evaporate after fulfilling its protective mission, achieving temperature-selective "intelligent" desorption.

[0020] After volatilization, the surface is atomically clean: there are no solid residues on the surface, and XPS analysis shows that the Ga / As ratio on the surface is close to the stoichiometric ratio, and the C and O contamination is lower than that of a single atomic layer.

[0021] Low cost, high throughput, and non-vacuum compatible: self-assembly deposition can be carried out in atmospheric pressure solutions without the need for expensive vacuum equipment, and batch impregnation processing can be performed, significantly reducing production costs; film thickness can be precisely controlled by solution concentration and time, with a wide process window.

[0022] Compatible with complex patterned substrates: Solution self-assembly process has excellent conformability and can form a uniform protective layer on the inner wall of trenches and vias with an aspect ratio >10:1; Laser selective evaporation can achieve high-precision patterned removal, and the linewidth can be controlled at the micrometer level. Detailed Implementation

[0023] The technical solutions in the embodiments will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection.

[0024] This invention overcomes the shortcomings of existing technologies by providing an anti-permeation protective layer for gallium arsenide wafers and its preparation and removal methods. The core technical problems to be solved include: (1) The protective layer must remain dense, crack-free, and low-permeability within a temperature range of 700±20℃, and be able to effectively block the diffusion of As and atmospheric impurities. (2) The protective layer must be able to spontaneously and completely volatilize at around 700°C through simple heat annealing after the high-temperature process is completed. The volatilization product is gaseous and there are no residual solid or liquid substances on the surface. (3) The removal process is a completely dry method, which does not involve any wet chemical reagents such as acids, alkalis, and organic solvents, thus avoiding chemical damage, contamination and pattern collapse on the GaAs surface; (4) The fabrication process of the protective layer must have the characteristics of low cost, high production capacity, and compatibility with wafers of different sizes and patterned substrates; (5) The surface of GaAs after volatilization should be atomically smooth and have a low surface state density, so that it can be directly used for subsequent epitaxial regrowth or gate dielectric deposition.

[0025] To address the aforementioned technical problems, this invention provides a gallium arsenide anti-permeation protective layer and its integration process based on a "coordination locking-self-emission" mechanism, and also provides a composite capping layer based on "stress mismatch-burst desorption" as a parallel or supplementary solution.

[0026] In a first aspect, embodiments of the present invention provide an organic-inorganic hybrid self-sacrificing protective layer: 1. Composition and structure of the protective layer: The protective layer is formed by thermosetting a metal-organic framework (MOF) derivative layer, which is formed by the coordination of organic ligands with gallium atoms on the surface of gallium arsenide. Its final form is a composite film containing an amorphous carbon network and gallium oxide (Ga2O3) or gallium suboxide (Ga2O), with a thickness controllable between 1 and 100 nm.

[0027] The organic ligand contains at least one ligand capable of reacting with Ga³. + Compounds with functional groups consisting of Ga atoms suspended on the surface to form coordinate bonds, preferably phosphonic acid groups (-PO(OH)2), carboxylic acid groups (-COOH), sulfonic acid groups (-SO3H), or hydroxamic acid groups. The main structure of the ligand molecule can be an alkyl chain (C4-C18), an aromatic group (benzene, biphenyl, naphthalene), or a combination thereof, and substituents such as tert-butyl and trifluoromethyl can be introduced to regulate the pyrolysis behavior. Preferred ligands include, but are not limited to: tert-butylphosphonic acid, n-hexadecylphosphonic acid, pyromellitic acid, terephthalic acid, 2,5-dihydroxyterephthalic acid, and 1,3,5-phenyltriphosphonic acid.

[0028] 2. Preparation process: The preparation of the protective layer includes the following steps: (1) Surface pretreatment: The gallium arsenide wafer is placed in a deoxidizing / deoxidizing agent solution to remove the native oxide and obtain a passivated surface. Preferably, an aqueous solution of ammonium sulfide ((NH4)2S) or a thioacetamide solution with a mass fraction of 5-25% is used, and the wafer is immersed at 20-60°C for 5-30 min, then rinsed with deionized water and dried with nitrogen; or hydrogen plasma treatment is used.

[0029] (2) Self-assembly deposition: The pretreated wafer is immersed in a solution containing organic ligands, or the ligands are applied to the wafer surface by spin coating, spraying, vapor deposition, etc. The solution uses an organic solvent as the medium, and the solvent is selected from one or more of ethanol, isopropanol, acetone, toluene, and N,N-dimethylformamide. The concentration of organic ligands is 0.1-100 mM, preferably 1-20 mM. The self-assembly temperature is 0-100℃, preferably 40-80℃, and the time is 1-120 min, preferably 10-60 min. During this process, the ligand molecules form stable coordination bonds with Ga atoms suspended on the GaAs surface through functional groups, and self-organize into a dense and ordered monolayer. By repeating the above deposition cycle (1-10 times), a multilayer self-assembled film can be obtained, and the thickness increases linearly with the number of cycles (approximately 1-5 nm per cycle).

[0030] (3) Thermal curing (pre-carbonization): The wafer with the self-assembled film deposited is placed in an inert atmosphere (N2, Ar) or a vacuum environment and heated to 200-400℃ at a heating rate of 1-20℃ / min, and held for 5-120min. During this stage, the organic ligands undergo partial pyrolysis and cross-linking to form an amorphous carbon network, while some coordinated Ga atoms are oxidized to Ga2O3 to form a dense carbon-gallium oxide composite layer. This layer exhibits excellent thermal stability below 600℃ and a water vapor permeability of <10%. - ²g / (m²·d).

[0031] (4) Self-emission: After completing the required high-temperature device process (such as ion implantation activation, ohmic contact alloy, etc.), place the wafer in a low-pressure inert atmosphere (N2, Ar, pressure <10 Torr, preferably <1 Torr) or a vacuum (<10 - In an environment with a temperature of 3 Torr (300°C), the temperature is increased to 680–720°C at a rate of 5–50°C / min and held for 1–30 min. At this temperature, a carbothermic reduction reaction occurs inside the protective layer. Ga2O3(s)+2C(s)→Ga2O(g)+2CO(g) or Ga2O3(s)+3C(s)→2Ga(g)+3CO(g) Ga₂O (boiling point approximately 650℃) and CO / CO₂ are both gaseous products that rapidly desorb from the surface. No solid residue remains from the reaction products, and the reaction only occurs at temperatures ≥680℃, ensuring the protective layer remains stable below this temperature.

[0032] (5) Optional post-treatment: After volatilization, a small amount of H2 or atomic hydrogen can be introduced to further reduce the trace oxides on the surface at 500-700℃ to obtain an atomically smooth hydrogen-terminated surface, which can be directly used for subsequent epitaxial growth.

[0033] 3. Key parameter control Ligand selection: By selecting ligands with different pyrolysis temperatures, the volatilization initiation temperature can be controlled within the range of 650–750 °C. For example, the volatilization peak of the tert-butylphosphonic acid derivative layer is about 695 °C, and that of the trimesoic acid derivative layer is about 710 °C.

[0034] Film thickness control: A single self-assembly cycle yields a film thickness of approximately 1–3 nm, with the total thickness precisely controlled by the number of cycles. A thickness of 5–30 nm is recommended to balance impermeability and rapid evaporation.

[0035] Curing conditions: Too high a curing temperature (>450℃) may lead to excessive graphitization of carbon, reducing reactivity; too low a temperature (<200℃) will result in an insufficiently dense film. 250–350℃ is preferred.

[0036] In a second aspect, embodiments of the present invention provide a stress mismatch-burst desorption composite capping layer: As a parallel or supplement to the first embodiment, the present invention also provides a multilayer composite protective layer that utilizes thermal stress and phase change to induce physical delamination.

[0037] 1. Layered structure: The composite cap layer comprises, from bottom to top: Underlying passivation layer: PECVD silicon oxynitride (SiO2) with a thickness of 1–20 nm x N_y (refractive index 1.6–1.9) primarily functions to chemically passivate the GaAs surface, block As diffusion, and provide good adhesion for the upper layer.

[0038] Intermediate sacrificial stress layer: a germanium-tin alloy with a thickness of 20–200 nm (Ge 1-x Sn x It consists of a Sn layer or a tellurium (Te) layer. The percentage of Sn atoms in GeSn is x = 10-30%, and its melting point is continuously adjustable in the range of 680-720℃. The purity of the Te layer is >99.99%.

[0039] Top sealing layer: PECVD silicon carbonitride (SiCN) with a thickness of 10-50nm, which has high hardness and brittleness, is used to provide mechanical constraint and enhance compactness.

[0040] 2. Preparation process: (1) Bottom layer deposition: PECVD is used, substrate temperature is 200~350℃, SiH4 / N2O / NH3 system, and the deposition rate is controllable.

[0041] (2) Intermediate layer deposition: GeSn can be deposited by magnetron sputtering (Ge target and Sn target co-sputtering) or electron beam evaporation, with the substrate temperature at room temperature to 150℃. After deposition, annealing (<300℃) is used to stabilize the amorphous state; the Te layer is deposited by thermal evaporation and the substrate is cooled.

[0042] (3) Top layer deposition: PECVD, substrate temperature <300℃, SiH4 / CH4 / NH3 or SiH4 / C2H4 / NH3 system.

[0043] 3. Removal mechanism and process conditions: The wafer, after completing the high-temperature process, is placed in a vacuum or inert atmosphere and rapidly heated (≥50℃ / min) to 700±20℃, held at that temperature for 0.5–5 min. During this process: The intermediate sacrificial layer melts (GeSn) or sublimates rapidly (Te), resulting in a rapid change in volume (GeSn melts and shrinks by about 5-10% in volume, while Te sublimates and expands by more than 10³ times in volume). The difference in thermal expansion coefficients between GeSn and GaAs substrates (Ge: ~6×10)-6 / K,GaAs:~5.7×10 -6 / K, the difference is small, but Sn can be added to adjust it appropriately) combined with the high elastic modulus of the top SiCN, a huge interfacial shear stress is generated; The SiCN layer is too brittle to withstand sudden stress changes, resulting in microcracks. Molten GeSn or Te vapors are ejected along the cracks, simultaneously physically breaking the underlying SiON film, causing the composite film to burst and detach from the wafer surface.

[0044] The detached membrane can be removed with the aid of airflow or gentle ultrasound. Only a very thin (<2nm) natural oxide remains on the GaAs surface, which can be easily removed with dilute hydrochloric acid or hydrogen plasma.

[0045] Thirdly, embodiments of the present invention also provide a hydrogen radical-assisted low-temperature desorption arsenic cap (As-cap): To address the problem of excessively low volatilization temperature of existing As-cap, this invention provides a modified solution that enables complete desorption at room temperature to 150°C, thus avoiding high-temperature failure.

[0046] 1. Structure: A catalyst metal film with a thickness of 1–10 nm is deposited in situ or ex-situ on the surface of the As-cap (0.5–2 μm thick) grown by MBE. The material is selected from nickel (Ni), palladium (Pd), platinum (Pt), or their alloys. The metal layer can be prepared by electron beam evaporation, sputtering, or chemical plating.

[0047] 2. Desorption process: A wafer with a catalyst / As-cap / GaAs structure is placed in a hydrogen radical environment. Hydrogen radicals can be generated through hot filament decomposition, microwave plasma, or radio frequency plasma. Process conditions: temperature 25–150℃, pressure 0.1–10 Torr, H2 flow rate 10–500 sccm, processing time 1–30 min. Under the action of the catalyst, H2 molecules decompose into highly reactive H atoms. These H atoms penetrate to the As / GaAs interface and react with As to generate gaseous AsH3 (boiling point -55℃), which is then rapidly removed. After desorption, a hydrogen-terminated GaAs surface is obtained, achieving an atomically clean interface without any heating.

[0048] Fourthly, embodiments of the present invention provide a laser-based selective evaporation patterning removal method: To achieve spatially selective removal of the protective layer, embodiments of the present invention provide a laser-assisted local heating volatilization process.

[0049] 1. Applicable objects: Protective layers with specific infrared absorption peaks, such as the organic-inorganic hybrid layer in the first technical solution and the GeSn layer (absorbing CO2 laser) in the second technical solution.

[0050] 2. Process: A CO2 laser with a wavelength of 9.2–11.2 μm (corresponding to the two-photon absorption band of GaAs and the infrared absorption bands of various protective layers) or a nanosecond pulsed laser with a wavelength of 532 nm / 1064 nm is used. The laser is focused onto a specific area on the wafer surface (such as the edge, back side, or scribe line) using an optical system. The laser power density is 10-1. 4 ~10 6 W / cm², scanning speed 1–100 mm / s. The protective layer is locally heated to over 700°C, causing volatilization / cracking, while the surrounding area remains at room temperature. This process enables maskless and waterless patterned removal, and is particularly suitable for wafer edge grain control and protective layer removal before backside thinning.

[0051] Example 1 1. Preparation of protective layer: Substrate: 2-inch semi-insulating GaAs(100) wafer, Cr-doped; Surface pretreatment: 25% (NH4)2S aqueous solution, soak at 50℃ for 20 min, rinse with deionized water for 30 s, and dry with N2; Ligand solution: 10 mM tert-butylphosphonic acid / anhydrous ethanol solution, filtered through a 0.22 μm PTFE membrane; Self-assembly deposition: Heating in a 60℃ water bath for 30 min, then rinsing with anhydrous ethanol and drying with N2; repeating the cycle 3 times. Thermosetting: N2 atmosphere (flow rate 5 slm), heating rate 5℃ / min, target temperature 300℃, hold for 20 min, then allow to cool naturally; Final film thickness: 8.2 ± 0.3 nm, measured by elliptic polarization spectroscopy.

[0052] 2. Application of high-temperature process simulation: The wafer with the protective layer was placed in a rapid thermal annealing furnace to simulate the ion implantation activation process. Process conditions: N2 atmosphere, 700℃, holding time for 5 min, heating rate 50℃ / s; Protective layer evaporation treatment: After annealing, the material is directly introduced into the cooling chamber of the same equipment, with no atmospheric exposure throughout the process.

[0053] 3. Application Data: Permeation resistance: Secondary ion mass spectrometry (SIMS) depth analysis, after annealing at 700℃ for 5 min, the As diffusion depth is <2nm (instrument detection limit), and there is no detectable oxide layer on the surface; Volatilization completion: X-ray photoelectron spectroscopy (XPS) surface scan, C1s signal atom concentration 0.3 at% (below background level), Ga 3d / As 3d peak ratio 1.02±0.02 (consistent with untreated cleavage planes); Surface morphology: Atomic force microscopy (AFM) 1×1μm² scanning, root mean square roughness (Rq) 0.18nm; Interface electrical properties: Minority carrier lifetime was measured by non-contact microwave photoconductivity attenuation method (μ-PCD), τ=12.8ns (reference die τ=2.1ns after annealing with the same process).

[0054] Example 2 1. Preparation of protective layer: Substrate: 4-inch GaAs(100) epitaxial wafer, Si doping concentration 1×10¹ 7 cm - ³; Surface pretreatment: Immerse in 10% thioacetamide aqueous solution at 60℃ for 15 min; Ligand solution: 5 mM pyromellitic acid / DMF solution; Self-assembly deposition: Heat in an oil bath at 80℃, soak for 60 min, remove and rinse with DMF, rinse twice with isopropanol, and dry with N2; cycle 5 times; Thermosetting: Ar atmosphere (flow rate 2 slm), heating rate 2℃ / min, target temperature 350℃, holding time 30min; Final film thickness: 11.8 ± 0.5 nm.

[0055] 2. High-temperature process applications: Application scenario: Ohmic contact alloying process for GaAs-based HEMT devices; Process conditions: Gas formation (5% H2 / 95% N2), 710℃, hold for 3 min; Protective layer evaporation: Maintain a vacuum of <0.1 Torr in the same cavity, heat to 710℃ and hold for 10 minutes.

[0056] 3. Application Data: Anti-permeation stability: After alloying at 710℃ for 3 min, SIMS showed an As external diffusion depth of <3nm; in the unprotected area, the As external diffusion depth was >50nm, and the Ga-rich layer thickness on the surface was ~12nm. Volatile residue: XPS wide scan, C concentration 0.2 at%, O concentration 0.5 at%, surface As / Ga ratio 0.98; Device performance: Transmission line model (TLM) testing showed a specific contact resistivity ρ_c = 2.3 × 10⁻⁶. -6 Ω·cm² (Traditional SiO2 protection + wet etching process ρ_c=5.1×10 -6 Ω·cm²); Surface reconstruction: In-situ observation by Reflection High Energy Electron Diffraction (RHEED) showed that the surface after volatilization exhibited a clear (2×4) reconstruction without halo rings.

[0057] Example 3 1. Preparation of protective layer: Substrate: 6-inch GaAs(100) wafer; Surface pretreatment: hydrogen plasma, 13.56MHz, power 50W, pressure 0.1Torr, H2 flow rate 100sccm, substrate temperature 100℃, treatment time 5min; Ligand solution: 20 mM hexadecylphosphonic acid / toluene solution; Self-assembled deposition: Immerse at 25℃ for 120 min, rinse with toluene, and dry with N2; cycle 10 times; Thermosetting: N2 atmosphere, heating rate 1℃ / min, target temperature 250℃, holding time 120min; Final film thickness: 23.5 ± 1.2 nm.

[0058] 2. High-temperature process applications: Application scenario: High-dose Si + Ion implantation (1×10¹) 5 cm - Activation annealing after (2, 80keV); Process conditions: N2 atmosphere, 695℃, holding time for 10 min, heating rate 20℃ / s; Protective layer volatilization: Same as the cavity, pressure <1 Torr, keep warm at 695℃ for 15 min.

[0059] 3. Application Data: Anti-permeability performance: After injection and annealing, the sheet resistance R_s = 285Ω / □ (the non-protected control sample R_s = 412Ω / □, due to the decrease in surface carrier concentration caused by As volatilization). Volatilization completion: Time-of-flight secondary ion mass spectrometry (TOF-SIMS), C3H7 + Fragment ion intensity was at the same level as the background, and no characteristic peaks of long-chain alkyl groups were observed. Surface chemical state: High-resolution XPS Ga 3d spectrum, with only Ga 3d characteristic peaks of GaAs (18.8 eV). Wafer uniformity: 9-point test film thickness RSD < 5%, surface reflectance RSD after volatilization < 2%.

[0060] Example 4 1. Preparation of protective layer: Substrate: GaAs(100) patterned substrate with trenches of 8:1 aspect ratio; Surface pretreatment: immersion in a 5% (NH4)2S + 2% NH4OH mixed solution at 40℃ for 10 min; Ligand solution: 2 mM 2,5-dihydroxyterephthalic acid / ethanol solution, with the addition of 0.5 mM Zn²⁺ + Auxiliary coordination; Self-assembled deposition: Immerse at 50℃ for 45 min, rinse with ethanol; cycle 4 times; Thermosetting: Vacuum (5×10) - ²Torr), heating rate 3℃ / min, target temperature 320℃, hold for 45min; Final film thickness: 15.3 nm in the planar region and 14.8 nm at the bottom of the trench sidewall (high conformality).

[0061] 2. High-temperature process applications: Application scenario: Trench isolation annealing; Process conditions: Vacuum annealing, 700℃, holding time 8 min; Protective layer volatilization: Heating continuously for 12 minutes under the same conditions.

[0062] 3. Application Data: Conformal coverage: Cross-sectional TEM observation showed that the film thickness at the bottom of the trench was 96% of that in the planar area and 92% in the middle of the sidewall. Complete volatilization: EDX elemental analysis at the bottom of the trench showed no detectable C and Zn signals; Interface state density: The interface state density D_it = 3.2 × 10¹¹ cm⁻¹ was measured using a high-frequency CV method in a metal-insulator-semiconductor structure. - ²eV - ¹(Surface D_it after traditional wet etching = 1.2 × 10¹² cm) - ²eV - ¹); Trench integrity: No cracks, no residual particles, and no lateral corrosion at the edges.

[0063] Example 5 1. Fabrication of layered structures: Substrate: GaAs(100), front-side device fabrication has been completed; The bottom passivation layer is made of PECVDSiON, a SiH4 / N2O / NH3 system, with a substrate temperature of 250℃, a thickness of 5.2±0.3nm, and a refractive index of 1.72. Intermediate sacrificial stress layer: Ge0.8Sn0.2, magnetron co-sputtering, Ge target DC 100W, Sn target RF 30W, Ar pressure 3mTorr, substrate temperature room temperature, thickness 78±4nm; Sn composition EDS quantitative analysis 19.8 at.% Top sealing layer: PECVDSiCN, SiH4 / CH4 / NH3 system, substrate temperature 280℃, thickness 22±1nm, hardness 18GPa.

[0064] 2. Application of burst desorption technology: Application scenario: Removal of the front protective layer before back-side thinning of the device; Process conditions: Ar atmosphere, heating rate 100℃ / min, target temperature 700℃, holding time 1min, natural cooling; Auxiliary cleaning: Gentle N2 air gun purging (pressure 5psi).

[0065] 3. Application Data: Peeling efficiency: According to the random 10 fields of view statistics of optical microscopy, the peeled area of ​​the composite film was 99.7%, and the diameter of the residual area was <3μm; Surface residue: XPS analysis of the residue area showed that the thickness of the SiON local residue was <2nm, and the C, Ge, and Sn signals were below the detection limit; Substrate damage: Differential interference phase contrast microscopy shows no scratches or pits on the surface; photoluminescence spectroscopy shows a peak intensity of 98% of the original substrate. Process window: >95% stripping can be achieved in the Sn component range of 15-25% (corresponding to melting temperature of 680-715℃), with the optimal range being 19-21% (700±5℃).

[0066] Example 6 1. Fabrication of layered structures: Substrate: 2-inch GaAs with InGaAs quantum well structure; Bottom layer: PECVDSiON, 3.8nm; Intermediate layer: High-purity Te (99.999%), thermally evaporated, evaporation source temperature 450℃, substrate cooled (10℃), deposition rate 0.5 Å / s, thickness 52±3 nm; Top layer: PECVDSiCN, 15±1nm.

[0067] 2. Application of burst desorption technology: Process conditions: Vacuum < 1 × 10 -5 Torr, heating rate 150℃ / min, target temperature 690℃, hold time 30s; Te sublimation characteristics: Vacuum gauge pressure instantaneously rises to 2×10 - ³Torr, lasting approximately 10 seconds.

[0068] 3. Application Data: Peeling rate: from heating to 690°C to complete peeling in <45 seconds, approximately 3 times faster than in Example 5; Peeling integrity: SEM full-section scan showed a 100% peeling rate with no visible residue; Quantum well luminescence characteristics: Low-temperature (77K) PL spectrum, peak wavelength 853nm, full width at half maximum (FWHM) 8.2meV (8.5meV for untreated control sample), no defect-related luminescence band; Te residue: ICP-MS digestion test showed that the surface Te atomic density was <1×10¹. 0 cm - ².

[0069] Example 7 1. Structure preparation: Substrate: GaAs(100) grown in situ using MBE, with a (2×4) reconstructed surface; As-cap deposition: cooled to -10℃, As4 beam, deposition thickness 1.2μm (RHEED oscillation calibration); Catalyst deposition: electron beam evaporation, Ni target, deposition rate 0.1 Å / s, thickness 3.0 ± 0.3 nm, substrate temperature maintained at -10 °C; Atmospheric exposure: Remove the MBE chamber and store it in a cleanroom environment for 7 days.

[0070] 2. Application of low-temperature desorption process: Equipment: Hot-wire hydrogen radical pyrolysis system; Process conditions: substrate temperature 100℃, hot wire temperature 1800℃, H2 flow rate 50 sccm, working pressure 0.5 Torr, processing time 10 min; Endpoint determination: QMS monitoring m / z=78 (AsH3) + The signal drops to the baseline.

[0071] 3. Application Data Desorption temperature: Traditional As-cap desorption requires 350℃, but in this embodiment, it is reduced to 100℃, a reduction of 250℃. Desorption rate: The peak AsH3 yield corresponds to a treatment time of 3.5 min, and complete desorption occurs in 10 min. Surface cleanliness: XPS As 3d / Ga 3d peak area ratio 1.05, no As2O3 (~44.5eV) or Ga2O3 characteristic peaks observed; AES detection showed no C, O, or Ni signals. Surface reconstruction: LEED exhibits a clear c(4×4) pattern, consistent with the surface obtained by As-cap desorption at 350℃ reported in the literature. Interfacial recombination: Time-resolved PL testing showed an interfacial recombination velocity S = 620 cm / s (after conventional 350℃ desorption of As-cap and atmospheric storage, S = 1.2 × 10⁻⁶). 5 (cm / s).

[0072] Example 8 1. Structure preparation: Substrate: GaAs(100), Al0.3Ga0.7As heterojunction; As-cap deposition: As2 beam, deposition thickness 0.8 μm; Catalyst deposition: electron beam evaporation, Pd, thickness 1.5 nm.

[0073] 2. Application of low-temperature desorption process: Process conditions: substrate temperature 25℃ (room temperature), hot wire temperature 1900℃, H2 flow rate 100 sccm, pressure 1.0 Torr, processing time 20 min.

[0074] 3. Application Data: Desorption temperature: Desorption at room temperature, without any auxiliary heating; Desorption efficiency: The AsH3 signal intensity monitored by QMS was 1.7 times that of Example 7 (higher catalytic activity per unit thickness). Surface morphology: AFMRq=0.21nm, no heterojunction step stacking anomaly; Heterojunction interface: The PL spectrum peak position deviates from that of the reference sample that has not undergone the As-cap process by <0.5 meV, and the interface has not degraded.

[0075] Example 9 1. Sample preparation: Protective layer: A tert-butylphosphonic acid-derived layer with a thickness of 8 nm was prepared according to Example 1; Pattern requirements: Remove only the 3mm ring area at the edge of the wafer, and retain the protective layer in the central area for subsequent processes.

[0076] 2. Laser evaporation process: Laser system: CO2 laser, wavelength 10.6μm, continuous wave mode; Optical parameters: Spot diameter 200 μm (Gaussian distribution), power density 5 × 10⁻⁶ 4 W / cm² (total power 15.7W); Scanning parameters: Scanning speed 20mm / s, line spacing 100μm (50% overlap), single scan; Environmental conditions: Atmospheric environment, no additional heating.

[0077] 3. Application Data: Selected area resolution: measured by optical microscopy, volatile / non-volatile boundary width <50μm, heat-affected zone <120μm; Volatilization completion: μ-Raman spectra on both sides of the boundary, C peak in the volatile region (1580 cm⁻¹) - ¹) Completely disappears, with the intensity of peak C in the non-volatile region remaining at 92%; Edge morphology: measured by a profilometer, there were no molten protrusions or depressions at the edges, and the height difference was <2nm; Backside compatibility: The backside of the wafer is not coated with a protective layer, so the laser does not focus on the backside and there is no damage.

[0078] Example 10 1. Sample preparation: Protective layer: A Ge0.8Sn0.2 composite capping layer was prepared according to Example 5; Objective: To selectively remove the protective layer from the scribe line area of ​​a chip with a scribe line width of 80 μm.

[0079] 2. Laser evaporation process: First laser: CO2 laser, 10.6 μm, used to heat the GeSn layer, power density 3 × 10⁻⁶. 4 W / cm²; Second laser: Nd:YAG, 532nm, used to assist in fracturing the top SiCN layer, power density 1×10⁻⁶ 4 W / cm², delay 50μs; Scanning strategy: dual beams coaxial, spot size 15μm×80μm (elliptical), single scan along the scribe line.

[0080] 3. Application Data: Cleanliness of the dicing channel: SEM observation showed that the SiON substrate was completely exposed, with no GeSn or SiCN residues and no cracks extending to the active area of ​​the chip. Lateral thermal effects: At a distance of 5 μm from the edge of the scribe line, the resistance change of the NiCr device is <0.3%; Process speed: Single dicing scan time 0.2s, 4-inch wafer full-wafer processing <5min; Mechanical strength: The fracture strength test of the chip after dicing showed no significant difference compared with the control group that removed the protective layer by wet method.

[0081] Comparative Example 1 1. Preparation of protective layer: Substrate: GaAs wafers from the same batch as in Example 1; Deposition equipment: PECVD, substrate temperature 250℃, SiH4 / N2O system; Film thickness: 100nm (standard protective layer thickness); Compactness: Refractive index 1.46 (consistent with SiO2 characteristics).

[0082] 2. High-temperature process applications: Process conditions: Same as in Example 1, N2 atmosphere, 700℃, 5min.

[0083] 3. Protective layer removal: Corrosive solution: buffered hydrofluoric acid (BHF, HF:NH4F=1:6). Corrosion time: room temperature, 120s (over-corrosion 50%); Cleaning: Rinse with deionized water for 5 minutes, then dry with N2.

[0084] 4. Comparison of data As shown in Table 1 below: Table 1 Summary of technical defects: Although Comparative Example 1 can achieve anti-penetration at 700℃, wet corrosion leads to surface oxidation, roughening, chemical residues, and lateral corrosion. XPS shows that C and O contamination are as high as 4.2 at% and 12.8 at%, respectively, and the surface state density increases by nearly 5 times, which cannot meet the interface requirements of high-sensitivity devices.

[0085] Comparative Example 2 1. Preparation of protective layer: Substrate: MBEGaAs from the same batch as in Example 7; As-cap deposition: MBE in situ, substrate temperature -20℃, As4 beam, thickness 1.0μm.

[0086] 2. Atmospheric exposure: Storage conditions: Cleanroom atmospheric environment, 7 days (consistent with Example 7).

[0087] 3. Protective layer removal: Equipment: UHV annealing chamber; Desorption process: heating rate 20℃ / min, target temperature 350℃, holding time 10min; Surface reconstruction: c(4×4).

[0088] 4. Comparison of data: As shown in Table 2 below: Table 2 Summary of technical shortcomings: Comparative Example 2 exposed the fundamental flaw of traditional As-cap in non-in-situ environments—atmospheric storage leads to the formation of As2O3 and carbon contamination on the surface, leaving residual carbon, oxygen, and As particles even after UHV desorption. The catalyst-assisted hydrogen radical desorption of this invention can be completed at room temperature to 100°C, completely avoiding the oxidation window before high-temperature desorption and obtaining an atomically clean surface.

[0089] Comparative Example 3 1. Preparation of protective layer: Substrate: GaAs from the same batch as in Example 5; Deposition process: MBE, substrate temperature 400℃, Ge source, thickness 200nm; Surface oxide layer: ~2nm GeO2 formed during atmospheric storage.

[0090] 2. High-temperature process applications: Process conditions: Same as in Example 5, 700℃, 5 min.

[0091] 3. Protective layer removal: Etching solution: 30% H2O2, room temperature; Etching time: 5 minutes (to ensure complete removal of Ge); Endpoint determination: The hydrophobic surface becomes hydrophilic.

[0092] 4. Comparison of data: As shown in Table 3 below: Table 3 Summary of technical shortcomings: Comparative Example 3 represents a typical dilemma of solid-phase epitaxial cap layers—removal must rely on chemical etching that may damage the substrate. H2O2 oxidation of the GaAs surface forms an amorphous oxide layer, which is difficult to fully restore the intrinsic surface even with dilute hydrochloric acid treatment. The stress burst desorption of this invention is a purely physical removal process that does not involve any redox reactions, and the surface chemical state remains intact.

[0093] The following four tables summarize the quantitative comparison of all 10 embodiments and 3 comparative embodiments across five key technical dimensions: Table 4 1. In conclusion, it can be seen that: Regarding the 700℃ process window: Examples 1-6 and 9-10 all confirmed that the protective layer was stable and dense in the range of 680-720℃, and the As diffusion depth after annealing at 700℃ was <3nm, while Comparative Example 2 had completely volatilized at 350℃ and lost its protective function.

[0094] Regarding dry removal: all examples achieve zero wet contact, while Comparative Examples 1 and 3 must use chemical reagents such as HF or H2O2, and the surface oxidation and residue problems cannot be eliminated.

[0095] Regarding interface quality: Example 1 had a surface roughness of 0.18 nm, close to the intrinsic value of cleavage (0.15 nm); Comparative Example 1, after wet etching, had a roughness of 0.47 nm, a degradation of 160%. Example 7 had an interface recombination velocity of 620 cm / s, reaching the level of in-situ UHV processes; Comparative Example 2, after atmospheric exposure, had a surface roughness (S) of 1.2 × 10⁻⁶. 5 cm / s, completely losing the application value of the device.

[0096] Regarding the non-obviousness of inventiveness: Comparative Example 1 / 3 represents the design paradigm of "physical barrier + wet removal", and Comparative Example 2 represents the "low-temperature sublimation" paradigm. This invention completely breaks away from the existing paradigms and establishes three new paradigms: "coordination locking-spontaneous volatilization" (Examples 1-4), "stress mismatch-explosive desorption" (Examples 5-6), and "catalytic hydrogenation-low-temperature volatilization" (Examples 7-8).

[0097] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 700℃ volatile gallium arsenide wafer anti-permeation protective layer, characterized in that, The protective layer is formed by thermosetting a metal-organic framework derived layer through coordination of organic ligands with gallium atoms on the surface of gallium arsenide. The protective layer can spontaneously generate gaseous products in the temperature range of 680 to 720°C, achieving residue-free removal.

2. The 700℃ volatile gallium arsenide wafer anti-permeation protective layer according to claim 1, characterized in that, The organic ligands include compounds containing at least one functional group selected from phosphonic acid, carboxylic acid, sulfonic acid, or hydroxamic acid groups; The main molecular structure of the organic ligand includes at least one of a C4-C18 alkyl chain, phenyl, biphenyl, or naphthyl group.

3. The 700℃ volatile gallium arsenide wafer anti-permeation protective layer according to claim 1, characterized in that, The thickness of the protective layer is 1–100 nm; the thermosetting is carried out in an inert atmosphere or in a vacuum, the curing temperature is 200–400 °C, and the curing time is 5–120 min.

4. The 700℃ volatile gallium arsenide wafer anti-permeation protective layer according to claim 1, characterized in that, The self-emission is carried out in a low-pressure inert atmosphere or vacuum, with a pressure below 10 Torr. During the volatilization process, a carbothermic reduction reaction occurs, and the reaction products include at least one of gaseous Ga2O, CO, and CO2.

5. A method for preparing a 700°C volatile gallium arsenide wafer anti-permeation protective layer according to any one of claims 1-4, characterized in that, Includes the following steps: S1. Perform surface pretreatment on the gallium arsenide wafer to remove native oxides; S2. Apply organic ligands to the pretreated gallium arsenide surface and perform self-assembly deposition to form a metal-organic framework layer in which the organic ligands are coordinated with the surface gallium atoms; S3. Perform thermal curing in an inert atmosphere or vacuum to form a dense, impermeable protective layer.

6. The preparation method according to claim 5, characterized in that, The surface pretreatment involves immersing the surface in a 5-25% ammonium sulfide or thioacetamide solution at 20-60°C for 5-30 minutes.

7. The preparation method according to claim 6, characterized in that, The self-assembly deposition is performed by immersion; the concentration of organic ligands in the immersion solution is 0.1–100 mM, the self-assembly temperature is 0–100 °C, and the self-assembly time is 1–120 min; the self-assembly deposition is cycled 1–10 times.

8. The application of a 700°C volatile gallium arsenide wafer anti-permeation protective layer according to any one of claims 1-4, characterized in that, The protective layer is applied in a gallium arsenide high-temperature process, the temperature of which is 680–720°C, and includes at least one of ion implantation activation annealing, ohmic contact alloying, or surface protection before epitaxial growth.

9. The application according to claim 8, characterized in that, The protective layer can also be applied to high-temperature processes of III-V compound semiconductor substrates, wherein the III-V compound semiconductor includes at least one of gallium arsenide, indium phosphide, or gallium antimonide.

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