A low-latency video protocol conversion system, method and storage medium

Abstract

The present invention relates to the technical field of video protocol data conversion, and more specifically, to a low-latency video protocol conversion system, method and storage medium. It includes: a video decoding module, a cache module, a synchronization processing module, a delay switching module and a video encoding module; the video decoding module is data-connected to the input end of the cache module; the input end of the delay switching module is data-connected to the output end of the cache module; the input end of the synchronization processing module is data-connected to the output end of the cache module, and the output end is connected to the data end of the delay switching module; the input end of the video encoding module is data-connected to the output end of the delay switching module. The present invention converts the decoded NDI protocol conversion signal into a unified standard frame time through the synchronization processing module and then performs data processing, thereby improving the conversion rate.

Description

Technical Field

[0001] The present invention relates to the technical field of video protocol data conversion, and more specifically, to a low-latency video protocol conversion system, method, and storage medium. Background Art

[0002] In an era of rapid development in media streaming network transmission, a variety of compression and transmission standards have gradually proliferated. These different compression and transmission standards have severely fragmented media streaming applications, making it difficult for platforms to interoperate. For example, users of NDI applications cannot connect to IPMX applications. Conventional technologies typically use two devices to convert the relevant protocols. This approach not only increases protocol data conversion time but also increases conversion costs, hindering user connectivity and interoperability. Summary of the Invention

[0003] In order to overcome the problem of long time required to complete related protocol conversion functions using two devices as described in the background art, the present invention provides a low-latency video protocol conversion system, method and storage medium.

[0004] In order to solve the above technical problems, the technical solutions of the present invention are as follows:

[0005] In a first aspect, the present invention provides a low-latency video protocol conversion system, comprising: a video decoding module, a cache module, a synchronization processing module, a delay switching module, and a video encoding module;

[0006] The video decoding module is data-connected to the input end of the cache module, and is used to decode the NDI protocol data and input the decoded frame data into the cache module;

[0007] The input end of the delay switching module is connected to the output end of the cache module, and is used to process and output the frame data stored in the cache module;

[0008] The input end of the synchronization processing module is data-connected to the output end of the cache module, and the output end is connected to the data end of the delay switching module, and is used to convert the frame data statistical time into a unified statistical frame frequency, and calculate the frequency deviation based on the frame frequency to provide a data reference to the delay switching module, complete frequency deviation tracking, and adjust the data extraction strategy of the delay switching module;

[0009] The input end of the video encoding module is data-connected to the output end of the delay switching module, and is used to perform IPMX protocol encapsulation on the data converted by the delay switching module.

[0010] Preferably, the synchronization processing module includes a frame rate counter for constructing a frame rate query table, a synchronizer for calculating the frequency deviation at the current frame moment, a synchronization regulator for compensating for the frequency deviation, and a synchronization tracker for providing a reference calculation value to the synchronization regulator. The output end of the cache module is connected to the data end of the delay switching module after passing through the frame rate counter, the synchronizer, the synchronization tracker and the synchronization regulator in sequence.

[0011] Preferably, the delay switching module includes a frame pulse detector for monitoring frame pulses before decoding and detecting decoded video frames, a delay superimposer for superimposing delays to control the startup conversion protocol to obtain frame data, a cache monitoring module for avoiding excessively rapid changes in row addresses, and a frame address adjustment module for selecting the data extraction strategy according to the jitter of the frame data. The output end of the cache module is connected to the input end of the video encoding module through the frame pulse detector, the delay superimposer, the cache monitoring module and the frame address adjustment module in sequence.

[0012] In a second aspect, the present invention provides a low-latency video protocol conversion method based on a low-latency video protocol conversion system, the method comprising:

[0013] The video decoding module decapsulates and decodes the data transmitted by the NDI protocol and stores it in the cache module;

[0014] The synchronization processing module converts the frame rate obtained from the cache module into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking;

[0015] The low-latency switching module adjusts the data extraction strategy according to the frame rate and performs protocol conversion;

[0016] The video encoding module performs IPMX protocol encapsulation on the data converted by the delay switching module protocol.

[0017] Preferably, the synchronization processing module converts the frame rate obtained from the cache module into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking, including:

[0018] The frame rate counter synchronously converts the frame rate obtained from the cache module into a 90kHz pulse statistical count;

[0019] The synchronizer locks and decodes the parameter information in the stable state and calculates the frequency offset FO at the current frame moment;

[0020] The synchronous tracker calculates the window-type frequency offset FO and the cumulative frequency offset FO;

[0021] The synchronous regulator calculates the frequency offset compensation FO' and completes the frequency offset tracking.

[0022] Preferably, the synchronizer locks and decodes parameter information in a stable state, and calculates the frequency offset FO at the current frame time, including:

[0023] fcw_90k=2^32*(1800 / sys_clk_cnt);

[0024] local_90k_cnt=(FT i –FT0)*fcw_90k;

[0025] local_90k_cnt≈i*1800;

[0026] FO=local_90k_cnt / (i*1800);

[0027] Among them, fcw_90k represents the frequency control word of 90khz, sys_clk_cnt represents the frequency value converted from the system clock, local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0028] Preferably, the synchronous regulator calculates the frequency offset compensation FO' to complete the frequency offset tracking, including:

[0029] fcw_90k'=2^32*(1800 / sys_clk_cnt');

[0030] local_90k_cnt'=(FT i –FT0)*fcw_90k';

[0031] FO'=local_90k_cnt' / (i*1800),

[0032] Among them, fcw_90k' represents the control word generated by the adjusted clock according to the frequency of 90khz, sys_clk_cnt' represents the frequency value converted to the adjusted system clock, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0033] Preferably, the low-latency switching module adjusts the data extraction strategy according to the frame rate and performs protocol conversion, including:

[0034] The frame pulse detector monitors the frame pulse before decoding and detects the video frame after decoding, and outputs the locking state of the continuously and stably detected frame pulse to the subsequent module for reference;

[0035] The time delay adder adds a time delay according to the arrival time of the frame pulse to control the acquisition of frame data of the start conversion protocol;

[0036] The cache monitoring module outputs data while decoding the frame data, and feeds back the changes in the row address to the FO adjustment;

[0037] The frame address adjustment module detects the jitter of the frame data before decoding to adjust the delayed output.

[0038] Preferably, the frame address adjustment module detects jitter of the frame data before decoding to adjust the delayed output, including:

[0039] When the jitter is too large and FO' cannot keep up quickly, the adjustment range of the frame delay is increased by the following formula: Frame overlap =

[0040] |local_90k_cnt'-local_90k_cnt| / 1800;

[0041] When FO'≈FO and remains stable, the synchronization relationship is re-established and the frame address is adjusted using the following formula: local_90k_cnt'=local_90k_cnt'±1800;

[0042] Among them, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, and local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames.

[0043] In a third aspect, the present invention provides a storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the low-latency video protocol conversion method as described in the second aspect is implemented.

[0044] Its beneficial effects are:

[0045] The present invention converts the decoded NDI protocol conversion signal into a unified standard frame time through a synchronization processing module and then performs data processing, thereby improving the conversion rate. The video decoding module decodes the NDI protocol data and inputs the decoded frame data into the cache module. The delay switching module processes and outputs the frame data stored in the cache module; the synchronization processing module converts the statistical time of the frame data stored in the cache module into a unified statistical frame frequency, and calculates the frequency deviation based on the frame frequency to provide a data reference to the delay switching module, completes frequency deviation tracking, and adjusts the data extraction strategy of the delay switching module; the video encoding module encapsulates the data converted by the delay switching module into the IPMX protocol, thereby improving the conversion rate between different protocols through a single device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a structural diagram of the low-latency video protocol conversion system provided by the present invention.

[0047] Figure 2 This is a structural diagram of the synchronization processing module provided by the present invention.

[0048] Figure 3 This is a structural diagram of the delay switching module provided by the present invention.

[0049] Figure 4 This is a flow chart for implementing the low-latency video protocol conversion method provided by the present invention.

[0050] Figure 5 This is a schematic diagram of the video protocol conversion provided by the present invention.

[0051] Figure 6 This is a flowchart of the implementation of the synchronization processing module provided by the present invention.

[0052] Figure 7 This is a flowchart of the implementation of the low-latency switching module provided by the present invention.

[0053] Wherein: video decoding module 10; cache module 20, delay switching module 30, synchronization processing module 40, video encoding module 50;

[0054] Frame rate counter 31, synchronizer 32, synchronization tracker 33, synchronization regulator 34;

[0055] Frame pulse detector 41 , delay adder 42 , cache monitoring module 43 , frame address adjustment module 44 . DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0057] The same or similar numbers in the drawings of the embodiments of the present application correspond to the same or similar parts; in the description of the present application, it should be understood that if there are terms such as "upper", "lower", "left", "right", "top", "bottom", "inside", "outside", etc. indicating orientations or positional relationships, they are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting this patent.

[0058] Example 1

[0059] like Figure 1 As shown, this embodiment provides a low-latency video protocol conversion system, including: a video decoding module 10, a cache module 20, a delay switching module 30, a synchronization processing module 40 and a video encoding module 50.

[0060] The video decoding module 10 is data-connected to the input end of the buffer module 20 . The video decoding module 10 is mainly used to decode NDI (Network Device Interface) protocol data and input the decoded frame data into the buffer module 20 .

[0061] The input end of the delay switching module 30 is connected to the output end of the buffer module 20. The delay switching module 30 is mainly used to process and output the frame data stored in the buffer module 20.

[0062] The input of the synchronization processing module 40 is data-connected to the output of the buffer module 20, and the output of the synchronization processing module 40 is data-connected to the data terminal of the delay switching module 30. The synchronization processing module 40 is primarily responsible for converting the statistical time of the frame data stored in the buffer module 20 into a unified statistical frame rate. It also calculates the frequency offset based on the frame rate and provides a data reference to the delay switching module 30, completing frequency offset tracking and adjusting the data extraction strategy of the delay switching module 30.

[0063] The input end of the video encoding module 50 is data-connected to the output end of the delay switching module 30. The video encoding module 50 is mainly used to encapsulate the data converted by the delay switching module 30 using the IPMX (Internet Protocol Media Exchange) protocol.

[0064] like Figure 2 As shown, the synchronization processing module 40 includes a frame rate counter 31, a synchronizer 32, a synchronization regulator 34 and a synchronization tracker 33. The output end of the cache module 20 is connected to the data end of the delay switching module 30 after passing through the frame rate counter 31, the synchronizer 32, the synchronization tracker 33 and the synchronization regulator 34 in sequence. The frame rate counter 31 is mainly used to construct a frame rate query table to convert the statistical time of the frame data stored in the cache module 20 into a unified statistical frame frequency. The synchronizer 32 is mainly used to calculate the frequency deviation of the current frame moment. The synchronization regulator 34 is mainly used to compensate for the frequency deviation. The synchronization tracker 33 is mainly used to provide a reference calculation value to the synchronization regulator 34.

[0065] In this embodiment, the frame rate counter 31 adopts a uniform statistical frequency of 90Khz.

[0066] In this embodiment, the synchronizer 32 uses the following FO (Frequency Offset) adjustment algorithm:

[0067] fcw_90k=2^32*(1800 / sys_clk_cnt);

[0068] local_90k_cnt=(FT i –FT0)*fcw_90k;

[0069] local_90k_cnt≈i*1800;

[0070] FO=local_90k_cnt / (i*1800);

[0071] Among them, fcw_90k represents the frequency control word of 90khz, sys_clk_cnt represents the frequency value converted from the system clock, local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0072] In this embodiment, the reference calculation values ​​of the synchronous tracker 33 include window-type frequency deviation and cumulative-type frequency deviation. The window-type frequency deviation mainly calculates the data information of the frequency deviation per second, while the cumulative-type frequency deviation mainly calculates the data information of the continuous frequency deviation.

[0073] In this embodiment, the synchronous regulator 34 calculates FO' (Frequency offset compensation) using the following algorithm:

[0074] fcw_90k'=2^32*(1800 / sys_clk_cnt');

[0075] local_90k_cnt'=(FT i –FT0)*fcw_90k';

[0076] FO'=local_90k_cnt' / (i*1800),

[0077] Among them, fcw_90k' represents the control word generated by the adjusted clock according to the frequency of 90khz, sys_clk_cnt' represents the frequency value converted to the adjusted system clock, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0078] like Figure 3As shown, the delay switching module 30 includes a frame pulse detector 41, a delay superimposed device 42, a cache monitoring module 43 and a frame address adjustment module 44. The output end of the cache module 20 is connected to the input end of the video encoding module 50 through the frame pulse detector 41, the delay superimposed device 42, the cache monitoring module 43 and the frame address adjustment module 44 in sequence. The frame pulse detector 41 is mainly used to monitor the frame pulse before decoding and detect the decoded video frame. The delay superimposed device 42 is mainly used to superimpose the delay to control the startup conversion protocol to obtain frame data. The cache monitoring module 43 is mainly used to feed back the change of the row address to calculate the frequency deviation FO adjustment to avoid the row address changing too fast. The frame address adjustment module 44 is mainly used to select the data extraction strategy according to the jitter of the frame data, that is, to control the read address to avoid the situation where the reader and writer step on each other and ensure the display effect.

[0079] In this embodiment, the data extraction strategy includes an inter-frame stable jitter extraction strategy, an inter-frame unstable jitter extraction strategy and a long delay extraction strategy. Among them, the inter-frame stable jitter extraction strategy is: when the inter-frame jitter is stable and the jitter time is small, the delay switching module 30 is adjusted to complete the reference jitter time adjustment and complete the balanced configuration of image quality and jitter. The inter-frame unstable jitter extraction strategy is: when the inter-frame jitter is unstable, the delay switching module 30 can be configured as a low delay mode. The low delay mode will be configured as a lower conversion delay. When the JPEG (Joint Photographic Experts Group, JPEG format) compressed stream network is not prepared enough to obtain data, the previous frame data will be read from the data cache to supplement the data integrity. The long delay extraction strategy is: a configurable 0-3 frame delay, the delay switching module 30 will extract data directly from the cache, the delay is large, but it can guarantee the conversion image quality to the greatest extent, and is used to ensure perfect image quality conversion.

[0080] In this embodiment, the frame address adjustment module 44 detects jitter of the frame data before decoding to adjust the delayed output, including:

[0081] When the jitter is too large and FO' cannot keep up quickly, the adjustment range of the frame delay is increased by the following formula: Frame overlap =

[0082] |local_90k_cnt'-local_90k_cnt| / 1800;

[0083] When FO'≈FO and remains stable, the synchronization relationship is re-established and the frame address is adjusted using the following formula: local_90k_cnt'=local_90k_cnt'±1800;

[0084] Among them, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, and local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames.

[0085] Through the above structural connection, the working principle of this embodiment can be as follows: the video decoding module 10 decodes the NDI protocol data and inputs the frame data formed after decoding into the cache module 20, and the delay switching module 30 processes and outputs the frame data stored in the cache module 20; the synchronization processing module 40 converts the statistical time of the frame data stored in the cache module 20 into a unified statistical frame frequency, and calculates the frequency deviation based on the frame frequency to provide data reference to the delay switching module 30, completes frequency deviation tracking, and adjusts the data extraction strategy of the delay switching module 30; the video encoding module 50 encapsulates the data converted by the delay switching module 30 into the IPMX protocol.

[0086] Example 2

[0087] like Figure 4 As shown, the present invention provides a low-latency video protocol conversion method, based on a low-latency video protocol conversion system, the method includes:

[0088] S101 , the video decoding module 10 decapsulates and decodes the data transmitted via the NDI protocol and stores the decoded data in the cache module 20 .

[0089] S102 , the synchronization processing module 40 converts the frame rate obtained from the buffer module 20 into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking.

[0090] S103 , the low-latency switching module 30 adjusts the data extraction strategy according to the frame rate and performs protocol conversion.

[0091] S104: The video encoding module 50 performs IPMX protocol encapsulation on the data converted by the delay switching module 30.

[0092] Please refer to Figure 5 , Figure 5 A schematic diagram of video protocol conversion provided by this embodiment is shown.

[0093] In steps S101-104, the video decoding module 10 processes the compressed stream network data of the NDI transmission protocol through the encoder and decoder and stores it in the cache module 20. Subsequently, the synchronization processing module 40 and the low-latency switching module 30 process the data and convert it into IPMX protocol data. The video encoding module 50 then converts it into a JPEG compressed stream network through the encoder.

[0094] Please combine Figure 6In step S102, the synchronization processing module 40 converts the frame rate obtained from the cache module 20 into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking, including:

[0095] S201 , the frame rate counter 31 synchronously converts the frame rate obtained from the buffer module 20 into a 90 kHz pulse statistical count.

[0096] S202: The synchronizer 32 locks the parameter information in the decoding stable state and calculates the frequency offset FO at the current frame time.

[0097] S203 , the synchronous tracker 33 calculates the window-type frequency offset FO and the cumulative-type frequency offset FO.

[0098] S204 , the synchronous regulator 34 calculates the frequency offset compensation FO′ to complete the frequency offset tracking.

[0099] In step S101, the frame rate counter 31 converts the frame rate into a 90kHz pulse statistical count. For example, a 50-frame video image has a 90kHz pulse count value of 1800. By comparing the converted count value with the pulse generated by the local count and the frame pulse, the clock deviation trend can be known.

[0100] In step S202, when the decoding generates an output, the parameter information of the decoding stable state is locked and the local_90k_cnt and the frame statistics count are reset. The synchronizer 32 locks the parameter information of the decoding stable state and calculates the frequency offset FO at the current frame moment in the following algorithm steps:

[0101] fcw_90k=2^32*(1800 / sys_clk_cnt);

[0102] local_90k_cnt=(FT i –FT0)*fcw_90k;

[0103] local_90k_cnt≈i*1800;

[0104] FO=local_90k_cnt / (i*1800);

[0105] Among them, fcw_90k represents the frequency control word of 90khz, sys_clk_cnt represents the frequency value converted from the system clock, local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0106] In step S203, to ensure accurate operation of the synchronous regulator 34, two types of frequency offsets (FOs) are calculated to optimize the regulator's operation. The window-type frequency offset FO counts the seconds to obtain frequency offset FO information per second and calculates the minimum, maximum, and average frequency offset FO values. The cumulative frequency offset FO continuously calculates the frequency offset FO during operation.

[0107] In step S204, in order to reduce the impact of frequency offset on output synchronization, it is necessary to appropriately adjust the frequency offset compensation FO, adjust sys_clk, and obtain sys_clk' so that FO' approaches FO. The synchronous regulator 34 calculates the frequency offset compensation FO' and completes the frequency offset tracking algorithm steps as follows:

[0108] fcw_90k'=2^32*(1800 / sys_clk_cnt');

[0109] local_90k_cnt'=(FT i –FT0)*fcw_90k';

[0110] FO'=local_90k_cnt' / (i*1800),

[0111] Among them, fcw_90k' represents the control word generated by the adjusted clock according to the frequency of 90khz, sys_clk_cnt' represents the frequency value converted to the adjusted system clock, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

[0112] Through steps S201-204, FO information can be acquired and clock tracking can be completed in a relatively short period of time. This feature utilizes frame rate stability for synchronization. In protocol conversion scenarios, frame rate reference information remains a reliable reference point, enabling source characteristic analysis and providing decision-making data for the low-latency conversion solution in step S103.

[0113] Please combine Figure 7 In step S103, the low-latency switching module 30 adjusts the data extraction strategy according to the frame rate and performs protocol conversion, including:

[0114] S301 , the frame pulse detector 41 monitors the frame pulses before decoding and detects the decoded video frames, and outputs the locking status of the continuously and stably detected frame pulses to the subsequent modules for reference.

[0115] S302 , the time delay adder 42 adds a time delay according to the arrival time of the frame pulse to control the acquisition of frame data of the start conversion protocol.

[0116] S303 , the cache monitoring module 43 outputs data while decoding the frame data, and feeds back the change of the row address to the FO adjustment.

[0117] S304 , the frame address adjustment module 44 detects jitter of the frame data before decoding to adjust the delayed output.

[0118] In step S301, the frame pulse should theoretically be stable, continuous, and have minimal jitter. When the frame pulse is detected continuously and stably, a locked state is output for subsequent reference. Pulse frames typically do not experience sudden interruptions; instead, they experience a range of acceleration and deceleration, which can lead to increased variability in the frame buffer. In this embodiment, not only are decoded video frames detected, but pre-decoded frame pulses are also monitored, as pre-decoded video frames exhibit greater jitter.

[0119] In step S302, the frame data acquisition for the start-up conversion protocol is controlled by adding a delay based on the arrival time of the frame pulse. By determining jitter, the delay addition can be controlled to a very suitable range. For example, in a low-jitter scenario, a data delay as low as 16 lines can be obtained.

[0120] In step S303, in low-jitter mode, the data frame decoded by the previous stage is not read until a frame is ready. Instead, it is output as the frame data is decoded. Therefore, the real-time status of the read and write data buffers must be strictly monitored, and accurate row address monitoring is required. At the same time, changes in the row address must also be fed back to the frequency offset (FO) adjustment to prevent excessive changes in the row address.

[0121] In step S304, the jitter change of the frame frequency will cause the read and write to step on each other in the low jitter mode. In order to ensure the display effect, it is necessary to control the read address. In this embodiment, the frame address adjustment module 44 detects the jitter of the frame data before decoding to determine whether the current jitter is too large. The frame address adjustment module 44 detects the jitter of the frame data before decoding to adjust the delayed output, including:

[0122] When the jitter is too large and FO' cannot keep up quickly, the adjustment range of the frame delay is increased by the following formula: Frame overlap =

[0123] |local_90k_cnt'-local_90k_cnt| / 1800;

[0124] When FO'≈FO and remains stable, the synchronization relationship is re-established and the frame address is adjusted using the following formula: local_90k_cnt'=local_90k_cnt'±1800;

[0125] Among them, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, and local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames.

[0126] While correcting local_90k_cnt', the frame address can be adjusted in stages to achieve lower latency output. At the same time, clock tracking needs to be readjusted. When the read and write row addresses stabilize again, and the write row address leads the read row address by a certain amount, the next frame is switched back to achieve normal operation in low-jitter scenarios.

[0127] Example 3:

[0128] This embodiment provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the low-latency video protocol conversion method of the second embodiment is implemented.

[0129] In this embodiment, the low-latency video protocol conversion method includes:

[0130] The video decoding module 10 decapsulates and decodes the data transmitted by the NDI protocol and stores it in the cache module 20.

[0131] The synchronization processing module 40 converts the frame rate obtained from the buffer module 20 into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking.

[0132] The low-latency switching module 30 adjusts the data extraction strategy according to the frame rate and performs protocol conversion.

[0133] The video encoding module 50 performs IPMX protocol encapsulation on the data converted by the delay switching module 30 .

[0134] Although the present invention is described in conjunction with the above specific embodiments, it is obvious that those skilled in the art can make many substitutions, modifications and changes based on the above content. Therefore, all such substitutions, improvements and changes are included in the spirit and scope of the appended claims. The above embodiments of the present invention are only examples made to clearly illustrate the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the field, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to list all the implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low-latency video protocol conversion system, characterized in that: include: Video decoding module, cache module, synchronization processing module, delay switching module and video encoding module; The video decoding module is data-connected to the input end of the cache module, and is used to decode the NDI protocol data and input the decoded frame data into the cache module; The input end of the delay switching module is connected to the output end of the cache module, and is used to process and output the frame data stored in the cache module; The input end of the synchronization processing module is data-connected to the output end of the cache module, and the output end of the synchronization processing module is data-connected to the data end of the delay switching module, and is used to convert the frame data statistical time into a unified statistical frame frequency, and calculate the frequency deviation based on the frame frequency to provide a data reference to the delay switching module, complete frequency deviation tracking, and adjust the data extraction strategy of the delay switching module; The delay switching module includes a frame pulse detector for monitoring frame pulses before decoding and detecting decoded video frames, a delay adder for adding delays to control the start of the conversion protocol to obtain frame data, a cache monitoring module for preventing row addresses from changing too quickly, and a frame address adjustment module for selecting the data extraction strategy based on the jitter of the frame data. The output end of the cache module is connected to the input end of the video encoding module through the frame pulse detector, the delay adder, the cache monitoring module, and the frame address adjustment module in sequence. The input end of the video encoding module is data-connected to the output end of the delay switching module, and is used to perform IPMX protocol encapsulation on the data converted by the delay switching module.

2. The low-latency video protocol conversion system according to claim 1, wherein: The synchronization processing module includes a frame rate counter for constructing a frame rate query table, a synchronizer for calculating the frequency deviation at the current frame moment, a synchronization regulator for compensating for the frequency deviation, and a synchronization tracker for providing a reference calculation value to the synchronization regulator. The output end of the cache module is connected to the data end of the delay switching module after passing through the frame rate counter, the synchronizer, the synchronization tracker and the synchronization regulator in sequence.

3. A low-latency video protocol conversion method, characterized in that: Based on the low-latency video protocol conversion system according to claim 1 or 2, the method includes: After decapsulating the data transmitted by the NDI protocol, the video decoding module decodes the transmitted data and stores it in the cache module; The synchronization processing module converts the frame rate obtained from the cache module into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking; The low-latency switching module adjusts the data extraction strategy according to the frame rate and performs protocol conversion; The video encoding module performs IPMX protocol encapsulation on the data converted by the delay switching module protocol.

4. The low-latency video protocol conversion method according to claim 3, wherein: The synchronization processing module converts the frame rate obtained from the cache module into a unified frame time statistical standard, compensates the local working clock, calculates the frequency deviation value and completes frequency deviation tracking, including: The frame rate counter synchronously converts the frame rate obtained from the cache module into a 90kHz pulse statistical count; The synchronizer locks and decodes the parameter information in the stable state and calculates the frequency offset FO at the current frame moment; The synchronous tracker calculates the window-type frequency offset FO and the cumulative frequency offset FO; The synchronous regulator calculates the frequency offset compensation FO' and completes the frequency offset tracking.

5. The low-latency video protocol conversion method according to claim 4, wherein: The synchronizer locks and decodes parameter information in a stable state, and calculates the frequency offset FO at the current frame time, including: fcw_90k = 2^32*(1800 / sys_clk_cnt); local_90k_cnt = (FT i – FT0) * fcw_90k; local_90k_cnt ≈ i*1800; FO = local_90k_cnt / (i*1800); Among them, fcw_90k represents the frequency control word of 90khz, sys_clk_cnt represents the frequency value converted from the system clock, local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

6. The low-latency video protocol conversion method according to claim 4, wherein: The synchronous regulator calculates the frequency offset compensation FO' to complete the frequency offset tracking, including: fcw_90k' = 2^32*(1800 / sys_clk_cnt'); local_90k_cnt' = (FT i – FT0) * fcw_90k'; FO' = local_90k_cnt' / (i*1800), Among them, fcw_90k' represents the control word generated by the adjusted clock according to the frequency of 90khz, sys_clk_cnt' represents the frequency value converted to the adjusted system clock, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, FT i Indicates the current frame time, FT0 indicates the initial frame time, and i indicates the frame count.

7. The low-latency video protocol conversion method according to claim 3, wherein: The low-latency switching module adjusts the data extraction strategy according to the frame rate and performs protocol conversion, including: The frame pulse detector monitors the frame pulse before decoding and detects the video frame after decoding, and outputs the locking state of the continuously and stably detected frame pulse to the subsequent module for reference; The time delay adder adds a time delay according to the arrival time of the frame pulse to control the acquisition of frame data of the start conversion protocol; The cache monitoring module outputs data while decoding the frame data, and feeds back the changes in the row address to the FO adjustment; The frame address adjustment module detects the jitter of the frame data before decoding to adjust the delayed output.

8. The low-latency video protocol conversion method according to claim 7, wherein: The frame address adjustment module detects jitter of the frame data before decoding to adjust the delayed output, including: When jitter is too large and FO' cannot keep up quickly, the adjustment range of frame delay is increased using the following formula: frame overlap = |local_90k_cnt' - local_90k_cnt| / 1800; When FO' ≈ FO and remains stable, the synchronization relationship is re-established and the frame address is adjusted using the following formula: local_90k_cnt' = local_90k_cnt' ± 1800; Among them, local_90k_cnt' represents the number of 90k pulses contained in the interval between two adjacent frames after the clock is adjusted, and local_90k_cnt represents the number of 90k pulses contained in the interval between two adjacent frames.

9. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the low-latency video protocol conversion method according to any one of claims 3 to 8 is implemented.

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