A signal measurement method, apparatus, device, medium, and product

Abstract

Embodiments of the present application disclose a signal measurement method, device, equipment, medium and product. According to first address information of each power supply controller connected by an SVID bus, a capture trigger condition of a target signal is set for each power supply controller. In a signal measurement process, second address information carried by each target signal transmitted by the SVID bus is detected. Whether the second address information meets the capture trigger condition corresponding to the target power supply controller is judged, and a target signal or a signal group in which the target signal is located, which meets the capture trigger condition, is captured. Therefore, correct capture of a signal corresponding to each power supply controller can be realized based on address information, and missing or wrong measurement of the signal corresponding to the power supply controller can be avoided, and thus signal quality problems can be found in time.

Description

Technical Field

[0001] This application relates to the field of power management technology, and in particular to a signal measurement method, apparatus, device, medium, and product. Background Technology

[0002] The SVID (Serial Voltage Identification) bus is used to control power management transmission between the CPU and power controller on Intel platforms. Its main purpose is to accurately and dynamically adjust the CPU voltage. Each CPU can communicate with multiple power controllers through the SVID bus.

[0003] When measuring the signals transmitted on the SVID bus, the oscilloscope probes are used to directly measure all the signals currently transmitted on the clock and data lines of the SVID bus. This fuzzy measurement method may lead to missing or incorrect measurement of the signal corresponding to a certain power controller. Summary of the Invention

[0004] The purpose of this application is to provide a signal measurement method, apparatus, device, medium, and product that can avoid missing or incorrect measurement of signals corresponding to the power controller.

[0005] To address the aforementioned technical problems, in a first aspect, embodiments of this application provide a signal measurement method, the method comprising:

[0006] Determine the first address information of each of the multiple power controllers connected by the series voltage identification mode (SVID) bus;

[0007] Based on each of the first address information, the capture trigger conditions for the target signal corresponding to each of the plurality of power controllers are set;

[0008] Detect the second address information carried by each target signal transmitted in the SVID bus;

[0009] The target signal whose second address information matches the capture trigger condition of the target power controller is captured to obtain the target signal or the signal group associated with the target power controller. The target power controller is any one of the plurality of power controllers.

[0010] Optionally, detecting the second address information carried by each target signal transmitted in the SVID bus includes:

[0011] A first detection point is set at the first target end corresponding to the SVID bus, where the first target end is the plurality of power controllers or the CPU connected to the SVID bus.

[0012] At the first detection point, the first N bits of each target signal are acquired, where N is the set target bit number;

[0013] Based on the values ​​of the first N bits, the second address information carried by each target signal is determined.

[0014] Optionally, before acquiring the first N bits of each target signal at the first detection point, the method further includes:

[0015] The target bit count is determined based on the number of start bits and the number of address bits of a single target signal.

[0016] Optionally, before setting the first detection point at the first target end of the SVID bus, the method further includes:

[0017] When the CPU drives the plurality of power controllers, the first target terminal is determined to be the plurality of power controllers;

[0018] When the CPU is driven by the plurality of power controllers, the first target terminal is identified as the CPU.

[0019] Optionally, the method further includes:

[0020] A second detection point is set at the second target end corresponding to the SVID bus, and a third detection point is set at the third target end corresponding to the SVID bus. The second target end is the CPU, and the third target end is the plurality of power controllers.

[0021] The receiver and transmitter of each signal are determined based on the time when each signal in the signal group associated with any of the target signals arrives at the second detection point and the third detection point, respectively.

[0022] Optionally, determining the receiver and transmitter of each signal based on the arrival times of each signal in the signal group associated with any of the target signals at the second detection point and the third detection point respectively includes:

[0023] For each signal whose arrival time at the second detection point is less than the arrival time at the third detection point, the transmitting end of each signal is determined to be the CPU, and the receiving end of each signal is determined to be the power controller corresponding to the associated target signal.

[0024] For each signal whose arrival time at the second detection point is greater than its arrival time at the third detection point, the receiving end of each signal is determined to be the CPU, and the sending end of each signal is determined to be the power controller corresponding to the associated target signal.

[0025] Optionally, before determining the receiving end and transmitting end of each signal based on the arrival times of each signal in the signal group associated with any of the target signals at the second detection point and the third detection point, the method further includes:

[0026] At the second detection point, the waveform of each signal transmitted by the SVID bus and the clock signal corresponding to each signal are acquired, and at the third detection point, the waveform of each signal and the clock signal corresponding to each signal are acquired.

[0027] Based on the waveform of each signal simultaneously acquired at the second and third detection points, and the clock signal corresponding to each signal, the time when each signal arrives at the second and third detection points is determined.

[0028] Secondly, embodiments of this application also provide a signal measurement device, the device comprising:

[0029] The first processing module is used to determine the first address information of each of the multiple power controllers connected by the series voltage identification mode SVID bus.

[0030] The second processing module is used to set the capture trigger conditions for the target signals corresponding to each of the plurality of power controllers according to the first address information.

[0031] The information detection module is used to detect the second address information carried by each target signal transmitted in the SVID bus;

[0032] The signal acquisition module is used to acquire the target signal whose second address information matches the acquisition trigger condition of the target power controller, and obtain the target signal or the signal group associated with the target power controller, wherein the target power controller is any one of the plurality of power controllers.

[0033] Thirdly, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the signal measurement method as described in the first aspect.

[0034] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implements the signal measurement method as described in the first aspect.

[0035] Fifthly, embodiments of this application also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the signal measurement method described in the first aspect.

[0036] As can be seen from the above technical solution, based on the first address information of each power controller connected by the SVID bus, the capture trigger conditions for the target signal are set for each power controller. During the signal measurement process, the second address information carried by each target signal transmitted by the SVID bus is detected. By judging whether the second address information meets the capture trigger conditions corresponding to the target power controller, the target signal or the signal group to which the target signal is located is captured if the second address information meets the capture trigger conditions. Thus, the correct capture of the signal corresponding to each power controller can be achieved based on the address information, which can avoid missing or incorrect measurement of the signal corresponding to the power controller, and thus timely detection of signal quality problems. Attached Figure Description

[0037] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating the implementation of a signal measurement method provided in this application embodiment;

[0039] Figure 2 A schematic diagram illustrating specific implementation steps for capturing a target signal, provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram illustrating specific implementation steps for distinguishing read and write signals in a signal group, as provided in an embodiment of this application.

[0041] Figure 4 This is a schematic diagram of the structure of a signal measurement device provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0044] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0045] Physically, SVID is a 3-wire interface. The SVID bus contains three signal lines: a clock line (one-way transmission signal), a data line (two-way transmission signal), and an alarm line (one-way transmission signal). This bus is used to control power management transmission between the CPU and the power controller (such as the VRM (Voltage Regulator Module) chip) on the Intel platform, with the main purpose of precisely and dynamically adjusting the CPU voltage.

[0046] Each CPU can communicate with multiple VRM chips via the SVID bus to control the VCore (Voltage Core) and DIMM (Dual-Inline Memory Modules) voltages. For example, when the CPU drives the VRM chip to adjust the CPU voltage, the CPU sends a call to the VRM chip using the data and clock lines of the SVID bus based on the VRM chip's address, waiting for the VRM chip to read the voltage setting information sent by the CPU. When the VRM chip responds to the call from the SVID module within the CPU and reads the voltage setting information, the CPU's main power supply VCORE (Voltage Core voltage) is generated, and then the number of phases of the PWM (Pulse Width Modulation) power supply is adjusted according to the CPU voltage.

[0047] Currently, when performing signal measurements, oscilloscope probes are used to directly measure the signals on the data lines and clock lines connected to multiple VRM chips. This fuzzy measurement method cannot distinguish the VRM chip associated with the signal, which means that the signal measured for a certain VRM chip may not be the signal that the VRM chip is communicating with the CPU. This can lead to missed or incorrect measurements of the corresponding signals of multiple VRM chips when performing signal measurements on multiple VRM chips, resulting in signal quality problems not being detected in time.

[0048] To address the problems existing in the aforementioned related technologies, this application sets the capture trigger conditions based on address information, thereby distinguishing the signals corresponding to each VRM chip during the signal capture stage, and accurately capturing the signals corresponding to each VRM chip based on the address information of each VRM chip, avoiding signal omissions and mismeasurements, and thus improving the accuracy of signal measurement.

[0049] The signal measurement method provided in this application will be described in detail below with reference to the accompanying drawings, through some embodiments and application scenarios.

[0050] Firstly, see [the following] Figure 1 The diagram shown is an implementation flowchart of a signal measurement method provided in this application embodiment. The method may include the following steps:

[0051] Step S101: Determine the first address information of each of the multiple power controllers connected by the Series Voltage Identification Mode (SVID) bus.

[0052] In practice, for multiple power controllers connected to the same SVID bus, each power controller is assigned a unique SVID bus name and address value. By using the address values ​​of each power controller as its own first address information, the power controllers can be distinguished based on this first address information.

[0053] For example, the bus name and address value of the power controller can be set according to Table 1 as shown below, where SVID Bus1 and SVID Bus2 are the SVID bus names under different setting types, VR Address is the address value of the power controller, and h represents hexadecimal.

[0054] VCCIN VDDQ1 00h VSA NA 01h VCCIO VDDQ2 02h VCCMCP NA 03h

[0055] Table 1

[0056] Step S102: Based on each of the first address information, set the capture trigger conditions for the target signals corresponding to the plurality of power controllers.

[0057] The capture trigger condition set according to the first address information is used to trigger the capture action on the signal carrying the first address information, which can avoid capturing signals carrying other address information, thereby distinguishing the signals corresponding to each power controller during the signal capture stage; the target signal corresponding to a certain power controller can be the first signal transmitted on the data line when the CPU communicates with the power controller (i.e., the signal carrying address information).

[0058] In practical implementation, the above-mentioned capture trigger condition can be set to trigger capture on a signal carrying the first address information. For example, for two power controllers connected to the same SVID bus, one power controller's SVID bus name and address value are set to VCCIN and 00h, and the other power controller's SVID bus name and address value are set to VSA and 01h. Then, during the communication between the CPU and VCCIN, the corresponding target signal transmitted on the data line will carry the address information of 00h, while during the communication between the CPU and VCCIN, the corresponding target signal transmitted on the data line will carry the address information of 01h.

[0059] It is understandable that during the simultaneous communication between the CPU and VCCIN and VSA, if the signal on the data line is directly measured with an oscilloscope probe at VCCIN or VSA, a combination of the target signals corresponding to VCCIN and VSA will be captured. The captured signal needs to be split and processed before the power management data carried by the target signals corresponding to VCCIN and VSA can be read. Conversely, during the communication between the CPU and VCCIN, if the signal on the data line is directly measured with an oscilloscope probe at VSA, the target signal corresponding to VCCIN will be captured, potentially leading to incorrect or missed measurements of the target signal corresponding to VSA. Therefore, this application sets capture trigger conditions for VCCIN and VSA based on their respective first address information (00h and 01h), thereby triggering capture actions for the target signals carrying address information 00h and 01h on the data lines, thus completing the capture of the target signal corresponding to each power controller and ensuring correct signal measurement.

[0060] Step S103: Detect the second address information carried by each target signal transmitted in the SVID bus.

[0061] The second address information can be the address value of the power controller (i.e., the first address information mentioned above). When the start bit information of each target signal is fixed (e.g., all are 010), the second address information can also be a combination of the start bit information and the address value of the power controller. For example, when the start bit information is fixed at 010, the second address information carried by the target signal corresponding to VCCIN can be represented as 01000h.

[0062] Step S104: Capture the target signal whose second address information matches the capture trigger condition of the target power controller to obtain the target signal or the signal group associated with the target signal, wherein the target power controller is any one of the plurality of power controllers.

[0063] In practice, the second address information carried by each target signal transmitted on the data line is read, and it is detected whether the second address information meets the capture trigger condition corresponding to the target power controller. If the second address information meets the capture trigger condition, the target signal carrying the second address information is captured, thereby achieving accurate capture of the target signal corresponding to the target power controller.

[0064] As can be seen from the above technical solution, based on the first address information of each power controller connected by the SVID bus, the capture trigger conditions for the target signal are set for each power controller. During the signal measurement process, the second address information carried by each target signal transmitted by the SVID bus is detected. By judging whether the second address information meets the capture trigger conditions corresponding to the target power controller, the target signal or the signal group to which the target signal is located is captured if the second address information meets the capture trigger conditions. Thus, the correct capture of the signal corresponding to each power controller can be achieved based on the address information, which can avoid missing or incorrect measurement of the signal corresponding to the power controller, and thus timely detection of signal quality problems.

[0065] Example 1

[0066] This embodiment describes specific implementation steps for capturing target signals. For example... Figure 2 As shown, the specific implementation steps include:

[0067] Step S201: Set a first detection point at the first target end corresponding to the SVID bus, wherein the first target end is the plurality of power controllers or the CPU connected to the SVID bus.

[0068] In practical implementation, when the first target end consists of multiple power controllers, a first detection point can be set at a location close to the multiple power controllers on the SVID bus, or a first detection point can be set at each power controller, and the target signal of the corresponding power controller can be captured at each first detection point. The first target end can be the transmitting end of the currently measured target signal, so as to correctly read the target signal according to the signal transmission timing during communication between the receiving end and the transmitting end.

[0069] In one possible implementation, when the CPU drives the plurality of power controllers, the first target end is determined to be the plurality of power controllers; when the plurality of power controllers drive the CPU, the first target end is determined to be the CPU. It is understood that when the CPU drives the plurality of power controllers, the CPU first initiates a call and sends data to each power controller, and each power controller then provides feedback based on the received data. Therefore, the target signal carrying address information is issued by the CPU and received by the power controller. By determining the first target end to the plurality of power controllers, it can be ensured that the first signal captured at the first detection point is the target signal corresponding to the power controller, rather than a feedback signal issued by that power controller. Similarly, when the power controller drives the CPU, the target signal carrying address information is issued by the power controller and received by the CPU. By determining the first target end to the CPU, it can be ensured that the first signal captured at the first detection point is the target signal corresponding to the power controller, rather than a feedback signal issued by the CPU to that power controller.

[0070] Step S202: At the first detection point, obtain the first N bits of each target signal, where N is the set target bit number.

[0071] In practical implementation, after connecting the data line and clock line in the SVID bus to the oscilloscope, since each signal group measured by the oscilloscope is mainly composed of the target signal and the feedback signal of the target signal, the oscilloscope can automatically read the first N bits of different signal groups to automatically obtain the first N bits of each target signal.

[0072] Step S203: Determine the second address information carried by each target signal based on the value of each of the first N bits.

[0073] It is understood that the first N bits should at least include the address value of the power controller carried by the target signal, so that the capture action can be triggered subsequently based on the second address information determined by the N bits. As one possible implementation, the target bit number can be determined based on the number of start bits and the number of address bits of a single target signal. Considering that the first two fields of the target signal are usually a start bit (whose corresponding start bit information is usually fixed at 010, with a bit number of 3) and an address bit (whose corresponding power controller address value, with a bit number of 4), the target bit number N can be set to 7, so that the combination of the 7 bits of start bit information and address information read is used as the second address information.

[0074] Step S204: Capture the target signal whose second address information matches the capture trigger condition of the target power controller to obtain the target signal corresponding to the target power controller or the signal group associated with the target signal.

[0075] In practical implementation, an oscilloscope can be used to directly capture the signal group (composed of the target signal and the corresponding feedback signal) associated with the target signal that meets the capture trigger condition and carries the second address information. This allows for the capture of all signals transmitted on the SVID bus during a single communication between the CPU and the corresponding power controller, thereby improving signal capture efficiency.

[0076] Example 2

[0077] This embodiment describes the specific implementation steps for distinguishing read and write signals in a signal group corresponding to a target signal. This application, by acquiring the arrival times of each signal in a signal group at the power controller and CPU, can distinguish between read and write operations for each signal in the signal group, thereby achieving accurate measurement of each signal in the signal group. For example... Figure 3 As shown, the specific implementation steps include:

[0078] Step S301: Set a second detection point at the second target end corresponding to the SVID bus, and set a third detection point at the third target end corresponding to the SVID bus. The second target end is the CPU, and the third target end is the plurality of power controllers.

[0079] In practical implementation, since the signals are transmitted bidirectionally on the data lines of the SVID bus (i.e., a group of signals will include write signals and read signals), in order to ensure the accuracy of signal measurement, detection points can be set at the CPU end and the power controller end to perform signal measurement, thereby distinguishing the read and write of each signal in the signal group.

[0080] Step S302: Determine the receiving end and transmitting end of each signal based on the time when each signal in the signal group associated with any of the target signals arrives at the second detection point and the third detection point respectively.

[0081] In practice, an oscilloscope probe can be used to simultaneously detect the signals on the data line and the clock line at the second and third detection points. Based on the detected data and clock signals, the arrival times of the same set of signals at the second and third detection points can be determined.

[0082] As one possible implementation, the waveform of each signal transmitted via the SVID bus and the corresponding clock signal are acquired at the second detection point, and simultaneously, the waveform of each signal and the corresponding clock signal are acquired at the third detection point. Based on the waveforms of each signal and the corresponding clock signals acquired simultaneously at the second and third detection points, the arrival times of each signal at the second and third detection points are determined. It is understood that by comparing the signal waveforms detected at the second and third detection points, the clock signals corresponding to each signal waveform detected at the second and third detection points can be matched, thereby determining the arrival times of the same signal waveform at the second and third detection points based on the clock signals.

[0083] Specifically, for each signal whose arrival time at the second detection point is less than its arrival time at the third detection point, the transmitting end of each signal is identified as the CPU, and the receiving end of each signal is identified as the power controller corresponding to the associated target signal. Similarly, for each signal whose arrival time at the second detection point is greater than its arrival time at the third detection point, the receiving end of each signal is identified as the CPU, and the transmitting end of each signal is identified as the power controller corresponding to the associated target signal. It can be understood that the signal emitted by the transmitting end can be called the writing signal of the transmitting end, and the signal emitted by the receiving end can be called the reading signal of the receiving end. That is to say, the read and write signals of the transmitting or receiving end are determined based on the read and write operations performed by the transmitting or receiving end on the signal. Therefore, by determining the receiving and transmitting ends of each signal, the corresponding read and write signals of the CPU and power controller can be quickly determined when performing signal measurements on them respectively.

[0084] It is understandable that by correctly capturing and distinguishing the signals of each power controller, the accuracy of power management-related tests such as signal quality testing and power supply debugging can be effectively improved. For example, when configuring the instructions to be sent by the CPU, the CPU and VRM chips are connected to the clock line, alarm line, and data line of the SVID bus, respectively. The CPU sends control instructions to multiple VRM chips. At this time, the signal capture method described in Implementation Method 1 can be used to capture the signal groups carrying control instructions corresponding to each VRM chip in the SVID bus. By distinguishing the reading and writing of signals, the control instructions issued by the CPU to each VRM chip and the feedback signals issued by the VRM chips to the control instructions can be quickly determined from the signal groups, so that technicians can analyze and debug them.

[0085] Secondly, embodiments of this application provide a signal measurement device, such as... Figure 4 As shown, the device includes:

[0086] The first processing module 21 is used to determine the first address information of each of the multiple power controllers connected by the series voltage identification mode SVID bus;

[0087] In this way, the address value of each power controller can be set as the first address information of each power controller, so as to distinguish each power controller according to the first address information.

[0088] The second processing module 22 is used to set the capture trigger conditions for the target signals corresponding to each of the plurality of power controllers according to the first address information.

[0089] The capture trigger condition is used to trigger a capture action on a signal carrying the first address information, which can prevent the capture of signals carrying other address information, thereby distinguishing the signals corresponding to each power controller during the signal capture phase. The target signal corresponding to a certain power controller can be the first signal transmitted on the data line when the CPU communicates with that power controller (i.e., the signal carrying address information).

[0090] Information detection module 23 is used to detect the second address information carried by each target signal transmitted in the SVID bus;

[0091] The second address information can be the address value of the power controller (i.e., the first address information mentioned above). When the start bit information of each target signal is fixed (e.g., all are 010), the second address information can also be a combination of the start bit information and the address value of the power controller. For example, when the start bit information is fixed at 010, the second address information carried by the target signal corresponding to VCCIN can be represented as 01000h.

[0092] The signal acquisition module 24 is used to acquire the target signal whose second address information matches the acquisition trigger condition of the target power controller, and obtain the target signal or the signal group associated with the target power controller, wherein the target power controller is any one of the plurality of power controllers.

[0093] Specifically, by reading the second address information carried by each target signal transmitted on the data line and detecting whether the second address information meets the capture trigger condition corresponding to the target power controller, and capturing the target signal carrying the second address information when the second address information meets the capture trigger condition, accurate capture of the target signal corresponding to the target power controller can be achieved. Furthermore, the signal group (composed of the target signal and the corresponding feedback signal) associated with the target signal whose second address information meets the capture trigger condition is directly captured. Thus, during a single communication between the CPU and the corresponding power controller, all signals transmitted on the SVID bus can be captured, thereby improving signal capture efficiency.

[0094] Optionally, the information detection module 23 includes:

[0095] The first detection submodule is used to set a first detection point at the first target end corresponding to the SVID bus, wherein the first target end is the plurality of power controllers or the CPU connected to the SVID bus.

[0096] The second detection submodule is used to acquire the first N bits of each target signal at the first detection point, where N is the set number of target bits;

[0097] The third detection submodule is used to determine the second address information carried by each target signal based on the value of each of the first N bits.

[0098] Optionally, before acquiring the first N bits of each target signal at the first detection point, the device further includes:

[0099] The third processing module is used to determine the target number of bits based on the number of bits in the start bit and the number of bits in the address bit of a single target signal.

[0100] Optionally, before setting the first detection point at the first target end of the SVID bus, the device further includes:

[0101] The fourth processing module is used to determine the first target terminal as the plurality of power controllers when the CPU drives the plurality of power controllers.

[0102] The fifth processing module is used to identify the first target terminal as the CPU when the CPU is driven by the plurality of power controllers.

[0103] Optionally, the device further includes:

[0104] The sixth processing module is used to set a second detection point at the second target end corresponding to the SVID bus and a third detection point at the third target end corresponding to the SVID bus, wherein the second target end is the CPU and the third target end is the plurality of power controllers;

[0105] The seventh processing module is used to determine the receiving end and transmitting end of each signal based on the time when each signal in the signal group associated with any of the target signals arrives at the second detection point and the third detection point, respectively.

[0106] Optionally, the seventh processing module includes:

[0107] The first processing submodule is used to determine the sending end of each signal as the CPU and the receiving end of each signal as the power controller corresponding to the associated target signal for each signal whose arrival time at the second detection point is less than the arrival time at the third detection point.

[0108] The second processing submodule is used to determine the CPU as the receiving end of each signal and the power controller corresponding to the associated target signal for each signal whose arrival time at the second detection point is greater than the arrival time at the third detection point.

[0109] Optionally, before determining the receiving end and transmitting end of each signal based on the arrival times of each signal in the signal group associated with any of the target signals at the second detection point and the third detection point, the device further includes:

[0110] The eighth processing module is used to acquire the waveform of each signal transmitted by the SVID bus and the clock signal corresponding to each signal at the second detection point, and at the third detection point to acquire the waveform of each signal and the clock signal corresponding to each signal.

[0111] The ninth processing module is used to determine the time when each signal arrives at the second detection point and the third detection point, respectively, based on the waveform of each signal simultaneously acquired at the second detection point and the third detection point, and the clock signal corresponding to each signal.

[0112] As can be seen from the above technical solution, based on the first address information of each power controller connected by the SVID bus, the capture trigger conditions for the target signal are set for each power controller. During the signal measurement process, the second address information carried by each target signal transmitted by the SVID bus is detected. By judging whether the second address information meets the capture trigger conditions corresponding to the target power controller, the target signal or the signal group to which the target signal is located is captured if the second address information meets the capture trigger conditions. Thus, the correct capture of the signal corresponding to each power controller can be achieved based on the address information, which can avoid missing or incorrect measurement of the signal corresponding to the power controller, and thus timely detection of signal quality problems.

[0113] It should be noted that the device embodiments are similar to the method embodiments, so the description is relatively simple. For relevant details, please refer to the method embodiments.

[0114] This application also provides an electronic device, see embodiments thereof. Figure 5 , Figure 5 This is a schematic diagram of the electronic device proposed in an embodiment of this application. Figure 5 As shown, the electronic device 100 includes a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus for communication. The memory 110 stores a computer program that can run on the processor 120 to implement the steps in the signal measurement method disclosed in the embodiments of this application.

[0115] This application also provides a computer-readable storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements the signal measurement method disclosed in this application.

[0116] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the signal measurement method disclosed in this application.

[0117] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0118] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0119] This application describes embodiments of methods, systems, devices, storage media, and program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0120] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0122] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0123] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0124] The above provides a detailed description of a signal measurement method, apparatus, device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A signal measurement method, characterized in that, The method includes: Determine the first address information of each of the multiple power controllers connected by the series voltage identification mode (SVID) bus; Based on each of the first address information, the capture trigger conditions for the target signal corresponding to each of the plurality of power controllers are set; Detect the second address information carried by each target signal transmitted in the SVID bus; The target signal whose second address information matches the capture trigger condition of the target power controller is captured to obtain the target signal or the signal group associated with the target signal, wherein the target power controller is any one of the plurality of power controllers; The detection of the second address information carried by each target signal transmitted in the SVID bus includes: A first detection point is set at the first target end corresponding to the SVID bus, where the first target end is the plurality of power controllers or the CPU connected to the SVID bus. At the first detection point, the first N bits of each target signal are acquired, where N is the set target bit number; Based on the values ​​of the first N bits, the second address information carried by each target signal is determined. Before setting the first detection point at the first target end of the SVID bus, the method further includes: When the CPU drives the plurality of power controllers, the first target terminal is determined to be the plurality of power controllers; When the CPU is driven by the plurality of power controllers, the first target terminal is identified as the CPU.

2. The method according to claim 1, characterized in that, Before acquiring the first N bits of each target signal at the first detection point, the method further includes: The target bit count is determined based on the number of start bits and the number of address bits of a single target signal.

3. The method according to any one of claims 1-2, characterized in that, The method further includes: A second detection point is set at the second target end corresponding to the SVID bus, and a third detection point is set at the third target end corresponding to the SVID bus. The second target end is the CPU, and the third target end is the plurality of power controllers. The receiver and transmitter of each signal are determined based on the time when each signal in the signal group associated with any of the target signals arrives at the second detection point and the third detection point, respectively.

4. The method according to claim 3, characterized in that, The step of determining the receiver and transmitter of each signal based on the arrival times of each signal in the signal group associated with any of the target signals at the second detection point and the third detection point, respectively, includes: For each signal whose arrival time at the second detection point is less than the arrival time at the third detection point, the transmitting end of each signal is determined to be the CPU, and the receiving end of each signal is determined to be the power controller corresponding to the associated target signal. For each signal whose arrival time at the second detection point is greater than its arrival time at the third detection point, the receiving end of each signal is determined to be the CPU, and the sending end of each signal is determined to be the power controller corresponding to the associated target signal.

5. The method according to claim 3, characterized in that, Before determining the receiving end and transmitting end of each signal based on the arrival times of each signal in the signal group associated with any of the target signals at the second detection point and the third detection point, the method further includes: At the second detection point, the waveform of each signal transmitted by the SVID bus and the clock signal corresponding to each signal are acquired, and at the third detection point, the waveform of each signal and the clock signal corresponding to each signal are acquired. Based on the waveform of each signal simultaneously acquired at the second and third detection points, and the clock signal corresponding to each signal, the time when each signal arrives at the second and third detection points is determined.

6. A signal measurement device, characterized in that, The device includes: The first processing module is used to determine the first address information of each of the multiple power controllers connected by the series voltage identification mode SVID bus. The second processing module is used to set the capture trigger conditions for the target signals corresponding to each of the plurality of power controllers according to the first address information. The information detection module is used to detect the second address information carried by each target signal transmitted in the SVID bus; The signal acquisition module is used to capture the target signal whose second address information matches the capture trigger condition of the target power controller, and obtain the target signal or the signal group associated with the target power controller, wherein the target power controller is any one of the plurality of power controllers. The information detection module includes: The first detection submodule is used to set a first detection point at the first target end corresponding to the SVID bus, wherein the first target end is the plurality of power controllers or the CPU connected to the SVID bus. The second detection submodule is used to acquire the first N bits of each target signal at the first detection point, where N is the set number of target bits; The third detection submodule is used to determine the second address information carried by each target signal based on the value of each of the first N bits. Before setting the first detection point at the first target end of the SVID bus, the device further includes: The fourth processing module is used to determine the first target terminal as the plurality of power controllers when the CPU drives the plurality of power controllers. The fifth processing module is used to identify the first target terminal as the CPU when the CPU is driven by the plurality of power controllers.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the signal measurement method as described in any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instruction is executed by the processor, it implements the signal measurement method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the signal measurement method as described in any one of claims 1 to 5.

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