True random number generator

Abstract

A true random number generator comprises: noise source circuit, first amplifier, first direct current isolation circuit, first direct current bias circuit, second amplifier, second direct current isolation circuit, second direct current bias circuit and latch connected in sequence; the noise source circuit is arranged to generate two independent noise signals; the first amplifier is arranged to amplify the two independent noise signals respectively; the first direct current isolation circuit is arranged to isolate direct current signal; the first direct current bias circuit is arranged to provide direct current bias for the second amplifier; the second amplifier is arranged to amplify the two independent noise signals amplified again; the second direct current isolation circuit is arranged to isolate direct current signal; the second direct current bias circuit is arranged to provide direct current bias for the latch; the latch is arranged to judge the size of the signal input from the second direct current isolation circuit, and output true random number according to the judgment result.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit design techniques, and in particular to a true random number generator. BACKGROUND

[0002] Random number generators are divided into "true" or "pseudo" random number generators. True random number generators extract randomness from the physical environment, and the generated sequence has independence and unpredictability. True random numbers are widely used in cryptography, and are of great significance to the security of cryptographic systems.

[0003] In the design and implementation of true random numbers, methods such as directly amplifying the noise source, oscillator sampling, and discrete-time chaos-based methods are generally used. The most widely used is the true random number generator based on oscillator sampling, which samples a relatively constant fast oscillation signal through a flip-flop by using a slow oscillation signal containing random jitter, to obtain a true random sequence. This method requires the slow oscillation signal to have sufficient phase noise, and has high requirements for the oscillation frequency and duty cycle of the high-frequency oscillator. The method of directly amplifying the noise source requires a high-gain, high-bandwidth amplifier to amplify the signal, and a comparator to compare the noise signal with a reference voltage to output a true random number sequence.

[0004] Figure 1 A true random number generator based on the method of directly amplifying the noise source is shown. The problems that need to be overcome in this method are the reference voltage of the comparator and the input offset of the comparator. The high and low of the reference voltage and the input offset of the comparator affect the threshold of the comparator flip-flop, which directly affects the randomness of the true random number. If the settings are not reasonable, the true random number generator may not even work.

[0005] The existing technology provides a suitable reference voltage for the comparator through a low-pass filter or a feedback loop. The low-pass filter has a large area and causes the two ends of the comparator to be mismatched, which is easily affected by common-mode interference. Adjusting the reference voltage of the comparator through a feedback loop increases the complexity of the circuit.

[0006] Figure 2 In the proximity scheme, the signal output by the bias circuit is sent to the positive input and negative input of the comparator at the same time. The comparator works in a common-mode amplification state, and the noise output by the bias circuit and the noise at the input of the comparator are amplified by the first stage of the comparator, and then sent to the second stage (D2S) of the comparator for further amplification, and then sent to the slicer circuit in the later stage for judgment. The slicer circuit will determine the high and low of the signal according to its own flip-flop point, and then sample the output signal of the slicer circuit through a D flip-flop to obtain a random number sequence.

[0007] The scheme solves the reference voltage problem of the comparator, because the bias voltage is simultaneously sent to the positive and negative terminals of the comparator, and the reference voltage is no longer needed to be provided. However, if there is a deviation in the first stage input tube of the comparator, the output DC level of the second stage (D2S) of the comparator will change high and low, and the flipping point of the Slicer is fixed, thereby causing the proportion of logic 1 and logic 0 of the output result to deviate, and affecting the randomness. SUMMARY

[0008] The application provides a true random number generator, which can realize a true random number generator with small circuit area, simple circuit and without subsequent circuit adjustment.

[0009] The application provides a true random number generator, which comprises:

[0010] The noise source circuit, the first amplifier, the first direct current isolation circuit, the first direct current bias circuit, the second amplifier, the second direct current isolation circuit, the second direct current bias circuit and the latch are sequentially connected.

[0011] The noise source circuit is configured to generate two independent noise signals.

[0012] The first amplifier is configured to amplify the two independent noise signals respectively.

[0013] The first direct current isolation circuit is configured to isolate the direct current signals in the amplified two independent noise signals.

[0014] The first direct current bias circuit is configured to provide direct current bias for the second amplifier.

[0015] The second amplifier is configured to amplify the two independent noise signals after isolation and amplification again.

[0016] The second direct current isolation circuit is configured to isolate the direct current signals in the signals amplified by the second amplifier.

[0017] The second direct current bias circuit is configured to provide direct current bias for the latch.

[0018] The latch is configured to judge the size of the signals input from the second direct current isolation circuit and output true random numbers.

[0019] In an exemplary embodiment, the noise source circuit comprises a first bias power supply, a first resistor and a second resistor.

[0020] The first bias power supply is connected with the first end of the first resistor and the first end of the second resistor respectively.

[0021] The second end of the first resistor and the second end of the second resistor are respectively an output terminal of the noise source circuit.

[0022] In an exemplary embodiment, the first amplifier and the second amplifier have the same circuit structure; each amplifier comprises a VDD power supply, a second bias power supply, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor.

[0023] The VDD power supply is connected to the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor, respectively; the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor; the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the second PMOS transistor is connected to the gate of the third PMOS transistor; the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, which are collectively a first output terminal of the amplifier; the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, which are collectively a second output terminal of the amplifier;

[0024] The drain of the second PMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor and the source of the second NMOS transistor are respectively connected to the drain of the first NMOS transistor; the gate of the third NMOS transistor is a first input terminal of the amplifier; the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor; the gate of the second NMOS transistor is a second input terminal of the amplifier; the source of the first NMOS transistor is grounded; and the gate of the first NMOS transistor is connected to the second bias power supply.

[0025] In an exemplary embodiment, the latch comprises a VDD power supply, a control clock, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and an RS flip-flop.

[0026] The VDD power supply is connected with the source of the fifth PMOS, the source of the sixth PMOS, the source of the seventh PMOS and the source of the eighth PMOS respectively; the gate of the fifth PMOS is connected with the control clock; the gate of the sixth PMOS is connected with the drain of the seventh PMOS and the gate of the seventh NMOS respectively; the drain of the sixth PMOS is connected with the gate of the seventh PMOS and the drain of the seventh NMOS respectively; the drain of the fifth PMOS and the drain of the sixth PMOS are connected as the first input end of the RS flip-flop; the gate of the eighth PMOS is connected with the control clock; the drain of the eighth PMOS is connected with the drain of the seventh PMOS as the second input end of the RS flip-flop; the source of the seventh NMOS is connected with the drain of the fifth NMOS; the gate of the seventh PMOS is connected with the gate of the eighth NMOS; the drain of the eighth NMOS is connected with the drain of the seventh PMOS;

[0027] The drain of the fifth NMOS is connected with the source of the seventh NMOS; the source of the eighth NMOS and the drain of the sixth NMOS are connected; the gate of the fifth NMOS is the differential signal input end of the amplifier; the source of the fifth NMOS is connected with the source of the sixth NMOS and the drain of the fourth NMOS respectively; the gate of the sixth NMOS is the differential signal input end of the amplifier; the source of the fourth NMOS is grounded; the gate of the fourth NMOS is connected with the control clock;

[0028] The output end of the RS flip-flop is the output end of the amplifier.

[0029] In an exemplary embodiment, the width-length ratio of the second PMOS and the third PMOS is less than the width-length ratio of the first PMOS and the fourth PMOS.

[0030] In an exemplary embodiment, the first direct-current blocking circuit and the second direct-current blocking circuit have the same circuit structure; each direct-current blocking circuit comprises two capacitors; each capacitor is connected with the output of each amplifier one by one.

[0031] In an exemplary embodiment, the first direct-current biasing circuit and the second direct-current biasing circuit have the same circuit structure; each direct-current biasing circuit comprises a third biasing power supply and two resistors;

[0032] The third biasing power supply is connected with the first end of each resistor respectively; the second end of each resistor is connected with one output end of the corresponding direct-current blocking circuit respectively.

[0033] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The advantages of the present application will be realized and attained by the structure particularly pointed out in the description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, but are not intended to limit the application.

[0035] Figure 1 A true random number generator realized by directly amplifying a noise source in the related art;

[0036] Figure 2 Another true random number generator realized by directly amplifying a noise source in the related art;

[0037] Figure 3 A schematic diagram of a true random number generator according to an embodiment of the present application;

[0038] Figure 4 A schematic diagram of another true random number generator according to an embodiment of the present application;

[0039] Figure 5 A schematic diagram of a noise source circuit of the true random number generator shown in Figure 4

[0040] A schematic diagram of an amplifier circuit of the true random number generator shown in Figure 6 Figure 4 A schematic diagram of a latch of the true random number generator shown in

[0041] DETAILED DESCRIPTION Figure 7 Figure 4 A schematic diagram of a true random number generator according to an embodiment of the present application, as shown in

[0042] Figure 3 A schematic diagram of a true random number generator according to an embodiment of the present application, as shown in Figure 3

[0043] The noise source circuit is configured to generate two independent noise signals;

[0044] The first amplifier is configured to amplify the two independent noise signals respectively;

[0045] ​​​The first direct-current isolation circuit is configured to isolate the direct-current signal in the two independent noise signals after amplification.

[0046] The first direct-current bias circuit is configured to provide direct-current bias for the second amplifier.

[0047] The second amplifier is configured to amplify the two independent noise signals after isolation and amplification.

[0048] The second direct-current isolation circuit is configured to isolate the direct-current signal in the signal after amplification by the second amplifier.

[0049] The second direct-current bias circuit is configured to provide direct-current bias for the latch.

[0050] The latch is configured to determine the size of the signal input from the second direct-current isolation circuit and output a true random number according to the determination result.

[0051] For example Figure 4 The true random number generator shown in the figure includes a noise source circuit, a first amplifier, a second amplifier, and a latch. The first amplifier and the second amplifier are ac-coupled through a capacitor (corresponding to the first direct-current isolation circuit described above), the second amplifier and the latch are ac-coupled through a capacitor (corresponding to the second direct-current isolation circuit described above), and are biased through resistors R1_R4 (corresponding to the first direct-current bias circuit and the second direct-current bias circuit described above).

[0052] In an exemplary embodiment, the noise source circuit includes a first bias power supply, a first resistor, and a second resistor.

[0053] The first bias power supply is connected to the first end of the first resistor and the first end of the second resistor, respectively.

[0054] The second end of the first resistor and the second end of the second resistor are output terminals of the noise source circuit, respectively.

[0055] For example Figure 5 The noise source circuit shown in the figure includes resistors R5 and R6 for generating thermal noise, and VCM is a bias voltage provided by an external source, which provides direct-current bias for the first amplifier in the later stage through resistors.

[0056] In an exemplary embodiment, the circuit structure of the first amplifier and the second amplifier is the same. Each amplifier includes a VDD power supply, a second bias power supply, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor.

[0057] The VDD power supply is connected with the source of the first PMOS, the source of the second PMOS, the source of the third PMOS and the source of the fourth PMOS respectively; the gate of the first PMOS is connected with the drain of the first PMOS; the gate of the second PMOS is connected with the drain of the third PMOS; the drain of the second PMOS is connected with the gate of the third PMOS; the drain of the first PMOS is connected with the drain of the second PMOS as the first output end of the amplifier; the gate of the fourth PMOS is connected with the drain of the fourth PMOS; the drain of the fourth PMOS is connected with the drain of the third PMOS as the second output end of the amplifier.

[0058] The drain of the second PMOS is connected with the drain of the third NMOS; the source of the third NMOS and the source of the second NMOS are connected with the drain of the first NMOS respectively; the gate of the third NMOS is the first input end of the amplifier; the drain of the second NMOS is connected with the drain of the third PMOS; the gate of the second NMOS is the second input end of the amplifier; the source of the first NMOS is grounded; the gate of the first NMOS is connected with the second bias power supply.

[0059] For example Figure 6 The amplifier shown includes MN1 (corresponding to the first NMOS above), MN2 (corresponding to the second NMOS above), MN3 (corresponding to the third NMOS above), MP1 (corresponding to the first PMOS above), MP2 (corresponding to the second PMOS above), MP3 (corresponding to the third PMOS above), MP4 (corresponding to the fourth PMOS above), VDD power supply, bias power supply for generating Vbn bias voltage, etc. Figure 6 VIN and VIP are differential input signals, and OUTN and OUTP are differential output signals. MN1 provides bias current, MN2 and MN3 are input tubes, MP1 and MP4 are diode-connected loads, MP2 and MP3 are cross-coupled to form negative resistance for improving the gain of the amplifier.

[0060] The gain of the amplifier is:

[0061]

[0062] For Figure 4The output N1 and N2 of the noise source are connected to the differential input of the first amplifier, and the output OUT1 and OUT2 are obtained after amplification. If there is an input offset voltage of the first amplifier, the DC level of the output OUT1 and OUT2 is not the same. The voltage signals N3 and N4 are obtained by AC coupling through the capacitors C1 and C2 and providing DC bias voltage through the resistors R1 and R2, at this time, N3 and N4 have the same DC level, and the voltage signals N5 and N6 are obtained after amplification by the second amplifier. The voltage signals N5 and N6 are sent to the latch, and the latch judges the size of the signals N5 and N6 and outputs the digital result.

[0063] In an exemplary embodiment, the latch comprises a VDD power supply, a control clock, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and an RS flip-flop;

[0064] The VDD power supply is connected to the source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube, respectively; the gate of the fifth PMOS tube is connected to the control clock; the gate of the sixth PMOS tube is connected to the drain of the seventh PMOS tube and the gate of the seventh NMOS tube, respectively; the drain of the sixth PMOS tube is connected to the gate of the seventh PMOS tube and the drain of the seventh NMOS tube, respectively; the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, which is used as the first input end of the RS flip-flop; the gate of the eighth PMOS tube is connected to the control clock; the drain of the eighth PMOS tube is connected to the drain of the seventh PMOS tube, which is used as the second input end of the RS flip-flop; the source of the seventh NMOS tube is connected to the drain of the fifth NMOS tube; the gate of the seventh PMOS tube is connected to the gate of the eighth NMOS tube; the drain of the eighth NMOS tube is connected to the drain of the seventh PMOS tube;

[0065] The drain of the fifth NMOS tube is connected to the source of the seventh NMOS tube; the source of the eighth NMOS tube is connected to the drain of the sixth NMOS tube; the gate of the fifth NMOS tube is used as the differential signal input end of the amplifier; the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube and the drain of the fourth NMOS tube, respectively; the gate of the sixth NMOS tube is used as the differential signal input end of the amplifier; the source of the fourth NMOS tube is grounded; the gate of the fourth NMOS tube is connected to the control clock;

[0066] The output end of the RS flip-flop is used as the output end of the amplifier.

[0067] For example Figure 7 The latch (which can be a latch of Strong Arm) includes MN4 (corresponding to the fourth NMOS transistor described above), MN5 (corresponding to the fifth NMOS transistor described above), MN6 (corresponding to the sixth NMOS transistor described above), MN7, MN8, MP5, MP6, MP7, MP8, VDD, LAT, RS flip-flop, etc. VIN and VIP are differential input signals, VOUT is an output signal of the latch circuit, and LAT is a control clock. MN5 and MN6 are differential input tubes, MN7, MN8, MP6, and MP7 form a positive feedback loop. When the input voltages VIP and VIN are different, the discharge speed of the output end also differs. After the end with the faster discharge speed drops to the threshold value, the positive feedback starts to act, and the end rapidly rises to VDD, and the other end is pulled down to the ground. When LAT is low, the circuit is in a reset state, and points A and B are pulled high. The RS flip-flop causes the output VOUT to maintain the last comparison result. When LAT is high, the circuit starts to compare the input signal size, and the RS latch updates the output result of VOUT according to the voltages of points A and B.

[0068] In an exemplary embodiment, a width-length ratio of the second PMOS transistor and the third PMOS transistor is less than a width-length ratio of the first PMOS transistor and the fourth PMOS transistor.

[0069] For Figure 6 In the circuit, as long as the width-length ratio of MP2 and MP3 is less than the width-length ratio of MP1 and MP4, the overall circuit is guaranteed to be negative feedback, and hysteresis does not occur.

[0070] In an exemplary embodiment, the first DC blocking circuit and the second DC blocking circuit have the same circuit structure; each DC blocking circuit includes two capacitors; and each capacitor is connected to the output of each amplifier one by one.

[0071] In an exemplary embodiment, the first DC blocking circuit and the second DC blocking circuit have the same circuit structure; each DC blocking circuit includes two capacitors; and each capacitor is connected to the output of each amplifier one by one.

[0072] The third bias power supply is connected to the first end of each resistor, respectively; and the second end of each resistor is connected to an output end of the corresponding DC blocking circuit, respectively.

[0073] The true random number generator of the embodiment has the following advantages:

[0074] 1) The two independent noise signals N1 and N2 are input to the first amplifier at the same time, so that the external impedance seen by the two input terminals of the first amplifier is the same, and the external interference received by the two input terminals of the first amplifier is also the same. The same external interference can be cancelled by the differential amplifier, thereby improving the suppression ability of the circuit to deterministic interference and noise. Traditional single-ended noise source input cannot cancel external common-mode interference.

[0075] 2) AC coupling is used between the amplifiers, which eliminates the influence of input offset of the first amplifier and the second amplifier. Since the amplifiers are not affected by DC offset, two-stage or three-stage low-gain high-bandwidth amplifiers can be used in the amplifier stage, so that the overall bandwidth and gain of the amplifier are improved, and the noise bandwidth is improved. Avoid the bandwidth limitation of single-stage high-gain amplifier.

[0076] 3) The Strong Arm latch is used to judge and latch the signal after the amplifier. The latch works in a differential state, avoiding the uncertainty of the flip voltage of the traditional slicer, which affects the judgment of the signal.

[0077] The present application describes a plurality of embodiments, but the description is exemplary rather than limiting, and it is obvious to those skilled in the art that there can be more embodiments and implementation schemes within the scope of the embodiments described in the present application. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0078] The present application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features and elements disclosed in the present application can also be combined with any conventional features or elements to form a unique inventive scheme defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive schemes to form another unique inventive scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any appropriate combination. Therefore, the embodiments are not limited other than according to the limitations made according to the appended claims and their equivalent replacements. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0079] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of certain steps, the method or process should not be limited to the order of steps presented, as the steps presented in the specification are not exhaustive of all possible sequential embodiments. Other steps can be provided without departing from the spirit or scope of the present application. Accordingly, where the method and / or process steps have not been expressly concluded above, the method and / or process steps shall not be deemed limited to the particular order presented in the specification. Further, the claims should not be limited to the steps of the method and / or process in the order presented in the specification, as the skilled person can readily appreciate that the order of steps can be varied and still remain within the spirit and scope of the present application.

[0080] Those of ordinary skill in the art will appreciate that all or certain steps in the methods disclosed above, functional modules / units in the systems and apparatuses, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division of the functional modules / units referred to in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Certain components or all components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on computer readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it should be appreciated by those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims

1. A true random number generator, characterized by, The application relates to a true random number generator. The application relates to a true random number generator. The noise source circuit is arranged to generate two independent noise signals. The two input ends of the first amplifier are connected with the two output ends of the noise source circuit one by one, and the first amplifier is arranged to amplify the two independent noise signals respectively. The two input ends of the first direct-current isolation circuit are connected with the two output ends of the first amplifier one by one, and the first direct-current isolation circuit is arranged to isolate the direct-current signals in the amplified two independent noise signals. The two output ends of the first direct-current bias circuit are connected with the two input ends of the second amplifier one by one, and the first direct-current bias circuit is arranged to provide direct-current bias for the second amplifier. The two input ends of the second amplifier are connected with the two output ends of the first direct-current isolation circuit one by one, and the second amplifier is arranged to amplify the two independent noise signals again. The two input ends of the second direct-current isolation circuit are connected with the two output ends of the second amplifier one by one, and the second direct-current isolation circuit is arranged to isolate the direct-current signals in the signals amplified by the second amplifier. The two output ends of the second direct-current bias circuit are connected with the two input ends of the latch one by one, and the second direct-current bias circuit is arranged to provide direct-current bias for the latch. The latch is arranged to judge the size of the signals input from the second direct-current isolation circuit under the action of the direct-current bias provided by the second direct-current bias circuit, and output true random numbers according to the judgment result. The circuit structure of the first amplifier and the second amplifier is the same. The latch comprises a VDD power supply, a control clock, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and an RS flip-flop. The VDD power supply is connected with the source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube respectively; the gate of the fifth PMOS tube is connected with the control clock; the gate of the sixth PMOS tube is connected with the drain of the seventh PMOS tube and the gate of the seventh NMOS tube respectively; the drain of the sixth PMOS tube is connected with the gate of the seventh PMOS tube and the drain of the seventh NMOS tube respectively; the drain of the fifth PMOS tube and the drain of the sixth PMOS tube are connected as the first input end of the RS flip-flop; the gate of the eighth PMOS tube is connected with the control clock; the drain of the eighth PMOS tube and the drain of the seventh PMOS tube are connected as the second input end of the RS flip-flop; the source of the seventh NMOS tube is connected with the drain of the fifth NMOS tube; the gate of the seventh PMOS tube is connected with the gate of the eighth NMOS tube; the drain of the eighth NMOS tube is connected with the drain of the seventh PMOS tube.

2. The true random number generator of claim 1, wherein The noise source circuit comprises a first bias power supply, a first resistor and a second resistor; The first bias power supply is connected with the first end of the first resistor and the first end of the second resistor respectively; The second end of the first resistor and the second end of the second resistor are connected as the output end of the noise source circuit.

3. The true random number generator of claim 1, wherein Each amplifier comprises a VDD power supply, a second bias power supply, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; The VDD power supply is connected with the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube respectively; the gate of the first PMOS tube is connected with the drain of the first PMOS tube; the gate of the second PMOS tube is connected with the drain of the third PMOS tube; the drain of the second PMOS tube is connected with the gate of the third PMOS tube; the drain of the first PMOS tube and the drain of the second PMOS tube are connected as the first output end of the amplifier; the gate of the fourth PMOS tube is connected with the drain of the fourth PMOS tube; the drain of the fourth PMOS tube and the drain of the third PMOS tube are connected as the second output end of the amplifier; The drain of the second PMOS tube is connected with the drain of the third NMOS tube; the source of the third NMOS tube and the source of the second NMOS tube are respectively connected with the drain of the first NMOS tube; the gate of the third NMOS tube is the first input end of the amplifier; the drain of the second NMOS tube is connected with the drain of the third PMOS tube; the gate of the second NMOS tube is the second input end of the amplifier; the source of the first NMOS tube is grounded; and the gate of the first NMOS tube is connected with the second bias power supply.

4. The true random number generator of claim 1, wherein, The drain of the fifth NMOS tube is connected with the source of the seventh NMOS tube; the source of the eighth NMOS tube is connected with the drain of the sixth NMOS tube; the gate of the fifth NMOS tube is the differential signal input end of the amplifier; the source of the fifth NMOS tube is respectively connected with the source of the sixth NMOS tube and the drain of the fourth NMOS tube; the gate of the sixth NMOS tube is the differential signal input end of the amplifier; the source of the fourth NMOS tube is grounded; and the gate of the fourth NMOS tube is connected with the control clock. The output end of the RS flip-flop is the output end of the amplifier.

5. The true random number generator of claim 3, wherein, The width-length ratio of the second PMOS tube and the third PMOS tube is less than the width-length ratio of the first PMOS tube and the fourth PMOS tube.

6. The true random number generator of claim 1, wherein, The first direct-current blocking circuit and the second direct-current blocking circuit have the same circuit structure; each direct-current blocking circuit comprises two capacitors; and each capacitor is connected with the output of each amplifier one by one.

7. The true random number generator of claim 1, wherein, The first direct-current biasing circuit and the second direct-current biasing circuit have the same circuit structure; each direct-current biasing circuit comprises a third bias power supply and two resistors; The third bias power supply is respectively connected with the first end of each resistor; and the second end of each resistor is respectively connected with one output end of the corresponding direct-current blocking circuit.

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