Method and device for determining the step size of a direct current simulation of a circuit

Abstract

The application provides a circuit direct current simulation step length determination method and device, and relates to the technical field of circuit analysis. The method comprises the following steps: inputting simulation information corresponding to a plurality of first Newton-Raphson (NR) iterations into a target model to obtain a simulation step length multiple output by the target model; and determining a second maximum simulation step length corresponding to a current NR iteration convergence according to the simulation step length multiple and a first maximum simulation step length corresponding to a last NR iteration convergence. The circuit direct current simulation step length determination method and device provided in the application embodiment can accelerate the direct current analysis speed in circuit simulation and improve the direct current analysis efficiency in circuit simulation.

Description

Technical Field

[0001] This application relates to the field of circuit analysis technology, and in particular to a method and apparatus for determining the DC simulation step size of a circuit. Background Technology

[0002] DC analysis in circuit simulation is exceptionally important as it forms the basis for other circuit analyses. In DC analysis, such as... Figure 1 The pseudo-transient analysis (PTA) method, as shown, has become a research hotspot in DC analysis and simulation of nonlinear circuits. This method uses implicit integration to solve a series of differential-algebraic equations (hereinafter referred to as the PTA equations) describing the circuit behavior and performance.

[0003] It is worth noting that the time step in PTA is not determined by accuracy. On the contrary, as long as the Newton-Raphson (NR) method converges, a larger time step can be chosen. Quickly determining the maximum time step corresponding to the convergence of each NR iteration helps the PTA converge faster, thus completing the DC analysis in the circuit simulation.

[0004] However, existing technologies lack methods to accelerate PTA convergence. Summary of the Invention

[0005] This application provides a method and apparatus for determining the DC simulation step size in circuit simulation, which can accelerate the DC analysis speed and improve the DC analysis efficiency in circuit simulation.

[0006] In a first aspect, embodiments of this application provide a method for determining the DC simulation step size of a circuit, including:

[0007] The simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model to obtain the simulation step size multiple output by the target model;

[0008] Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration;

[0009] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0010] The simulation information includes:

[0011] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0012] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0013] The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges;

[0014] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0015] In one embodiment, the target model is trained as follows:

[0016] The simulation information corresponding to multiple first NR iterations is used as samples, and the simulation step size multiples corresponding to the multiple first NR iterations are used as labels to train the initial model and obtain the target model.

[0017] In one embodiment, inputting simulation information corresponding to multiple first NR iterations into the target model includes:

[0018] The simulation information corresponding to the multiple first NR iterations is normalized, and the normalized simulation information is input into the target model.

[0019] In one embodiment, the residuals of the system of equations are expressed by the following formula:

[0020]

[0021] Where Res represents the residual of the system of equations, X represents the solution vector of the circuit at a certain moment, and t represents the virtual time point in the simulation.

[0022] In one embodiment, the maximum simulation step size corresponding to the convergence of the NR iteration is determined in the following way:

[0023] When the NR iteration converges and the current simulation step size is equal to the preset simulation step size, the current simulation step size is taken as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0024] If the NR iteration fails to converge and the current simulation step size is less than the preset simulation step size, the simulation step size for the next NR iteration is determined as follows:

[0025] Determine the step size interval to which the current simulation step size belongs;

[0026] The difference between the current simulation step size and the granularity corresponding to the step size interval is used as the simulation step size corresponding to the next NR iteration.

[0027] Perform the next NR iteration until the NR iteration converges, and take the simulation step size at this time as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0028] The larger the value corresponding to the step size interval, the larger the granularity of the step size interval.

[0029] In one embodiment, the target model is constructed based on a Long Short-Term Memory (LSTM) network.

[0030] Secondly, embodiments of this application provide a circuit DC simulation step size determination device, comprising:

[0031] The input module is used to input the simulation information corresponding to multiple first Newton-Raphson NR iterations into the target model to obtain the simulation step size multiple output by the target model;

[0032] The determination module is used to determine the second maximum simulation step size corresponding to the convergence of the current NR iteration based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration;

[0033] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0034] The simulation information includes:

[0035] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0036] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0037] The changing trend of the solution characterizes the changing trend of the solutions of the PTA equation system at both ends of the maximum simulation step size when the NR iteration converges;

[0038] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0039] Thirdly, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect.

[0040] Fourthly, this application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0041] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0042] The circuit DC simulation step size determination method and apparatus provided in this application determine the simulation step size by predicting the current simulation step size multiple based on simulation information corresponding to the Newton-Raphson (NR) iteration. On one hand, predicting the simulation step size multiple instead of the actual simulation step size reduces the learning cost of the target model, improves the accuracy of model prediction, accelerates the convergence speed of the model during the training phase, and significantly reduces the time cost of the training phase. On the other hand, using the target model to determine the simulation step size reduces the number of NR iterations, improves the efficiency of NR iterations, and thus improves the efficiency of PTA iterations. Therefore, the technical solution proposed in this application can accelerate the DC analysis speed and improve the efficiency of DC analysis in circuit simulation. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the pseudo-transient analysis (PTA) method in the prior art;

[0045] Figure 2 This is a flowchart illustrating the method for determining the DC simulation step size of a circuit according to an embodiment of this application.

[0046] Figure 3 This is a schematic diagram of the coarse- and fine-grained PTA iterative algorithm provided in the embodiments of this application;

[0047] Figure 4 This is a schematic diagram of the circuit DC simulation step size determination device provided in the embodiments of this application;

[0048] Figure 5 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In the description of the embodiments of this application, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the process of creating this application, the inventors considered the following aspects:

[0052] Large-scale integrated circuit (chip) simulation technology is an indispensable and crucial step in the chip design process, and DC analysis in circuit simulation is exceptionally important as it forms the basis for other analyses. In DC analysis, such as... Figure 1 The PTA (Pseudo-transient analysis) method, as shown, has become a research hotspot in DC analysis and simulation of nonlinear circuits. The basic principle of PTA is to connect a pseudo-inductor in series with each independent voltage source and each nonlinear voltage-related branch, and a pseudo-capacitor with each independent current source and each nonlinear current-related branch, and then perform transient analysis. PTA uses implicit integration to solve a system of differential-algebraic equations (PTA equations) describing the circuit behavior and performance. First, an appropriate time step is selected for Newton-Raphson (NR) iteration. If the NR iteration does not converge, the time step is rolled back, and a new time step is selected based on the relevant information from the previous NR iteration. The NR iteration is then repeated until it converges. After NR convergence, the converged time step is used for PTA iteration. If PTA iteration does not converge, the NR iteration is repeated, and the newly obtained converged time step is used again for PTA iteration until it converges.

[0053] In pseudo-transient methods, the time step is not determined by accuracy. As long as the Newton-Raphson (NR) method converges, a larger time step can be chosen. While there has been considerable research on time-varying methods for calculating DC operating points, research on time step control methods is relatively limited. Some preliminary studies suggest that considering residuals, solution trends, and other simulation processes, and artificially fitting the model to control the time step, can significantly improve simulation efficiency, achieving speedups of up to 104 times. This demonstrates the immense potential for accelerating the simulation process through step control.

[0054] Classical time step control uses a simple iteration count method to determine the time step. This method uses two options (IMAX and IMIN) to control the time step. If the NR iteration count at the current time point exceeds IMAX, a rollback mechanism is triggered, the simulation state reverts to the previous time point, and the new time step needs to be reduced to k times the original time step. If the Newton-Raphson (NR) iteration count at the current time point is between IMAX and IMIN, the new time step remains unchanged from the original time step. If the NR iteration count at the current time point is less than IMIN, the new time step needs to be increased to a times the original time step. However, choosing appropriate parameters (including IMAX, IMIN, initial step size, and step size growth rate) is a very difficult problem and cannot provide different step size growth and reduction ratios for different circuits.

[0055] The adaptive step size control method is based on the idea of ​​relaxation transformation. This method is a heuristic approach with expert experience, and it also shows good acceleration by considering the changes of some state variables in the PTA iteration process. The method implements time step size control in two parts. The time step increment is controlled by the number of NR iterations, the relative change of solution X, and the decrease in the residual of F(X). The time step decrement is achieved by reducing the time step by a certain decay ratio when NR fails to converge. However, this strategy still faces the problem of choosing suitable parameters.

[0056] Current simple formulas for human fitting cannot accurately and completely express the various features in the simulation process. Machine learning technology, on the other hand, uses computers as tools and aims to realistically and in real-time simulate human learning methods. It also effectively improves learning efficiency by dividing existing content into knowledge structures. Compared to traditional methods that solve each problem from the ground up and lack knowledge accumulation, machine learning focuses on extracting high-level features or patterns that can be reused in other relevant or similar situations, avoiding repetitive and complex analyses.

[0057] This application discloses a pseudo-transient analysis method in a deep learning model-enhanced DC analysis approach for large-scale nonlinear circuits. This method constructs an LSTM (Long Short-Term Memory) network with timing information capture capabilities to achieve intelligent control of the time step size during DC analysis of large-scale nonlinear circuits based on the pseudo-transient algorithm. Based on the principles and characteristics of pseudo-transient analysis, the solution process can be viewed as a supervised learning problem. At each simulation time point, the neural network model can predict the optimal time step size based on the simulation characteristics of previous steps (ensuring convergence of the NR iteration at the current time point). This method achieves relatively accurate step size prediction for most circuits, allowing for the selection of a better step size during simulation. It reduces the step size back-off portion of the original pseudo-transient algorithm, significantly improving simulation convergence efficiency.

[0058] Figure 2 This is a flowchart illustrating the method for determining the DC simulation step size of a circuit according to an embodiment of this application. (Refer to...) Figure 2 This application provides a method for determining the DC simulation step size of a circuit, which may include:

[0059] Step 210: Input the simulation information corresponding to multiple first Newton-Raphson NR iterations into the target model to obtain the simulation step size multiple output by the target model;

[0060] Step 220: Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration.

[0061] The first NR iteration is performed before the current NR iteration; multiple first NR iterations include the previous NR iteration;

[0062] The simulation information includes:

[0063] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0064] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0065] The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges;

[0066] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0067] It should be noted that the execution subject of the circuit DC simulation step size determination method provided in this application embodiment can be a computer device, such as a computer device loaded with various circuit simulator software, such as a mobile phone, tablet computer, laptop computer, PDA, etc. The following uses a simulator executing the circuit DC simulation step size determination method as an example to illustrate the circuit DC simulation step size determination method provided in this application embodiment.

[0068] The Newton-Raphson (NR) iterative algorithm involves giving appropriate initial values, substituting these initial values ​​into the equations, and iterating until the absolute value of the difference between two adjacent solution vectors is less than a predetermined allowable error. In step 210, the first Newton-Raphson NR iteration can refer to the iteration performed before the current NR iteration, and multiple first NR iterations can include the previous NR iteration. Simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model. The target model learns and predicts the next simulation step size using the input simulation information and outputs the simulation step size multiple (the ratio between the current simulation step size and the previous simulation step size). The simulation information can include the number of NR iterations, the residuals of the equation system, the trend of solution changes, and the time step size of the previous step.

[0069] The NR iteration count represents the number of iterations required for the NR iteration to converge. After each simulation step size is determined, the simulator uses the Newton-Raphson NR algorithm to iterate until the error analysis does not exceed the confidence range; this number of iterations is the NR iteration count. The simulation time cost is mainly concentrated in the number of iterations, and the introduction of the NR iteration count can evaluate the time cost spent on outputting the simulation step size.

[0070] The residuals of the equation system can characterize the degree to which the solution of the PTA equation system in the NR iterations deviates from the true solution. In the PTA method, the time step is not determined by accuracy; on the contrary, as long as the Newton-Raphson (NR) method converges, a larger time step can be chosen. Figure 1 As shown, the PTA method first performs NR iterations until NR converges, obtaining the maximum time step, which is then used for PTA iterations. If the PTA iterations do not converge, NR iterations are performed again, and the newly obtained maximum time step for NR iteration convergence is used again for PTA iterations until the PTA iterations converge. The residuals of the equation system can represent the degree to which the solution of each PTA equation system converges to the final true solution.

[0071] The trend of the solution can characterize the trend of the solutions of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges. This trend can be described by the variance of the solution over a certain interval. When the solution changes drastically, the variance is large; when the solution tends to be stable, the variance approaches 0. This characteristic quantity, compared to the residual, can more precisely reflect the trend of the solution curve during the matrix solving process.

[0072] The previous time step size represents the maximum simulation step size corresponding to the previous NR iteration. The previous time step size serves as the base for increasing the current time step size, determining the basis on which the current time step is increased.

[0073] In step 220, the simulator can obtain the simulation step size multiple output by the target model in step 210, as well as the first maximum simulation step size corresponding to the convergence of the previous NR iteration, and multiply the two to obtain the second maximum simulation step size corresponding to the convergence of the current NR iteration. Both the first and second maximum simulation step sizes obtained by the simulator can be used for PTA iteration.

[0074] The circuit DC simulation step size determination method provided in this application determines the simulation step size by predicting the current simulation step size multiple based on simulation information corresponding to the Newton-Raphson (NR) iteration. On one hand, predicting the simulation step size multiple instead of the actual simulation step size reduces the learning cost of the target model, improves the accuracy of model prediction, accelerates the convergence speed of the model during the training phase, and significantly reduces the time cost of the training phase. On the other hand, using the target model to determine the simulation step size reduces the number of NR iterations, improves the efficiency of NR iterations, and thus improves the efficiency of PTA iterations. Therefore, the technical solution proposed in this application can accelerate the DC analysis speed and improve the efficiency of DC analysis in circuit simulation.

[0075] In one embodiment, the target model is trained as follows:

[0076] The simulation information corresponding to multiple first NR iterations is used as samples, and the simulation step size multiples corresponding to multiple first NR iterations are used as labels to train the initial model and obtain the target model.

[0077] The initial model can be trained by using simulation information samples corresponding to multiple first NR iterations and simulation step size multiple labels corresponding to multiple first NR iterations, thereby obtaining the target model.

[0078] The target model can use simulation information corresponding to multiple first Newton-Raphson (NR) iterations as samples. This simulation information can include the number of NR iterations, residuals of the equation system, trends in solution changes, and the time step size of the previous step. Each first NR iteration can have a corresponding simulation step size multiple, which can be used as a label. The simulation information samples corresponding to multiple first NR iterations and their corresponding simulation step size multiple labels are used as training samples to train the initial model. When the accuracy of the initial model reaches the target requirement, the target model can be obtained. When the target model receives simulation information corresponding to multiple first Newton-Raphson NR iterations, it can predict and output the simulation step size multiple.

[0079] The time cost of simulator simulation is mainly concentrated in the number of iterations. Training the target model allows the simulation step size multiple to be predicted through the simulation information corresponding to the NR iteration, without having to repeat the NR iteration multiple times. This greatly improves the efficiency of NR iteration, saves time, and thus speeds up DC analysis in circuit simulation and improves the efficiency of DC analysis in circuit simulation.

[0080] In one embodiment, simulation information corresponding to multiple first NR iterations is input into the target model, including:

[0081] The simulation information corresponding to multiple first NR iterations is normalized, and the normalized simulation information is input into the target model.

[0082] Before inputting the simulation information corresponding to multiple first NR iterations into the target model, these simulation information can be normalized first, and then the normalized simulation information can be input into the target model.

[0083] The target model can input simulation information with a unified data type, namely a one-dimensional row vector. Therefore, simulation information such as residuals and voltages can be standardized. The simulator can have the function of normalizing the simulation information. For example, for voltages with a matrix structure, the simulator can normalize each voltage solution curve by the variance of the solution curve describing each voltage fluctuation, resulting in a one-dimensional row vector of size N (e.g., 10, 20, etc.). Then, for simulation information of the one-dimensional column vector type, such as residuals, in order to describe the convergence distance of the current PTA equation system, the simulator can take the standard deviation to normalize the residuals and generate a scalar. Afterwards, the simulator can concatenate the independent features into a one-dimensional row vector according to the column direction.

[0084] The simulator can concatenate all processed one-dimensional row vectors into a large matrix as the training set for the target model. However, the different value ranges and dimensions of each column's features in the training set can increase training time and even cause the target model to fail to converge. Therefore, for each column of the training set, maximum and minimum value normalization can be used to achieve numerical uniformity.

[0085] For the residuals of the equation system and the trend of solution changes, the simulator can convert the vector into a scalar by calculating the second norm in 5-step units. In particular, since different circuits have different characteristics, the simulator can also normalize the data collected from each circuit on a circuit-by-circuit basis to preserve these characteristics. On the one hand, this solves the problem of data range, ensuring that the data does not contain extreme values ​​that could cause the target model to be affected by extreme values ​​and exhibit instability; on the other hand, it preserves the simulation step size characteristics of different circuits, thereby making the model's generalization ability stronger.

[0086] Normalizing the simulation information from the NR iteration facilitates target model learning and simulation step size prediction, thereby improving the efficiency of the NR iteration and accelerating DC analysis in circuit simulation.

[0087] In one embodiment, the residuals of the system of equations are expressed by the following formula:

[0088]

[0089] Where Res represents the residual of the system of equations, X represents the solution vector of the circuit at a certain moment, and t represents the virtual time point in the simulation.

[0090] The residuals of the equation system can characterize the degree to which the solution of the PTA equation system in the NR iteration deviates from the true solution. For example... Figure 1 As shown, the basic principle of the pseudo-transient analysis (PTA) method is to connect a pseudo-inductor in series with each independent voltage source and each nonlinear voltage-dependent branch, and to connect a pseudo-capacitor with each independent current source and each nonlinear current-dependent branch, and then perform transient analysis. c can represent the value of the inserted pseudo-capacitor. During the NR iteration's convergence to the final true solution, the residuals will generally approach 0.

[0091] In pseudo-transient simulation, there is a certain correlation between the simulation step size at the current time point and the simulation step size at previous time points. The residual of the equation system, as a form of simulation information, can reflect the degree to which the solution of the PTA equation system converges to the final true solution. It plays an important role in the target model learning the mapping relationship between simulation information and simulation step size, which is beneficial for the target model to accurately predict the time step, accelerate the DC analysis speed in circuit simulation, and improve the DC analysis efficiency in circuit simulation.

[0092] In one embodiment, the maximum simulation step size corresponding to the convergence of the NR iteration is determined as follows:

[0093] When the NR iteration converges and the current simulation step size is equal to the preset simulation step size, the current simulation step size is taken as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0094] If the NR iteration fails to converge and the current simulation step size is less than the preset simulation step size, the simulation step size for the next NR iteration is determined as follows:

[0095] Determine the current simulation step size to belong to the step size interval;

[0096] The difference between the current simulation step size and the granularity corresponding to the step size interval is used as the simulation step size for the next NR iteration.

[0097] Perform the next NR iteration until the NR iteration converges, and take the simulation step size at this time as the maximum simulation step size corresponding to the convergence of the NR iteration;

[0098] The larger the value corresponding to the step size interval, the larger the granularity of the step size interval.

[0099] In one embodiment, the PTA method can consist of two layers of iteration: an outer PTA iteration and an inner NR iteration. The goal of pseudo-transient analysis is to find the optimal simulation step size in each PTA iteration. For the efficiency of PTA iteration simulation, a larger simulation step size, while ensuring NR iteration convergence, reduces the number of discrete time points that need to be computed, resulting in higher simulation efficiency. Otherwise, if the NR iteration fails to converge, a rollback will occur, and the NR iteration will be repeated, leading to additional computational overhead. Therefore, while ensuring NR convergence, the optimal simulation step size can be approximated by using the largest possible simulation step size.

[0100] According to such Figure 3 The diagram shows a PTA iterative algorithm combining coarse and fine granularity. In each PTA iteration, when the inner NR iteration converges, the simulation step size can be increased by twice the coarse granularity. During the increase of the simulation step size, the simulation step size can be marked in two ways to find the maximum simulation step size corresponding to the convergence of the NR iteration.

[0101] The first approach is to mark the simulation step size as the maximum simulation step size corresponding to the convergence of the NR iteration when the NR iteration converges, provided that the NR iteration converges. It is worth noting that the preset simulation step size can be a manually set maximum simulation step size or a maximum simulation step size limited by other methods; this application does not specifically limit this.

[0102] The second scenario is when the NR iteration does not converge and the simulation step size has not increased to the preset simulation step size. In this case, the fine-grained search can start from the current non-converging simulation step size, determine the simulation step size corresponding to the next NR iteration according to the current simulation step size minus the granularity corresponding to the step size interval to which the step size belongs, and continue the NR iteration until convergence. The simulation step size at this time can be marked as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0103] Both the step size interval and the corresponding granularity can be set according to actual needs. The larger the value of the step size interval, the larger the granularity. For example, a step size interval of 10-20 can be set to a granularity of 0.5, and a step size interval of 0-10 can be set to a granularity of 0.1. Similarly, the step size interval can also be set to 10-20, 5-10, 0-5, etc. This application does not impose specific limitations on the setting of the step size interval and its corresponding granularity.

[0104] Traditional methods, when the simulation step size is reduced to a coarse-grained size, result in overly aggressive PTA iterations, making it difficult to accurately obtain the maximum simulation step size. This application addresses this by adding a fine-grained search, i.e., using a hybrid coarse-grained and fine-grained approach. By setting the simulation step size range and the corresponding granularity, the appropriate granularity can be automatically selected based on the simulation step size to reduce the simulation step size for NR iteration, thereby accurately and quickly obtaining the maximum simulation step size.

[0105] In one embodiment, the target model is built based on a Long Short-Term Memory (LSTM) network.

[0106] The target model can be constructed based on a Long Short-Term Memory (LSTM) network. LSTM is a type of temporal recurrent neural network specifically designed to address the long-term dependency problem inherent in general Recurrent Neural Networks (RNNs). In pseudo-transient simulations, the simulation step size at the current time point is correlated with the simulation information at previous time points; the information between simulation time points is not independent. The simulation information at the current time point can influence the choice of subsequent time steps, but the duration of this influence is uncertain. Traditional backpropagation (BP) neural networks lack the ability to process temporal information, and recurrent neural networks (RNNs) suffer from long-term dependency problems. LSTM can handle temporally correlated information, and its unique network structure can determine the lifespan of information transmitted within the network. Therefore, using LSTM as a neural network model to enhance pseudo-transient analysis is logically feasible.

[0107] By constructing the target model using a Long Short-Term Memory (LSTM) network, the dependency of information at different time points is resolved. Moreover, its unique network structure has the ability to select the memory information in the network, which is more in line with the time step control mechanism of pseudo-transient analysis. This enables accurate prediction of the simulation step size, accelerates the DC analysis speed in circuit simulation, and improves the efficiency of DC analysis in circuit simulation.

[0108] The following example, using a circuit DC simulation step size determination method provided in an embodiment of this application, further illustrates the technical solution of this application.

[0109] This example includes the following steps:

[0110] S1. Data Labeling Stage. This stage mainly aims to find the optimal simulation step size at each time point when performing pseudo-transient analysis on different circuits. That is, the maximum time step size at which the NR iteration can converge at the current time point, which serves as the labeled data in supervised learning.

[0111] S2. Feature Selection Stage. This stage primarily determines which features to select for learning and predicting the optimal simulation step size. The selected features must be relevant to changes in the simulation step size and possess good generalization ability. Based on the characteristics and principles of pseudo-transient analysis, features related to the simulation step size include the number of NR iterations, the residuals of the equation system, the trend of the solution curve, and the time step size of the previous step.

[0112] S3. Data Processing Stage. This stage mainly involves processing the selected features and labeled data, including data normalization, data scaling, and data computational transformation. This application can use the simulation information from the first five steps to learn and predict the simulation step size for the next step (sixth step).

[0113] S4. The data can be divided into training and test sets, using circuits as units. The ratio of training to test sets is 7:3. Circuits in the test set are not allowed for learning; therefore, they are unknown data for the target model and represent a direct standard for evaluating model performance. The training set is used for the model to learn the temporal relationship between features and labels. The loss during training can be used to measure the model's performance on the training set.

[0114] S5. Model Validation Phase on the Simulator. This phase primarily verifies the performance of the target model during actual simulations. In this phase, the target model and the simulator interact in real-time. The simulator processes features for the model, and the target model outputs a multiple of the simulation step size to the simulator based on these features. This multiple is multiplied by the previous simulation step size before proceeding to the next simulation step. This process continues until the simulation concludes. By comparing the total number of NR iterations and the number of pseudo-transient steps, the training effectiveness of the target model can be verified.

[0115] This application employs LSTM to capture timing information in pseudo-transient analysis to predict the simulation step size. Based on the simulation step size control, it intelligently provides an optimal time step size at each time point, thereby reducing the time wasted by backoff and exhibiting good adaptive capabilities. It can provide different simulation step size control strategies for different circuits. Using a predicted step size multiple reduces the learning difficulty of the network. During data processing, the label to be predicted is converted into the ratio between the current simulation step size and the previous simulation step size. This ensures that even with a large step size, the ratio remains within an acceptable range. Circuit-based data normalization preserves the differences in data between different circuits, thus solving the data range problem while retaining the step size characteristics of different circuits.

[0116] The circuit DC simulation step size determination device provided in the embodiments of this application is described below. The circuit DC simulation step size determination device described below and the circuit DC simulation step size determination method described above can be referred to in correspondence.

[0117] Figure 4 A schematic diagram of the circuit DC simulation step size determination device provided in this application embodiment is shown. (Refer to...) Figure 4 The device may include:

[0118] The input module 410 is used to input the simulation information corresponding to multiple first Newton-Raphson NR iterations into the target model to obtain the simulation step size multiple output by the target model;

[0119] The determination module 420 is used to determine the second maximum simulation step size corresponding to the convergence of the current NR iteration based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration;

[0120] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0121] The simulation information includes:

[0122] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0123] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0124] The changing trend of the solution characterizes the changing trend of the solutions of the PTA equation system at both ends of the maximum simulation step size when the NR iteration converges;

[0125] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0126] The circuit DC simulation step size determination device provided in this application determines the simulation step size by predicting the current simulation step size multiple based on the simulation information corresponding to the Newton-Raphson (NR) iteration. On one hand, predicting the simulation step size multiple instead of the actual simulation step size reduces the learning cost of the target model, improves the accuracy of model prediction, accelerates the convergence speed of the model during the training phase, and significantly reduces the time cost of the training phase. On the other hand, using the target model to determine the simulation step size reduces the number of NR iterations, improves the efficiency of NR iterations, and thus improves the efficiency of PTA iterations. Therefore, the technical solution proposed in this application can accelerate the DC analysis speed and improve the efficiency of DC analysis in circuit simulation.

[0127] In one embodiment,

[0128] The target model is trained in the following manner:

[0129] The simulation information corresponding to multiple first NR iterations is used as samples, and the simulation step size multiples corresponding to the multiple first NR iterations are used as labels to train the initial model and obtain the target model.

[0130] In one embodiment, the input module 410 is specifically used for:

[0131] The simulation information corresponding to the multiple first NR iterations is normalized, and the normalized simulation information is input into the target model.

[0132] In one embodiment,

[0133] The residuals of the system of equations are expressed by the following formula:

[0134]

[0135] Where Res represents the residual of the system of equations, X represents the solution vector of the circuit at a certain moment, and t represents the virtual time point in the simulation.

[0136] In one embodiment, the maximum simulation step size corresponding to the convergence of the NR iteration is determined in the following way:

[0137] When the NR iteration converges and the current simulation step size is equal to the preset simulation step size, the current simulation step size is taken as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0138] If the NR iteration fails to converge and the current simulation step size is less than the preset simulation step size, the simulation step size for the next NR iteration is determined as follows:

[0139] Determine the step size interval to which the current simulation step size belongs;

[0140] The difference between the current simulation step size and the granularity corresponding to the step size interval is used as the simulation step size corresponding to the next NR iteration.

[0141] Perform the next NR iteration until the NR iteration converges, and take the simulation step size at this time as the maximum simulation step size corresponding to the convergence of the NR iteration.

[0142] The larger the value corresponding to the step size interval, the larger the granularity of the step size interval.

[0143] In one embodiment,

[0144] The target model is constructed based on the Long Short-Term Memory (LSTM) network.

[0145] It should be noted that the circuit DC simulation step size determination device provided in this application embodiment can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Here, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail.

[0146] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communication interface 520, and the memory 530 communicate with each other via the communication bus 540. The processor 510 can call a computer program in the memory 530 to execute the steps of the circuit DC simulation step size determination method, such as including:

[0147] The simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model to obtain the simulation step size multiple output by the target model;

[0148] Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration;

[0149] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0150] The simulation information includes:

[0151] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0152] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0153] The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges;

[0154] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0155] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] On the other hand, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the circuit DC simulation step size determination method provided by the above methods, for example including:

[0157] The simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model to obtain the simulation step size multiple output by the target model;

[0158] Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration;

[0159] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0160] The simulation information includes:

[0161] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0162] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0163] The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges;

[0164] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0165] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).

[0166] In another aspect, embodiments of this application also provide a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can perform the steps of the circuit DC simulation step size determination method provided by the above methods, such as including:

[0167] The simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model to obtain the simulation step size multiple output by the target model;

[0168] Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration;

[0169] The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration;

[0170] The simulation information includes:

[0171] The NR iteration count represents the number of iterations required for the NR iteration to converge.

[0172] The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution;

[0173] The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges;

[0174] The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration.

[0175] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0176] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0177] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for determining the step size in DC simulation of a circuit, characterized in that, include: The simulation information corresponding to multiple first Newton-Raphson NR iterations is input into the target model to obtain the simulation step size multiple output by the target model; Based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration, determine the second maximum simulation step size corresponding to the convergence of the current NR iteration; The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration; The simulation information includes: The NR iteration count represents the number of iterations required for the NR iteration to converge. The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution; The trend of solution variation characterizes the trend of solution variation of the PTA equation system adjacent to the maximum simulation step size when the NR iteration converges; The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration. The maximum simulation step size corresponding to the convergence of the NR iteration is determined in the following way: When the NR iteration converges and the current simulation step size is equal to the preset simulation step size, the current simulation step size is taken as the maximum simulation step size corresponding to the convergence of the NR iteration. If the NR iteration fails to converge and the current simulation step size is less than the preset simulation step size, the simulation step size for the next NR iteration is determined as follows: Determine the step size interval to which the current simulation step size belongs; The difference between the current simulation step size and the granularity corresponding to the step size interval is used as the simulation step size corresponding to the next NR iteration. Perform the next NR iteration until the NR iteration converges, and take the simulation step size at this time as the maximum simulation step size corresponding to the convergence of the NR iteration. The larger the value corresponding to the step size interval, the larger the granularity of the step size interval.

2. The method for determining the DC simulation step size of a circuit according to claim 1, characterized in that, The target model is trained in the following manner: The simulation information corresponding to multiple first NR iterations is used as samples, and the simulation step size multiples corresponding to the multiple first NR iterations are used as labels to train the initial model and obtain the target model.

3. The method for determining the DC simulation step size of a circuit according to claim 1, characterized in that, The step of inputting simulation information corresponding to multiple first NR iterations into the target model includes: The simulation information corresponding to the multiple first NR iterations is normalized, and the normalized simulation information is input into the target model.

4. The method for determining the DC simulation step size of a circuit according to claim 1, characterized in that, The residuals of the system of equations are expressed by the following formula: ； Where Res represents the residuals of the system of equations. X The solution vector of the circuit at a certain moment. t This represents a virtual point in time during the simulation.

5. The method for determining the DC simulation step size of a circuit according to any one of claims 1 to 4, characterized in that, The target model is constructed based on the Long Short-Term Memory (LSTM) network.

6. A circuit DC simulation step size determination device, characterized in that, include: The input module is used to input the simulation information corresponding to multiple first Newton-Raphson NR iterations into the target model to obtain the simulation step size multiple output by the target model; The determination module is used to determine the second maximum simulation step size corresponding to the convergence of the current NR iteration based on the simulation step size multiple and the first maximum simulation step size corresponding to the convergence of the previous NR iteration; The first NR iteration is performed before the current NR iteration; the plurality of first NR iterations include the previous NR iteration; The simulation information includes: The NR iteration count represents the number of iterations required for the NR iteration to converge. The residuals of the equation system characterize the degree to which the solution of the PTA equation system in the NR iteration is far from the true solution; The changing trend of the solution characterizes the changing trend of the solutions of the PTA equation system at both ends of the maximum simulation step size when the NR iteration converges; The time step of the previous step represents the maximum simulation step size corresponding to the previous NR iteration. The maximum simulation step size corresponding to the convergence of the NR iteration is determined in the following way: When the NR iteration converges and the current simulation step size is equal to the preset simulation step size, the current simulation step size is taken as the maximum simulation step size corresponding to the convergence of the NR iteration. If the NR iteration fails to converge and the current simulation step size is less than the preset simulation step size, the simulation step size for the next NR iteration is determined as follows: Determine the step size interval to which the current simulation step size belongs; The difference between the current simulation step size and the granularity corresponding to the step size interval is used as the simulation step size corresponding to the next NR iteration. Perform the next NR iteration until the NR iteration converges, and take the simulation step size at this time as the maximum simulation step size corresponding to the convergence of the NR iteration. The larger the value corresponding to the step size interval, the larger the granularity of the step size interval.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the circuit DC simulation step size determination method as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the circuit DC simulation step size determination method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the circuit DC simulation step size determination method as described in any one of claims 1 to 5.

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