Display device

Abstract

A display device may include: a display panel including a display area in which subpixels are disposed, and a non-display area adjacent to the display area and in which a second pad portion is disposed; a printed circuit board including a first pad portion for outputting a voltage to the display panel; and a circuit film including a first end connected to the first pad portion of the printed circuit board and a second end connected to the second pad portion of the display panel. The display device may further include an analog-to-digital converter to receive a voltage output from the first pad portion or the second pad portion via a line in the circuit film electrically connecting the first pad portion and the second pad portion, and output a value corresponding to the input voltage for detecting a bonding state of at least one internal component within the display device.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate to a display device. BACKGROUND

[0002] As the information society develops, the demand for display devices for displaying images in various forms is increasing, and in recent years, various display devices such as liquid crystal display devices and organic light emitting display devices have been used.

[0003] Recently, in order to provide a highly immersive image viewing environment to users, various form factors of display devices have been used.

[0004] Examples in which a flexible display device is various form factors have been proposed. The flexible display device can implement various designs and has the advantages of portability and durability. The flexible display device can be implemented as various types of display devices such as a bendable display device, a foldable display device, and a rollable display device.

[0005] In addition, the flexible display device has a key feature of providing a user with an experience of a shape variable of the flexible display. Therefore, a flexible display device with high durability is needed so that shape change can be repeatedly performed. SUMMARY

[0006] For example, when the flexible display is repeatedly bent and straightened during its service life, the bonding conditions of internal components can be deteriorated and peeled off or disconnected, which can impair image quality and shorten the service life of the flexible display device. Therefore, there is a need to be able to accurately detect and identify the damaged internal bonding conditions and their specific locations within the flexible display device, and to be able to dynamically adjust the allowable bending characteristics of the flexible display device based on the identified internal bonding conditions.

[0007] Embodiments of the disclosure can provide a display device.

[0008] Additional advantages and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or can be learned from practice of the disclosure. The purposes and other advantages of the inventive concepts provided herein will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0009] Embodiments of the present disclosure can provide a display device including a display panel including a display area in which a plurality of sub-pixels are disposed and a non-display area located around or adjacent to the display area and in which a pad portion is disposed, a printed circuit board including a pad portion for outputting a plurality of voltages to the display panel, a circuit film including one end connected to a first pad portion which is the pad portion of the printed circuit board and the other end connected to a second pad portion which is the pad portion of the display panel, and an analog-to-digital converter for receiving a voltage output from the first pad portion or a voltage output from the second pad portion through a wire of the circuit film electrically connecting the first pad portion and the second pad portion and outputting a digital value corresponding to the input voltage.

[0010] Embodiments of the present disclosure can provide a display device including a display panel including a display area in which a plurality of sub-pixels are disposed and a non-display area located around or adjacent to the display area and in which a pad portion is disposed, a printed circuit board including a pad portion for outputting a plurality of voltages input to the display panel, a circuit film including one end connected to a first pad portion which is the pad portion of the printed circuit board and the other end connected to a second pad portion which is the pad portion of the display panel, and an analog-to-digital converter for receiving a voltage output from the first pad portion or a voltage output from the second pad portion through a wire of the circuit film electrically connecting the first pad portion and the second pad portion, wherein a flexible characteristic of the display panel is changed according to a voltage value input to the analog-to-digital converter.

[0011] According to embodiments of the present disclosure, a display device in which a flexible characteristic can be adjusted according to a connection state between components of a flexible display device can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 A display device according to embodiments of the present disclosure is schematically illustrated.

[0014] Figure 2 is a perspective view of a flexible display device including a display device according to embodiments of the present disclosure.

[0015] Figure 3A sub-pixel structure and configuration for compensating for a characteristic value of a sub-pixel of a display apparatus according to an embodiment of the disclosure is schematically illustrated.

[0016] Figure 4 Components configured to provide various voltage supplies to a display panel in a display apparatus according to an embodiment of the disclosure are illustrated.

[0017] Figure 5 A circuit film according to an embodiment of the disclosure is specifically illustrated.

[0018] Figure 6 An electrical connection relationship for detecting a degree of junction of a circuit film in a display apparatus according to an embodiment of the disclosure is illustrated.

[0019] Figure 7 A principle in which an output voltage varies according to a degree of junction of a circuit film in a display apparatus according to an embodiment of the disclosure is schematically illustrated.

[0020] Figure 8 An analog-digital converter in which an input has an output voltage in a display apparatus according to an embodiment of the disclosure is illustrated.

[0021] Figure 9 Another diagram illustrating an electrical connection relationship for detecting a degree of junction of a circuit film in a display apparatus according to an embodiment of the disclosure is illustrated.

[0022] Figure 10 A diagram schematically illustrating a principle in which an output voltage varies according to a degree of junction of a circuit film in a display apparatus according to an embodiment of the disclosure is illustrated.

[0023] Figure 11 An analog-digital converter in which an input selectively has a first output voltage and a second output voltage in a display apparatus according to an embodiment of the disclosure is illustrated.

[0024] Figure 12 A characteristic in which a host system adjusts a bending characteristic based on a junction control signal is illustrated. DETAILED DESCRIPTION

[0025] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which the same or similar components are designated by the same or similar reference numerals and symbols, even when shown in different drawings from each other. Also, in the following description of examples or embodiments of the present disclosure, a detailed description of well-known functions and components incorporated herein will be omitted when it is determined that it can make the subject matter of some embodiments of the present disclosure rather unclear. The terms such as “include,” “have,” “comprise,” “comprise,” “consist of,” and “consist in” used herein are generally intended to allow the addition of other components, unless the term is used together with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” can be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence, or number of elements, etc., but is merely used to distinguish the corresponding element from other elements.

[0027] When it is mentioned that a first element is “connected or coupled to,” “contacts or overlaps,” etc., a second element, it should be interpreted that not only the first element can be “directly connected or coupled to” or “directly contact or overlap” the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled” or “contact or overlap” each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are “connected or coupled” or “contact or overlap” each other.

[0028] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe processes or operations of elements or configurations, or flows or steps in an operation, a process, a manufacturing method, unless used together with the term “directly” or “immediately,” these terms can be used to describe non-continuous or non-sequential processes or operations.

[0029] In addition, when any dimensions, relative dimensions, etc. are mentioned, even when the relevant description is not specified, the numerical value or corresponding information of the element or feature (e.g., level, range, etc.) should be considered to include a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external impacts, noise, etc.). In addition, the term “may” fully encompasses all meanings of the term “can.”

[0030] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 FIG. 1 is a diagram illustrating a display device 100 according to an embodiment of the disclosure.

[0032] Referring to Figure 1 The display device 100 according to an embodiment of the disclosure can include a display panel 110, a data driving circuit 120 and a gate driving circuit 130 for driving the display panel 110, and a timing controller 140 configured to control the data driving circuit 120 and the gate driving circuit 130.

[0033] Signal lines such as a plurality of data lines DL and a plurality of gate lines GL can be disposed on a substrate on the display panel 110. A plurality of sub-pixels SP electrically connected to the plurality of data lines DL and the plurality of gate lines GL can be disposed on the display panel 110.

[0034] The display panel 110 can include a display area AA in which an image is displayed and a non-display area NA in which an image is not displayed. A plurality of sub-pixels SP for displaying an image are disposed in the display area AA. The data driving circuit 120 and the gate driving circuit 130 can be mounted in the non-display area NA, or a pad portion connected to the data driving circuit 120 or the gate driving circuit 130 can be disposed.

[0035] The data driving circuit 120 is a circuit configured to drive the plurality of data lines DL and can supply a data voltage to the plurality of data lines DL. The gate driving circuit 130 is a circuit configured to drive the plurality of gate lines GL and can supply a gate signal (also referred to as a gate voltage or a scan signal) to the plurality of gate lines GL. The timing controller 140 can supply a data driving timing control signal DCS to the data driving circuit 120 to control the operation of the data driving circuit 120. The timing controller 140 can supply a gate driving timing control signal GCS for controlling the operation timing of the gate driving circuit 130 to the gate driving circuit 130.

[0036] The timing controller 140 can start scanning according to the timing implemented in each frame, convert input image data input from the outside to match a data signal format used by the data driving circuit 120, supply the converted image data DATA to the data driving circuit 120, and control the data driving at an appropriate time according to the scanning.

[0037] The timing controller 140 can receive various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input image data enable signal DE, and a clock signal CLK, as well as input image data, from the host system 150.

[0038] To control the data driving circuit 120 and the gate driving circuit 130, the timing controller 140 can receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, a clock signal CLK, and the like, and can generate various control signals (e.g., DCS, GCS, and the like) to be output to the data driving circuit 120 and the gate driving circuit 130.

[0039] The timing controller 140 can output various data driving timing control signals DCS including a source start pulse SSP, a source sampling clock SSC, and the like, in order to control the data driving circuit 120.

[0040] The timing controller 140 can output various gate driving timing control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like, in order to control the gate driving circuit 130.

[0041] The data driving circuit 120 receives the converted image data DATA from the timing controller 140 and drives a plurality of data lines DL.

[0042] The data driving circuit 120 can include one or more source driver integrated circuits SDIC.

[0043] Each source driver integrated circuit SDIC can be connected to the display panel 110 by a tape automated bonding (TAB) method, or can be connected to a bonding pad of the display panel 110 in a chip on glass (COG) method, or can be implemented in a chip on film (COF) method to be electrically connected to the display panel 110.

[0044] The gate driving circuit 130 can output a gate signal having an on-level voltage or a gate signal having an off-level voltage under the control of the timing controller 140. The gate driving circuit 130 can drive a plurality of gate lines GL by providing the plurality of gate lines GL with a gate signal having an on-level voltage.

[0045] The gate driving circuit 130 can be connected to the display panel 110 by a tape automated bonding (TAB) method, or can be connected to a bonding pad of the display panel 110 in a chip on glass (COG) method or a chip on panel (COP) method, or can be electrically connected to the display panel 110 according to a chip on film (COF) method.

[0046] The gate drive circuit 130 may be formed in the non-display area NA of the display panel 110 in a gate-in-panel (GIP) type. The gate drive circuit 130 may be provided on or connected to the substrate of the display panel 110. In the case of the gate-in-panel (GIP) type, the gate drive circuit 130 may be provided in the non-display area NA of the substrate. In the case of a chip-on-glass (COG) method or a chip-on-film (COF) method, the gate drive circuit 130 may be connected to the substrate of the display panel 110.

[0047] If the gate driving circuit 130 turns on a specific gate line GL, the data driving circuit 120 may convert image data received from the timing controller 140 into analog data voltages to be supplied to the plurality of data lines DL.

[0048] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on a driving method, a panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0049] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on a driving method, a panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0050] The timing controller 140 may be a timing controller used in conventional display technology, or may be a control device capable of further performing other control functions including a timing controller, or may be a circuit within a control device. The timing controller 140 may be implemented using various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0051] The timing controller 140 may be mounted on a printed circuit board (PCB), a flexible printed circuit board (FPCB), etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board (PCB), the flexible printed circuit board (FPCB), etc.

[0052] The timing controller 140 may transmit / receive signals to / from the data driving circuit 120 according to one or more predetermined interfaces. Here, for example, the interfaces may include a low voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0053] The timing controller 140 can include a storage medium such as one or more registers.

[0054] The display device 100 according to an embodiment of the disclosure can be a display device including a liquid crystal display (LCD) device having a backlight unit, or can be a self-emissive display device such as an organic light-emitting diode (OLED) display, a quantum dot display, and a micro light-emitting diode (micro LED) display.

[0055] In the case where the display device 100 according to an embodiment of the disclosure is an OLED display, each sub-pixel SP can include an organic light-emitting diode (OLED) that emits light as a light-emitting element. If the display device 100 according to an embodiment of the disclosure is a quantum dot display, each sub-pixel SP can include a light-emitting device made of a quantum dot, which is a semiconductor crystal that emits light by itself. In the case where the display device according to an embodiment of the disclosure is a micro LED display, each sub-pixel SP can include a micro LED as a light-emitting device that emits light by itself and is made of an inorganic material. Hereinafter, for convenience of description, the display device 100 according to an embodiment of the disclosure will be described taking an OLED display as an example, but the disclosure is not limited thereto.

[0056] Further, in the case where the display device 100 according to an embodiment of the disclosure is a self-emissive display device, the display panel 110 according to an embodiment of the disclosure can be a flexible display panel.

[0057] Figure 2 is a perspective view of a flexible display device 200 including the display device 100 according to an embodiment of the disclosure.

[0058] Referring to Figure 2 , the flexible display device 200 according to an embodiment of the disclosure can include the display device 100 and a back cover 210 disposed on a rear side of the display device 100. In addition, the flexible display device 200 according to an embodiment of the disclosure can further include a cover member 220 disposed on a rear side of the back cover 210.

[0059] The flexible display device 200 according to an embodiment of the disclosure can change to a flat shape or a curved shape. Specifically, in the flexible display device 200 according to an embodiment of the disclosure, the shape can change from a flat shape to a curved shape, or the shape can change from a curved shape to a flat shape. Accordingly, the flexible display device 200 according to an embodiment of the disclosure can be implemented in various forms such as a bendable display device, a foldable display device, or a rollable display device.

[0060] Referring to Figure 2According to embodiments of the present disclosure, the flexible display apparatus 200 can have one or more bending axes. For example, in the flexible display apparatus 200, the shape of the flexible display apparatus 200 can be changed such that the left and right sides of the display apparatus 100 face forward with respect to the bending axes.

[0061] The flexible display apparatus 200 can be folded based on the one or more bending axes.

[0062] The one or more bending axes can be located at the center of the flexible display apparatus 200, or can be positioned close to the edges away from the center.

[0063] Referring to Figure 2 The bending axes can extend from the upper side to the lower side of the flexible display apparatus 200. Alternatively, the bending axes can extend from the left side to the right side of the flexible display apparatus, or alternatively, from one side to the other side, or in a diagonal direction.

[0064] Further, in the case where the shape of the flexible display apparatus 200 is changed from a flat shape to a curved shape or from a curved shape to a flat shape, stress can be applied to components disposed within the display apparatus 100 and the back cover 210 due to the change in shape.

[0065] For example, the shape of the flexible display apparatus 200 can be changed from a normal flat shape in a normal phase during a transforming period. When the transforming period is terminated, the flexible display apparatus 200 can have a normal curved shape.

[0066] Alternatively, the shape of the flexible display apparatus 200 can be changed from a normal curved shape during a transforming period. When the transforming period is terminated, the shape of the flexible display apparatus can be a normal flat shape.

[0067] Compared to a normal state, more stress can be applied to the display apparatus 100 during the transforming period in which the shape change occurs. Accordingly, there can be a problem in which the state of junction between components of the display apparatus 100 deteriorates during the transforming period, and this problem needs to be addressed. For example, when the flexible display is repeatedly bent or folded, the display components can be damaged (e.g., cracked, not joined, disconnected, etc.).

[0068] Figure 3 is a diagram briefly illustrating the structure of a sub-pixel SP of a display apparatus according to an embodiment of the present disclosure and a configuration for sensing and compensating for a characteristic value (e.g., a voltage threshold, mobility, OLED deterioration) of the sub-pixel SP.

[0069] Referring to Figure 3Each of the plurality of sub-pixels SP can include a light emitting device ED, a drive transistor DRT, a scan transistor SCT, and a storage capacitor Cst.

[0070] The light emitting device ED can include a first electrode and a second electrode and a light emitting layer EL between the first electrode and the second electrode.

[0071] The first electrode of the light emitting device ED is a pixel electrode PE, and the second electrode of the light emitting device ED is a common electrode CE.

[0072] The pixel electrode PE of the light emitting device ED can be an electrode provided in each of the sub-pixels SP, and the common electrode CE can be an electrode commonly provided in all of the sub-pixels SP. Here, the pixel electrode PE can be an anode, and the common electrode CE can be a cathode. Alternatively, the pixel electrode PE can be a cathode, and the common electrode CE can be an anode.

[0073] For example, the light emitting device ED can be an organic light emitting diode OLED, a light emitting diode LED, or a quantum dot light emitting device.

[0074] The drive transistor DRT is a transistor for driving the light emitting device ED, and can include a first node N1, a second node N2, a third node N3, etc.

[0075] The first node N1 of the drive transistor DRT can be a gate node of the drive transistor DRT, and can be electrically connected to a source node or a drain node of the scan transistor SCT. The second node N2 of the drive transistor DRT can be a source node or a drain node of the drive transistor DRT, and can be electrically connected to a source node or a drain node of the sensing transistor SENT, and can also be electrically connected to the pixel electrode PE of the light emitting device ED. The third node N3 of the drive transistor DRT can be electrically connected to a drive voltage line DVL that provides a high potential drive voltage EVDD.

[0076] The scan transistor SCT can be controlled by a scan pulse SCAN, which is a kind of gate signal, and can switch electrical connection between the first node N1 of the drive transistor DRT and a data line DL. That is, the scan transistor SCT can be turned on or off according to a scan pulse SCAN provided from a scan line SCL, which is a kind of gate line GL, and can control electrical connection between the data line DL and the first node N1 of the drive transistor DRT.

[0077] The scan transistor SCT can be turned on by a scan pulse SCAN having an on level voltage, and can transfer a data voltage Vdata provided from the data line DL to the first node N1 of the drive transistor DRT.

[0078] Here, in a case where the scan transistor SCT is an n-type transistor, the on-level voltage of the scan pulse SCAN can be a high-level voltage. If the scan transistor SCT is a p-type transistor, the on-level voltage of the scan pulse SCAN can be a low-level voltage.

[0079] The storage capacitor Cst can be electrically connected to the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to a voltage difference between both ends, and functions to maintain the voltage difference between both ends for a predetermined frame time. Accordingly, during the predetermined frame time, the corresponding sub-pixel SP can emit light.

[0080] Referring to Figure 3 Each of the plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 according to the embodiment of the disclosure can further include a sensing transistor SENT.

[0081] The sensing transistor SENT can be controlled by a sensing pulse SENSE, which is a kind of gate signal, and can be electrically connected to the second node N2 of the driving transistor DRT and the reference voltage line RVL. That is, the sensing transistor SENT turns on or off according to the sensing pulse SENSE provided from the sensing line SENL, which is another kind of gate line GL, and can switch the electrical connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0082] The second node N2 of the driving transistor DRT is also referred to as a sensing node.

[0083] The sensing transistor SENT can be turned on by the sensing pulse SENSE having an on-level voltage, and can transfer an initialization voltage VpreR, VpreS, etc. provided from the reference voltage line RVL to the second node N2 of the driving transistor DRT. The reference voltage line RVL is also referred to as a sensing line.

[0084] The first initialization switch RPRE can switch the electrical connection between the reference voltage line RVL and the first initialization voltage providing node NpreR. The first initialization switch RPRE includes one end electrically connected to the reference voltage line RVL and the other end electrically connected to the first initialization voltage providing node NpreR.

[0085] The first initialization voltage VpreR is applied to the first initialization voltage providing node NpreR.

[0086] The second initialization switch SPRE can switch an electrical connection between the reference voltage line RVL and the second initialization voltage supply node NpreS. The second initialization switch SPRE includes one end electrically connected to the reference voltage line RVL and the other end electrically connected to the second initialization voltage supply node NpreS.

[0087] The second initialization voltage VpreS is applied to the second initialization voltage supply node NpreS. The voltage level of the second initialization voltage VpreS can be different from the voltage level of the first initialization voltage VpreR.

[0088] When a data voltage Vdata for image display is input to the data line DL, the first initialization voltage VpreR can be a voltage input for initializing a voltage of the second node N2 of the driving transistor DRT. For example, the data voltage Vdata for image display is supplied to the first node N1 of the driving transistor DRT, and the first initialization voltage VpreR is supplied to the second node N2 of the driving transistor DRT, so that a potential difference can be generated between both ends of the storage capacitor Cst.

[0089] When a voltage for sensing a characteristic value of the sub-pixel SP is input to the data line DL, the second initialization voltage VpreS can be a voltage input for initializing a voltage of the second node N2 of the driving transistor DRT. For example, the voltage Vdata for sensing a characteristic value of the sub-pixel SP is supplied to the first node N1 of the driving transistor DRT, and the second initialization voltage VpreS can be supplied to the second node N2 of the driving transistor DRT, so that a potential difference can be generated between both ends of the storage capacitor Cst.

[0090] The power management circuit can generate the first initialization voltage VpreR and / or the second initialization voltage VpreS and output the generated voltage to each node.

[0091] The sensing transistor SENT can be turned on by a sensing pulse SENSE having an on level voltage, and transfer a voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0092] Here, if the sensing transistor SENT is an n-type transistor, the on level voltage of the sensing pulse SENSE can be a high level voltage. If the sensing transistor SENT is a p-type transistor, the on level voltage of the sensing pulse SENSE can be a low level voltage.

[0093] When driving is performed to sense the characteristic value of the sub-pixel SP, the function of the sensing transistor SENT for transferring the voltage of the second node N2 of the drive transistor DRT to the reference voltage line RVL can be used. In this case, the voltage transferred to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0094] Each of the drive transistor DRT, the scan transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In the embodiments of the present disclosure, for ease of description, each of the drive transistor DRT, the scan transistor SCT, and the sensing transistor SENT is an n-type as an example.

[0095] The storage capacitor Cst does not necessarily have to be a parasitic capacitor (e.g., Cgs, Cgd) as an internal capacitor between the gate node and the source node (or the drain node) of the drive transistor DRT, but can be an external capacitor intentionally designed outside the drive transistor DRT.

[0096] The scan line SCL and the sensing line SENL can be different gate lines GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be independent. That is, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same or different.

[0097] Alternatively, the scan line SCL and the sensing line SENL can be the same gate line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP can be connected to one gate line GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same.

[0098] Figure 3 The structure of the sub-pixel SP illustrated is merely an example, and various modifications can be made by further including one or more transistors or further including one or more capacitors.

[0099] In addition, in Figure 3 , the sub-pixel SP structure is described assuming that the display device 100 is a self-emissive display device. However, in the case of the display device 100 being a liquid crystal display device, each sub-pixel SP can include a transistor and a pixel electrode.

[0100] Referring to Figure 3 The display device 100 according to the embodiment of the disclosure can include a line capacitor Crv1. The line capacitor Crv1 can be a capacitor element electrically connected to the reference voltage line RVL or a parasitic capacitor formed on the reference voltage line RVL.

[0101] Further, the data driving circuit described above can include one or more source driver integrated circuits SDICs.

[0102] Referring to Figure 3 The source driver integrated circuit SDIC can include a digital-to-analog converter DAC. The timing controller 140 can convert input image data according to a preset interface and output the converted image data to the digital-to-analog converter DAC.

[0103] In some cases, the source driver integrated circuit SDIC can further include an analog-to-digital converter ADC. The analog-to-digital converter ADC can sense a voltage value of the reference voltage line RVL. The voltage sensed by the analog-to-digital converter ADC can be a voltage reflecting a characteristic value of the sub-pixel SP.

[0104] The sampling switch SAM can be configured to switch electrical connection between the analog-to-digital converter ADC and the reference voltage line RVL. The sampling switch SAM can be provided in the source driver integrated circuit SDIC.

[0105] Further, the characteristic value of the sub-pixel SP can be a characteristic value of the driving transistor DRT or the light emitting device ED. The characteristic value of the driving transistor DRT can include a threshold voltage and a mobility of the driving transistor DRT. The characteristic value of the light emitting device ED can include a threshold voltage of the light emitting device ED.

[0106] The analog-to-digital converter ADC can receive an analog voltage, convert the analog voltage into a digital value, and output the digital value to the timing controller 140.

[0107] The timing controller 140 can include a memory 310 storing information of a characteristic value of the sub-pixel SP, and a compensation circuit 320 for performing a calculation for compensating for a change in the characteristic value of the sub-pixel SP based on the information stored in the memory 310.

[0108] The information for compensating for the characteristic value of the sub-pixel SP can be stored in the memory 310. For example, information on a threshold voltage and a mobility of the driving transistor DRT of each of the plurality of sub-pixels SP can be stored in the memory 310, or information on a threshold voltage of the light emitting device ED included in the sub-pixel SP can be stored in the memory 310.

[0109] Information on the threshold voltage of the light emitting device ED can be stored in a look-up table LUT of the memory 310.

[0110] The compensation circuit 320 can calculate the degree of change of the characteristic value of the sub-pixel SP based on the digital value input from the analog-digital converter ADC and the characteristic value information of the sub-pixel SP stored in the memory 310. The characteristic value of the sub-pixel SP stored in the memory 310 can be updated based on the calculated information.

[0111] The timing controller 140 can convert the image data by reflecting the change in the characteristic value of the sub-pixel SP calculated by the compensation circuit 320 and output the converted image data to the digital-analog converter DAC.

[0112] The digital-analog converter DAC can output a data voltage Vdata in which the change in the characteristic value of the sub-pixel SP is reflected to the data line DL.

[0113] The above-described process of sensing and compensating for the change in the characteristic value of the sub-pixel SP is also referred to as a "sub-pixel characteristic value compensation process".

[0114] Figure 4 Components configured to provide various voltages to the display panel 110 in a display device according to an embodiment of the disclosure are illustrated.

[0115] Referring to Figure 4 , a display device according to an embodiment of the disclosure can include one or more circuit films CF connected to the display panel 110, and a source driver integrated circuit SDIC mounted on the circuit film CF.

[0116] Referring to Figure 4 , one end of the circuit film CF can be connected to the display panel 110. One end of the circuit film CF can be bonded to a pad portion of the display panel 110. The circuit film CF can be bonded to the pad portion located on the front surface of the display panel 110 and bent in the rear direction of the display panel 110.

[0117] The other end of the circuit film CF can be connected to the source printed circuit board SPCB.

[0118] The source printed circuit board SPCB can be connected to the other end of the one or more circuit films CF. For example, referring to Figure 4 , one source printed circuit board SPCB can be connected to the first to eighth circuit films CF1 to CF8.

[0119] The source printed circuit board SPCB can be electrically connected to the control printed circuit board CPCB through a connection member.

[0120] For example, the connection member can be implemented as a flexible flat cable (FFC). The flexible flat cable (FFC) can be connected to the connectors CNT provided on the source printed circuit board SP CB and the control printed circuit board CPCB, respectively, and can be electrically connected between the source printed circuit board SP CB and the control printed circuit board CPCB.

[0121] The timing controller 140 can be mounted on the control printed circuit board CPCB. The power management circuit 410 can also be mounted on the control printed circuit board CPCB. One control printed circuit board CPCB can be connected to two or more source printed circuit boards SP CB.

[0122] Further, referring to Figure 4 In a case where the display panel 110 is a flexible display panel, the shape of the display panel 110 can be changed.

[0123] For example, as Figure 2 indicated, the display apparatus 100 can be bent based on a bending axis extending in a vertical direction during a transformation period. Accordingly, the shape of the display panel 110 can also be bent based on the bending axis.

[0124] If the display panel 110 is bent, stress can be applied to the circuit film CF configured to electrically connect the display panel 110 and the source printed circuit board SP CB.

[0125] Specifically, in a direction of both ends of the source printed circuit board SP CB, the stress can act more strongly, and a stronger force can be applied to the circuit films (e.g., CF1 and CF8) connected at both ends of the source printed circuit board SP CB.

[0126] Accordingly, the junction between the display panel 110 and the circuit film CF can be weakened. For example, the junction of the circuit film CF connected to both ends of the source printed circuit board SP CB to which the maximum stress is applied can be poor (e.g., one of the circuit films CF can be peeled off or disconnected).

[0127] Accordingly, there is a need for a method for easily detecting the junction state of one or more circuit films CF. Further, there is a need for a method to increase the durability and prolong the lifespan of the display apparatus by adaptively changing the transformation characteristic value (e.g., the length of the transformation period, the bending curvature, etc.) of the display apparatus based on the junction state of the circuit film CF.

[0128] Figure 5 The circuit film CF is specifically exemplified, and a plurality of circuit films CF can be included in the display apparatus.

[0129] Referring to Figure 5The source driver integrated circuit SDIC can be mounted on the circuit film CF. The source driver integrated circuit SDIC can be disposed on the circuit film CF in a chip on film (COF) type.

[0130] The circuit film CF can include one or more first pins 510a and one or more second pins 510b connected to the display panel, and one or more third pins 520a and one or more fourth pins 520b connected to the source printed circuit board SPCB.

[0131] The one or more first pins 510a are configured to output a data voltage transmitted from the source driver integrated circuit SDIC to the display panel.

[0132] The one or more second pins 510b can be electrically connected to the fourth pins 520b. The circuit film CF can further include wires 530 for electrically connecting the second pins 510b with the fourth pins 520b. The circuit film CF can further include wires 530 for electrically connecting the source driver integrated circuit SDIC with the first pins 510a. The circuit film CF can further include wires 530 for electrically connecting the third pins 520a with the source driver integrated circuit SDIC.

[0133] A direct current (DC) voltage (e.g., a low potential driving voltage EVSS, a first initialization voltage VpreR, etc.) transmitted from the source printed circuit board SPCB can be input to the one or more fourth pins 520b.

[0134] An analog-to-digital converter reference voltage VTRA transmitted from the source printed circuit board SPCB can be input to the one or more fourth pins 520b.

[0135] An analog-to-digital converter can convert an input analog voltage into a digital value within a preset range and output the digital value. A relationship between the input analog voltage and the converted digital value can have linearity represented as a linear function. For certain reasons, an anomaly in which an analog voltage value input to the analog-to-digital converter cannot be converted into a digital value using linearity, an anomaly in which a slope of the linear function fluctuates, or an anomaly in which an offset value fluctuates can occur. The analog-to-digital converter reference voltage VTRA can be input to the analog-to-digital converter, and a digital value output from the analog-to-digital converter can be detected, so that it can be checked whether an anomaly occurs in the analog-to-digital converter.

[0136] In a case in which the analog-to-digital converter is located inside the source driver integrated circuit SDIC, the analog-to-digital converter reference voltage VTRA can be input to the source driver integrated circuit SDIC.

[0137] The voltage input to the fourth pin 520b can be transmitted to the second pin 510b through the wire 530. One or more second pins 510b can transmit the DC voltage transmitted through the wire 530 to the display panel.

[0138] Image data DATA input from the timing controller can be input to one or more third pins 520a. The image data DATA can be image data converted according to a preset interface (e.g., an LVDS interface, etc.). Data driving control signals input from the timing controller can be input to one or more third pins 520a.

[0139] The image data DATA input to one or more third pins 520a can be transmitted to the source driver integrated circuit SDIC through the wire 530.

[0140] The source driver integrated circuit SDIC can output a data voltage to one or more first pins 510a based on the input image data DATA.

[0141] One or more first pins 510a and one or more second pins 510b can be connected to a pad portion provided on the display panel. One or more third pins 520a and one or more fourth pins 520b can be electrically connected to a pad portion of the source printed circuit board SPCB.

[0142] The circuit films CF can be bent at the bending line such that at least a portion of the circuit films CF is disposed on the rear side of the display panel (e.g., the circuit films CF can be bent or folded such that they can be disposed behind the display panel).

[0143] Figure 6 An electrical connection relationship for detecting a degree of junction of the circuit films CF in a display device according to an embodiment of the disclosure is illustrated.

[0144] Reference Figure 6 In the display device according to an embodiment of the disclosure, an input voltage Vin transmitted to a pad portion 610 (hereinafter, referred to as a first pad portion) of the source printed circuit board SPCB through the source printed circuit board SPCB is input to a pad portion 620 (hereinafter, referred to as a second pad portion) of the display panel 110 through the circuit films CF.

[0145] The second pad portion 620 receiving the input voltage Vin can transmit an output voltage Vout. Alternatively, the input voltage Vin input to the second pad portion 620 can be input to the first pad portion 610 through the circuit films CF, and the first pad portion 610 can transmit the output voltage Vout.

[0146] The output voltage Vout output from the first land portion 610 or the output voltage Vout output from the second land portion 620 can be input to an analog-to-digital converter. In a case where the analog-to-digital converter is located inside the source driver integrated circuit SDIC, the output voltage Vout can be input to the source driver integrated circuit SDIC.

[0147] Hereinafter, it is assumed for convenience of description that the output voltage Vout output from the first land portion 610 is input to the analog-to-digital converter located inside the source driver integrated circuit SDIC, however, the present disclosure is not limited thereto.

[0148] The above-described embodiments will be described in detail below.

[0149] The input voltage Vin transmitted from the source printed circuit board SP CB is input to the first pin 612a located on the first land portion 610. The input voltage Vin input to the first pin 612a can be transmitted to the film pin FP of the circuit film CF, which can correspond to the fourth pin 520b of the fourth land portion 520. Figure 5 The input voltage Vin transmitted to the circuit film CF can be input to the second pin 622a located on the second land portion 620.

[0150] The voltage level of the input voltage Vin transmitted to the second pin 622a can vary depending on the degree of engagement between the circuit film CF and the first pin 612a.

[0151] If the degree of engagement between the circuit film CF and the first pin 612a is good, the contact area between the circuit film CF and the first pin 612a is wide, and the resistance of the first pin 612a can be small. However, if the degree of engagement between the circuit film CF and the first pin 612a is poor, the contact area between the circuit film CF and the first pin 612a is narrow, and the resistance of the first pin 612a can be high. For example, if there is good electrical contact between the pin of the circuit film CF and the first and second land portions, the resistance is low, but if there is poor electrical contact (e.g., due to peeling / disengagement), the resistance is high.

[0152] Accordingly, a voltage reflecting the degree of engagement between the first pin 612a and the circuit film CF can be input to the second pin 622a.

[0153] The voltage input to the second pin 622a can be input to the third pin 622b located in the second land portion 620. The voltage input to the third pin 622b can reflect the degree of engagement between the circuit film CF and the second pin 622a.

[0154] If the degree of engagement between the circuit film CF and the second pin 622a is good, the contact area between the circuit film CF and the second pin 622a is wide, and the resistance of the second pin 622a can be small. However, if the degree of engagement between the circuit film CF and the second pin 622a is poor, the contact area between the circuit film CF and the second pin 622a is narrow, and the resistance of the second pin 622a can be high.

[0155] Therefore, the voltage reflecting the degree of engagement between the second pin 622a and the circuit film CF can be input to the third pin 622b. In addition, as described above, the voltage reflecting the degree of engagement between the first pin 612a and the circuit film CF can be input to the second pin 622a.

[0156] The voltage input to the third pin 622b can be input to the fourth pin 612b located in the first land portion 610. The voltage input to the fourth pin 612b can reflect the degree of engagement between the circuit film CF and the third pin 622b. The reason why the voltage input to the fourth pin 612b can reflect the degree of engagement between the circuit film CF and the third pin 622b is as described above.

[0157] For the same reason as described above, the output voltage Vout output from the fourth pin 612b can reflect the degree of engagement between the circuit film CF and the fourth pin 612b.

[0158] Referring to Figure 6 The output voltage Vout output from the fourth pin 612b can be input to the source driver integrated circuit SDIC.

[0159] Therefore, the output voltage Vout input to the source driver integrated circuit SDIC can reflect the degree of engagement between the circuit film CF and the source printed circuit board SPCB. In addition, the output voltage Vout input to the source driver integrated circuit SDIC can reflect the degree of engagement between the circuit film CF and the display panel 110.

[0160] The input voltage Vin input to the first pin 612a can be a voltage generated and output from the power management circuit 410 (refer to Figure 4 ).

[0161] The voltage level of the input voltage Vin can be set to a value of a voltage level that can be converted into one digital value by the analog-digital converter. For example, the input voltage Vin can be the analog-digital converter reference voltage VRTA.

[0162] Further, the first pad portion 610 can include one or more image data transmission pins 614 for transmitting image data DATA to the source driver integrated circuit SDIC. The second pad portion 620 can include one or more data voltage transmission pins 624 for transmitting a data voltage Vdata output from the source driver integrated circuit SDIC to a corresponding data line. The one or more image data transmission pins 614 can be bonded to the circuit film CF. The one or more data voltage transmission pins 624 can be bonded to the circuit film CF.

[0163] Figure 6 The illustrated circuit film CF can be Figure 4 At least one or more of the illustrated first to eighth circuit films CF1 to CF8.

[0164] Figure 4 All of the illustrated first to eighth circuit films CF1 to CF8 can have a line structure for inputting an output voltage Vout to the source driver integrated circuit SDIC as Figure 6 illustrated.

[0165] In some cases, Figure 4 Among the illustrated first to eighth circuit films CF1 to CF8, the circuit films located at both ends of the source printed circuit board SPCB (e.g., the first circuit film CF1 and the eighth circuit film CF8) can have a line structure for inputting an output voltage Vout to the source driver integrated circuit SDIC. The remaining circuit films other than the circuit films located at both ends of the source printed circuit board SPCB (e.g., the second to seventh circuit films CF2 to CF7) can not have a line structure as Figure 6 illustrated. Thus, the circuit films CF located in an area in which stress is concentrated due to bending can have a line structure as Figure 6 illustrated. For example, Figure 6 The circuit film CF of the type illustrated can be located in an area of a flexible display expected to experience the greatest bending stress.

[0166] Figure 7 The principle that the output voltage Vout varies according to the degree of bonding of the circuit film in a display apparatus according to an embodiment of the disclosure is schematically illustrated.

[0167] Referring to Figure 7 In a display apparatus according to an embodiment of the disclosure, the voltage level of the voltage output from the second pin 622a to the third pin 622b can vary according to the degree of bonding between the circuit film and the first pin 612a and the degree of bonding between the circuit film and the second pin 622a.

[0168] That is, the degree of engagement between the circuit film and the first pin 612a with respect to the voltage output from the second pin 622a can be used as the variable resistor 710.

[0169] In addition, the degree of engagement between the circuit film and the second pin 622a with respect to the voltage output from the second pin 622a can be used as the variable resistor 710.

[0170] Further, the voltage level of the output voltage Vout output from the fourth pin 612b can vary depending on the degree of engagement between the circuit film and the third pin 622b and the degree of engagement between the circuit film and the fourth pin 612b.

[0171] That is, the degree of engagement between the circuit film and the third pin 622b with respect to the output voltage Vout output from the fourth pin 612b can be used as the variable resistor 720.

[0172] In addition, the degree of engagement between the circuit film and the fourth pin 612b with respect to the output voltage Vout output from the fourth pin 612b can be used as the variable resistor 720.

[0173] Therefore, the voltage level of the output voltage Vout output from the fourth pin 612b can reflect the degrees of engagement between the circuit film and the first pin 612a, the second pin 622a, the third pin 622b, and the fourth pin 612b.

[0174] Figure 8 An analog-to-digital converter ADC to which the output voltage Vout is input in the display device according to an embodiment of the disclosure is exemplified.

[0175] Referring to Figure 8 In the display device according to an embodiment of the disclosure, the output voltage Vout is input to the analog-to-digital converter ADC.

[0176] The analog-to-digital converter ADC can receive the output voltage Vout, convert the output voltage into a corresponding digital value, and output a current state signal CSS. The analog-to-digital converter ADC can be located within the above-described source driver integrated circuit SDIC. Therefore, the current state signal CSS can be output from the source driver integrated circuit SDIC.

[0177] The current state signal CSS output from the analog-to-digital converter ADC can be input to the timing controller 140.

[0178] The timing controller 140 can calculate information about the engagement state of the circuit film based on the current state signal CSS input from the analog-to-digital converter ADC.

[0179] For example, the timing controller 140 can determine, based on the input current state signal CSS, that the bonding state of the circuit film is in a normal range state, in a slightly worse state, or in a very worse state.

[0180] Further, for example, if the voltage level of the output voltage Vout input to the analog-to-digital converter ADC is 6V, the analog-to-digital converter ADC can output a value 1023 as the current state signal CSS. The value 1023 can be a value indicating that the bonding state of the circuit film is in a normal range state.

[0181] The timing controller 140 can determine, based on the input value 1023, that the bonding state of the circuit film is in a normal range.

[0182] As another example, in a case where the voltage level of the output voltage Vout input to the analog-to-digital converter ADC is 3V, the analog-to-digital converter ADC can output a value 500 as the current state signal CSS. The value 500 can be a value indicating that the bonding state of the circuit film is in a slightly worse state.

[0183] The timing controller 140 can determine, based on the input value 500, that the bonding state of the circuit film is in a slightly worse state.

[0184] As another example, if the voltage level of the output voltage Vout input to the analog-to-digital converter ADC is 0V, the analog-to-digital converter ADC can output a value 0 as the current state signal CSS. The value 0 can be a value indicating that the bonding state of the circuit film is in a very worse state (e.g., the bonding is broken and there is a disconnection between the pin and the pad).

[0185] The timing controller 140 can determine, based on the input value 0, that the bonding state of the circuit film is in a very worse state.

[0186] Further, referring to Figure 8 , the timing controller 140 can output a bending control signal BCS to the host system 150 based on the input current state signal CSS. For example, the timing controller 140 can further include a memory 810 for outputting a different bending control signal BCS based on the input current state signal CSS.

[0187] The host system 150 can adjust the flexibility characteristics of the display apparatus based on the bending control signal BCS input from the timing controller 140.

[0188] For example, the host system 150 can adjust a bending speed of the display apparatus or a bending angle of the display apparatus based on the bending control signal BCS input from the timing controller 140. Accordingly, further deterioration of the bonded state of the circuit film can be reduced or prevented (e.g., as the bonded state becomes worse, control can be performed so as to limit or prevent bending of the flexible display so as to limit or stop damage).

[0189] Figure 9 FIG. 11 is another diagram illustrating an electrical connection relationship for detecting a degree of bonding of a circuit film CF in a display apparatus according to an embodiment of the present disclosure.

[0190] Referring to FIG. 11, Figure 9 In order to detect a degree of bonding of a circuit film CF in a display apparatus according to an embodiment of the present disclosure, an input voltage Vin can be input to a first pin 612a located on a first pad portion 610.

[0191] The input voltage Vin input to the first pin 612a can be input to a wide area pin 622 located in a second pad portion 620 through the circuit film CF.

[0192] The wide area pin 622 can be connected to two or more thin film pins FP. For example, the wide area pin 622 in the second pad portion 620 can overlap with at least three pins in the circuit film CF.

[0193] A voltage transmitted from the wide area pin 622 is output to one or more pins located on the first pad portion 610 via internal wires.

[0194] Referring to FIG. 11, Figure 9 A fourth pin 612b and a fifth pin 612c located on the first pad portion 610 can transmit an output voltage Vout to an analog-to-digital converter. The analog-to-digital converter can be located within a source driver integrated circuit. In this case, the output voltage Vout can be input to the source driver integrated circuit SDIC.

[0195] A voltage level of the output voltage Vout transmitted by the fourth pin 612b can reflect a degree of bonding between the circuit film CF and the first pin 612a and a degree of bonding between the circuit film CF and the wide area pin 622. The voltage level of the output voltage Vout transmitted by the fourth pin 612b can reflect a degree of bonding between the fourth pin 612b and the circuit film CF.

[0196] The voltage level of the output voltage Vout transmitted from the fifth pin 612c can reflect the degree of bonding between the circuit film CF and the first pin 612a and the degree of bonding between the circuit film CF and the wide-area pin 622. The voltage level of the output voltage Vout transmitted from the fifth pin 612c can reflect the degree of bonding between the fifth pin 612c and the circuit film CF.

[0197] Therefore, the voltage level of the output voltage Vout transmitted from the fourth pin 612b and the voltage level of the output voltage Vout transmitted from the fifth pin 612c can collectively reflect the degree of bonding between the first pin 612a and the wide-area pin 622.

[0198] In addition, by comparing the voltage level of the output voltage Vout transmitted from the fourth pin 612b and the voltage level of the output voltage Vout transmitted from the fifth pin 612c, it is possible to have the same effect as comparing the degree of bonding between the fourth pin 612b and the circuit film CF and the degree of bonding between the fifth pin 612c and the circuit film CF with each other (for example, since both of these pins should receive the same voltage from the wide-area pin 622, assuming that the bonding condition is ideal). Therefore, it is possible to specifically detect the position of the pin that is poorly bonded to the circuit film CF (for example, it is possible to isolate and identify each pin having a poor bonding state).

[0199] The first pin 612a can be located on the inner side compared to the fourth pin 612b and the fifth pin 612c. Therefore, it is possible to relatively reduce the possibility of bonding defects between the first pin 612a and the circuit film CF. Therefore, by comparing the voltage level of the output voltage Vout output from the fourth pin 612b and the voltage level of the output voltage Vout output from the fifth pin 612c, it is possible to relatively easily and accurately estimate the position of the poorly bonded pin.

[0200] Therefore, in the display device according to the embodiment of the present disclosure, it is possible to specifically identify and determine the bonding state between each pin located in the pad portion and the circuit film CF.

[0201] Figure 10 is a diagram schematically illustrating that the output voltages Vout1 and Vout2 vary depending on the degree of bonding of the circuit film in the display device according to the embodiment of the present disclosure (for example, Vout1 and Vout2 should be the same voltage from the wide-area pin 622 when the bonding condition is ideal, but as the bonding deteriorates, Vout1 and Vout2 can start to deviate and be different from each other).

[0202] Referring to Figure 10 The input voltage Vin input to the first pin 612a is input to the wide-area pin 622 through the circuit film.

[0203] The voltage input to the wide area pin 622 can be transferred to the fourth pin 612b, and the first output voltage Vout1 can be output from the fourth pin 612b. The voltage input to the wide area pin 622 can be transferred to the fifth pin 612c, and the second output voltage Vout2 can be output from the fifth pin 612c.

[0204] Accordingly, a change in the resistance value in the first voltage transfer path 1010 can be reflected in the first output voltage Vout1 output through the second voltage transfer path 1020. The change in the resistance value in the first voltage transfer path 1010 can be reflected in the second output voltage Vout2 output through the third voltage transfer path 1030.

[0205] In addition, the first output voltage Vout1 can reflect a bonding state between the fourth pin 612b and the circuit film. The second output voltage Vout2 can reflect a bonding state between the fifth pin 612c and the circuit film. Accordingly, the display device according to the embodiment of the disclosure can easily determine the position of the pin having a poor bonding state.

[0206] Figure 11 An analog-to-digital converter ADC to which the first output voltage Vout1 and the second output voltage Vout2 are selectively input in the display device according to the embodiment of the disclosure is exemplified.

[0207] Referring to Figure 11 The display device according to the embodiment of the disclosure can further include a switch circuit 1110 electrically connected to an input terminal of the analog-to-digital converter ADC.

[0208] The switch circuit 1110 can include one or more switching elements. For example, the switch circuit 1110 can be implemented as a multiplexer circuit including one or more switching elements.

[0209] An output terminal of the switch circuit 1110 can be electrically connected to the input terminal of the analog-to-digital converter ADC.

[0210] The switch circuit 1110 can include two or more input terminals. For example, the first output voltage Vout1 and the second output voltage Vout2 can be input to the two or more input terminals of the switch circuit 1110, respectively.

[0211] Accordingly, the first output voltage Vout1 or the second output voltage Vout2 can be selectively input to the input terminal of the analog-to-digital converter ADC according to the operation of the switch circuit 1110.

[0212] The timing controller 140 can output a sampling signal SAMP for controlling the switching timing of the switching circuit 1110. The operation timing of the switching circuit 1110 can be controlled by the sampling signal SAMP.

[0213] According to the operation of the switching circuit 1110, the analog-digital converter ADC can output the current state signal CSS according to the voltage level of the first output voltage Vout1, or can output the current state signal CSS according to the voltage level of the second output voltage Vout2.

[0214] The timing controller 140 can specifically determine the position of the pin having a poor bonding state based on the current state signal CSS. The timing controller 140 can specifically determine the degree of bonding defect of the pin having a poor bonding state (for example, how much the voltage differs from the expected voltage when the bonding condition is ideal, since the timing controller 140 can measure the voltage).

[0215] The timing controller 140 can output a bending control signal BCS based on the input current state signal CSS.

[0216] The host system 150 can receive the bending control signal BCS and adjust the bending characteristics or the flexibility characteristics of the display device.

[0217] Figure 12 The characteristics of the host system adjusting the bending characteristics based on the bending control signal BCS are exemplified.

[0218] Referring to Figure 12 The timing controller 140 can output the bending control signal BCS to the host system 150.

[0219] The bending control signal BCS can include a first bending control signal BCSa output through a first communication line and a second bending control signal BCSb output through a second communication line.

[0220] The first bending control signal BCSa output through the first communication line can have different digital values according to whether the bonding state of the circuit film is relatively good or poor.

[0221] For example, in the case where the value of the first bending control signal BCSa output through the first communication line is 0, it can mean that the bonding state of the circuit film is relatively good. If the value of the first bending control signal BCSa is 1, it means that the bonding state of the circuit film is relatively poor.

[0222] The host system 150 can not change the bending characteristics based on the value of the first bending control signal BCSa output through the first communication line, or can stop the bending. For example, the timing controller 140 can act as a type of regulator device that can control how much and how fast the flexible display device is allowed to bend based on internal bonding conditions between components. In this way, image quality can be protected, and the lifespan of the display device can be extended.

[0223] In addition, the timing controller 140 can output a second bending control signal BCSb to the host system 150 through the second communication line in order to adaptively change the bending characteristics of the display device according to the degree of poor bonding of the circuit film.

[0224] For example, if the bonding state of the display device is good, the timing controller 140 can output a combination (0, 0) of the first bending control signal BCSa and the second bending control signal BCSb to the host system 150. The host system 150 can control the display panel to normally perform a bending operation (e.g., can normally perform a bending operation at a relatively fast speed and a high degree of bending).

[0225] For example, if the bonding state of the display device is slightly poor, the timing controller 140 can output a combination (0, 1) of the first bending control signal BCSa and the second bending control signal BCSb to the host system 150. The host system 150 can reduce or lower the bending speed of the display device, thereby mitigating stress that can act on the circuit film (e.g., slowing down the bending operation).

[0226] For example, if the bonding state of the display device becomes worse, the timing controller 140 can output a combination (1, 0) of the first bending control signal BCSa and the second bending control signal BCSb to the host system 150. The host system 150 can further mitigate stress acting on the circuit film by increasing the bending curvature of the display device (e.g., reducing the amount of bending allowed so that there is a larger radius of curvature).

[0227] For example, if the bonding state of the display device is the worst, the timing controller 140 can output a combination (1, 1) of the first bending control signal BCSa and the second bending control signal BCSb to the host system 150. The host system 150 can control the display device not to bend, so that stress to the circuit film does not act.

[0228] Accordingly, the timing controller 140 can output a signal for changing the bending characteristics (e.g., bending speed, bending curvature, etc.) of the display device to the host system 150 according to the bonding state of the circuit film. When the internal bonding state of the circuit film deteriorates over time, the host system 150 can dynamically change the bending characteristics of the display device in stages.

[0229] The host system 150 can perform the above-described operations based on values pre-stored in the lookup table 1200.

[0230] Accordingly, the display device according to an embodiment of the disclosure can provide a display device in which the flexibility characteristic is adjusted according to the connection state between components of the flexible display device.

[0231] The above description regarding the voltage transmitted through the circuit film CF is as follows.

[0232] Referring to FIG. 12, the display device according to an embodiment of the disclosure can include a display panel 620, a source printed circuit board 610, and a circuit film CF. Figure 6 Figure 12 The voltage output from the second pin 622a or the voltage output from the third pin 622b can be a voltage reflecting the degree of the bonding defect between the circuit film and the first pin 612a. In addition, the voltage output from the fourth pin 612b can be a voltage reflecting the degree of the bonding defect between the circuit film and the second pin 622a and the third pin 622b.

[0233] Accordingly, the voltage output from the pad portion 620 of the display panel (hereinafter, refer to Figure 6 ) or the pad portion 610 of the source printed circuit board (hereinafter, refer to Figure 6 ) can be measured through the wire of the circuit film, and thus it is easy to determine whether the circuit film CF has a bonding defect. For example, the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board can be input to an analog-to-digital converter, and thus it is easy to identify the degree of the bonding defect of the circuit film CF.

[0234] Accordingly, in the display device according to an embodiment of the disclosure, the display panel (or the display device) can have different flexibility characteristics according to the magnitude of the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board.

[0235] For example, in the case where the level of the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board and input to the analog-to-digital converter is included in a predetermined first range, the display panel can be normally bent.

[0236] For example, if the level of the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board and input to the analog-to-digital converter is included in a second range, which is a voltage level range lower than the first range, the bending speed of the display panel can be slowed down or reduced. The second range can be a predetermined voltage level section.

[0237] ​Also, for example, if the level of the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board and input to the analog-to-digital converter is included in a third range, which is a range of voltage levels lower than the first range, the bending curvature of the display panel can increase. The third range can be a preset range of voltage levels.

[0238] The third range and the second range can be non-overlapping ranges or overlapping ranges.

[0239] That is, in some cases, there can be a range of voltage levels in which the bending speed of the display panel becomes slower (the voltage level corresponds to the second range) and the curvature of the bending of the display panel also increases (the voltage level corresponds to the third range).

[0240] For example, if the level of the voltage output from the pad portion 620 of the display panel or the pad portion 610 of the source printed circuit board and input to the analog-to-digital converter is included in a fourth range, which is a range of voltage levels lower than the first range, the display panel can not enter the transformation period.

[0241] That is, if the voltage level input to the analog-to-digital converter is lower than a certain threshold voltage, it can be understood that the resistance is very large due to the bonding defect of the circuit film, and thus the display panel (or the display apparatus) can be controlled so that the flexible operation is no longer performed.

[0242] The above-described embodiments of the disclosure can be briefly summarized as follows.

[0243] The embodiments of the disclosure can provide a display apparatus 100 including a display panel 110 including a display area AA in which a plurality of sub-pixels are disposed and a non-display area NA located around the display area AA and in which a pad portion is disposed, a printed circuit board PCB including a pad portion for outputting a plurality of voltages input to the display panel 110, a circuit film CF including one end connected to a first pad portion 610 which is the pad portion of the printed circuit board PCB and the other end connected to a second pad portion 620 which is the pad portion of the display panel 110, and an analog-to-digital converter ADC for receiving a voltage output from the first pad portion 610 or a voltage output from the second pad portion 620 through a wire 530 of the circuit film CF electrically connecting the first pad portion 610 and the second pad portion 620 and outputting a digital value (e.g., CSS) corresponding to the input voltage (e.g., Vout).

[0244] Embodiments of the disclosure can provide a display device 100 that is a flexible display device bent to a predetermined angle during a transformation period.

[0245] In the analog-to-digital converter ADC of an embodiment of the disclosure, the level of the input voltage (e.g., Vout) can vary depending on the degree of bonding between one end of the circuit film CF and the printed circuit board PCB and the degree of bonding between the other end of the circuit film CF and the display panel 110.

[0246] In an embodiment of the disclosure, a plurality of data lines DL electrically connected to a plurality of sub-pixels SP can be disposed in the display area AA, and a source driver integrated circuit SDIC for supplying a data voltage Vdata to the plurality of data lines DL can be disposed on the circuit film CF in a chip on film (COF) type.

[0247] In an embodiment of the disclosure, the analog-to-digital converter ADC can be located within the source driver integrated circuit SDIC.

[0248] Embodiments of the disclosure can provide a display device 100 further including a timing controller 140 for receiving a digital value (e.g., CSS) output from the analog-to-digital converter ADC.

[0249] In an embodiment of the disclosure, the timing controller 140 can output a bend control signal BCS for adjusting a bending characteristic of the display device 100 based on the input digital value (e.g., CSS).

[0250] Embodiments of the disclosure can provide a display device 100 including a host system 150 that receives the bend control signal BCS.

[0251] In an embodiment of the disclosure, the host system 150 can adjust the length of a transformation period during which the shape of the display device 100 is changed.

[0252] In an embodiment of the disclosure, the host system 150 can adjust a bending curvature at which the display device 100 is bent.

[0253] In an embodiment of the disclosure, the host system 150 can control the display device 100 not to enter the transformation period.

[0254] In an embodiment of the disclosure, the timing controller 140 can output a control signal BCS for controlling the flexible characteristic of the display device 100 differently by stages based on the bonding state between the display panel 110 and the circuit film CF.

[0255] In an embodiment of the disclosure, an analog-to-digital converter ADC can receive a voltage from two different pins (e.g., fourth pin 612b and fifth pin 612c) located on the first pad portion 610, respectively.

[0256] An embodiment of the disclosure can provide a display device 100 further including a switching circuit 1110 for switching an electrical connection between the two different pins and the analog-to-digital converter ADC.

[0257] In an embodiment of the disclosure, the printed circuit board PCB can be a source printed circuit board (SPCB) to which a voltage input to the display panel is transmitted.

[0258] An embodiment of the disclosure can provide a display device 100 including a display panel 110 including a display area AA in which a plurality of sub-pixels SP are disposed and a non-display area NA located around the display area AA and in which a pad portion is disposed, a printed circuit board PCB including a pad portion for outputting a plurality of voltages input to the display panel 110, a circuit film CF including one end connected to a first pad portion 610 that is the pad portion of the printed circuit board PCB and another end connected to a second pad portion 620 that is the pad portion of the display panel 110, and an analog-to-digital converter ADC for receiving a voltage output from the first pad portion 610 or a voltage output from the second pad portion 620 through a wire 530 of the circuit film CF electrically connecting the first pad portion 610 and the second pad portion 620, wherein a flexible characteristic of the display panel 110 varies according to a voltage value input to the analog-to-digital converter ADC.

[0259] In an embodiment of the disclosure, when the voltage value input to the analog-to-digital converter ADC decreases, a bending speed of the display panel can decrease.

[0260] In an embodiment of the disclosure, when the voltage value input to the analog-to-digital converter ADC decreases, a bending curvature of the display panel bent can increase (e.g., by changing a previously allowed curvature radius from a small radius (e.g., a large amount of bending) to a larger curvature radius (e.g., a small amount of bending), an allowed amount of bending can decrease.

[0261] In an embodiment of the disclosure, when the voltage value input to the analog-to-digital converter ADC decreases, the display device 100 can be fixed to a normal state without entering a transformation period.

[0262] In this way, embodiments of the present disclosure can accurately detect and identify damaged internal joint conditions and their specific locations within a flexible display device, and dynamically adjust the allowable bending characteristics of the flexible display device based on the identified internal joint conditions to maintain high image quality and extend the life of the flexible display device. In addition, embodiments of the present disclosure can better detect defective or damaged flexible display devices during manufacturing.

[0263] The above description is given to enable those skilled in the art to implement and use the technical ideas of the present disclosure, and is provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown, but is in the widest scope consistent with the claims. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical ideas within their equivalent scope should be interpreted as included within the scope of the present disclosure.

[0264] CROSS-REFERENCE TO RELATED APPLICATIONS

[0265] This application claims priority to Korean Patent Application No. 10-2021-0192882 filed in Korea on December 30, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A display device, comprising: a display panel including a display area and a non-display area, wherein a plurality of sub-pixels are disposed in the display area, the non-display area is positioned adjacent to the display area and has a second pad portion disposed in the non-display area; a printed circuit board, the printed circuit board comprising a first pad portion for outputting a plurality of voltages to the display panel; a circuit film, the circuit film comprising a first end and a second end, the first end being connected to the first pad portion of the printed circuit board, and the second end being connected to the second pad portion of the display panel, wherein the printed circuit board includes a power management circuit configured to generate a voltage and transmit the generated voltage as an input voltage to the circuit film; an analog-to-digital converter configured to receive a voltage output from the first pad portion or a voltage output from the second pad portion through a line in the circuit film electrically connecting the first pad portion and the second pad portion, and output a digital value corresponding to the received voltage for use in detecting a bonding state of at least one internal component in the display device; a timing controller configured to receive the digital value output from the analog-to-digital converter, wherein the timing controller is further configured to output a bending control signal based on the digital value, the bending control signal being used to adjust a bending characteristic of the display device; and a host system configured to receive the bending control signal and change the bending characteristic of the display device based on the received bending control signal, If the bonding state of the display device is poor, the host system is configured to reduce a bending speed of the display device or increase a bending curvature of the display device in order to relieve stress acting on the circuit film.

2. The display device according to claim 1, wherein The display device is a flexible display device configured to bend by a predetermined amount based on a predetermined angle during a transformation period.

3. The display device according to claim 1, wherein In the analog-to-digital converter, the level of the received voltage varies according to the degree of bonding between the first end of the circuit film and the first pad portion of the printed circuit board and the degree of bonding between the second end of the circuit film and the second pad portion of the display panel.

4. The display device according to claim 1, further comprising: a plurality of data lines electrically connected to the plurality of sub-pixels and disposed in the display area; as well as A source driver integrated circuit is configured to supply data voltages to the plurality of data lines, the source driver integrated circuit being provided on the circuit film in a chip-on-film type.

5. The display device according to claim 4, wherein The analog-to-digital converter is located within the source driver integrated circuit. The display device according to claim 1 , wherein: The host system is further configured to adjust a length of a transition period during which the shape of the display device changes from a curved state to a non-curved state or from the non-curved state to the curved state.

7. The display device according to claim 1, wherein The host system is further configured to adjust a curvature at which the display device is bent during the transition period.

8. The display device according to claim 1, wherein The host system is also configured to prevent the display device from entering a transition period based on the engagement state of the at least one internal component within the display device, during which the shape of the display device changes from a bent state to a non-bent state or from the non-bent state to the bent state.

9. The display device according to claim 1, wherein The timing controller is further configured to output a control signal based on a bonding state between the display panel and the circuit film, the control signal being used to control at least one flexibility characteristic of the display device differently in stages.

10. The display device according to claim 1, wherein The analog-to-digital converter is further configured to receive voltages from two different pins located on the first pad portion, respectively. 11 . The display device according to claim 10 , further comprising a switch circuit configured to switch electrical connections between the two different pins and the analog-to-digital converter.

12. The display device according to claim 1, wherein The printed circuit board is a source printed circuit board to which a voltage input to the display panel is transmitted.

13. A display device, comprising: a display panel including a display area and a non-display area, wherein a plurality of sub-pixels are disposed in the display area, the non-display area is positioned adjacent to the display area and has a second pad portion disposed in the non-display area; a printed circuit board, the printed circuit board comprising a first pad portion for outputting a plurality of input voltages to the display panel; a circuit film, the circuit film comprising a first end and a second end, the first end being connected to the first pad portion of the printed circuit board, and the second end being connected to the second pad portion of the display panel, wherein the printed circuit board includes a power management circuit configured to generate a voltage and transmit the generated voltage as an input voltage to the circuit film; and an analog-to-digital converter configured to receive an input voltage output from the first pad portion or an input voltage output from the second pad portion through a line in the circuit film electrically connecting the first pad portion and the second pad portion, wherein the flexibility characteristics of the display panel vary according to the input voltage input to the analog-to-digital converter, and When the input voltage input to the analog-to-digital converter decreases, the bending speed of the display panel decreases, or the curvature of the display panel increases.

14. A display device, comprising: a flexible display panel, the flexible display panel comprising a plurality of sub-pixels and a second pad portion; a printed circuit board, the printed circuit board comprising a first pad portion for outputting a plurality of voltages to the flexible display panel; a circuit film, the circuit film comprising a first end and a second end, the first end being connected to the first pad portion of the printed circuit board, and the second end being connected to the second pad portion of the flexible display panel, wherein the printed circuit board includes a power management circuit configured to generate a voltage and transmit the generated voltage as an input voltage to the circuit film; A controller configured to: receiving a voltage output from the first pad portion or a voltage output from the second pad portion through a line in the circuit film electrically connecting the first pad portion and the second pad portion, and outputting a value corresponding to an engagement state of at least one internal component within the display device; a timing controller configured to receive the value output from the controller, wherein the timing controller is further configured to output a bending control signal based on the value, the bending control signal being used to adjust a bending characteristic of the display device; and a host system configured to receive the bending control signal and change the bending characteristic of the display device based on the received bending control signal, If the bonding state is poor, the host system is configured to reduce a bending speed of the display device or increase a bending curvature of the display device in order to relieve stress acting on the circuit film.

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