Gate drive circuit and display device

Abstract

Embodiments of the present disclosure relate to a gate drive circuit and a display device, by a start capacitor that controls a voltage level of a Q node at a timing at which the gate drive circuit outputs a gate signal having an on level and a pump capacitor that controls the voltage level of the Q node in a period in which the gate signal having the on level is output, a level of the gate signal can be stably maintained even in a case in which the gate signal having the on level is output for a long time.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a gating drive circuit and a display device. Background Technology

[0002] The display device may include multiple sub-pixels disposed in the display panel and various circuits driving the multiple sub-pixels.

[0003] The display device may include, for example, a gating drive circuit that controls the driving timing of multiple sub-pixels and a data drive circuit that provides data voltages corresponding to image data to the multiple sub-pixels.

[0004] If the output signal of the gating drive circuit that controls the driving timing of the sub-pixel is not properly provided to the sub-pixel, a driving abnormality of the sub-pixel may occur. As a result, the quality of the image displayed on the display panel may deteriorate. Summary of the Invention

[0005] Embodiments of this disclosure can provide a display device that can stably maintain the output signal provided by the gating drive circuit to the sub-pixels disposed in the display panel and improve the driving characteristics of the display panel.

[0006] Embodiments of this disclosure may provide a display device comprising: a display panel having a plurality of sub-pixels; a plurality of gate lines electrically connected to at least one of the plurality of sub-pixels; and a gate driving circuit outputting gate signals to the plurality of gate lines, wherein the gate driving circuit comprises: a pull-up transistor controlled by a voltage level of a Q node; a pull-down transistor controlled by a voltage level of a QB node; a pump capacitor electrically connected between a Q node and an input terminal of a gate clock signal; and a pump transistor electrically connected between the pump capacitor and the Q node and controlled by the gate signals output to the gate lines.

[0007] Embodiments of this disclosure may provide a display device comprising: a plurality of sub-pixels disposed in a display panel; a first gating driving circuit that outputs a first gating signal to the plurality of sub-pixels; and a second gating driving circuit that outputs a second gating signal to the plurality of sub-pixels, wherein, in a frame period, the period during which the second gating signal has a conduction level is greater than the period during which the first gating signal has a conduction level, and wherein the second gating driving circuit includes: a pump control unit electrically connected between a Q node and an input terminal of a gating clock signal, and controlled by the voltage level of the second gating signal.

[0008] Embodiments of this disclosure may provide a gating drive circuit comprising: a pull-up transistor controlled by the voltage level of a Q node and electrically connected between an input terminal of a first gating drive voltage and an output terminal of a gating signal; a pull-down transistor controlled by the voltage level of a QB node and electrically connected between an input terminal of a second gating drive voltage and an output terminal of the gating signal; a pump capacitor electrically connected between a Q node and an input terminal of a gating clock signal; a pump transistor electrically connected between the pump capacitor and the Q node; and a feed transistor electrically connected between the gate node of the pump transistor and the input terminal of the first gating drive voltage and controlled by the voltage level of the gating signal.

[0009] According to various embodiments of this disclosure, since the voltage level of the Q node included in the gating drive circuit is kept within a constant range by using the gating signal that controls the emission period of the sub-pixel, the performance of the gating drive circuit can be improved while stably maintaining the level of the gating signal output during the emission period. Attached Figure Description

[0010] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a diagram that schematically illustrates the configuration of a display device according to an embodiment of the present disclosure;

[0012] Figure 2 This is a diagram illustrating an example of a circuit structure for a sub-pixel included in a display device according to an embodiment of the present disclosure;

[0013] Figure 3 This is a diagram illustrating an example of the configuration of a gating drive circuit according to an embodiment of the present disclosure;

[0014] Figure 4 This is a diagram illustrating an example of the configuration of the light-emitting control block of a gating drive circuit according to an embodiment of the present disclosure;

[0015] Figures 5 to 7 This is a diagram illustrating an example of the circuit structure of the light-emitting control block of the gating drive circuit according to an embodiment of the present disclosure; and

[0016] Figure 8 This is an example Figure 7 A diagram showing an example of the driving timing of the light-emitting control block of the gating drive circuit. Detailed Implementation

[0017] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented by way of example, and the same reference numerals and symbols can be used to denote the same or similar components even if the components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein are omitted where it is determined that the description may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of other components, unless used with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0018] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from other elements.

[0019] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that the first element can not only be "directly connected or joined" or "directly contact or overlap" with the second element, but also that a third element can be "inserted" between the first element and the second element, or that the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0020] When time-related terms such as “after,” “following,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, treatment, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0021] Furthermore, when referring to any size, relative size, etc., even without a specified description, it should be assumed that the numerical or corresponding information of the component or feature (e.g., level, range, etc.) includes the tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0022] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 1This is a diagram schematically illustrating the configuration of a display device 100 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The display device 100 may include a display panel 110, as well as a gating drive circuit 120, a data drive circuit 130, and a controller 140 for driving the display panel 110.

[0025] The display panel 110 may include a display area AA with multiple sub-pixels SP and a non-display area located outside the display area AA.

[0026] Multiple gate lines GL and multiple data lines DL can be arranged on the display panel 110. Multiple sub-pixels SP can be located in the area where the gate lines GL and data lines DL intersect.

[0027] The gating drive circuit 120 is controlled by the controller 140 and sequentially outputs scanning signals to multiple gating lines GL arranged on the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0028] According to one driving method, the gating driving circuit 120 may include one or more gating driver integrated circuits (GDICs) and may be located only on one side of the display panel 110, or may be located on both sides of the display panel 110.

[0029] Each gate driver integrated circuit (GDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-board (TAB) method or a chip-on-glass (COG) method. Alternatively, each gate driver integrated circuit (GDIC) can be implemented using an in-panel gate-in-patch (GIP) method and then directly disposed on the display panel 110. Alternatively, the gate driver integrated circuit (GDIC) can be integrated and disposed on the display panel 110. Alternatively, each gate driver integrated circuit (GDIC) can be implemented using a chip-on-film (COF) method with component mounting on a film connected to the display panel 110.

[0030] The data driving circuit 130 receives image data DATA from the controller 140 and converts the image data DATA into an analog data voltage Vdata. Then, the data driving circuit 130 outputs the data voltage Vdata to each data line DL according to the timing of the scan signal applied through the gate line GL, so that each of the plurality of sub-pixels SP emits light with a brightness according to the image data DATA.

[0031] The data drive circuit 130 may include one or more source driver integrated circuits (SDICs).

[0032] Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc.

[0033] Each source driver integrated circuit (SDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-board (TAB) method or a chip-on-glass (COG) method. Alternatively, each source driver integrated circuit (SDIC) can be directly disposed on the display panel 110. Alternatively, the source driver integrated circuit (SDIC) can be integrated and arranged on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method. In this case, each source driver integrated circuit (SDIC) can be mounted on a film connected to the display panel 110 and can be electrically connected to the display panel 110 via wiring on the film.

[0034] The controller 140 can provide various control signals to the gating drive circuit 120 and the data drive circuit 130, and control the operation of the gating drive circuit 120 and the data drive circuit 130.

[0035] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the gating drive circuit 120 and the data drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0036] The controller 140 can allow the gating drive circuit 120 to output a scan signal according to the timing implemented in each frame. The controller 140 can convert data signals received from the outside into a data signal format that conforms to the data signal format used in the data drive circuit 130, and then output the converted image data to the data drive circuit 130.

[0037] The controller 140 receives various timing signals (including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal DE, clock signal CLK, etc.) and image data from an external source (e.g., a host system).

[0038] The controller 140 can use various timing signals received from the outside to generate various control signals, and can output the control signals to the gating drive circuit 120 and the data drive circuit 130.

[0039] For example, in order to control the gating drive circuit 120, the controller 140 can output various gating control signals GCS, including gating start pulse GSP, gating shift clock GSC, gating output enable signal GOE, etc.

[0040] The strobe start pulse (GSP) controls the start timing of operation for one or more strobe driver integrated circuits (GDICs) constituting the strobe drive circuit 120. The strobe shift clock (GSC), serving as a clock signal common to one or more strobe driver integrated circuits (GDICs), controls the shift timing of the scan signal. The strobe output enable signal (GOE) specifies timing information for one or more strobe driver integrated circuits (GDICs).

[0041] In addition, in order to control the data drive circuit 130, the controller 140 can output various data control signals DCS, including source start pulse SSP, source sampling clock SSC, source output enable signal SOE, etc.

[0042] The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SSC is a clock signal used to control the timing of data sampling in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0043] The display device 100 may also include a power management integrated circuit for providing various voltages or currents to the display panel 110, the gating drive circuit 120, the data drive circuit 130, etc., or for controlling the various voltages or currents to be provided to them.

[0044] Each subpixel SP is an area defined by the intersection of the gate line GL and the data line DL, and at least one circuit element including a light-emitting element may be disposed in the subpixel SP.

[0045] For example, when the display device 100 is an organic light-emitting display device, organic light-emitting diodes (OLEDs) and various circuit elements can be disposed on multiple sub-pixels SP. Since the current supplied to the organic light-emitting diodes (OLEDs) is controlled by various circuit elements, each sub-pixel SP can represent a brightness corresponding to image data.

[0046] Alternatively, in some cases, light-emitting diodes (LEDs) or micro LEDs (μLEDs) can be disposed on sub-pixels (SPs).

[0047] Figure 2 This is a diagram illustrating an example of a circuit structure of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0048] Reference Figure 2 Each of the plurality of sub-pixels SP disposed in the display panel 110 may include a light-emitting element ED. The sub-pixel SP may include a driving transistor DRT that drives the light-emitting element ED.

[0049] The light-emitting element (ED) can be electrically connected, for example, between the third node N3 and the voltage line providing the first driving voltage VDD. The first driving voltage VDD can be, for example, a high-potential driving voltage. The third node N3 can be the source node or drain node of the driving transistor DRT.

[0050] In addition to the light-emitting element ED and the driving transistor DRT, the sub-pixel SP may include at least one transistor and at least one capacitor.

[0051] For example, a subpixel SP may include six transistors SWT1, SWT2, SWT3, SWT4, SWT5, and SWT6. The subpixel SP may also include a storage capacitor Cstg and a light-emitting element capacitor Ced.

[0052] Figure 2 An example of the circuit structure of a sub-pixel SP is shown. The number of transistors, capacitors, and signal lines included in the sub-pixel SP, and their connection structure, can vary. For example, the sub-pixel SP may also include sensing lines and sensing transistors. Furthermore, Figure 2 An example is given where the transistors included in the sub-pixel SP are P-type, but at least some of the transistors included in the sub-pixel SP can be N-type. When at least some of the transistors included in the sub-pixel SP are N-type, the configuration and operation described below can be modified accordingly. These modified configurations and operations also fall within the scope of this application.

[0053] The first switching transistor SWT1 can be electrically connected between the first node N1 and the data line DL, which provides the data voltage Vdata. The first switching transistor SWT1 can be controlled by the first scan signal SCAN1 provided through the gating line GL.

[0054] The second switching transistor SWT2 can be electrically connected between the second node N2 and the fourth node N4. The second node N2 can be the gate node of the driving transistor DRT. The fourth node N4 can be the drain node or source node of the driving transistor DRT. The second switching transistor SWT2 can be controlled by the first scan signal SCAN1 provided through the gating line GL.

[0055] The third switching transistor SWT3 can be electrically connected between the first node N1 and the voltage line providing the reference voltage Vref. The third switching transistor SWT3 can be controlled by the light emission control signal EM provided through the gating line GL.

[0056] The fourth switching transistor SWT4 can be electrically connected between the fourth node N4 and the voltage line providing the second drive voltage VSS. The fourth switching transistor SWT4 can be controlled by a light emission control signal provided through the gating line GL.

[0057] The fifth switching transistor SWT5 can be electrically connected between the fourth node N4 and the voltage line providing the reference voltage Vref. The fifth switching transistor SWT5 can be controlled by the second scan signal SCAN2 provided through the gating line GL.

[0058] The sixth switching transistor SWT6 can be electrically connected between the third node N3 and the voltage line providing the first drive voltage VDD. The sixth switching transistor SWT6 can be controlled by the first scan signal SCAN1 provided through the gating line GL.

[0059] The storage capacitor Cstg can be electrically connected between the first node N1 and the second node N2. The light-emitting element capacitor Ced can be electrically connected between the third node N3 and the voltage line providing the first driving voltage VDD. The light-emitting element capacitor Ced can be a capacitor intentionally disposed outside the light-emitting element, or it can be a capacitor inside the light-emitting element ED.

[0060] The switching transistor SWT can be controlled by the scan signal SCAN and the light emission control signal EM provided through the gate line GL, and the light emission element ED can be driven.

[0061] For example, the switching transistor SWT can be turned on according to the timing of providing the first scan signal SCAN1 and the second scan signal SCAN2. The timing of providing the first scan signal SCAN1 can be different from the timing of providing the second scan signal SCAN2. For example, the timing of providing the second scan signal SCAN2 can be before the timing of providing the first scan signal SCAN1. The second scan signal SCAN2 can be the scan signal SCAN output at the timing of driving the previous strobe line GL.

[0062] When the second scan signal SCAN2 is provided, the fifth switching transistor SWT5 can be turned on. The reference voltage Vref can then be provided to the fourth node N4, and the fourth node N4 can be initialized.

[0063] The period during which the second scan signal SCAN2 with a conduction level is provided can be called the "initialization period".

[0064] When the first scan signal SCAN1 is provided, the first switching transistor SWT1, the second switching transistor SWT2, and the sixth switching transistor SWT6 can be turned on.

[0065] When the first switching transistor SWT1 is turned on, the data voltage Vdata can be applied to the first node N1. When the second switching transistor SWT2 and the sixth switching transistor SWT6 are turned on, the threshold voltage of the driving transistor DRT, reflecting the voltage of the first driving voltage VDD, can be applied to the second node N2.

[0066] The period during which the first scan signal SCAN1 with a conduction level is provided can be called the "data write period".

[0067] When the light emission control signal EM is provided, the third switching transistor SWT3 and the fourth switching transistor SWT4 can be turned on.

[0068] The voltage level of the first node N1 can be changed according to the reference voltage Vref. The voltage of the second node N2, which is connected to the first node N1, can also be changed. When the drive transistor DRT is turned on according to the change in the voltage of the second node N2, the drive transistor DRT can output a drive current corresponding to the data voltage Vdata.

[0069] When the driving transistor DRT is driving and the fourth switching transistor SWT4 is in the on state, the light-emitting element ED can represent the brightness corresponding to the driving current.

[0070] The period during which a light-emitting control signal EM with a conduction level is provided can be called the "light-emitting period".

[0071] As described above, the sub-pixel SP can be operated by a scan signal SCAN and an emission control signal EM provided via a gate line GL. The circuits providing the scan signal SCAN and the emission control signal EM can be configured as separate circuits, or they can be integrated circuits.

[0072] Figure 3 This is a diagram illustrating an example configuration of the gating drive circuit 120 according to an embodiment of the present disclosure.

[0073] Reference Figure 3 The selection drive circuit 120 may include a scanning block and a light emission control block.

[0074] The scanning block and the light-emitting control block included in the gating drive circuit 120 can be provided with various control signals (e.g., gating start signal, gating clock signal) and various voltages (e.g., first gating drive voltage, second gating drive voltage), and can be driven.

[0075] The scan block can include multiple circuit elements, can be supplied with various voltages and control signals, and can output the scan signal SCAN to the gating line GL.

[0076] For example, a scan block can be operated by providing a scan start signal SVST and a scan clock signal SCLK. The carry signal from the timing output of the scan block's output scan signal SCAN can be input as the scan start signal SVST for the next scan block. Furthermore, the signal from the timing output of the scan block's output scan signal SCAN can be input as the scan reset signal SRST for the previous scan block (e.g., the immediately preceding scan block, or the scan block preceding the immediately preceding scan block).

[0077] The number of scan clock signals SCLK can vary depending on the driving method of the scan block. Figure 3 The scan block shown represents an example controlled by four scan clock signals SCLK1, SCLK2, SCLK3, and SCLK4.

[0078] A first scan drive voltage SVGL and a second scan drive voltage SVGH can be provided to the scan block. The scan block can provide a scan signal SCAN to the sub-pixel SP, which is using at least one of the first scan drive voltage SVGL or the second scan drive voltage SVGH, according to the timing of the scan start signal SVST and the scan clock signal SCLK.

[0079] The light-emitting control block can be driven by the light-emitting control start signal EVST and the light-emitting control clock signal ECLK, and can output the light-emitting control signal EM to the gate line GL.

[0080] The carry signal from the timing output of the light emission control signal EM by the light emission control block can be used as the light emission control start signal EVST and input to the next light emission control block. Since the light emission control block controls the light emission period of the sub-pixel SP, the light emission control signal EM can remain on for a relatively long period. The light emission control block can terminate the output of the light emission control signal EM according to a separately provided light emission control reset signal ERST.

[0081] Depending on the driving method of the light-emitting control block, the number of light-emitting control clock signals ECLK can be different. Figure 3 The illustrated light control block represents an example controlled by two light control clock signals, ECLK1 and ECLK2.

[0082] A first light-emitting control drive voltage EVGL and a second light-emitting control drive voltage EVGH can be provided to the light-emitting control block. The light-emitting control block can output the light-emitting control signal EM by using the first light-emitting control drive voltage EVGL and the second light-emitting control drive voltage EVGH, based on the timing of the light-emitting control start signal EVST and the light-emitting control clock signal ECLK.

[0083] As described above, the subpixel SP can be driven by the scan signal SCAN output by the scan block and the light emission control signal EM output by the light emission control block, and can display an image based on the image data.

[0084] Since the emission control signal EM remains on during the emission period of the sub-pixel SP, the ratio of the period during which the emission control block outputs the emission control signal EM with an on level in a frame period can be relatively high.

[0085] The embodiments of this disclosure can provide a method for stably maintaining the on-state level of the light emission control signal EM output by the light emission control block during the light emission period of a frame period.

[0086] Figure 4 This is a diagram illustrating an example of the configuration of the light-emitting control block of the gating drive circuit 120 according to an embodiment of the present disclosure.

[0087] Reference Figure 4 The light emission control block may include a pull-up transistor Tup, a pull-down transistor Tdn, a Q node control unit 121, a QB node control unit 122, and a pump control unit 123.

[0088] The pull-up transistor Tup can be electrically connected between the input terminal of the first light-emitting control drive voltage EVGL and the output terminal of the light-emitting control signal EM. The pull-up transistor Tup can be controlled by the voltage level of the Q node EQ. The first light-emitting control drive voltage EVGL can, for example, be a low-level drive voltage.

[0089] The pull-up transistor Tup can control the output of the light-emitting control signal EM with a conduction level to the gate line GL.

[0090] The pull-down transistor Tdn can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the output terminal of the light-emitting control signal EM. The pull-down transistor Tdn can be controlled by the voltage level of the QB node EQB. The second light-emitting control drive voltage EVGH can, for example, be a high-level drive voltage.

[0091] The pull-down transistor Tdn can control the output of the light emission control signal EM with a cutoff level to the gate line GL.

[0092] Q-node control unit 121 may include various circuit elements and can control the voltage level of Q-node EQ. QB-node control unit 122 may include various circuit elements and can control the voltage level of QB-node EQB.

[0093] The pump control unit 123 can be electrically connected to the Q node EQ. At least one of the following can be provided to the pump control unit 123: a light emission control start signal EVST, a light emission control clock signal ECLK, a first light emission control drive voltage EVGL, or a second light emission control drive voltage EVGH.

[0094] The pump control unit 123 can input a light-emitting control signal EM output through the output terminal of the light-emitting control signal EM. The pump control unit 123 operates according to the voltage level of the light-emitting control signal EM.

[0095] The pump control unit 123 can operate according to the light emission control signal EM, and the voltage level of the Q node EQ can be controlled by using various signals and voltages input to the pump control unit 123.

[0096] The pump control unit 123 can, for example, control the voltage level of the Q node EQ during the period when the light emission control signal EM with a conduction level is output. The pump control unit 123 can control the voltage level of the Q node EQ to maintain the level of the pull-up transistor Tup during the output period of the light emission control signal EM with a conduction level.

[0097] During the period when the light emission control signal EM with a conduction level is output, the voltage level of the Q node EQ can be stably maintained by the pump control unit 123.

[0098] Because the voltage level of the Q node EQ is maintained stably, even when the period of outputting the light emission control signal EM with the conduction level is long, the light emission control signal EM with the conduction level can be stably provided to the sub-pixel SP.

[0099] The pump control unit 123 may include various circuit elements for controlling the voltage level of the Q node EQ according to the light emission control signal EM.

[0100] Figures 5 to 7 This is a diagram illustrating an example of the circuit structure of the light-emitting control block of the gating drive circuit 120 according to an embodiment of the present disclosure. Figure 8 This is an example Figure 7 A diagram showing an example of the driving timing of the light-emitting control block of the gating drive circuit 120.

[0101] Reference Figure 5 This example illustrates the case where the light-emitting control block is controlled by the first light-emitting control clock signal ECLK1.

[0102] The pump control unit 123 included in the light emission control block can be electrically connected to the Q node of the light emission control block. The pump control unit 123 can be electrically connected to the output terminal of the light emission control signal EM.

[0103] The pump control unit 123 may include at least one capacitor and at least one transistor.

[0104] For example, the pump control unit 123 may include a pump capacitor Cpump, a pump transistor Tpump, a feed transistor Tfeed, and a clock transistor Tpclk.

[0105] The pump capacitor Cpump can be electrically connected between the Q node EQ and the input terminal of the first light-emitting control clock signal ECLK1. The pump transistor Tpump can be electrically connected between the pump capacitor Cpump and the Q node EQ. The gate node of the pump transistor Tpump can be electrically connected to the node between the pump transistor Tpump and the pump capacitor Cpump. The node between the pump transistor Tpump and the pump capacitor Cpump can also be the source node of the pump transistor Tpump.

[0106] The feed transistor Tfeed can be electrically connected between the gate node of the pump transistor Tpump and the input terminal of the first light emission control drive voltage EVGL. The gate node of the feed transistor Tfeed can be electrically connected to the output terminal of the light emission control signal EM. The feed transistor Tfeed can operate according to the voltage level of the light emission control signal EM.

[0107] The clock transistor Tpclk can be electrically connected between the pump capacitor Cpump and the input terminal of the first light-emitting control clock signal ECLK1. The clock transistor Tpclk can operate according to the voltage level of the light-emitting control start signal EVST.

[0108] A light-emitting control start signal EVST with a conduction level can be provided to the light-emitting control block during the driving period of the light-emitting control block. The light-emitting control start signal EVST with a conduction level can be provided to the Q node EQ through the first transistor T1.

[0109] When the voltage level of node Q (EQ) becomes the level of the pull-up transistor Tup, the first light-emitting control drive voltage EVGL can be output to the output terminal of the light-emitting control signal EM. This allows the output of the light-emitting control signal EM with a conduction level.

[0110] A light emission control signal EM with a conduction level can be applied to the gate node of the feed transistor Tfeed included in the pump control unit 123 while being provided to the gate line GL.

[0111] The feed transistor Tfeed can be turned on by the light-emitting control signal EM with a conduction level.

[0112] When the feed transistor Tfeed is turned on, the first light-emitting control drive voltage EVGL can be applied to the gate node of the pump transistor Tpump. The voltage level of the first light-emitting control drive voltage EVGL can be the same as the level at which the pump transistor Tpump is turned on.

[0113] When the pump transistor Tpump is turned on, the pump capacitor Cpump can be electrically connected to the Q node EQ. The pump capacitor Cpump and the Q node EQ can be connected.

[0114] During the period when the light-emitting control block is being driven, the clock transistor Tpclk can be turned on by the light-emitting control start signal EVST. The first light-emitting control clock signal ECLK1 can be applied to the pump capacitor Cpump through the clock transistor Tpclk.

[0115] The first light emission control clock signal ECLK1 can be a pulse-shaped signal. The first light emission control clock signal ECLK1 can include a first level (e.g., low level) and a second level (e.g., high level). The first light emission control clock signal ECLK1 can be a signal that alternates between the first level and the second level, and the sum of the periods at the first level and the periods at the second level can be called a cycle.

[0116] During the period when the light emission control start signal EVST is at the on level, the level of the first light emission control clock signal ECLK1 can change multiple times. When the level of the first light emission control clock signal ECLK1 changes, the voltage level of the Q node EQ may fluctuate because the pump capacitor Cpump is connected to the Q node EQ.

[0117] For example, refer to Figure 5 In the example shown in Example 1, when the first light-emitting control clock signal ECLK1 changes from low to high, the voltage level of the Q node EQ can remain stable without fluctuation because the pump transistor Tpump, which is electrically connected to the gate node and the source node, is located between the pump capacitor Cpump and the Q node EQ.

[0118] When the first light-emitting control clock signal ECLK1 changes from high to low, the voltage level of the Q node EQ can be reduced because the current can flow from the pump transistor Tpump to the pump capacitor Cpump.

[0119] The structure, which connects the first light emission control clock signal ECLK1 and the Q node EQ via a pump capacitor Cpump and a pump transistor Tpump, allows the voltage level of the Q node EQ to decrease when the first light emission control clock signal ECLK1 changes from high to low.

[0120] During the period when the light-emitting control block outputs the light-emitting control signal EM with a conduction level, the voltage level of the Q node EQ can be stably maintained at the level of the pull-up transistor Tup.

[0121] Since the voltage level of Q node EQ can decrease according to the cycle of the first light emission control clock signal ECLK1, the difference between the voltage level of Q node EQ and the level of the pull-up transistor Tup can gradually increase during the period when the light emission control signal EM with the conduction level is output.

[0122] For example, refer to Figure 5 In the example shown in Example 2, the voltage level of the Q node EQ can be reduced during the timing of outputting the light emission control signal EM with an on level. During the period in which the output of the light emission control signal EM with an on level is maintained (e.g., the portion indicated by 501), the voltage level of the Q node EQ can be gradually reduced.

[0123] Since the voltage level of the Q node EQ remains stably low during the period when the light control signal EM with the conduction level is output, the light control signal EM with the conduction level of the light control block can be stably output.

[0124] Furthermore, the timing of the output of the light-emitting control signal EM, which has a conduction level obtained from the light-emitting control start signal EVST, may not require the pump capacitor Cpump to control the voltage level of the Q-node EQ. For example, as indicated by 502, the voltage level of the Q-node EQ may not be low enough.

[0125] In the structure of the light emission control block including the pump control unit 123, by sufficiently reducing the voltage level of the Q node EQ during the timing of the output of the light emission control signal EM with the on level, the embodiments of the present disclosure can maintain the voltage level of the Q node EQ completely stably during the driving period of the light emission control block.

[0126] Reference Figure 6 The light emission control block may include a pump control unit 123 electrically connected to the Q node EQ and operating according to the light emission control signal EM. The light emission control block may include a start-up capacitor Cboot electrically connected between the Q node EQ and the output terminal of the light emission control signal EM.

[0127] The Q-node EQ can be connected to the output terminal of the light control signal EM via the start-up capacitor Cboot. The voltage level of the Q-node EQ can fluctuate according to the voltage level fluctuations at the output terminal of the light control signal EM.

[0128] For example, refer to Figure 6In the example shown in Example 1 (e.g., the part indicated by 601), during the timing of the output of the light control signal EM with a conduction level, the start capacitor Cboot can reduce the voltage level of the Q node EQ as the level of the light control signal EM decreases.

[0129] During the period when the light emission control signal EM is kept at the on level, the voltage level of the Q node EQ can be reduced by pumping the capacitor Cpump according to the cycle of the first light emission control clock signal ECLK1.

[0130] exist Figure 6 In the example shown in Example 2 (e.g., the part indicated by 602), the difference between the voltage level of the Q node EQ and the voltage level of the light emission control signal EM can increase during the timing of the output light emission control signal EM having a conduction level. Subsequently, in the part indicated, for example, by 603, the pump capacitor Cpump can operate according to the first light emission control clock signal ECLK1, and the voltage level of the Q node EQ can gradually decrease.

[0131] When the output light-emitting control signal EM with a conduction level is timed, the voltage level of Q node EQ can decrease by a greater amount than the voltage level of Q node EQ decreases according to the cycle of the first light-emitting control clock signal ECLK1.

[0132] When the output of the light control signal EM with a conduction level is timed, the voltage level of the Q node EQ can be sufficiently reduced by activating the capacitor Cboot.

[0133] During the period when the output of the light control signal EM with a conduction level is maintained, the voltage level of the Q node EQ can be kept at a sufficiently low voltage level by the pump capacitor Cpump.

[0134] During the emission period of sub-pixel SP, the level of the emission control signal EM output by the emission control block can be stably maintained.

[0135] Figure 7 A specific example of the circuit structure of the light-emitting control block including the pump control unit 123 described above is given. Figure 8 Example Figure 7 The example shown is a driving timing of the light-emitting control block.

[0136] Reference Figure 7 and Figure 8In addition to the pull-up transistor Tup and the pull-down transistor Tdn, the light-emitting control block may include multiple transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, Tup_c, Tdn_c, Tdmy, Tpump, Tfeed, Tpclk, Tprst and at least one capacitor Cpump, Cboot.

[0137] The first transistor T1 can be electrically connected between the input terminal of the light emission control start signal EVST and the Q' node EQ'. The first transistor T1 can operate according to the voltage level of the first light emission control clock signal ECLK1.

[0138] The second transistor T2 can be electrically connected between the input terminal of the light emission control start signal EVST and the gate node of the seventh transistor T7. The second transistor T2 can operate according to the voltage level of the first light emission control clock signal ECLK1.

[0139] The third transistor T3 can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the Q' node EQ'. The third transistor T3 can operate according to the voltage level of the QB node EQB.

[0140] The fourth transistor T4 can be electrically connected between the input terminal of the first light-emitting control drive voltage EVGL and the QB node EQB. The fourth transistor T4 can operate according to the voltage level of the node between the fifth transistor T5 and the sixth transistor T6.

[0141] The fifth transistor T5 and the sixth transistor T6 can be electrically connected between the input terminals of the first light-emitting control drive voltage EVGL and the second light-emitting control drive voltage EVGH. The fifth transistor T5 can operate according to the voltage level of the first light-emitting control drive voltage EVGL. The sixth transistor T6 can operate according to the voltage level of node Q' EQ'.

[0142] The seventh transistor T7 and the eighth transistor T8 can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the QB node EQB. The seventh transistor T7 can operate according to the signal provided by the second transistor T2. The eighth transistor T8 can operate according to the voltage level of the Q' node EQ'.

[0143] The ninth transistor T9 can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the Q node EQ. The tenth transistor T10 can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the output terminal of the light-emitting control signal EM. The ninth transistor T9 and the tenth transistor T10 can be operated according to the light-emitting control reset signal ERST.

[0144] The pull-up transistor Tup_c and pull-down transistor Tdn_c used for outputting the carry signal can be separately located in the light emission control block from the pull-up transistor Tup and pull-down transistor Tdn used for outputting the light emission control signal EM. A dummy transistor Tdmy can be electrically connected between node Q'EQ' and node Q'EQ.

[0145] The startup capacitor Cboot can be electrically connected between the output terminal of the Q node EQ and the light control signal EM.

[0146] The pump capacitor Cpump can be electrically connected between the Q node EQ and the input terminal of the first light control clock signal ECLK1.

[0147] The pump transistor Tpump can be electrically connected between the pump capacitor Cpump and the Q node EQ. The pump transistor Tpump can operate according to the signal provided by the feed transistor Tfeed.

[0148] The feed transistor Tfeed can be electrically connected between the gate node of the pump transistor Tpump and the input terminal of the first light emission control drive voltage EVGL. The feed transistor Tfeed can operate according to the voltage level of the light emission control signal EM.

[0149] The clock transistor Tpclk can be electrically connected between the pump capacitor Cpump and the input terminal of the first light-emitting control clock signal ECLK1. The clock transistor Tpclk can operate according to the voltage level of the light-emitting control start signal EVST.

[0150] The reset transistor Tprst can be electrically connected between the input terminal of the second light-emitting control drive voltage EVGH and the pump capacitor Cpump. The reset transistor Tprst can also be electrically connected to the gate node of the pump transistor Tpump. The reset transistor Tprst can operate according to the voltage level of the QB node EQB.

[0151] When a light-emitting control reset signal ERST with a conduction level is provided, the ninth transistor T9 and the tenth transistor T10 can be turned on, and the second light-emitting control drive voltage EVGH can be provided to the output terminals of the Q node EQ and the light-emitting control signal EM. The Q node EQ can be kept high, the QB node EQB can be kept low, and the light-emitting control signal EM can be output at the cutoff level.

[0152] An EVST signal with a conduction level can be provided to the luminescence control block during the frame period.

[0153] The level of Q node EQ can go low. The level of QB node EQB can go high. When the level of Q node EQ goes low, the pull-up transistor Tup can be turned on.

[0154] The first light-emitting control drive voltage EVGL can be output to the output terminal of the light-emitting control signal EM via the pull-up transistor Tup. This allows for the output of the light-emitting control signal EM with a conduction level. The voltage level of the Q node EQ can be reduced by the start-up capacitor Cboot according to the output of the light-emitting control signal EM with a conduction level.

[0155] The feed transistor Tfeed can be turned on during the period when the output light emission control signal EM has an on-level. Since the feed transistor Tfeed is in the on state, the first light emission control drive voltage EVGL can be applied to the gate node of the pump transistor Tpump. The pump transistor Tpump can remain in the on state during the period when the output light emission control signal EM has an on-level.

[0156] During the period when the light emission control start signal EVST with a conduction level is provided, the clock transistor Tpclk can be in the conduction state.

[0157] When the clock transistor Tpclk is on, the voltage level of the Q node EQ, electrically connected to the pump capacitor Cpump, can fluctuate according to the first light emission control clock signal ECLK1. The voltage level of the Q node EQ can decrease according to the cycle of the first light emission control clock signal ECLK1. During the period when the light emission control signal EM is output with an on level, the voltage level of the Q node EQ can be stably maintained at the level of the on pull-up transistor Tup. During the light emission period of the sub-pixel SP, the output of the light emission control signal EM with an on level can be stably maintained.

[0158] At the timing of the termination of the light emission period, the light emission control start signal EVST can be changed to the cutoff level.

[0159] The voltage level of Q node EQ can be changed to a high level, and the voltage level of QB node EQB can be changed to a low level. The pull-up transistor Tup can be turned off, and the pull-down transistor Tdn can be turned on. The second light emission control drive voltage EVGH can be output to the output terminal of the light emission control signal EM through the pull-down transistor Tdn. The light emission control signal EM with a cutoff level can be provided to the sub-pixel SP.

[0160] The reset transistor Tprst can be turned on based on the voltage level of the QB node EQB. The second light-emitting control drive voltage EVGH can be supplied to the gate node of the pump transistor Tpump through the reset transistor Tprst. The pump transistor Tpump can be turned off.

[0161] When a cutoff-level light emission control signal EM is applied to the gate node of the feed transistor Tfeed, the feed transistor Tfeed can be turned off. When a cutoff-level light emission control start signal EVST is provided, the clock transistor Tpclk can be turned off.

[0162] During the period when the output of the light control signal EM with a cutoff level is being performed, the pump capacitor Cpump may not operate.

[0163] As described above, during the period when the light emission control signal EM with a conduction level is output, the voltage level of the Q node EQ can be stably maintained by the pump control unit 123 operated by the light emission control signal EM.

[0164] By maintaining the output of the luminescence control signal EM stably during a long frame period, the driving characteristics of the sub-pixel SP that emits light according to the output signal of the luminescence control block can be improved.

[0165] The embodiments described above will be briefly described below.

[0166] The display device 100 according to an embodiment of the present disclosure may include a display panel 110 having a plurality of sub-pixels SP, a plurality of gating lines GL electrically connected to at least one of the plurality of sub-pixels SP, and a gating drive circuit 120 that outputs gating signals to the plurality of gating lines GL.

[0167] The gating drive circuit 120 may include a pull-up transistor Tup controlled by the voltage level of the Q node, a pull-down transistor Tdn controlled by the voltage level of the QB node, a pump capacitor Cpump electrically connected between the Q node and the input terminal of the gating clock signal, and a pump transistor Tpump electrically connected between the pump capacitor Cpump and the Q node and controlled by the gating signal output to the gating line GL.

[0168] The gate node of the pump transistor Tpump can be electrically connected to the node between the pump transistor Tpump and the pump capacitor Cpump.

[0169] During the period when the pump transistor Tpump is turned on, the voltage level of the Q node can be maintained when the level of the gate clock signal changes from the first level to the second level. Conversely, the voltage level of the Q node can be changed when the level of the gate clock signal changes from the second level to the first level.

[0170] During the period when the pump transistor Tpump is turned on, the difference between the voltage level of the Q node and the voltage level of the pull-up transistor Tup can increase.

[0171] The gating drive circuit 120 may include a feed transistor Tfeed electrically connected between the gate node of the pump transistor Tpump and the input terminal of the first gating drive voltage and controlled by the voltage level of the gating signal output to the gating line GL.

[0172] The level of the first strobe drive voltage can be the level of the turn-on pump transistor Tpump.

[0173] The gating drive circuit 120 may include a clock transistor Tpclk electrically connected between the pump capacitor Cpump and the input terminal of the gating clock signal and controlled by the voltage level of the gating start signal.

[0174] During the period when the voltage level of the strobe start signal is the same as the level of the turn-on clock transistor Tpclk, the voltage level of the strobe clock signal can be changed multiple times.

[0175] During the period when the voltage level of the strobe start signal is the same as the level of the turn-on clock transistor Tpclk, the voltage level of the Q node can be changed according to the cycle of the strobe clock signal.

[0176] The gating drive circuit 120 may include a reset transistor Tprst electrically connected between the gate node of the pump transistor Tpump and the input terminal of the second gating drive voltage and controlled by the voltage level of the QB node.

[0177] The level of the second strobe drive voltage can be the level of the cutoff pump transistor Tpump.

[0178] The gating drive circuit 120 may include a startup capacitor Cboot electrically connected between the Q node and the output terminal of the gating signal.

[0179] Each of the multiple sub-pixels SP may include a light-emitting element ED, a driving transistor DRT that provides driving current to the light-emitting element ED, and multiple switching transistors SWT that control the driving timing of the driving transistor DRT and the light-emitting element ED.

[0180] The aforementioned strobe signal can be used to control the switch transistor SWT among multiple switch transistors SWTs that has the longest on-time period in the frame period.

[0181] The display device 100 according to the embodiments of the present disclosure may include a plurality of sub-pixels SP disposed in a display panel 110, a first gating driving circuit that outputs a first gating signal to the plurality of sub-pixels SP, and a second gating driving circuit that outputs a second gating signal to the plurality of sub-pixels SP.

[0182] Within a frame period, the period during which the second strobe signal is at the on level can be longer than the period during which the first strobe signal is at the on level.

[0183] The second gating drive circuit may include a pump control unit 123 electrically connected between the Q node and the input terminal of the gating clock signal and controlled by the voltage level of the second gating signal.

[0184] The pump control unit 123 can operate during the period when the second strobe signal has a conduction level.

[0185] The pump control unit 123 may include a pump capacitor Cpump electrically connected to an input terminal of a strobe clock signal. The pump capacitor Cpump may be electrically connected to a Q node during the period when the second strobe signal has an on level.

[0186] The gating drive circuit 120 according to an embodiment of the present disclosure may include a pull-up transistor Tup controlled by the voltage level of the Q node and electrically connected between the input terminal of the first gating drive voltage and the output terminal of the gating signal, a pull-down transistor Tdn controlled by the voltage level of the QB node and electrically connected between the input terminal of the second gating drive voltage and the output terminal of the gating signal, a pump capacitor Cpump electrically connected between the Q node and the input terminal of the gating clock signal, a pump transistor Tpump electrically connected between the pump capacitor Cpump and the Q node, and a feed transistor Tfeed electrically connected between the gate node of the pump transistor Tpump and the input terminal of the first gating drive voltage and controlled by the voltage level of the gating signal.

[0187] The gating drive circuit 120 may include a startup capacitor Cboot electrically connected between the Q node and the output terminal of the gating signal.

[0188] The change in the voltage level of the Q node due to the timing of the strobe signal changing from the cutoff level to the on level can be greater than the change in the voltage level of the Q node due to the cycle of the strobe clock signal.

[0189] The foregoing description has been presented to enable any person skilled in the art to implement and use the technical ideas of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The foregoing description and drawings provide examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure. Therefore, the scope of this disclosure is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical ideas within the scope of their equivalents should be interpreted as being included within the scope of this disclosure.

[0190] Cross-reference of related applications

[0191] This application claims priority to Korean Patent Application No. 10-2021-0193711, filed on December 31, 2021, which is incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel, wherein multiple sub-pixels are provided; Multiple gate lines, wherein the multiple gate lines are electrically connected to at least one of the multiple sub-pixels; as well as A gating driving circuit outputs gating signals to the plurality of gating lines. The gating drive circuit includes: A pull-up transistor, wherein the pull-up transistor is controlled by the voltage level of the Q node; A pull-down transistor, which is controlled by the voltage level of the QB node; A pump capacitor, electrically connected between the Q node and the input terminal of the strobe clock signal; and A pump transistor, electrically connected between the pump capacitor and the Q node, and controlled by a gating signal output to the gating line. During the period when the pump transistor is on, the voltage level of the Q node causes the pull-up transistor to turn on, and The gating signal is a light emission control signal.

2. The display device according to claim 1, wherein, The gate node of the pump transistor is electrically connected to the node between the pump transistor and the pump capacitor.

3. The display device according to claim 1, wherein, During the period when the pump transistor is turned on, when the level of the strobe clock signal changes from a first level to a second level, the voltage level of the Q node is maintained, and when the level of the strobe clock signal changes from the second level to the first level, the voltage level of the Q node is changed.

4. The display device according to claim 3, wherein, The gate node of the pump transistor is electrically connected to the node between the pump transistor and the pump capacitor, and the pump transistor is a P-type transistor. The second level is higher than the first level.

5. The display device according to claim 3, wherein, During the period when the pump transistor is turned on, the voltage level of the gating clock signal changes multiple times.

6. The display device according to claim 1, wherein, During the period when the pump transistor is turned on, the difference between the voltage level of the Q node and the voltage level of the pull-up transistor increases.

7. The display device according to claim 6, wherein, The pull-up transistor is a P-type transistor, and during the period when the pump transistor is turned on, the voltage level of the Q node is less than the voltage level at which the pull-up transistor is turned on.

8. The display device according to claim 1, wherein, The gating drive circuit also includes: A feed transistor is electrically connected between the gate node of the pump transistor and the input terminal of the first gating drive voltage, and is controlled by the voltage level of the gating signal output to the gating line.

9. The display device according to claim 8, wherein, The level of the first strobe drive voltage is the level at which the pump transistor is turned on.

10. The display device according to claim 1, wherein, The gating drive circuit also includes: A clock transistor is electrically connected between the pump capacitor and the input terminal of the strobe clock signal, and is controlled by the voltage level of the strobe start signal.

11. The display device according to claim 10, wherein, During the period when the voltage level of the strobe start signal is the level at which the clock transistor is turned on, the voltage level of the strobe clock signal changes multiple times.

12. The display device according to claim 10, wherein, During the period when the voltage level of the strobe start signal is the level at which the clock transistor is turned on, the voltage level of the Q node changes according to the cycle of the strobe clock signal.

13. The display device according to claim 1, wherein, The gating drive circuit also includes: A reset transistor is electrically connected between the gate node of the pump transistor and the input terminal of the second gating drive voltage, and is controlled by the voltage level of the QB node.

14. The display device according to claim 13, wherein, The level of the second strobe drive voltage is the level at which the pump transistor is turned off.

15. The display device according to claim 1, wherein, The gating drive circuit also includes: A start capacitor is electrically connected between the Q node and the output terminal of the strobe signal.

16. The display device according to claim 15, wherein, The change in voltage level of the Q node during the timing of the strobe signal changing from off level to on level is greater than the change in voltage level of the Q node according to the cycle of the strobe clock signal.

17. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes: Light-emitting elements; A driving transistor that provides a driving current to the light-emitting element; and Multiple switching transistors control the driving timing of the light-emitting element and the driving transistor. The strobe signal is provided to control the switching transistor among the plurality of switching transistors that has the longest on-time during the frame period.

18. A display device, the display device comprising: Multiple sub-pixels, wherein the multiple sub-pixels are disposed in the display panel; A first gating driving circuit outputs a first gating signal to the plurality of sub-pixels; as well as A second gating driving circuit outputs a second gating signal to the plurality of sub-pixels. In a frame period, the period during which the second strobe signal is at the on level is longer than the period during which the first strobe signal is at the on level. The second gating drive circuit includes: The pump control unit is electrically connected between the Q node and the input terminal of the gating clock signal, and is controlled by the voltage level of the second gating signal. During the period when the second strobe signal has the on level, the pump control unit operates to maintain the voltage level of the Q node, and The second strobe signal is a light emission control signal.

19. The display device according to claim 18, wherein, The pump control unit operates during the period when the second strobe signal has a conduction level.

20. The display device according to claim 18, wherein, The pump control unit includes a pump capacitor having a first terminal electrically connected to the input terminal of the strobe clock signal, and During the period when the second strobe signal has a conduction level, the pump capacitor has a second terminal electrically connected to the Q node.

21. The display device according to claim 20, wherein, The pump control unit further includes a pump transistor electrically connected between the pump capacitor and the Q node, and controlled by the second strobe signal. The gate node of the pump transistor is electrically connected to the node between the pump transistor and the pump capacitor.

22. A gating driving circuit, the gating driving circuit comprising: A pull-up transistor, which is controlled by the voltage level of the Q node and electrically connected between the input terminal of the first gating drive voltage and the output terminal of the gating signal; A pull-down transistor, which is controlled by the voltage level of the QB node and is electrically connected between the input terminal of the second gating drive voltage and the output terminal of the gating signal; A pump capacitor, which is electrically connected between the Q node and the input terminal of the strobe clock signal; A pump transistor, the pump transistor being electrically connected between the pump capacitor and the Q node; as well as A feed transistor is electrically connected between the gate node of the pump transistor and the input terminal of the first gating drive voltage, and is controlled by the voltage level of the gating signal. During the period when the pump transistor is on, the voltage level of the Q node causes the pull-up transistor to turn on, and The gating signal is a light emission control signal.

23. The gating driving circuit according to claim 22, further comprising: A start capacitor is electrically connected between the Q node and the output terminal of the strobe signal.

24. The gating drive circuit according to claim 23, wherein, The change in the voltage level of the Q node during the timing of the strobe signal changing from the off level to the on level is greater than the change in the voltage level of the Q node according to the cycle of the strobe clock signal.

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