Semiconductor package device

Abstract

The disclosure relates to a semiconductor packaging device. The semiconductor packaging device comprises a dielectric element, a radiation excitation source comprising a vertical part extending from an end of the dielectric element to an interior of the dielectric element, and the vertical part and the dielectric element jointly form a dielectric resonator antenna. The semiconductor packaging device can reduce the amount of high dielectric constant material, thereby reducing the manufacturing cost of the semiconductor packaging device, and is conducive to improving economic benefits.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus. Background Technology

[0002] There are many challenges to overcome in the development of high-frequency millimeter-wave circuit technology. Antennas used in high-frequency millimeter-wave transceivers have smaller sizes and effective areas due to the shorter wavelengths. However, higher-frequency millimeter-wave and terahertz antenna signals suffer severe attenuation, making it crucial to increase antenna gain.

[0003] To increase antenna gain, the current approach is to form a dielectric coating on the antenna surface. The dielectric coating forms a reflective interface between different media, allowing the dielectric coating to guide electromagnetic waves through the focusing principle and propagate within the dielectric coating, thereby achieving characteristics such as improved directivity and gain. Figure 1 This is a schematic diagram of such a semiconductor packaging device. For example... Figure 1 As shown, a dielectric coating 12 is disposed on the substrate 10. An antenna 11 is disposed between the substrate 10 and the dielectric coating 12. In this semiconductor packaging device, the dielectric coating 12 needs to cover the antenna 11, therefore its area is relatively large. Since the dielectric coating 12 needs to be made of a high dielectric constant (dk) material, its cost is high. Therefore... Figure 1 The semiconductor packaging device shown has the problem of high manufacturing cost.

[0004] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging device.

[0006] The semiconductor packaging apparatus disclosed herein includes:

[0007] Dielectric elements;

[0008] A radiation excitation source includes a vertical portion extending from the end of the dielectric element into the interior of the dielectric element, the vertical portion and the dielectric element together forming a dielectric resonator antenna.

[0009] In some alternative embodiments, the semiconductor packaging device further includes a substrate, the dielectric element is disposed on the substrate, and the vertical portion extends perpendicularly to the surface of the substrate.

[0010] In some alternative embodiments, the radiation excitation source further includes a horizontal portion disposed between the dielectric element and the substrate and connected to the end of the vertical portion.

[0011] In some alternative implementations, the vertical portion is a conductive post, a stud, or a solder ball.

[0012] In some alternative implementations, the vertical section is a directional antenna or a dipole antenna.

[0013] In some alternative embodiments, the substrate includes a grounding line, and the horizontal portion is electrically connected to the grounding line.

[0014] In some alternative embodiments, the semiconductor packaging device further includes electronic components disposed on the surface of the substrate.

[0015] In some alternative implementations, the electronic component is a radio frequency chip, a passive component, or a connection component.

[0016] In some alternative embodiments, the number of dielectric elements is at least two, and each dielectric element is provided with a corresponding radiation excitation source.

[0017] In some alternative embodiments, at least two of the dielectric elements are distributed in an array on the surface of the substrate.

[0018] In some alternative implementations, there are gaps between the different dielectric elements.

[0019] In the semiconductor packaging apparatus provided in this disclosure, a radiation excitation source is formed by utilizing a vertical portion extending from the end of the self-dielectric element into the interior of the dielectric element. This reduces the amount of high dielectric constant material used, thereby lowering the manufacturing cost of the semiconductor packaging apparatus and improving economic efficiency. Attached Figure Description

[0020] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0021] Figure 1 This is a schematic diagram of a semiconductor packaging device in the prior art;

[0022] Figures 2-5 These are, in sequence, a first schematic diagram to a fourth schematic diagram of a semiconductor packaging apparatus according to embodiments of the present disclosure.

[0023] Symbol explanation:

[0024] 10. Substrate; 11. Antenna; 12. Dielectric coating; 100. Substrate; 110. Grounding line; 200. Dielectric element; 300. Radiation excitation source; 310. Vertical part; 320. Horizontal part; 400. Radio frequency chip; 410. Molding material; 420. Shielding layer; 500. Passive element; 600. Connecting element. Detailed Implementation

[0025] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0026] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0027] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0028] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0029] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0030] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] This disclosure provides a semiconductor packaging apparatus. Figures 2-5 These are, in sequence, a first schematic diagram to a fourth schematic diagram of a semiconductor packaging apparatus according to embodiments of the present disclosure.

[0032] Figure 2 A longitudinal cross-section of the semiconductor packaging device is shown. (See figure) Figure 2 As shown, the semiconductor package includes a dielectric element 200 and a radiation excitation source 300. The radiation excitation source 300 includes a vertical portion 310. The vertical portion 310 extends from the end of the dielectric element 200 into the interior of the dielectric element 200. The vertical portion 310 and the dielectric element 200 together form a dielectric resonator antenna.

[0033] In this embodiment, the dielectric element 200 can be made of a high dielectric constant material, and its shape is, for example, a cube or a cylinder.

[0034] In some embodiments, the vertical part 310 may be a directional antenna (Yagi) or a dipole antenna (Dipole).

[0035] like Figure 2 As shown, the semiconductor packaging device also includes a substrate 100. A dielectric element 200 is disposed on the substrate 100, and the vertical portion 310 extends perpendicularly to the upper surface of the substrate 100.

[0036] like Figure 2 As shown, the radiation excitation source 300 also includes a horizontal portion 320. The horizontal portion 320 is disposed between the dielectric element 200 and the substrate 100 and is connected to the end of the vertical portion 310.

[0037] In one manufacturing method, electroplating can be performed on the surface of substrate 100 to form a horizontal portion 320, then conductive pillars can be provided on the surface of substrate 100 to form a vertical portion 310, and finally dielectric elements 200 can be provided around the vertical portion 310 to form a dielectric resonator antenna.

[0038] In another manufacturing method, the straight conductor can be bent to form a horizontal portion 320 and a vertical portion 310, the horizontal portion 320 can be connected to the surface of the substrate 100, and finally a dielectric element 200 can be provided around the vertical portion 310 to form a dielectric resonator antenna.

[0039] Figure 3 This is another schematic diagram of the semiconductor packaging device. (See diagram below.) Figure 3 As shown, a grounding line 110 is provided inside the substrate 100. The horizontal portion 320 is electrically connected to the grounding line 110. Figure 3 The exact path of the electrical connection is omitted in the text.

[0040] like Figure 3As shown, electronic components, including an RF chip 400, passive components 500, and connecting components 600, are also disposed on the lower surface of the substrate 100. The RF chip 400 is used to process RF signals. The RF chip 400 is also provided with a molding material 410 and a shielding layer 420 for protection. The passive components 500 are, for example, capacitors, resistors, or inductors. The connecting components 600 are used to realize external connections of the semiconductor package device, such as a Universal Serial Bus (USB) interface, a board-to-board connector, or a hot bar.

[0041] Figure 4 It shows Figure 3 The three-dimensional structure of a semiconductor packaging device. For example... Figure 4 As shown, the semiconductor packaging device includes multiple dielectric elements 200, each of which has a corresponding radiation excitation source 300. The multiple dielectric elements 200 are distributed in an array on the surface of the substrate 100. This method is beneficial for improving the directivity and gain of the antenna structure.

[0042] like Figure 4 As shown, there are gaps between the different dielectric elements 200. Alternatively, multiple dielectric elements 200 can be fabricated as a single unit, and insulating material can be injected to define the different dielectric elements 200. It is easy to understand that, compared to fabricating as a single unit, Figure 4 Physical isolation between different dielectric components 200 can reduce the amount of dielectric material used, which is beneficial to further reduce manufacturing costs.

[0043] Figure 5 yes Figure 3 This is a variation of the semiconductor packaging device shown. Figure 3 In the middle, the vertical part 310 is a conductive pillar. And... Figure 5 In this embodiment, the vertical portion 310 is a solder ball. In other embodiments, the vertical portion 310 may also be a stud or other form.

[0044] In the semiconductor packaging apparatus provided in this disclosure, a radiation excitation source 300 is formed by utilizing a vertical portion 310 extending from the end of the self-dielectric element 200 into the interior of the dielectric element 200. This reduces the amount of high dielectric constant material used, thereby lowering the manufacturing cost of the semiconductor packaging apparatus and improving economic efficiency.

[0045] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: The substrate has an upper surface and a lower surface; A dielectric element is disposed on the upper surface of the substrate; An radio frequency chip is disposed on the lower surface of the substrate; A radiation excitation source is disposed on the upper surface of the substrate, including a vertical portion and a horizontal portion; The vertical portion extends from the end of the dielectric element into the interior of the dielectric element, and the vertical portion and the dielectric element together form a dielectric resonator antenna; The horizontal portion is disposed between the dielectric element and the substrate, and is connected to the end of the vertical portion; The vertical portion is a conductive post or a solder ball, and the horizontal portion is exposed outside the dielectric element; The substrate includes a grounding line, and the horizontal portion is electrically connected to the grounding line.

2. The semiconductor packaging apparatus according to claim 1, wherein, The vertical portion extends perpendicularly to the surface of the substrate.

3. The semiconductor packaging apparatus according to claim 1, wherein, The vertical part is a directional antenna or a dipole antenna.

4. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging device further includes electronic components disposed on the surface of the substrate.

5. The semiconductor packaging apparatus according to claim 1, wherein, The number of dielectric elements is at least two, and each dielectric element is provided with a corresponding radiation excitation source. The at least two dielectric elements are distributed in an array on the surface of the substrate.

6. The semiconductor packaging apparatus according to claim 5, wherein, There are gaps between the different dielectric elements.

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