A three-way AD parallel complete correlation clock recovery system suitable for low signal-to-noise ratio

Abstract

The present invention is a 3-way AD parallel perfect correlation clock recovery system adapted to low signal-to-noise ratio, belonging to the field of satellite-to-ground information transmission. The system includes a matched filter module, an AD sampling module, a timing error extraction module, a loop filter module, and a sampling clock phase adjustment module. The present invention adopts a clock recovery method combining multi-symbol perfect correlation operation with maximum likelihood selection, which greatly reduces the signal-to-noise ratio of the clock recovery system that can work normally. At the same time, the traditional single AD sampling method is improved to 3AD parallel sampling, which reduces the limitation of the single AD chip sampling frequency on the symbol transmission rate.

Description

Technical Field

[0001] The invention relates to the field of information transmission, and in particular to a 3-way AD parallel complete correlation clock recovery system adapting to low signal-to-noise ratio. Background Art

[0002] In the field of satellite-to-ground information transmission, when a synchronous orbit satellite transmits information to the ground, the information transmission rate cannot be too high due to the limited transmission power of the satellite. In order to increase the information transmission rate of a synchronous orbit satellite to the ground, channel coding technology is generally used to reduce the system's requirements for transmission power. Ideally, using high-gain coding, when Eb / N0 (the ratio of energy per information bit to noise power spectral density) is -1.6dB, the system can reach the Shannon limit of the QPSK transmission system for information transmission rate.

[0003] However, stable clock recovery is a prerequisite for using high-gain coding in satellite-to-ground information transmission systems. The existing clock recovery method, in the QPSK system mode, has a minimum working threshold of Eb / N0 between 0dB and -1dB. This shows that when high-gain coding is still fully effective, the clock recovery loop is already in a "lost lock" state. Summary of the invention

[0004] In view of this, the present invention proposes a 3-way AD parallel complete correlation clock recovery system that is adaptable to low signal-to-noise ratio. The present invention can increase the maximum transmission symbol rate and give full play to the channel coding efficiency.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A three-way AD parallel complete correlation clock recovery system adapting to low signal-to-noise ratio includes the following modules:

[0007] The matched filter module divides the input baseband signal into three identical signals and performs matched filtering on each of the divided signals;

[0008] AD sampling module, according to the sampling clock phase adjustment module output sampling clock signal f clk , AD sampling is performed on each signal after matched filtering; among them, the second AD sampling output is the code element peak value, and its sampling clock signal is f clk , f clk The frequency value is equal to the code element rate of the input baseband signal; the third AD sampling output is the code element lag value, and its sampling clock frequency value is equal to the sampling clock signal f clk The frequency value, phase lag f clk Delay Δt; the first AD sampling output is the code element advance value, and its sampling clock frequency value is equal to the sampling clock signal f clkThe frequency value, phase lead f clk Delay Δt; the value of Δt is less than half of the symbol period;

[0009] The timing error extraction module receives the code element peak value, code element lag value, and code element advance value from the AD sampling module, calculates the timing error, and outputs the timing error signal to the loop filtering module;

[0010] The loop filter module filters the timing error signal through a second-order IIR filter to obtain a clock phase adjustment signal, and outputs the signal to the sampling clock phase adjustment module;

[0011] The sampling clock phase adjustment module adjusts the sampling clock phase according to the clock phase adjustment signal, and converts the adjusted sampling clock signal f clk Output to AD sampling module.

[0012] Furthermore, in the matched filtering module, the matched filtering is implemented by an analog circuit composed of a capacitor, an inductor and a resistor.

[0013] Furthermore, the timing error extraction module works as follows:

[0014] The current symbol peak value and the m-1 previous symbol peak values, a total of m symbol peak values, are grouped into one group, and an energy-complete correlation operation is performed, where m ≥ 2; the energy-complete correlation operation is performed as follows: each group of m symbol peak values ​​is multiplied and added with 2^m local codes, and 2^m correlation values ​​are obtained after the operation is completed, namely, p1, p2, p3, p4, ..., p2^m;

[0015] The maximum likelihood selection method is used to select the available correlation value among p1, p2, p3, p4, ..., p2^m, that is, the maximum value is selected as the available correlation value p max ;

[0016] The codeword advance value signal is subjected to energy correlation operation with the codeword advance values ​​of the adjacent m codewords, wherein m≥2; the energy correlation operation is performed as follows: the current codeword advance value and the previous m-1 codeword advance values ​​are grouped into a group, each group of m codeword advance values; each group of m codeword advance values ​​is respectively correlated with p max The corresponding local code performs multiplication and addition operations, and the operation result is the advanced correlation value of the current code element;

[0017] The code element lag value signal is subjected to energy correlation operation with the code element lag values ​​of the adjacent m code elements, wherein m ≥ 2; the energy correlation operation is performed as follows: the current code element lag value and the previous m-1 code element lag values ​​are grouped into a group, each group of m code element lag values; each group of m code element lag values ​​is respectively correlated with p max The corresponding local code performs multiplication and addition operations, and the operation result is the lag correlation value of the current code element;

[0018] The timing error signal is obtained by subtracting the delayed correlation value from the advanced correlation value of the current symbol; or, the timing error signal is obtained by subtracting the delayed correlation value from the advanced correlation value of the current symbol.

[0019] Furthermore, the 2^m local codes are specifically: permutations and combinations of m code pieces are traversed to form 2^m local codes, and each code piece takes a value of 0 or 1.

[0020] Furthermore, the timing error extraction module operates once in each symbol period.

[0021] The beneficial effects of the present invention are:

[0022] 1. The present invention adopts a clock recovery method combining multi-symbol perfect correlation operation with maximum likelihood selection, which greatly reduces the signal-to-noise ratio of the clock recovery system for normal operation.

[0023] 2. By applying the present invention, in the QPSK system, the lowest working threshold of clock recovery can be lower than -3dB, so that the high-gain coding function of the satellite-to-ground information transmission system can be fully utilized.

[0024] 3. The present invention improves the traditional single AD sampling method into 3AD parallel sampling, thereby reducing the limitation of the single AD chip sampling frequency on the symbol transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0026] Figure 1 It is a block diagram of the clock recovery principle of the satellite-to-ground information transmission system.

[0027] Figure 2 This is a block diagram of the principle of multi-symbol energy-correlated clock error extraction.

[0028] Figure 3 It is the positional relationship between the peak sampling time and the code element center. DETAILED DESCRIPTION

[0029] A three-way AD parallel complete correlation clock recovery system suitable for low signal-to-noise ratio, such as Figure 1 As shown, it includes the following 5 modules:

[0030] The matched filter module S1 divides the input baseband signal into three identical signals; each of the divided signals is subjected to matched filtering, and the matched filtering is implemented by an analog circuit composed of capacitors, inductors and resistors.

[0031] AD sampling module S2 performs AD sampling on each signal after matched filtering, with a total of 3 AD samplings; the second AD sampling output is the code element peak value, and the sampling clock signal f clk The signal f clk The sampling clock phase adjustment module outputs the signal to the AD sampling module; clk The frequency value is equal to the symbol rate of the input baseband signal; the third AD sampling output is the symbol lag value, and the sampling signal clock frequency value is equal to f clk , phase lag f clk Delay Δt; the first AD sampling output is the code element advance value, and the sampling clock frequency value is equal to f clk , phase advance f clk Delay Δt. The value of Δt is less than half of the symbol period.

[0032] The timing error extraction module S3 receives the symbol peak value, symbol lag value, and symbol advance value from the AD sampling module, calculates the timing error, and outputs the timing error signal to the loop filtering module.

[0033] The loop filter module S4 completes the low-pass filtering function of the clock phase error and is composed of a second-order loop structure. By adjusting the parameter value of the loop, the capture speed, capture accuracy and capture bandwidth of the clock synchronization loop can be controlled; and the output is sent to the sampling clock phase adjustment module.

[0034] The sampling clock phase adjustment module S5, clock phase adjustment, completes the mapping process of the clock phase value to the actual output clock phase, and is implemented using a numerically controlled oscillator (NCO). The sampling clock phase is adjusted according to the clock phase, and the adjusted sampling clock signal f clk Output to AD sampling module.

[0035] like Figure 2 As shown, the working mode of the timing error extraction module S3 is:

[0036] S31, perform energy correlation operation on the codeword peak signal and the codeword peaks of the adjacent m codewords, wherein m is ≥ 2; the energy correlation operation is that the current codeword peak and the previous m-1 codeword peaks form a group, each group has m codeword peaks; each group of m codeword peaks is multiplied and added with 2^m local codes respectively, and after the operation is completed, 2^m correlation values ​​are obtained, namely p1, p2, p3, p4, ..., p2^m.

[0037] S32, select the maximum value p from p1, p2, p3, p4, ..., p2^m max .

[0038] S33, p max The corresponding local code is sent to S34 and S35.

[0039] S34, performs energy correlation operation on the codeword advance value signal and the codeword advance values ​​of the adjacent m codewords, wherein m is ≥ 2; the energy correlation operation is to form a group of the current codeword advance value and the previous m-1 codeword advance values, each group of m codeword advance values; each group of m codeword advance values ​​is multiplied and added with the local code sent by S33, and the operation result is the advance correlation value of the current codeword.

[0040] S35, performs energy correlation operation on the codeword lag value signal and the codeword lag values ​​of the adjacent m codewords, wherein m is ≥ 2; the energy correlation operation is to form a group of the current codeword lag value and the previous m-1 codeword lag values, each group of m codeword lag values; each group of m codeword lag values ​​is multiplied and added with the local code sent by S33, and the operation result is the lag correlation value of the current codeword.

[0041] S35, performs energy correlation operation on the codeword lag value signal and the codeword lag values ​​of the adjacent m codewords, wherein m is ≥ 2; the energy correlation operation is to form a group of the current codeword lag value and the previous m-1 codeword lag values, each group of m codeword lag values; each group of m codeword lag values ​​is multiplied and added with the local code sent by S33, and the operation result is the lag correlation value of the current codeword.

[0042] S36, subtract the delayed correlation value from the advanced correlation value of the current symbol to obtain a timing error signal; or subtract the delayed correlation value from the advanced correlation value from the current symbol to obtain a timing error signal.

[0043] This system improves the AD sampling module, and improves the traditional single AD or 2AD, 4AD, 8AD and other even number AD sampling methods to 3AD sampling, such as Figure 1 As shown. The intermediate AD sampling S22 is advanced and delayed by Δt to obtain the sampling time of the advanced AD sampling S21 and the delayed AD sampling S23. Δt can be taken as long as it is less than half of the symbol period, and the specific value is not very strict. In specific implementation, a sampling clock signal can be delayed by 1 and 2 times to obtain another sampling clock.

[0044] In this way, each AD only needs to be sampled once per symbol; therefore, the highest symbol rate transmitted by the system can reach the highest sampling frequency of the AD.

[0045] This system also improves the AD sampling timing error correction module, and improves the signal-to-noise ratio of the clock phase signal through multi-symbol complete energy correlation; in the multi-symbol complete energy correlation process, the correlation value is determined by maximum likelihood selection. Since the local correlation code uses multiple combinations of traversal in the complete correlation operation to achieve the demodulation of the transmission signal, the maximum correlation value of multiple consecutive symbols and the local code is used for clock error calculation, and the calculated value is used as the clock phase error value. Figure 2 shown.

[0046] 2^M local codes are formed by traversing and permuting M chips, each chip taking the value of "0" or "1", to form 2^M local codes. If M is 3, there are 8 local codes such as "000", "001", and "010"; if M is 4, there are 16 local codes such as "0000", "0001", and "0010".

[0047] like Figure 3 As shown, the timing error signal is obtained by subtracting the lag correlation value from the advance correlation value of the current codeword; or the timing error signal is obtained by subtracting the advance correlation value from the lag correlation value of the current codeword, which means that when the peak sampling moment is aligned with the codeword center, the lag correlation value and the advance correlation value are equal; when the peak sampling moment lags behind the codeword center, the lag correlation value is less than the advance correlation value, the sampling moment error signal (lag correlation value - advance correlation value) is negative (lag direction is positive), and the sampling clock phase is advanced; when the peak sampling moment is ahead of the codeword center, the lag correlation value is greater than the advance correlation value, the sampling moment error signal (lag correlation value - advance correlation value) is positive (lag direction is positive), and the sampling clock phase is delayed.

[0048] In short, in the field of satellite-to-ground information transmission, high-gain coding is used. When Eb / N0 (ratio of energy per information bit to noise power spectrum density) is -1.6dB, the system can reach the Shannon limit of information transmission rate (QPSK system signal). However, stable clock recovery is a prerequisite for using high-gain coding in satellite-to-ground information transmission systems. In the existing clock recovery method, the lowest working threshold is Eb / N0 at 0dB in the QPSK system mode, that is, when the high-gain coding is still fully effective, the clock loop is already in a "lost lock" state. To this end, the present invention proposes a 3-way AD parallel perfect correlation clock recovery system that is suitable for low signal-to-noise ratio. It adopts a multi-symbol perfect correlation operation combined with a maximum likelihood selection clock recovery method, which greatly reduces the signal-to-noise ratio of the clock recovery system for normal operation. At the same time, the traditional single AD sampling method is improved to 3AD parallel sampling, which reduces the limitation of the single AD chip sampling frequency on the symbol transmission rate. In the QPSK modulation mode, the lowest working threshold Eb / N0 of the clock recovery of the present invention is lower than -3dB, which can ensure that the channel coding efficiency is fully utilized.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Claims

1. A three-way AD parallel complete correlation clock recovery system adapting to low signal-to-noise ratio, characterized in that: Includes the following modules: The matched filter module divides the input baseband signal into three identical signals and performs matched filtering on each of the divided signals; AD sampling module, according to the sampling clock phase adjustment module output sampling clock signal f clk , AD sampling is performed on each signal after matched filtering; among them, the second AD sampling output is the code element peak value, and its sampling clock signal is f clk , f clk The frequency value is equal to the code element rate of the input baseband signal; the third AD sampling output is the code element lag value, and its sampling clock frequency value is equal to the sampling clock signal f clk The frequency value, phase lag f clk Delay Δt; the first AD sampling output is the code element advance value, and its sampling clock frequency value is equal to the sampling clock signal f clk The frequency value, phase lead f clk Delay Δt; the value of Δt is less than half of the symbol period; The timing error extraction module receives the code element peak value, code element lag value, and code element advance value from the AD sampling module, calculates the timing error, and outputs the timing error signal to the loop filtering module; The loop filter module filters the timing error signal through a second-order IIR filter to obtain a clock phase adjustment signal, and outputs the signal to the sampling clock phase adjustment module; The sampling clock phase adjustment module adjusts the sampling clock phase according to the clock phase adjustment signal, and converts the adjusted sampling clock signal f clk Output to AD sampling module.

2. A three-way AD parallel perfect correlation clock recovery system adapting to low signal-to-noise ratio according to claim 1, characterized in that: In the matched filter module, the matched filter is implemented using an analog circuit composed of capacitors, inductors and resistors.

3. A three-way AD parallel perfect correlation clock recovery system adapting to low signal-to-noise ratio according to claim 1, characterized in that: The timing error extraction module works as follows: The current symbol peak value and the m-1 previous symbol peak values, a total of m symbol peak values, are grouped into one group, and an energy-complete correlation operation is performed, where m ≥ 2; the energy-complete correlation operation is performed as follows: each group of m symbol peak values ​​is multiplied and added with 2^m local codes, and 2^m correlation values ​​are obtained after the operation is completed, namely, p1, p2, p3, p4, ..., p2^m; The maximum likelihood selection method is used to select the available correlation value among p1, p2, p3, p4, ..., p2^m, that is, the maximum value is selected as the available correlation value p max ; The codeword advance value signal is subjected to energy correlation operation with the codeword advance values ​​of the adjacent m codewords, wherein m≥2; the energy correlation operation is performed as follows: the current codeword advance value and the previous m-1 codeword advance values ​​are grouped into a group, each group of m codeword advance values; each group of m codeword advance values ​​is respectively correlated with p max The corresponding local code performs multiplication and addition operations, and the operation result is the advanced correlation value of the current code element; The code element lag value signal is subjected to energy correlation operation with the code element lag values ​​of the adjacent m code elements, wherein m ≥ 2; the energy correlation operation is performed as follows: the current code element lag value and the previous m-1 code element lag values ​​are grouped into a group, each group of m code element lag values; each group of m code element lag values ​​is respectively correlated with p max The corresponding local code performs multiplication and addition operations, and the operation result is the lag correlation value of the current code element; The timing error signal is obtained by subtracting the delayed correlation value from the advanced correlation value of the current symbol; or, the timing error signal is obtained by subtracting the delayed correlation value from the advanced correlation value of the current symbol.

4. A three-way AD parallel perfect correlation clock recovery system adapting to low signal-to-noise ratio according to claim 3, characterized in that: The 2^m local codes are specifically: permutations and combinations of m code pieces are traversed to form 2^m local codes, and each code piece takes a value of 0 or 1.

5. The three-way AD parallel perfect correlation clock recovery system adapting to low signal-to-noise ratio according to claim 1 is characterized in that: The timing error extraction module works once in each symbol period.

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