A distribution radio area topology identification device

Abstract

This invention discloses a distribution transformer area topology identification device, comprising: an MCU control unit, a feature signal injection unit, a data acquisition unit, and a frequency selective amplification unit; the MCU control unit is electrically connected to the feature signal injection unit via a wire, and the feature signal injection unit is electrically connected to a power line; the MCU control unit is electrically connected to the frequency selective amplification unit via a wire, and the frequency selective amplification unit is electrically connected to the data acquisition unit via a wire, and the data acquisition unit is electrically connected to a power line. This invention solves the technical problem of how to accurately and quickly perform topology identification and output the topology identification results.

Description

Technical Field

[0001] This invention relates to the field of smart grid technology, and in particular to a distribution area topology identification device. Background Technology

[0002] In the development of smart grids, to achieve the goals of "measurability, observability, and controllability" and promote the construction of distribution network automation oriented towards fault self-healing, transformer substation topology identification is a necessary technical foundation for advancing the construction of digital distribution networks. Traditionally, distribution substations mainly establish topological relationships through manually maintained archives. However, due to issues such as complex on-site lines, numerous devices, and concealed equipment installations, problems remain, including low precision, discrepancies between maps and reality, and a lack of intelligent identification methods, making it difficult to meet the requirements for refined management of distribution substations. Among existing solutions for accurate identification of transformer substation topology relationships, those based on big data analysis require large amounts of data, have long identification cycles, and their accuracy is affected by load fluctuations. While those based on electrical signal distortion are fast and accurate, the large distortion signals can affect power quality and pose certain safety hazards. Therefore, the most widely used solution is the identification method based on characteristic current injection. The current injection method is relatively simple, but different implementation methods have significantly different identification effects when extracting and identifying characteristic signals from the background of the power grid. Especially in industrial distribution network environments with large background currents and severe noise interference, weak characteristic signals are very likely to be submerged by large background noise, making it extremely difficult to extract and identify characteristic signals. Currently, topology identification using characteristic current injection relies on relatively weak characteristic current signals, with peak currents typically below 400mA and not exceeding 600mA. However, in a power grid environment, the background current in distribution transformer areas generally exceeds 1000A, reaching up to 3000A in extreme cases, meaning a peak current could reach 4242A. The characteristic signal differs from the background signal by more than 10,000 times. To distinguish the characteristic signal against such a large background, simply scaling the sampled signal proportionally places excessive demands on the dynamic response range and accuracy of the acquisition equipment, often resulting in inaccurate identification results and low success rates under high current conditions. Therefore, there is an urgent need to propose a distribution transformer area topology identification device to solve the technical problem of how to accurately and quickly perform topology identification and output the results. Summary of the Invention

[0003] The main objective of this invention is to provide a distribution area topology identification device, which aims to solve the technical problem of how to accurately and quickly perform topology identification and output the topology identification results.

[0004] To achieve the above objectives, the present invention provides a distribution radio station topology identification device, wherein the distribution radio station topology identification device includes: an MCU control unit, a feature signal injection unit, an acquisition unit, and a frequency selective amplification unit;

[0005] The MCU control unit is electrically connected to the output of the feature signal injection unit via a wire, and the feature signal injection unit is electrically connected to the power line; the MCU control unit is electrically connected to the input of the frequency selective amplification unit via a wire, the frequency selective amplification unit is electrically connected to the input of the acquisition unit via a wire, and the acquisition unit is electrically connected to the power line.

[0006] In one preferred embodiment, the MCU control unit includes a processor D1;

[0007] Pin 10 of the processor D1 is connected to the frequency selective amplifier unit;

[0008] Pin 29 of the processor D1 is connected to the feature signal injection unit.

[0009] In one preferred embodiment, the feature signal injection unit includes a full-wave rectifier circuit; the full-wave rectifier circuit includes a rectifier bridge BR1, pin 1 of the rectifier bridge BR1 is connected to the neutral wire of the power line, pin 2 of the rectifier bridge BR1 is connected to the live wire of the power line, pin 3 of the rectifier bridge BR1 is connected to the current injection control circuit, and pin 4 of the rectifier bridge BR1 is grounded.

[0010] In one preferred embodiment, the feature signal injection unit includes a self-powered circuit, which includes a MOSFET Q1. The gate of the MOSFET Q1 is connected to the VDC terminal through a resistor R10, and the source of the MOSFET Q1 is connected to a resistor R7. The other end of the resistor R7 is connected to a current injection control circuit and a resistor R3, respectively. The other end of the resistor R3 is connected to a capacitor C13, a Zener diode V1, and the gate of the MOSFET Q1, respectively. The other ends of the capacitor C13 and the Zener diode V1 are grounded.

[0011] In one preferred embodiment, the feature signal injection unit includes a current injection control circuit, which includes an optocoupler D2. Pin 1 of the optocoupler D2 is connected to the VCC terminal; pin 2 of the optocoupler D2 is connected to the collector of a transistor VT2, the base of the transistor is connected to the MCU control unit through a dynamic response circuit, and the emitter of the transistor is grounded; pin 3 of the optocoupler D2 is connected to a complementary drive circuit and a resistor R21, the other end of the resistor R21 is grounded, the complementary drive circuit is connected to the gate of a MOSFET Q2 through a resistor R14, the gate of the MOSFET Q2 is also connected to a resistor R18, a capacitor C18, and a Zener diode V2, the source of the MOSFET Q2 is connected to a full-wave rectifier circuit and a self-powered circuit, and the drain of the MOSFET Q2 is connected to a resistor R19. The resistor R18, capacitor C18, Zener diode V2, and resistor R19 are grounded; pin 4 of the optocoupler D2 is connected to the VDC terminal.

[0012] In one preferred embodiment, the dynamic response circuit includes a resistor R16, one end of which is connected to the MCU control unit and a capacitor C16, the other end of which is connected to a resistor R15, the other end of which is connected to the base of a diode VD2, a resistor R17, and a transistor VT2, and the other ends of the resistor R16, the diode VD2, and the resistor R17 are grounded.

[0013] In one preferred embodiment, the acquisition unit includes an acquisition circuit, which includes a current transformer T1. Pins 1 and 2 of the current transformer are connected to dual diodes V3 and V4, respectively, and the other end of dual diode V3 is connected to the other end of dual diode V4. Pins 1 and 2 of the current transformer are also connected to the input terminal of a first filter circuit. The output terminal of the first filter circuit is connected to resistors R22 and R23 and a frequency selective amplifier unit, respectively, and the other ends of resistors R22 and R23 are grounded.

[0014] In one preferred embodiment, the first filter circuit includes a capacitor C20. One end of the capacitor C20 is connected to the dual diode V3 and the inductor L1, respectively. The other end of the capacitor C20 is connected to the capacitor C22 and the ground terminal, respectively. The other end of the capacitor C22 is connected to the inductor L2, respectively. The other end of the inductor L2 is connected to the resistor R23 and the capacitor C21, respectively. The other end of the capacitor C21 is connected to the capacitor C19 and the ground terminal, respectively. The other end of the capacitor C19 is connected to the resistor R22 and the other end of the inductor L1, respectively.

[0015] In one preferred embodiment, the frequency selective amplification unit includes a common-mode output conversion circuit, which includes an operational amplifier U1A. Pins 1 and 2 of the operational amplifier U1A are connected to the VCC terminal. Pin 3 of the operational amplifier U1A is connected to resistors R24 and R26, respectively, and the other end of resistor R26 is connected to the acquisition unit. Pin 4 of the operational amplifier U1A is connected to resistors R28 and R31, respectively, and the other end of resistor R28 is connected to the acquisition unit. The other end of resistor R31 is grounded. Pin 5 of the operational amplifier U1A is connected to resistor R24 ​​and the frequency selective amplification circuit.

[0016] In one preferred embodiment, the frequency selective amplification unit includes a frequency selective amplification circuit. The frequency selective amplification circuit includes an operational amplifier U1B whose pin 1 is connected to resistor R25 and capacitor C24. The other end of capacitor C24 is connected to a common-mode output conversion circuit via resistor R27. The other end of resistor R25 is connected to capacitor C23 and pin 3 of operational amplifier U1B. The other end of capacitor C23 is connected to the other end of capacitor C24. Pin 2 of operational amplifier U1B is connected to resistors R30 and R32. The other end of resistor R30 is connected to VCC, and the other end of resistor R32 is grounded. Pin 3 of operational amplifier U1B is connected to the MCU control unit via a second filtering circuit.

[0017] In the above technical solution of the present invention, the distribution transformer area topology identification device includes an MCU control unit, a feature signal injection unit, an acquisition unit, and a frequency selective amplification unit. The MCU control unit is electrically output-connected to the feature signal injection unit via a wire, and the feature signal injection unit is electrically connected to the power line. The MCU control unit is electrically input-connected to the frequency selective amplification unit via a wire, and the frequency selective amplification unit is electrically input-connected to the acquisition unit via a wire. The acquisition unit is electrically connected to the power line. The present invention uses the frequency selective amplification unit to selectively amplify the feature signal acquired by the acquisition unit. This increases the feature signal and improves the sampling accuracy while reducing its difference from the background signal, thereby improving the topology identification success rate and solving the technical problem of how to accurately and quickly perform topology identification and output the topology identification results. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a distribution radio area topology identification device according to an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the MCU control unit according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a full-wave rectifier circuit according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the self-powered circuit according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the current injection control circuit according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the combination of the acquisition unit and the frequency-selective amplification unit in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the equivalent model of the common-mode output conversion circuit according to an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of the equivalent model of the frequency-selective amplifier circuit in an embodiment of the present invention.

[0027] Explanation of icon numbers:

[0028] 1. MCU control unit; 2. Feature signal injection unit; 3. Frequency selective amplification unit; 4. Acquisition unit; 5. Power management unit; 6. Peripheral devices.

[0029] The realization of the objective, functional characteristics and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] It should be noted that all directional indicators (such as up, down, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0032] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0033] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0034] See Figure 1 According to one aspect of the present invention, the present invention provides a distribution radio station topology identification device, wherein the distribution radio station topology identification device includes: an MCU control unit 1, a feature signal injection unit 2, an acquisition unit 4, and a frequency selective amplification unit 3;

[0035] The MCU control unit 1 is electrically connected to the feature signal injection unit 2 via a wire, and the feature signal injection unit 2 is electrically connected to the power line; the MCU control unit 1 is electrically connected to the frequency selective amplification unit 3 via a wire, and the frequency selective amplification unit 3 is electrically connected to the acquisition unit 4 via a wire, and the acquisition unit 4 is electrically connected to the power line.

[0036] Specifically, in this embodiment, the MCU control unit 1 can be an HC32F460 MCU. The MCU control unit 1 is a high-performance microprocessor based on ARM Corex-M4 with a maximum operating frequency of 168MHz. It integrates 512KB of Flash, 192KB of SRAM, and provides two independent ADCs and multiple external communication interfaces. This invention does not impose specific limitations, and the MCU control unit 1 can be configured according to specific needs.

[0037] Specifically, in this embodiment, the MCU control unit 1 is used to output a specific modulation signal and control the characteristic signal injection unit 2 to generate a characteristic current through the modulation signal, and to receive characteristic signals generated by other distribution area topology identification devices collected by the frequency selective amplification unit 3; the MCU control unit 1 includes a processor D1; pin 10 of the processor D1 is connected to the frequency selective amplification unit 3, and pin 10 is an ADC pin. The frequency selective amplification unit 3 transmits the collected and processed signal TP_signal to the processor D1 through the ADC pin. The processor D1 determines whether the collected characteristic signal contains characteristic current information, and sequentially determines whether other devices are injecting characteristic current at this moment; pin 29 of the processor D1 is connected to the characteristic signal injection unit 2, and pin 29 is a PWM output interface CTRL. Pin 29 is configured to a low level. When the device needs to inject characteristic current, the processor D1 will control the pin to output a characteristic modulation signal as needed, and can also fine-tune the effective value of the characteristic current by adjusting the duty cycle of the modulation signal.

[0038] Specifically, in this embodiment, pins 1 and 2 of processor D1 are configured as UART ports for local maintenance of processor D1; pin 5 of processor D1 is connected to capacitor C3 and pin 1 of crystal oscillator Y1, and pin 2 of crystal oscillator Y1 is connected to capacitor C6 and pin 6 of processor D1; pin 7 of processor D1 is connected to resistor R1 and capacitor C7, with the other end of resistor R1 connected to the power supply; pins 8, 23, 35, and 47 of processor D1 are grounded; pin 9 of processor D1 is connected to capacitors C8 and C9 and the power supply; pin 22 of processor D1 is grounded through capacitor C10; pin 24 of processor D1 is connected to capacitors C11 and C12 and the power supply; pin 36 of processor D1 is connected to capacitors C4 and C5 and the power supply; pin 48 of processor D1 is connected to capacitors C1 and C2 and the power supply; and pins 3 and 4 of crystal oscillator Y1 are connected to capacitor C6 and crystal oscillator Y1. The other ends of capacitors C3, C1, C2, C7, C8, C9, C11, C12, C4, and C5 are grounded. Pins 39 and 43 of processor D1 are serial ports used for communication between processor D1 and peripheral device 6. Capacitors C1, C2, C4, C5, C8, C9, C10, C11, and C12 are decoupling capacitors used to prevent external power supply noise from affecting the performance of processor D1, and to prevent noise generated by processor D1 from being transmitted to the power line and affecting other power-consuming chips. Crystal oscillator Y1 provides an external clock source for processor D1. Capacitors C1 and C6 are crystal oscillator load capacitors used to match the internal resonant circuit of the crystal oscillator, making the circuit easy to start and in a reasonable excitation state. Resistor R1 and capacitor C7 are used for power-on reset of MCU control unit 1, so that when processor D1 is powered on, the brief charging time of capacitor C7 helps the chip complete hardware initialization.

[0039] Specifically, in this embodiment, the feature signal injection unit 2 includes a full-wave rectifier circuit; the full-wave rectifier circuit includes a rectifier bridge BR1, pin 1 of which is connected to resistor R9 and resistor RV1 respectively, the other end of resistor R9 is connected to the neutral wire of the power line, pin 2 of the rectifier bridge BR1 is connected to a resettable fuse F1 through resistor R8, the other end of the resettable fuse F1 is connected to the other end of resistor RV1 and the live wire of the power line respectively, pin 3 of the rectifier bridge BR1 is connected to the current injection control circuit, and pin 4 of the rectifier bridge BR1 is grounded. The live wire of the power line is connected through the rectifier bridge BR1. The AC voltage across the neutral and live wires is rectified to remove the negative half-cycle of the voltage sinusoidal signal, resulting in a DC voltage V_TP. Resistor RV1 is a varistor that provides protection; it activates when the voltage between the live and neutral wires is too high, clamping the voltage to a safe range that the subsequent circuit can withstand, ensuring that the subsequent circuit is not damaged by surges. The resettable fuse F1 provides current limiting protection; it trips when the current is too high to prevent damage to components or circuits. Resistors R8 and R9 are voltage divider resistors; they share some of the voltage during the power consumption of the subsequent circuit, reducing its power consumption.

[0040] Specifically, in this embodiment, the feature signal injection unit 2 includes a self-powered circuit, which includes a MOSFET Q1. The drain of the MOSFET Q1 is connected to the VDC terminal through a resistor R10. The source of the MOSFET Q1 is connected to resistors R7 and R2 in sequence. The other end of resistor R2 is connected to the current injection control circuit and resistor R6 in sequence. The other end of resistor R6 is connected to resistor R3 in sequence through resistors R5 and R4. The other end of resistor R3 is connected to capacitor C13, Zener diode V1, and the gate of the MOSFET Q1 in sequence. The other ends of capacitor C13 and Zener diode V1 are grounded. The Zener diode V1 can control the gate voltage V of the MOSFET Q1. G Once the voltage stabilizes to a constant level, current limiting protection is provided by resistors R3, R4, R5, R6, and R10. Capacitor C13 ensures that the voltage near the zero-crossing point is within acceptable limits. G The voltage is stable when V_TP ≥ V G -V GSth At this time, MOSFET Q1 will operate in the constant current region, and V GS ≈V GSth Then the source voltage V of MOSFET Q1 S ≈V G -V GSthThis achieves a constant VDC voltage. Resistors R2 and R7 act as voltage dividers, reducing the voltage difference between the drain and source of MOSFET Q1 and decreasing the power consumption of MOSFET Q1. The self-feeding circuit also includes capacitor C14, one end of which is connected to the VDC terminal, and the other end of which is grounded. Capacitor C14 is an energy storage capacitor used to ensure the stability of VDC voltage near the zero crossing point.

[0041] Specifically, in this embodiment, the feature signal injection unit 2 includes a current injection control circuit, which includes an optocoupler D2. Pin 1 of the optocoupler D2 is connected to the VCC terminal through a resistor R11, which is a current-limiting pull-up resistor. Pin 2 of the optocoupler D2 is connected to the collector of a transistor VT2. The base of the transistor is connected to the MCU control unit 1 through a dynamic response circuit, and the emitter of the transistor is grounded. Pin 3 of the optocoupler D2 is connected to a complementary drive circuit through a resistor R12, which is a current-limiting resistor. Pin 3 of the optocoupler D2 is also connected to a resistor R21, the other end of which is grounded. The resistor R21 provides an initial state for pin 3 of the optocoupler D2, ensuring that its default level is low. The complementary drive circuit is connected to a resistor R14 and a diode VD1. The other end of the resistor R14 is connected to the gate of a MOSFET Q2, and the other end of the diode VD1 is connected to the gate of the MOSFET Q2 through a resistor R13. The gate of the MOSFET Q2 is connected to resistor R18, capacitor C18, and Zener diode V2. The source of the MOSFET Q2 is connected to both the full-wave rectifier circuit and the self-powered circuit. The drain of the MOSFET Q2 is connected to capacitor C17, resistor R19, and resistor R20. The other end of capacitor C17 is connected to the gate of the MOSFET Q2. Resistor R18, capacitor C18, Zener diode V2, resistor R20, and resistor R19 are grounded. Resistor R18 ensures... The voltage is stable near the zero crossing point. The capacitor C17 is a filter capacitor, which can prevent the current from changing drastically when the MOSFET Q2 is turned on or off, thus preventing overshoot. The four pins of the optocoupler D2 are connected to the VDC terminal and the capacitor C15 respectively. The other end of the capacitor C15 is grounded. The capacitor C15 is an energy storage capacitor, which can ensure the stability of the VDC voltage during the switching process of the optocoupler. When current flows through pins 1 and 2 of the optocoupler D2, the internal light-emitting diode of the optocoupler D2 is activated, and pins 3 and 4 of the optocoupler D2 are turned on.

[0042] Specifically, in this embodiment, the dynamic response circuit includes a resistor R16. One end of the resistor R16 is connected to the MCU control unit 1 and the capacitor C16, respectively. The other end of the capacitor C16 is connected to a resistor R15. The other end of the resistor R15 is connected to the base of the diode VD2, the resistor R17, and the transistor VT2, respectively. The other ends of the resistor R16, the diode VD2, and the resistor R17 are grounded. The resistor R16 provides a hardware initialization level for the CTRL, ensuring that the CTRL remains at a low level when it is not controlled by software. The capacitor C16 is a DC blocking capacitor, the resistor R15 is a current limiting resistor, the diode VD2 is a clamping diode, and the resistor R17 is a return current resistor. Only when the voltage of the CTRL changes high or low will the base voltage of the transistor VT2 change accordingly, preventing the microcontroller from "locking up" due to overheating.

[0043] Specifically, in this embodiment, the complementary drive circuit includes transistors VT1 and VT3. The collector of transistor VT1 is connected to VDC, the base of transistor VT1 is connected to resistor R12, the emitter of transistor VT1 is connected to the emitter of transistor VT3, resistor R14, and diode VD1, respectively, the base of transistor VT3 is connected to one end of resistor R21, and the collector of transistor VT3 is grounded. Transistors VT1 and VT3 are mutually exclusive. When the CTRL signal changes from low to high, the base of transistor VT3 also changes accordingly, pins 3 and 4 of optocoupler D2 are turned on, transistor VT1 is turned on, and VT3 is turned off. VDC can pull the gate of MOSFET Q2 high through current-limiting resistor R14, and then be regulated by diode V2. Similar to the self-powered circuit described above, when V_TP≥V G -V GSth At this time, MOSFET Q2 will operate in the constant current region, and V GS ≈V GSth Then the source voltage V of MOSFET Q2 S ≈V G -V GSth This allows a constant current to be generated through the constant current load resistors R19 and R20. When the CTRL signal changes from high to low, the base of transistor VT2 is grounded accordingly, pins 3 and 4 of optocoupler D2 are cut off, transistor VT1 is cut off, and transistor VT3 is turned on. The gate voltage of MOSFET Q2 can be discharged more quickly through the current limiting resistor R13 and diode VD1 via transistor VT3. The resistance of resistor R13 is much smaller than that of R14, so MOSFET Q2 is quickly cut off and no current is generated. Resistor R18 ensures that the gate initial level of MOSFET Q2 is low, preventing malfunction.

[0044] Specifically, in this embodiment, the acquisition unit 4 includes an acquisition circuit, which includes a current transformer T1. Pins 1 and 2 of the current transformer are connected to dual diodes V3 and V4, respectively, and the other end of dual diode V3 is connected to the other end of dual diode V4. Pins 1 and 2 of the current transformer are also connected to the input terminal of a first filter circuit. The output terminal of the first filter circuit is connected to resistors R22 and R23 and a frequency selective amplifier unit 3, respectively, and the other ends of resistors R22 and R23 are grounded. The current transformer T1 acquires the characteristic signal injection unit from the previous distribution network topology identification device. The characteristic signal generated by element 2 is protected by dual diodes V3 and V4. After passing through the first filter circuit, high-frequency interference in the characteristic signal is initially filtered out. The resistors R22 and R23 are sampling resistors, selected within the load resistance range of the current transformer T1. The collected characteristic signal can be converted into a voltage signal, where the characteristic signal is a current signal. At this time, the converted voltage signal is still a differential mode signal. The acquisition unit 4 is used to acquire the characteristic signal generated by the characteristic signal injection unit 2 in the previous distribution substation topology identification device. The characteristic signal is sampled by the current transformer T1 through the power line and then transmitted to the power mode output conversion circuit.

[0045] Specifically, in this embodiment, the first filtering circuit is a π-type LC filtering circuit. The π-type filtering circuit includes a capacitor C20. One end of the capacitor C20 is connected to the dual diode V3 and the inductor L1, respectively. The other end of the capacitor C20 is connected to the capacitor C22 and the ground terminal, respectively. The other end of the capacitor C22 is connected to the inductor L2, respectively. The other end of the inductor L2 is connected to the resistor R23 and the capacitor C21, respectively. The other end of the capacitor C21 is connected to the capacitor C19 and the ground terminal, respectively. The other end of the capacitor C19 is connected to the resistor R22 and the other end of the inductor L1, respectively. The π-type LC filtering circuit initially filters out high-frequency interference signals in the collected feature signals. This invention is not specifically limited, and can be set according to needs.

[0046] Specifically, in this embodiment, the frequency selective amplification unit 3 includes a common-mode output conversion circuit, which includes an operational amplifier U1A. Pins 1 and 2 of the operational amplifier U1A are connected to the VCC terminal. Pin 3 of the operational amplifier U1A is connected to resistors R24 and R26, and the other end of resistor R26 is connected to resistor R23. Pin 4 of the operational amplifier U1A is connected to resistors R28 and R31, and the other end of resistor R28 is connected to resistor R22. The other end of resistor R31 is grounded. Pin 5 of the operational amplifier U1A is connected to resistor R24 ​​and the frequency selective amplification circuit. The resistance values ​​of resistors R24, R26, R28, and R31 are equal. If the voltage across the input signal in the common-mode output conversion circuit is U... in U in Including U i1 and U i2 The voltage from the output signal to ground is U. out The voltages at the positive and negative input terminals of the operational amplifier are U and U, respectively. A+ and U A- According to the principle of virtual short and virtual short, such as Figure 7 As shown, we can obtain: U A+ =U A- ;

[0047]

[0048]

[0049] Where R24 = R26 = R28 = R31, therefore, U out =(U i2 -U i1 ).

[0050] Specifically, in this embodiment, the frequency selective amplification unit 3 includes a frequency selective amplification circuit. The frequency selective amplification circuit includes an operational amplifier U1B whose pin 1 is connected to resistor R25 and capacitor C24. The other end of capacitor C24 is connected to pin 5 of operational amplifier U1A in the common-mode output conversion circuit via resistor R27. The other end of resistor R25 is connected to capacitor C23 and pin 3 of operational amplifier U1B. The other end of capacitor C23 is connected to the other end of capacitor C24. Pin 2 of operational amplifier U1B is connected to resistor R30 and... Resistor R32 is connected, with the other end of resistor R30 connected to VCC and the other end of resistor R32 grounded. Pin 3 of operational amplifier U1B is connected to pin 10 of processor D1 in MCU control unit 1 via a second filter circuit. The frequency-selective amplification unit 3 amplifies the acquired feature signal, amplifies the signal in the frequency band where the feature current is located, and suppresses the power frequency background signal to reduce the difference between the feature signal and the background signal, improve the topology recognition success rate, and ensure that the processed signal does not exceed the sampling voltage range, thus preventing clipping. Capacitors C23 and C24 have the same capacitance value. If the voltage across the input signal of the frequency-selective amplification circuit is V... in The voltage from the output signal to ground is V. out The voltages at the positive and negative output terminals of the operational amplifier are V respectively. B+ and V B- ,like Figure 8 As shown, let the position of point A be V. A Based on the voltage-current relationship and the virtual short-current and virtual open-current theorems, we can obtain:

[0051] V B+ =V B- =0 (1)

[0052] jωC 24 (V A -V B- )+(V out -V B- ) / R 25 =0 (2)

[0053] (V A -V in ) / R 27 +(V A -V out )jωC 23 +(V A -V B- )jωC 24 =0 (3)

[0054] Let V' A =V A -V - ,V'in =V in -V - ,V' out =V out -V - Substituting equation (1) into equations (2) and (3), we get:

[0055] jωC 24 V A ′+V out ′ / R 25 =0 (4)

[0056] V A ′(1 / R 27 +jωC 23 +jωC 24 )-V out jωC 23 -V in ′ / R 27 =0 (5)

[0057] Substituting equation (4) into equation (5), we get:

[0058] H(jω)′=V out ′ / V in ′=R 25 / R 27 {j[1 / R 27 / ωC 24 -ωC 23 R 25 ]-(C 23 +C 24 ) / C 24} (6)

[0059] Setting its imaginary part to 0, the center frequency is:

[0060]

[0061] H(jf0)=-R 25 / [(1+C 23 / C 24 )R 27 (8)

[0062] Where C23 = C24 = C;

[0063] Center frequency:

[0064] The amplification factor at the center frequency is: H(jf0) = -R 25 / 2R 27

[0065] The input-output ratio at any frequency is: H(jω) = R 25 / {R 27 {j[1 / R 27 / ωC-ωCR 25 ]-2}}

[0066] Substituting the above formula into H(jω), simplifying it to the form H(jω)=-(a+bj), the phase difference between the frequency-selective amplified signal and the original signal is:

[0067] By calculating the input-output ratio at any frequency and the phase difference between the frequency-selectively amplified signal and the original signal, the original data can be derived from the sampled data, thereby enabling real-time feedback of the magnitude of the power frequency current and the injected characteristic current in the power grid.

[0068] Specifically, in this embodiment, the second filtering circuit includes a resistor R29 and a capacitor C25. The resistor R29 is connected to pin 3 of the operational amplifier U1B, and the other end of the resistor R29 is connected to pin 10 of the processor D1 in the MCU control unit 1 and the capacitor C25. The other end of the capacitor C25 is grounded. The second filtering circuit further filters out high-frequency interference in the signal before the signal is input to the processor D1, ensuring the stability of the signal. This invention is not specifically limited, and can be set according to needs.

[0069] Specifically, in this embodiment, the distribution transformer area topology identification device further includes a power management unit 5 and a peripheral device 6. The power management unit 5 is connected to the power line, which includes a live wire and a neutral wire, and the power of the power line is provided by the mains power. The power management unit 5 is used to supply power to each unit circuit. The peripheral device 6 is connected to the MCU control unit 1 and is used to implement other functions of the distribution transformer area topology identification device. This invention does not impose specific limitations, and specific settings can be made as needed.

[0070] Specifically, in this embodiment, the distribution area topology identification device can function as both a transmitting device and an identification device, used in topology identification devices at various levels within the distribution area. When used as a transmitting device, processor D1 outputs a modulation pattern with specific rules. The signal contains feature code information, and the signal bit width time corresponding to each bit in the feature code is T. The modulation of the modulation signal is as follows: if a bit of the feature code is 1, a square wave signal of a specific frequency is output within the corresponding time T; if a bit of the feature code is 0, it remains at a low level within the corresponding time T. The modulation signal is connected to the feature signal injection unit 2. When the modulation signal is high, a constant current is generated on the power line; when the modulation signal is low, no current is generated. In this way, a feature current signal corresponding to the modulation signal can be injected into the power line. This current signal not only has the same frequency as the square wave frequency of the modulation signal but also contains the feature code information in the modulation signal. When used as an identification device, the current on the power line is collected in real time through the current transformer T1 and input to the frequency selective amplifier unit 3. The signal after frequency selective amplification is then connected to the ADC pin of the processor D1. The processor D1 analyzes the sampled data at a specific frequency and compares it with the feature code of the characteristic current signal to determine whether the characteristic current has been collected, thereby determining the topology relationship. Within the distribution area, the current direction on the power line is fixed, flowing only from the lower-level equipment to the upper-level equipment, that is, only from the lower-level distribution area topology identification device to the upper-level distribution area topology identification device, and ultimately all flowing to the distribution area transformer. Therefore, the characteristic current injected by the transmitting equipment will only be recognized by its upper-level equipment. That is, the characteristic current output by the characteristic signal injection unit 2 in the lower-level distribution area topology identification device, transmitted through the power line, will only be recognized by the acquisition unit 4 in the upper-level distribution area topology identification device. Therefore, by notifying all equipment in the distribution area to inject characteristic current in sequence and collecting the topology identification information of all equipment, the distribution area topology relationship can be obtained, thus completing the distribution area topology identification.

[0071] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A distribution station area topology identification device, characterized in that, The distribution station area topology identification device includes: an MCU control unit, a feature signal injection unit, a data acquisition unit, and a frequency selective amplification unit; The MCU control unit is electrically connected to the output of the feature signal injection unit via a wire, and the feature signal injection unit is electrically connected to the power line; the MCU control unit is electrically connected to the input of the frequency selective amplification unit via a wire, the frequency selective amplification unit is electrically connected to the input of the acquisition unit via a wire, and the acquisition unit is electrically connected to the power line. The MCU control unit includes a processor D1; Pin 10 of the processor D1 is connected to the frequency selective amplifier unit; Pin 29 of the processor D1 is connected to the feature signal injection unit; The MCU control unit uses an HC32F460 processor; The frequency selective amplification unit includes a common-mode output conversion circuit and a frequency selective amplification circuit; The common-mode output conversion circuit includes an operational amplifier U1A. Pins 1 and 2 of the operational amplifier U1A are connected to the VCC terminal. Pin 3 of the operational amplifier U1A is connected to resistors R24 and R26, with the other end of resistor R26 connected to the acquisition unit. Pin 4 of the operational amplifier U1A is connected to resistors R28 and R31, with the other end of resistor R28 connected to the acquisition unit and the other end of resistor R31 grounded. Pin 5 of the operational amplifier U1A is connected to resistor R24 ​​and the frequency selective amplifier circuit. The frequency selective amplification unit includes a frequency selective amplification circuit. The frequency selective amplification circuit includes an operational amplifier U1B whose pin 1 is connected to resistor R25 and capacitor C24. The other end of capacitor C24 is connected to a common-mode output conversion circuit via resistor R27. The other end of resistor R25 is connected to capacitor C23 and pin 3 of operational amplifier U1B. The other end of capacitor C23 is connected to the other end of capacitor C24. Pin 2 of operational amplifier U1B is connected to resistors R30 and R32. The other end of resistor R30 is connected to VCC, and the other end of resistor R32 is grounded. Pin 3 of operational amplifier U1B is connected to the MCU control unit via a second filtering circuit. The second filter circuit includes a resistor R29 and a capacitor C25. The resistor R29 is connected to pin 3 of the operational amplifier U1B. The other end of the resistor R29 is connected to pin 10 of the processor D1 in the MCU control unit and the capacitor C25. The other end of the capacitor C25 is grounded.

2. The distribution area topology identification device according to claim 1, characterized in that, The feature signal injection unit includes a full-wave rectifier circuit; the full-wave rectifier circuit includes a rectifier bridge BR1, pin 1 of the rectifier bridge BR1 is connected to the neutral wire of the power line, pin 2 of the rectifier bridge BR1 is connected to the live wire of the power line, pin 3 of the rectifier bridge BR1 is connected to the current injection control circuit, and pin 4 of the rectifier bridge BR1 is grounded.

3. The distribution area topology identification device according to claim 1, characterized in that, The feature signal injection unit includes a self-powered circuit, which includes a MOSFET Q1. The gate of the MOSFET Q1 is connected to the VDC terminal through a resistor R10. The source of the MOSFET Q1 is connected to a resistor R7. The other end of the resistor R7 is connected to the current injection control circuit and a resistor R3. The other end of the resistor R3 is connected to a capacitor C13, a Zener diode V1, and the gate of the MOSFET Q1. The other ends of the capacitor C13 and the Zener diode V1 are grounded.

4. A distribution area topology identification device according to claim 1, characterized in that, The feature signal injection unit includes a current injection control circuit, which includes an optocoupler D2. Pin 1 of the optocoupler D2 is connected to the VCC terminal. Pin 2 of the optocoupler D2 is connected to the collector of transistor VT2. The base of the transistor is connected to the MCU control unit through a dynamic response circuit, and the emitter of the transistor is grounded. Pin 3 of the optocoupler D2 is connected to a complementary drive circuit and a resistor R21. The other end of the resistor R21 is grounded. The complementary drive circuit is connected to the gate of MOSFET Q2 through a resistor R14. The gate of MOSFET Q2 is also connected to a resistor R18, a capacitor C18, and a Zener diode V2. The source of MOSFET Q2 is connected to a full-wave rectifier circuit and a self-powered circuit. The drain of MOSFET Q2 is connected to a resistor R19. The resistor R18, capacitor C18, Zener diode V2, and resistor R19 are grounded. Pin 4 of the optocoupler D2 is connected to the VDC terminal.

5. A distribution area topology identification device according to claim 4, characterized in that, The dynamic response circuit includes a resistor R16. One end of the resistor R16 is connected to the MCU control unit and the capacitor C16. The other end of the capacitor C16 is connected to a resistor R15. The other end of the resistor R15 is connected to the base of the diode VD2, the resistor R17 and the transistor VT2. The other ends of the resistor R16, the diode VD2 and the resistor R17 are grounded.

6. A distribution area topology identification device according to claim 1, characterized in that, The acquisition unit includes an acquisition circuit, which includes a current transformer T1. Pins 1 and 2 of the current transformer are connected to dual diodes V3 and V4, respectively. The other end of dual diode V3 is connected to the other end of dual diode V4. Pins 1 and 2 of the current transformer are also connected to the input terminal of a first filter circuit. The output terminal of the first filter circuit is connected to resistors R22 and R23 and a frequency selective amplifier unit, respectively. The other ends of resistors R22 and R23 are grounded.

7. A distribution area topology identification device according to claim 6, characterized in that, The first filter circuit includes a capacitor C20. One end of the capacitor C20 is connected to the dual diode V3 and the inductor L1, respectively. The other end of the capacitor C20 is connected to the capacitor C22 and the ground terminal, respectively. The other end of the capacitor C22 is connected to the inductor L2, respectively. The other end of the inductor L2 is connected to the resistor R23 and the capacitor C21, respectively. The other end of the capacitor C21 is connected to the capacitor C19 and the ground terminal, respectively. The other end of the capacitor C19 is connected to the resistor R22 and the other end of the inductor L1, respectively.

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