Array substrate, display panel and display device

Abstract

The application relates to an array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of pixel circuits, an initialization signal line and a first power voltage signal line. The pixel circuit comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially away from the substrate. Each initialization signal line extending along a first direction is connected through a target connecting line extending along a second direction. Each initialization signal line is located at the second metal layer. The initialization nodes of two pixel circuits located at both sides of the target connecting line are connected with the target connecting line, and the target connecting line is located at the third metal layer. The first power voltage signal line extending along the second direction is located at the fourth metal layer, and the first power voltage signal line is used for transmitting a first power signal. The array substrate can reduce the number of connecting lines connecting the initialization signal line and the pixel circuit, thereby saving the wiring space.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] At present, in the display product, the pixel circuit is mainly used to drive the pixel to emit light. In the driving process of the pixel circuit, the initialization signal is needed to initialize the corresponding node of the pixel circuit, so as to better write the data signal.

[0003] However, in the array substrate of the existing display product, the initialization signal line needs to transmit the initialization signal to each pixel circuit. Therefore, there are many wirings on the array substrate of the display product, which limits the wiring space of the array substrate and is not conducive to the improvement of the pixel density. SUMMARY

[0004] Therefore, it is necessary to provide an array substrate, a display panel and a display device to solve the problem of limited wiring space of the array substrate due to too many wirings on the array substrate in the related art.

[0005] In a first aspect, the present application provides an array substrate, comprising: a substrate, a plurality of pixel circuits, an initialization signal line and a first power voltage signal line; wherein the pixel circuit comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially away from the substrate; wherein

[0006] Each initialization signal line extending along the first direction is connected by a target connection line extending along the second direction; wherein each initialization signal line is located in the second metal layer, and the initialization nodes of the two pixel circuits located on both sides of the target connection line are respectively connected with the target connection line, and the target connection line is located in the third metal layer;

[0007] The first power voltage signal line extending along the second direction is located in the fourth metal layer, and the first power voltage signal line is used to transmit the first power signal.

[0008] The array substrate provided in the embodiments of the present application can form a mesh structure by connecting each initialization signal line extending in the first direction through the target connection line extending in the second direction, thereby reducing the voltage drop of the initialization signal on the initialization signal line, being conducive to maintaining the potential uniformity of the initialization signal, and further being conducive to improving the display uniformity of the low gray scale of the display panel. On this basis, since the initialization nodes of the two pixel circuits located on both sides of the target connection line are connected with the target connection line respectively, for one initialization signal line, it is not necessary to set each row of initialization signal lines to correspond to each pixel circuit of the adjacent row one by one as in the related art, thereby the number of connection lines connecting the initialization signal line and the pixel circuit can be reduced, thereby the wiring space can be saved, being conducive to the miniaturization of the pixel, and further being conducive to improving the pixel density.

[0009] In a second aspect, the present application provides a display panel, comprising the array substrate as described above.

[0010] The display panel provided in the embodiments of the present application comprises the array substrate of the above embodiments, and the array substrate of the above embodiments reduces the voltage drop of the initialization signal on the initialization signal line, thereby being conducive to improving the display uniformity of the low gray scale of the display panel. In addition, the array substrate reduces the number of connection lines connecting the initialization signal line and the pixel circuit, saves the wiring space, and is conducive to the miniaturization of the pixel and the improvement of the pixel density, and therefore, the display panel of the embodiments of the present application can have a higher pixel density, thereby being conducive to improving the display effect of the display panel.

[0011] In a third aspect, the present application provides a display device, comprising the display panel as described above.

[0012] The display device provided in the embodiments of the present application comprises the display panel of the above embodiments, and since the display panel of the above embodiments improves the display uniformity of the low gray scale of the display panel and can have a higher pixel density, the display effect of the display panel is good, and therefore, the display device provided in the embodiments of the present application also has a good display effect. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0014] Figure 1 A planar layout structure schematic diagram of an array substrate provided in the related art;

[0015] Figure 2A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application;

[0016] Figure 3 A schematic diagram of a planar layout structure of an array substrate provided by another embodiment of the present application;

[0017] Figure 4 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present application;

[0018] Figure 5 A schematic diagram of a planar layout structure of an array substrate provided by still another embodiment of the present application;

[0019] Figure 6 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 An enlarged view of the portion I in FIG. 4;

[0020] Figure 7 A schematic diagram of a planar layout structure of an array substrate provided by yet another embodiment of the present application;

[0021] Figure 8 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 7 An enlarged view of the portion II in FIG. 5;

[0022] Figure 9 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 A schematic diagram of a structure of an active layer in FIG. 6;

[0023] Figure 10 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 A schematic diagram of a structure of a first metal layer M1 in FIG. 6;

[0024] Figure 11 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 A schematic diagram of a structure of a second metal layer MC in FIG. 6;

[0025] Figure 12 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 A schematic diagram of a structure of a third metal layer M2 in FIG. 6;

[0026] Figure 13 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 5 A schematic diagram of a structure of a fourth metal layer M3 in FIG. 6;

[0027] Figure 14 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 7 A schematic diagram of a structure of an active layer in FIG. 7;

[0028] Figure 15 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 7 A schematic diagram of a structure of a first metal layer M1 in FIG. 7;

[0029] Figure 16 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 7 A schematic diagram of a structure of a second metal layer MC in FIG. 7;

[0030] Figure 17 A schematic diagram of a planar layout structure of an array substrate provided by an embodiment of the present application; Figure 7A structural schematic diagram of the third metal layer M2;

[0031] Figure 18 A structural schematic diagram of the fourth metal layer M3; Figure 7 A structural schematic diagram of the fourth metal layer M3;

[0032] Figure 19 A structural schematic diagram of another display panel provided by an embodiment of the present application;

[0033] Figure 20 A structural schematic diagram of a display device provided by an embodiment of the present application.

[0034] Explanation of reference signs:

[0035] 10-pixel circuit, 11-first initialization signal line, 12-second initialization signal line, 13-first initialization connection line, 14-second initialization connection line, 20-pixel circuit, 201-initialization node, 2011-first initialization node, 2012-second initialization node, 21-initialization signal line, 211-first initialization signal line, 212-second initialization signal line, 22-target connection line, 221-first target connection line, 222-second target connection line, 23-first node connection line, 24-second node connection line, 241-first sub-connection line, 242-second sub-connection line, 243-third sub-connection line, 31-first power voltage signal line, 41-data signal line, 51-first scan signal line, 52-second scan signal line, 53-emission control signal line, 54-first plate, 55-second plate; 200-array substrate, 300-opposite substrate, 400-emitting element, 2000-display device, 2001-display panel. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein in the specification merely describe specific embodiments of the present application for the purpose of understanding the present application and are not intended to limit the present application.

[0038] Figure 1 A planar layout structural schematic diagram of an array substrate provided by the related art is shown in FIG. 1. As shown in FIG. 1, the array substrate includes a plurality of pixel circuits 10, a first initialization signal line 11, a second initialization signal line 12, a first initialization connection line 13, and a second initialization connection line 14. Figure 1As shown, the array substrate includes a first initialization signal line 11 and a second initialization signal line 12 extending along a first direction, a first initialization connection line 13 and a second initialization connection line 14 extending along a second direction, wherein the first direction can be an X direction, and the second direction can be a Y direction. The first initialization signal line 11 is electrically connected to the first initialization connection line 13 through a via, and the second initialization signal line 12 is electrically connected to the second initialization connection line 14 through a via. The first initialization signal line 11 transmits a first initialization signal Vref1 to a pixel circuit 10 in an adjacent row through the first initialization connection line 13, and the second initialization signal line 12 and the fourth initialization signal line 14 are used to transmit a second initialization signal Vref2. From Figure 1 It can be found that, corresponding to each planar region where the pixel circuit 10 is located, there is a first initialization signal line 11, a second initialization signal line 12, a first initialization connection line 13 and a second initialization connection line 14 passing therethrough, respectively.

[0039] Therefore, based on the above Figure 1 It can be found that there are many wirings on the array substrate of the display product, which limits the wiring space of the array substrate and is not conducive to the improvement of the pixel density.

[0040] Based on the above technical problems, the inventors have found that, by changing the wiring of the connection line connecting the initialization signal line and the pixel circuit, the connection line is connected to multiple pixel circuits at the same time, which can reduce the wiring on the array substrate. Based on this, the inventors have further researched the technical scheme of the embodiments of the present application. Specifically, the present application provides an array substrate, which comprises: a substrate, a plurality of pixel circuits, initialization signal lines, and a first power voltage signal line; wherein the pixel circuit comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer successively away from the substrate; each initialization signal line extending along a first direction is connected through a target connection line extending along a second direction; wherein each initialization signal line is located in the second metal layer, and the initialization nodes of two pixel circuits located on both sides of the target connection line are connected to the target connection line, respectively, and the target connection line is located in the third metal layer; the first power voltage signal line extending along the second direction is located in the fourth metal layer, and the first power voltage signal line is used to transmit a first power signal.

[0041] By using the above scheme, each initialization signal line extending along the first direction is connected through the target connection line extending along the second direction, and since the initialization nodes of the two pixel circuits located on both sides of the target connection line are connected to the target connection line, respectively, for a initialization signal line, it is not necessary to set each row of initialization signal lines to correspond to each pixel circuit in an adjacent row one by one as in the related art, thereby reducing the number of connection lines connecting the initialization signal lines and the pixel circuits, saving the wiring space, being conducive to the miniaturization of the pixel, and further being conducive to the improvement of the pixel density.

[0042] The above is the core idea of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] Figure 2 A schematic diagram of a planar layout structure of an array substrate provided in an embodiment of the present application is shown in FIG. 1. Figure 3 A schematic diagram of another planar layout structure of an array substrate provided in an embodiment of the present application is shown in FIG. 2. The array substrate includes a substrate, a plurality of pixel circuits 20, an initialization signal line 21, and a first power voltage signal line 31. The pixel circuit 20 includes a first metal layer M1, a second metal layer MC, a third metal layer M2, and a fourth metal layer M3 in sequence away from the substrate. As shown in FIG. 2, each initialization signal line 21 extending in a first direction is connected by a target connection line 22 extending in a second direction. The initialization signal line 21 is located in the second metal layer MC. The initialization nodes 201 of the two pixel circuits 20 located on both sides of the target connection line 22 are connected to the target connection line 22, and the target connection line 22 is located in the third metal layer M2. The first power voltage signal line 31 extending in the second direction is located in the fourth metal layer M3, and the first power voltage signal line 31 is used to transmit a first power signal. Figure 2 Figure 3 The first direction can be the X direction, and the second direction can be the Y direction. The initialization node 201 is a node of the pixel circuit 20 receiving an initialization signal Vref.

[0044] It should be noted that, A schematic diagram of a layout structure of an array substrate designed by mirroring is shown in FIG. 3.

[0045] A schematic diagram of a layout structure of an array substrate designed by mirroring is shown in FIG. 3. Figure 2 The layout design shown in FIG. 4 can be adapted to an array substrate based on the LTPO (Low Temperature Polycrystalline Oxide) technology. Figure 3 The layout design shown in FIG. 5 can be adapted to an array substrate based on the LTPS (Low Temperature Poly-silicon) technology. Figure 2 Figure 3 The layout design shown in FIG. 4 can be adapted to an array substrate based on the LTPO (Low Temperature Polycrystalline Oxide) technology. Figure 2 The layout design shown in FIG. 5 can be adapted to an array substrate based on the LTPS (Low Temperature Poly-silicon) technology. Figure 3 The layout design shown in FIG. 4 can be adapted to an array substrate based on the LTPO (Low Temperature Polycrystalline Oxide) technology.

[0046] The layout design shown in FIG. 5 can be adapted to an array substrate based on the LTPS (Low Temperature Poly-silicon) technology. Figure 2 ​As shown, each initialization signal line 21 is electrically connected with the target connection line 22 through the via, so that the initialization signal line 21 is connected with the target connection line 22 in parallel through the via, the resistance of the whole line formed by the two is reduced, thereby reducing the voltage drop of the initialization signal Vref on the initialization signal line 21, which is beneficial to maintaining the potential uniformity of the initialization signal Vref, and further beneficial to improving the display uniformity of the low gray scale of the display panel. Please refer to Figure 2 , between the two initialization signal lines 21, the initialization nodes 201 of the two pixel circuits 20 located on both sides of the target connection line 22 are respectively connected with the target connection line 22, so that the area where the two adjacent pixel circuits 20 are located can be provided with only one target connection line 22, and the planar area where the two pixel circuits 20 are located only passes through one target connection line 22, and if the scheme in the related art is used, the planar area where each pixel circuit 20 is located passes through one target connection line 22, and it can be found by comparison that the scheme of the embodiment significantly reduces the number of target connection lines 22, saves the wiring space, is beneficial to the miniaturization of the pixel, and further beneficial to improving the pixel density. It should be noted that in the related art, the first power voltage signal line 31 extending along the second direction is located on the third metal layer M2, and in the embodiment, the first power voltage signal line 31 extending along the second direction is located on the fourth metal layer M3, thereby leaving a horizontal space on the third metal layer M2, thereby facilitating the wiring of the target connection line 22.

[0047] Optionally, the substrate 20 provided by the embodiment of the present application can be a flexible substrate or a rigid substrate, which is not limited by the embodiment of the present application.

[0048] In summary, the array substrate provided by the embodiment of the present application connects each initialization signal line extending along the first direction through the target connection line extending along the second direction, which can form a mesh structure, reduces the voltage drop of the initialization signal on the initialization signal line, is beneficial to maintaining the potential uniformity of the initialization signal, and further beneficial to improving the display uniformity of the low gray scale of the display panel. On this basis, since the initialization nodes of the two pixel circuits located on both sides of the target connection line are respectively connected with the target connection line, for one initialization signal line, it is not necessary to one-to-one correspond each pixel circuit of the adjacent row to each initialization signal line of the row as in the related art, thereby the number of connection lines connecting the initialization signal line and the pixel circuit can be reduced, thereby the wiring space can be saved, which is beneficial to the miniaturization of the pixel, and further beneficial to improving the pixel density.

[0049] Figure 4 A structure schematic diagram of a pixel circuit provided by the embodiment of the present application. On the basis of the above scheme, please refer to Figure 2 and Figure 3 Optionally, the initialization signal line 21 is used for transmitting the first initialization signal Vref1 or the second initialization signal Vref2 (i.e.Figure 2 and Figure 3 The initialization signal Vref is the first initialization signal Vref1 or the second initialization signal Vref2, the first initialization signal Vref1 is used to initialize the gate of the driving transistor T0 of the pixel circuit 20, and the second initialization signal Vref2 is used to initialize the anode of the light emitting device.

[0050] The initialization signal line 21 extending in the first direction can be used to transmit the first initialization signal Vref1, and the initialization signal line 21 is located in the second metal layer MC and connected by the target connection line 22 extending in the second direction. At this time, the initialization signal line 21 transmits the first initialization signal Vref1 to the target connection line 22, and then transmits the first initialization signal Vref1 to the initialization nodes 201 of the two pixel circuits 20 located on both sides of the target connection line 22 through the target connection line 22.

[0051] As shown in Figure 4 The pixel circuit 20 includes a driving transistor T0, a storage capacitor Cst, a writing transistor T1, a threshold compensation transistor T2, a first initialization transistor T3, a second initialization transistor T4, a first light emitting control transistor T5, and a second light emitting control transistor T6. The initialization node 201 receives the first initialization signal Vref1 and transmits the first initialization signal Vref1 to the first electrode of the first initialization transistor T3. In the initialization stage, the first initialization transistor T3 is turned on, so as to transmit the first initialization signal Vref1 to the gate of the driving transistor T0 of the pixel circuit 20, and initialize the gate of the driving transistor T0.

[0052] Similarly, the initialization signal line 21 extending in the first direction can be used to transmit the second initialization signal Vref2, and the initialization signal line 21 is located in the second metal layer MC and connected by the target connection line 22 extending in the second direction. At this time, the initialization signal line 21 transmits the second initialization signal Vref2 to the target connection line 22, and then transmits the second initialization signal Vref2 to the initialization nodes 201 of the two pixel circuits 20 located on both sides of the target connection line 22 through the target connection line 22. The initialization node 201 receives the second initialization signal Vref2 and transmits the second initialization signal Vref2 to the first electrode of the second initialization transistor T4. In the writing stage, the second initialization transistor T4 is turned on, so as to transmit the second initialization signal Vref2 to the anode of the light emitting device, and initialize the anode of the light emitting device.

[0053] The initialization signal line 21 can also include a first initialization signal line 211 for transmitting the first initialization signal Vref1 and a second initialization signal line 212 for transmitting the second initialization signal Vref2, which will be further described in the following embodiments.

[0054] Figure 5 A schematic diagram of another planar layout structure of an array substrate provided in an embodiment of this application; Figure 6 for Figure 5 Enlarged view of section I in the middle. Figure 7 This is a schematic diagram of another planar layout structure of an array substrate provided in an embodiment of this application; Figure 8 for Figure 7 Enlarged view of section II.

[0055] Based on the above solutions, optionally, please refer to Figure 5 to Figure 8 The initialization signal line 21 includes a first initialization signal line 211 and a second initialization signal line 212 arranged alternately in the second direction. The first initialization signal line 211 is used to transmit the first initialization signal Vref1, and the second initialization signal line 212 is used to transmit the second initialization signal Vref2. The target connection line 22 includes a first target connection line 221 and a second target connection line 222 arranged alternately in the first direction. Two adjacent first initialization signal lines 211 are connected through the first target connection line 221, and two adjacent second initialization signal lines 212 are connected through the second target connection line 222.

[0056] Optionally, the distance between adjacent first initialization signal lines 211 and second initialization signal lines 212 is equal. This ensures that the first initialization signal lines 211 and second initialization signal lines 212 are uniformly arranged, optimizing the routing of the array substrate.

[0057] Optionally, the distance between adjacent first target connection lines 221 and second target connection lines 222 is equal. This ensures that the first target connection lines 221 and second target connection lines 222 are uniformly arranged, optimizing the routing of the array substrate.

[0058] In applications, such as Figure 4 As shown, the pixel circuit 20 includes a driving transistor T0, a first initialization transistor T3, and a second initialization transistor T4. The first terminal of the first initialization transistor T3 receives a first initialization signal Vref1, and the second terminal of the first initialization transistor T3 is connected to the gate of the driving transistor T0. The first terminal of the second initialization transistor T4 receives a second initialization signal Vref2, and the second terminal of the second initialization transistor T4 is connected to the anode of the light-emitting device. When the first initialization transistor T3 is turned on, the first initialization signal Vref1 initializes the gate of the driving transistor T0 of the pixel circuit 20. When the second initialization transistor T4 is turned on, the second initialization signal Vref2 initializes the anode of the light-emitting device. Thus, the initialization of the gate of the driving transistor T0 and the anode of the light-emitting device is achieved through the first initialization signal Vref1 and the second initialization signal Vref2, ensuring the uniformity of the display effect during the light-emitting phase.

[0059] It can be understood that two adjacent first initialization signal lines 211 are connected through the first target connection line 221, and the first target connection line 221 is also used for transmitting the first initialization signal Vref1. The first initialization signal line 211 and the first target connection line 221 form a parallel first mesh structure line, the resistance of the first mesh structure line is reduced relative to the first initialization signal line 211, and the first mesh structure line is used to help maintain the potential uniformity of the first initialization signal Vref1, and then help ensure the initialization uniformity of the gate of the driving transistor T0 of each pixel circuit 20, thereby improving the display uniformity of the display panel. Two adjacent second initialization signal lines 212 are connected through the second target connection line 222, and the second target connection line 222 is also used for transmitting the second initialization signal Vref2. The second initialization signal line 212 and the second target connection line 222 form a parallel second mesh structure line, the resistance of the second mesh structure line is reduced relative to the second initialization signal line 212, and the first mesh structure line is used to help maintain the potential uniformity of the second initialization signal Vref2, and then help ensure the initialization uniformity of the anode of the light emitting device, thereby improving the display uniformity of the display panel.

[0060] Please refer to Figure 5 to Figure 8 , the first initialization signal line 211 and the second initialization signal line 212 are staggered in the second direction. One first initialization signal line 211 can be connected to the first initialization nodes 2011 of two adjacent rows of pixel circuits 20 through the first target connection line 221, and one first initialization signal line 211 can be connected to the second initialization nodes 2012 of two adjacent rows of pixel circuits 20 through the second target connection line 222. The first initialization signal line 211 and the second initialization signal line 212 arranged adjacent to each other are respectively connected to the first initialization node 2011 and the second initialization node 2012 of the same pixel circuit 20. The total number of the first initialization signal line 211 and the second initialization signal line 212 is close to the number of rows of pixel circuits 20, rather than twice the number of rows of pixel circuits 20 as in the related art. For example, as shown in Figure 6 , two rows of pixel circuits 20 only need three signal lines, thereby reducing the wiring and saving the wiring space.

[0061] Exemplarily, in a case that the distance between the first initialization signal line 211 and the second initialization signal line 212 arranged adjacently is equal, for each planar region where the pixel circuit 20 is located, there can be only one first initialization signal line 211 or one second initialization signal line 212 passing through, instead of one first initialization signal line 11 and one second initialization signal line 12 passing through as in the related art, thereby reducing the number of the first initialization signal line 211 and the second initialization signal line 212, and further saving the wiring space.

[0062] Figure 9 For Figure 5 the structure schematic diagram of the active layer in the second embodiment; Figure 10 For Figure 5 the structure schematic diagram of the first metal layer M1 in the second embodiment; Figure 11 For Figure 5 the structure schematic diagram of the second metal layer MC in the second embodiment; Figure 12 For Figure 5 the structure schematic diagram of the third metal layer M2 in the second embodiment; Figure 13 For Figure 5 the structure schematic diagram of the fourth metal layer M3 in the second embodiment; Figure 14 For Figure 7 the structure schematic diagram of the active layer in the third embodiment; Figure 15 For Figure 7 the structure schematic diagram of the first metal layer M1 in the third embodiment; Figure 16 For Figure 7 the structure schematic diagram of the second metal layer MC in the third embodiment; Figure 17 For Figure 7 the structure schematic diagram of the third metal layer M2 in the third embodiment; Figure 18 For Figure 6 the structure schematic diagram of the fourth metal layer M3 in the third embodiment. Wherein, Figure 5 and Figure 6 the structure diagram of each film layer please refer to Figure 9 to Figure 13 , Figure 7 and Figure 8 the structure diagram of each film layer please refer to Figure 14 to Figure 18 .

[0063] On the basis of the above scheme, optionally, please refer to Figure 5 to Figure 8 the pixel circuit 20 includes a first initialization node 2011 and a second initialization node 2012, the first initialization node 2011 is used for receiving the first initialization signal Vref1 of the first initialization node 2011, and the second initialization node 2012 is used for receiving the second initialization signal Vref2 of the second initialization node 2012. Wherein, the first target connecting line 221 and the second target connecting line 222 arranged adjacently are respectively connected with the first initialization node 2011 and the second initialization node 2012 of the same pixel circuit 20.

[0064] It can be understood that the first electrode of the first initialization transistor T3 is connected with the first initialization node 2011, so that the first electrode of the first initialization transistor T3 receives the first initialization signal Vref1; the first electrode of the second initialization transistor T4 is connected with the second initialization node 2012, so that the first electrode of the second initialization transistor T4 receives the second initialization signal Vref2.

[0065] Similarly, the first target connection lines 221 and the second target connection lines 222 are staggered in the first direction, one first target connection line 221 is connected with the first initialization nodes 2011 of the two adjacent pixel circuits 20, and one first target connection line 221 can be connected with the second initialization nodes 2012 of the two adjacent pixel circuits 20, so that the first target connection lines 221 and the second target connection lines 222 arranged adjacently correspond to the first initialization nodes 2011 and the second initialization nodes 2012 of the same pixel circuit 20 respectively. Therefore, the total number of the first target connection lines 221 and the second target connection lines 222 is close to the number of rows of the pixel circuits 20, instead of being twice the number of rows of the pixel circuits 20 as in the related art. For example, as shown in Figure 6 two rows of pixel circuits 20, only three target connection lines are needed, thereby reducing the wiring and saving the wiring space.

[0066] On the basis of the above scheme, optionally, referring to Figure 5 to Figure 8 In the first direction, the first initialization nodes 2011 of the two adjacent pixel circuits 20 are connected through the first node connection lines 23, and the first target connection lines 221 are connected with the first node connection lines 23. In the first direction, the second initialization nodes 2012 of the two adjacent pixel circuits 20 are connected through the second node connection lines 24, and the second target connection lines 222 are connected with the second node connection lines 24. Among them, the first node connection lines 23 and the second node connection lines 24 can extend along the first direction, so that in the first direction, the first initialization nodes 2011 of the two adjacent pixel circuits 20 are connected through the first node connection lines 23, and the second initialization nodes 2012 of the two adjacent pixel circuits 20 are connected through the second node connection lines 24.

[0067] It can be understood that the first initialization node 2011 of the two adjacent pixel circuits 20 is connected through the first node connection line 23, the first target connection line 221 is connected with the first node connection line 23, and then the first target connection line 221 is connected with the first initialization node 2011 of the two adjacent pixel circuits 20, so that the first target connection line 221 can transmit the first initialization signal Vref1 to the two adjacent pixel circuits 20, instead of the prior art in which the first initialization connection line 11 can only transmit the first initialization signal Vref1 to the pixel circuits 10 in the adjacent row, so that the first target connection line 221 is relatively less, the wiring of the array substrate in the embodiment of the application is reduced, and the wiring space is saved.

[0068] The second initialization node 2012 of the two adjacent pixel circuits 20 is connected through the second node connection line 24, the second target connection line 222 is connected with the second node connection line 24, and then the second target connection line 222 is connected with the second initialization node 2012 of the two adjacent pixel circuits 20, so that the second target connection line 222 can transmit the second initialization signal Vref2 to the two adjacent pixel circuits 20, instead of the prior art in which the second initialization connection line 14 can only transmit the second initialization signal Vref2 to the pixel circuits 10 in the adjacent row, so that the second target connection line 222 is relatively less, the wiring of the array substrate in the embodiment of the application is reduced, and the wiring space is saved

[0069] On the basis of the above scheme, optionally, please refer to Figure 12 and Figure 17 The first node connection line 23 is located in the third metal layer M2.

[0070] Since the first target connection line 221 is located in the third metal layer M2, in the case that the first node connection line 23 is located in the third metal layer M2, the first target connection line 221 does not need to be connected with the first node connection line 23 through a via, which is beneficial to reduce the process flow and avoid the problem of abnormal damage to the corresponding film layer caused by punching.

[0071] On the basis of the above scheme, optionally, please refer to Figure 9 and Figure 14 The array substrate further comprises an active layer, and the first initialization node 2011 is located in the active layer. Wherein, please refer to Figure 6 and Figure 8 The first node connection line 23 is connected with the first initialization node 2011 of the two adjacent pixel circuits 20 through the first via respectively.

[0072] Wherein, the first initialization transistor T3 can be a low-temperature polysilicon thin film transistor, and at this time, the active layer is a low-temperature polysilicon active layer. The first initialization transistor T3 can also be an oxide thin film transistor, and at this time, the active layer is an oxide active layer.

[0073] It can be understood that the first initialization transistor T3 includes an active layer, and the first initialization node 2011 located in the active layer is beneficial to transmitting the first initialization signal Vref1 to the first initialization transistor T3. Wherein, the active layer is located between the third metal layer M2 and the substrate, and the first node connecting line 23 and the first initialization node 2011 are located in different layers, so that the first via is arranged between the first node connecting line 23 and the first initialization node 2011, so that the first node connecting line 23 is connected with the first initialization node 2011 of the two adjacent pixel circuits 20 through the first via, so that the first initialization signal Vref1 on the first target connecting line 221 can be transmitted to the first initialization node 2011 through the first node connecting line 23 and the first via.

[0074] On the basis of the above scheme, optionally, please refer to Figure 2 , the two pixel circuits 20 located on both sides of the target connecting line 22 are mirror arranged. It should be noted that please refer to Figure 5 and Figure 6 , the target connecting line 22 includes the first target connecting line 221 and the second target connecting line 222, so in this embodiment, the two pixel circuits 20 located on both sides of the first target connecting line 221 are mirror arranged, and the two pixel circuits 20 located on both sides of the second target connecting line 222 are also mirror arranged.

[0075] Please refer to Figure 9 , the array substrate further includes an active layer, and the second initialization node 2012 and the second node connecting line 24 are located in the active layer.

[0076] Wherein, the two pixel circuits 20 located on both sides of the target connecting line 22 are mirror arranged, that is, the two pixel circuits 20 located on both sides of the target connecting line 22 are symmetrical. The second initialization node 2012 and the second node connecting line 24 are located in the active layer, and the second initialization node 2012 and the second node connecting line 24 are arranged in the same layer, and the second target connecting line 222 is connected with the active layer, so that the second initialization signal Vref2 can be transmitted to the second initialization node 2012 without multiple transmissions.

[0077] In addition, the second initialization node 2012 and the second node connecting line 24 can be located at the same position of the active layer, which is the intersection of the active layer and the symmetry axis of the two pixel circuits 20. Thus, the extension length of the second node connecting line 24 is reduced, and the wiring space is saved.

[0078] In the embodiment, the two adjacent pixel circuits 20 are completely mirror-symmetrical, the active layer lengths of the two adjacent pixel circuits 20 have no difference, thus the active layer resistances of the adjacent pixels have almost no difference, so that the difference of the active layer resistances of the adjacent pixels is extremely small, and then the reset effect of each pixel circuit 20 is guaranteed to be consistent, so as to improve the display uniformity.

[0079] On the basis of the above scheme, optionally, referring to Figure 5 and Figure 6 , the second target connection line 222 is connected with the second node connection line 24 through the second via.

[0080] As shown in Figure 9 and Figure 12 , the second target connection line 222 is located in the third metal layer M2, the second node connection line 24 is located in the active layer, and the second target connection line 222 and the second node connection line 24 are located in different layers. As shown in Figure 6 , the second target connection line 222 is connected with the second node connection line 24 through the second via, so as to realize the electrical connection between the second target connection line 222 and the second node connection line 24.

[0081] On the basis of the above scheme, optionally, referring to Figure 7 and Figure 8 , each pixel circuit 20 is arranged in an array, the orthographic projection of the first target connection line 221 on the substrate intersects with the orthographic projection of a pixel circuit 20 on the substrate; the orthographic projection of the second target connection line 222 on the substrate intersects with the orthographic projection of a pixel circuit 20 on the substrate.

[0082] As shown in Figure 17 , the first target connection line 221 and the second target connection line 222 are located in the third metal layer M2, the first node connection line 23 can be located in the third metal layer M2, and at least part of the second node connection line 24 can be the third metal layer M2, so that the first target connection line 221 can be directly connected with the first node connection line 23, and the second target connection line 222 can be directly connected with the second node connection line 24.

[0083] In the embodiment, in the case that the orthogonal projection of the first target connection line 221 on the substrate intersects with a part of the orthogonal projection of a pixel circuit 20 on the substrate, the first target connection line 221 can be connected with the end of the first node connection line 23, so as to connect the first target connection line 221 with the first initialization node 2011 of the adjacent two pixel circuits 20. Similarly, in the case that the orthogonal projection of the second target connection line 222 on the substrate intersects with a part of the orthogonal projection of a pixel circuit 20 on the substrate, the second target connection line 222 can be connected with the end of the second node connection line 24, so as to connect the second target connection line 222 with the second initialization node 2012 of the adjacent two pixel circuits 20.

[0084] On the basis of the above scheme, optionally, referring to Figure 7 and Figure 8 , the pixel circuits 20 are arranged in an array, and the second node connection line 24 comprises a first sub-connection line 241, a second sub-connection line 242 and a third sub-connection line 243 connected in sequence. Referring to Figure 16 and Figure 17 , the first sub-connection line 241 and the third sub-connection line 243 are located in the third metal layer M2, and the second sub-connection line 242 is located in the second metal layer MC.

[0085] As shown in Figure 16 and Figure 17 , since the first sub-connection line 241 and the third sub-connection line 243 are located in the third metal layer M2, and the second sub-connection line 242 is located in the second metal layer MC, the first sub-connection line 241 and the third sub-connection line 243 are connected with the second metal layer MC through vias, respectively, so that the second initialization signal Vref2 can be transmitted from the first sub-connection line 241 to the third sub-connection line 243, and by locating the second sub-connection line 242 in the second metal layer MC, the wiring space of the array substrate is reasonably arranged to meet the size design of the array substrate.

[0086] On the basis of the above scheme, optionally, referring to Figure 14 , the array substrate further comprises an active layer, and the second initialization node 2012 is located in the active layer. Referring to Figure 8The first end of the first sub-connection line 241 is connected with the second initialization node 2012 of the first pixel circuit 20 through a third via, and the first end of the first sub-connection line 241 is also connected with the second target connection line 222. The second end of the first sub-connection line 241 is connected with the first end of the second sub-connection line 242 through a fourth via. The second end of the second sub-connection line 242 is connected with the first end of the third sub-connection line 243 through a fifth via. The second end of the third sub-connection line 243 is connected with the second initialization node 2012 of the second pixel circuit 20 through a sixth via. At least part of the first pixel circuit 20 and at least part of the second pixel circuit 20 are located on both sides of the second target connection line 222.

[0087] The second initialization node 2012 is located in the active layer, so that the second initialization signal Vref2 received by the second initialization node 2012 can be transmitted to the first electrode of the second initialization transistor T4, and then when the second initialization transistor T4 is turned on, the second initialization signal Vref2 can be transmitted to the anode of the light emitting device, thereby initializing the anode of the light emitting device.

[0088] As shown in Figure 8 , since the first end of the first sub-connection line 241 is connected with the second initialization node 2012 of the first pixel circuit 20 through a third via, and the first end of the first sub-connection line 241 is also connected with the second target connection line 222, the second initialization signal Vref2 on the second target connection line 222 can be transmitted to the first end of the first sub-connection line 241, and then transmitted to the second initialization node 2012 of the first pixel circuit 20 through the third via, thereby initializing the anode of the light emitting device driven by the first pixel circuit 20 in the initialization stage. The second end of the first sub-connection line 241 is connected with the first end of the second sub-connection line 242 through a fourth via. The second end of the second sub-connection line 242 is connected with the first end of the third sub-connection line 243 through a fifth via. The second end of the third sub-connection line 243 is connected with the second initialization node 2012 of the second pixel circuit 20 through a sixth via, so that the second initialization signal Vref2 on the first end of the first sub-connection line 241 can be transmitted to the second end of the third sub-connection line 243 through the second sub-connection line 242, and then transmitted to the second initialization node 2012 of the second pixel circuit 20 through the sixth via, thereby initializing the anode of the light emitting device driven by the second pixel circuit 20 in the initialization stage.

[0089] On the basis of the above scheme, optionally, please refer to Figure 13 and Figure 18 The array substrate further comprises a data signal line 41 located in the fourth metal layer M3.

[0090] The data signal line 41 is used for transmitting a data signal. As shown in Figure 4As shown, the pixel circuit 20 comprises a write transistor T1, a first electrode of the write transistor T1 is connected with the data signal line 41, a second electrode of the write transistor T1 is connected with the first electrode of the drive transistor T0, in the write stage, the write transistor T1 is turned on, the data signal is written into the first electrode of the drive transistor T0 through the first electrode and the second electrode of the write transistor T1. In the embodiment, by locating the data signal line 41 on the fourth metal layer M3, space is left on the third metal layer M2, facilitating the routing of the target connection line 22.

[0091] On the basis of the above scheme, optionally, referring to Figure 4 , the pixel circuit 20 comprises a storage capacitor Cst. Referring to Figure 10 、 Figure 11 、 Figure 15 and Figure 16 , the first plate 54 of the storage capacitor Cst is located on the first metal layer M1, the second plate 55 of the storage capacitor Cst is located on the second metal layer MC, and the first plate 54 and the second plate 55 overlap in the direction perpendicular to the plane on which the substrate lies.

[0092] In the above scheme, the gate of the drive transistor T0 is located on the first metal layer M1, and the first plate 54 of the storage capacitor Cst is located on the same layer as the gate of the drive transistor T0, so that the first plate 54 of the storage capacitor Cst and the gate of the drive transistor T0 can be formed in the same process by using the same mask during the manufacturing of the array substrate, without the need to manufacture a mask for the first plate 54 of the storage capacitor Cst and the gate of the drive transistor T0 separately, thereby reducing the number of masks used in the manufacturing process of the array substrate, lowering the process cost, and simplifying the process steps. In addition, in the initialization stage, when the first initialization transistor T3 is turned on, the first initialization signal Vref1 is transmitted to the first plate 54 of the storage capacitor Cst and the gate of the drive transistor T0 through the first initialization transistor T3, so as to initialize the first plate 54 of the storage capacitor Cst and the gate of the drive transistor T0. The second plate 55 of the storage capacitor Cst is located on the second metal layer MC, and since the initialization signal line 21 is located on the second metal layer MC, the second plate 55 of the storage capacitor Cst and the initialization signal line 21 are located on the same layer, so that the second plate 55 of the storage capacitor Cst and the initialization signal line 21 can be formed in the same process by using the same mask during the manufacturing of the array substrate, without the need to manufacture a mask for the second plate 55 of the storage capacitor Cst and the initialization signal line 21 separately, thereby reducing the number of masks used in the manufacturing process of the array substrate, lowering the process cost, and simplifying the process steps.

[0093] On the basis of the above scheme, optionally, referring to Figure 10 and Figure 15The array substrate further includes a first scan signal line 51, a second scan signal line 52, and a light emission control signal line 53. The first scan signal line 51, the second scan signal line 52, and the light emission control signal line 53 are respectively located in the first metal layer M1, and the second scan signal line 52 is located between the first scan signal line 51 and the light emission control signal line 53. The first scan signal line 51 is used to output a first scan signal, the second scan signal line 52 is used to output a second scan signal, and the light emission control signal line 53 is used to output a light emission control signal.

[0094] like Figure 4 As shown, the pixel circuit 20 includes a driving transistor T0, a storage capacitor Cst, a write transistor T1, a threshold compensation transistor T2, a first initialization transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. The gates of the write transistor T1, threshold compensation transistor T2, first initialization transistor T3, second initialization transistor T4, first light-emitting control transistor T5, and second light-emitting control transistor T6 are located on the first metal layer M1. Therefore, the gate of the first initialization transistor T3 can be connected to the first scan signal line 51 to receive the first scan signal; the gates of the write transistor T1, threshold compensation transistor T2, and second initialization transistor T4 can be connected to the second scan signal line 52 to receive the second scan signal; and the gates of the first light-emitting control transistor T5 and second light-emitting control transistor T6 can be connected to the light-emitting control signal line 53 to receive the light-emitting control signal.

[0095] In the initialization phase, the first initialization transistor T3 turns on in response to the first scan signal, transmitting the first initialization signal Vref1 to the first plate 54 of the storage capacitor Cst and the gate of the driving transistor T0, thus initializing the first plate 54 of the storage capacitor Cst and the gate of the driving transistor T0. Then, in the writing phase, the gates of the writing transistor T1, the threshold compensation transistor T2, and the second initialization transistor T4 turn on in response to the second scan signal. The data signal is written to the gate of the driving transistor T0 via the first and second terminals of the writing transistor T1, the first and second terminals of the driving transistor T0, and the first and second terminals of the threshold compensation transistor T2. During this phase, the second initialization signal Vref2 is written to the anode of the light-emitting device via the first and second terminals of the second initialization transistor T4, thus initializing the anode of the light-emitting device. Subsequently, during the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on in response to the light-emitting control signal. The first terminal of the driving transistor T0 is connected to the first power supply voltage signal PVDD, and the second terminal is connected to the light-emitting device. This, in turn, connects the second power supply voltage signal PVEE output from the second power supply voltage signal line, thereby enabling the driving transistor T0 to provide driving current to the light-emitting device and drive the light-emitting device to emit light.

[0096] Based on the same inventive concept, the embodiment of the present application further provides a display panel, Figure 19 FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application. The display panel provided by the embodiment of the present application comprises the array substrate 200 described in the embodiment of the present application, further comprises an opposite substrate 300 arranged opposite to the array substrate 200 and a plurality of light emitting elements 400 arranged between the array substrate 200 and the opposite substrate 300; and a pixel circuit is used to drive the light emitting elements 400 to emit light. Optionally, the light emitting element 400 can comprise an anode electrode, a light emitting material layer and a cathode electrode arranged in a stack. Optionally, the opposite substrate 300 can comprise a polaroid or a touch substrate, etc. Optionally, the display panel provided by the embodiment of the present application can further comprise an encapsulation layer (not shown in the figure) between the light emitting element 400 and the opposite substrate 300, which is used to protect the light emitting element 400 from water and oxygen. Optionally, the encapsulation layer can be a glass encapsulation layer or a thin film encapsulation layer, which is not limited in the embodiment of the present application.

[0097] Based on the same inventive concept, the embodiment of the present application further provides a display device, Figure 20 FIG. 1 is a structural schematic diagram of a display device according to an embodiment of the present application. The display device 2000 provided by the embodiment of the present application comprises the display panel 2001 according to any embodiment of the present application. Optionally, the display device provided by the embodiment of the present application can be a mobile phone as shown in FIG. 2. It can be understood that the display device in the embodiment of the present application can also be an OLED display device, a QLED display device, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device or any product or component having a display function, and the embodiments disclosed in the present application do not limit the display device. Figure 20 It can be understood that the display device in the embodiment of the present application can also be an OLED display device, a QLED display device, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device or any product or component having a display function, and the embodiments disclosed in the present application do not limit the display device.

[0098] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.

[0099] The technical features of the above-described embodiments can be combined arbitrarily, and in order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, it should be considered that it is within the scope of the present specification.

[0100] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises a substrate, a plurality of pixel circuits, an initialization signal line, and a first power voltage signal line; wherein the pixel circuit comprises a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer in sequence away from the substrate; wherein Each initialization signal line extending in the first direction is connected by a target connection line extending in the second direction; wherein each initialization signal line is located in the second metal layer, and initialization nodes of two pixel circuits located on both sides of the target connection line are respectively connected with the target connection line, and the target connection line is located in the third metal layer; The first power voltage signal line extending in the second direction is used for transmitting a first power signal; The target connection line comprises first target connection lines and second target connection lines staggered in the first direction, and between adjacent first target connection lines and second target connection lines in the first direction, one pixel circuit is arranged.

2. The array substrate of claim 1, wherein, The initialization signal line comprises first initialization signal lines and second initialization signal lines staggered in the second direction, the first initialization signal line is used for transmitting a first initialization signal, and the second initialization signal line is used for transmitting a second initialization signal; Two adjacent first initialization signal lines are connected by the first target connection line, and two adjacent second initialization signal lines are connected by the second target connection line.

3. The array substrate of claim 2, wherein, The pixel circuit comprises a first initialization node for receiving the first initialization signal and a second initialization node for receiving the second initialization signal; wherein The first target connection line and the second target connection line arranged adjacently correspond to the first initialization node and the second initialization node of the same pixel circuit, respectively.

4. The array substrate according to claim 2, wherein In the first direction, the first initialization nodes of two adjacent pixel circuits are connected by a first node connection line, and the first target connection line is connected with the first node connection line; In the first direction, the second initialization nodes of two adjacent pixel circuits are connected by a second node connection line, and the second target connection line is connected with the second node connection line.

5. The array substrate of claim 4, wherein, The first node connection line is located in the third metal layer.

6. The array substrate of claim 4, wherein, The array substrate further comprises an active layer, and the first initialization node is located in the active layer; wherein the first node connection line is connected with the first initialization nodes of the two adjacent pixel circuits by a first via.

7. The array substrate of claim 4, wherein, The two pixel circuits located on both sides of the target connection line are mirror arranged, the array substrate further comprises an active layer, and the second initialization node and the second node connection line are located in the active layer.

8. The array substrate of claim 7, wherein, The second target connection line is connected with the second node connection line by a second via.

9. The array substrate of claim 4, wherein, Each pixel circuit is arranged in an array, a normal projection of the first target connection line on the substrate intersects with a normal projection of a pixel circuit on the substrate, and a normal projection of the second target connection line on the substrate intersects with a normal projection of a pixel circuit on the substrate.

10. The array substrate of claim 4, wherein, The pixel circuits are arranged in an array, and the second node connection line comprises a first sub-connection line, a second sub-connection line and a third sub-connection line connected in sequence, the first sub-connection line and the third sub-connection line are located in the third metal layer, and the second sub-connection line is located in the second metal layer.

11. The array substrate of claim 10, wherein, The array substrate further comprises an active layer, the second initialization node is located in the active layer, a first end of the first sub-connection line is connected with the second initialization node of a first pixel circuit through a third via hole, and the first end of the first sub-connection line is also connected with the second target connection line, a second end of the first sub-connection line is connected with a first end of the second sub-connection line through a fourth via hole, a second end of the second sub-connection line is connected with a first end of the third sub-connection line through a fifth via hole, and a second end of the third sub-connection line is connected with the second initialization node of a second pixel circuit through a sixth via hole, at least part of the first pixel circuit and at least part of the second pixel circuit are located on two sides of the second target connection line.

12. The array substrate of claim 1, wherein, The initialization signal line is used for transmitting a first initialization signal or a second initialization signal, the first initialization signal is used for initializing a gate of a driving transistor of the pixel circuit, and the second initialization signal is used for initializing an anode of a light-emitting device.

13. The array substrate of claim 1, wherein, The array substrate further comprises a data signal line located in the fourth metal layer.

14. The array substrate of claim 1, wherein, The pixel circuit comprises a storage capacitor, a first plate of the storage capacitor is located in the first metal layer, a second plate of the storage capacitor is located in the second metal layer, and the first plate and the second plate overlap in a direction perpendicular to a plane in which the substrate is located.

15. The array substrate of claim 1, wherein, The array substrate further comprises a first scan signal line, a second scan signal line and a light-emitting control signal line, the first scan signal line, the second scan signal line and the light-emitting control signal line are respectively located in the first metal layer, and the second scan signal line is located between the first scan signal line and the light-emitting control signal line.

16. The array substrate of claim 1, wherein, The first power voltage signal line is located in the fourth metal layer.

17. A display panel, characterized by An array substrate as claimed in any one of claims 1-16.

18. A display device comprising: A display panel as claimed in claim 17.

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