Pixel circuit, driving method thereof, display panel and display device

Abstract

The application relates to a pixel circuit and a driving method thereof, a display panel and a display device. The pixel circuit comprises a driving transistor, a data writing module, a first end of the data writing module being used for receiving and writing a data signal and a compensation signal in a data writing stage in time. A storage module is connected with a gate of the driving transistor, and is used for storing a first electric potential of a driving node when the data signal is written, and storing a second electric potential of the driving node when the compensation signal is written. The first electric potential is provided to the gate of the driving transistor in a light emitting stage. The second electric potential is provided to the gate of the driving transistor in a preset time period of the light emitting stage. A threshold value compensation module is connected with the gate and the drain of the driving transistor respectively. The second electric potential is used to compensate the gate potential change amount of the driving transistor, so that the gate potential of the driving transistor can be kept stable, the brightness of a light emitting element can be kept stable, the brightness fluctuation of the light emitting element is reduced, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method thereof, a display panel and a display device. BACKGROUND

[0002] With the development of display technology, people's demand for display products is more and more diversified. Display products will adopt different refresh rates for display in different application scenarios. For example, a higher refresh rate driving mode is used to drive display of dynamic pictures to ensure the smoothness of the display picture, and a lower refresh rate driving mode is used to drive display of static pictures to reduce the power consumption of the display product. However, the traditional display product is prone to brightness fluctuation when displaying at a low refresh rate, which affects the display effect. SUMMARY

[0003] The present application provides a pixel circuit, a driving method thereof, a display panel and a display device. A second potential is provided for the gate of a driving transistor in a preset time period of a light emitting stage, thereby solving the problem of brightness fluctuation when the display product displays at a low refresh rate.

[0004] In a first aspect, an embodiment of the present application provides a pixel circuit, comprising:

[0005] a driving transistor, configured to generate a driving current to drive a light emitting element to emit light;

[0006] a data writing module, a first end of the data writing module being configured to receive a data signal and a compensation signal in a time-division manner in a data writing stage, and the data writing module being configured to write the received data signal and compensation signal to a driving node respectively, the driving node being a gate node of the driving transistor;

[0007] a storage module, connected to the gate of the driving transistor, configured to store a first potential of the driving node when the data signal is written, and store a second potential of the driving node when the compensation signal is written; wherein the first potential is a potential provided to the gate of the driving transistor in a light emitting stage; and the second potential is a potential provided to the gate of the driving transistor in a preset time period of the light emitting stage;

[0008] a threshold compensation module, connected to the gate of the driving transistor and a second end of the driving transistor respectively, configured to short the gate of the driving transistor and the second end of the driving transistor when turned on.

[0009] In a second aspect, an embodiment of the present application provides a display panel, comprising the pixel circuit provided in the first aspect.

[0010] In a third aspect, an embodiment of the present application provides a display device including the display panel provided in the second aspect.

[0011] In a fourth aspect, an embodiment of the present application provides a driving method of a pixel circuit, including a data writing stage and a light emitting stage; wherein,

[0012] In the data writing stage, a data writing module receives a data signal and a compensation signal in time division manner, and writes the received data signal and compensation signal into a driving node respectively, a storage module stores a first potential of the driving node when the data signal is written, and stores a second potential of the driving node when the compensation signal is written; wherein the driving node is a gate node of a driving transistor.

[0013] In the light emitting stage, the storage module provides the stored first potential to the gate node of the driving transistor, and in a preset time period of the light emitting stage, the storage module provides the stored second potential to the gate node of the driving transistor.

[0014] The pixel circuit provided by the embodiment of the present application can generate a driving current to drive the light emitting element to emit light by setting the driving transistor. The data writing module receives a data signal and a compensation signal in time division manner in the data writing stage, and writes the received data signal and compensation signal into a driving node between the data writing module and the gate node of the driving transistor, and the storage module can store a first potential of the driving node when the data signal is written, and store a second potential of the driving node when the compensation signal is written. The threshold compensation module is connected with the gate node and the second end of the driving transistor respectively, and short-circuits the gate node and the second end of the driving transistor when turned on, so as to eliminate the influence of the threshold voltage of the driving transistor on the gate potential of the driving transistor. In the light emitting stage, the first potential stored by the storage module can be provided to the gate node of the driving transistor, so as to control the size of the driving current generated by the driving transistor, to control the light emitting brightness of the light emitting element. However, due to the existence of the threshold compensation module, there will be a leakage current flowing from the threshold compensation module to the gate node of the driving transistor, so that the potential of the gate node of the driving transistor changes. Therefore, in a preset time period of the light emitting stage, the second potential stored by the storage module can be provided to the gate node of the driving transistor, to compensate for the amount of change of the gate potential of the driving transistor. When the display panel displays at a low refresh rate, the leakage time of the gate node of the driving transistor is prolonged, and the leakage time of the gate node of the driving transistor is too long, which will cause the gate voltage of the driving transistor to be unstable. The amount of change of the gate potential of the driving transistor is compensated by the second potential, so that the gate potential of the driving transistor remains stable, so that the brightness of the light emitting element remains stable, the brightness fluctuation of the light emitting element is reduced, and the display effect is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0016] Figure 1 Structure diagram of pixel circuit in prior art in one embodiment;

[0017] Figure 2 Structure diagram of pixel circuit in one embodiment;

[0018] Figure 3 Structure diagram of pixel circuit in another embodiment;

[0019] Figure 4 Structure diagram of pixel circuit in one embodiment including the first storage unit specific structure of method;

[0020] Figure 5 Structure diagram of pixel circuit in one embodiment including the second storage unit specific structure of method;

[0021] Figure 6 Structure diagram of pixel circuit in another embodiment;

[0022] Figure 7 Driving timing diagram of pixel circuit in one embodiment;

[0023] Figure 8 Driving timing diagram of pixel circuit in another embodiment;

[0024] Figure 9 Structure diagram of pixel circuit in another embodiment;

[0025] Figure 10 Structure diagram of pixel circuit in another embodiment;

[0026] Figure 11 Structure diagram of pixel circuit in another embodiment;

[0027] Figure 12 Structure diagram of pixel circuit in another embodiment;

[0028] Figure 13 Structure diagram of pixel circuit in another embodiment;

[0029] Figure 14 Structure diagram of pixel circuit in another embodiment;

[0030] Figure 15 Structure diagram of pixel circuit in another embodiment;

[0031] Figure 16 Structure diagram of pixel circuit in another embodiment;

[0032] Figure 17 Driving timing diagram of pixel circuit in another embodiment;

[0033] Figure 18 Structure diagram of display panel in another embodiment;

[0034] Figure 19 Structure diagram of display panel in another embodiment;

[0035] Figure 20 Structure diagram of display panel in another embodiment;

[0036] Figure 21 Structure diagram of display device in another embodiment;

[0037] Figure 22 Flow chart of driving method of pixel circuit in another embodiment;

[0038] Figure 23 Flow chart of driving method of pixel circuit in another embodiment;

[0039] Figure 24 Flow chart of driving method of pixel circuit in another embodiment.

[0040] Explanation of reference signs:

[0041] M1 - driving transistor, 10 - data writing module, 20 - storage module, N1 - driving node, D1 - light emitting element, 21 - first storage unit, 22 - second storage unit, S1 - first scan signal, M2 - first transistor, C1 - first storage capacitor, C2 - second storage capacitor, M3 - second transistor, S2 - second scan signal, 30 - threshold compensation module, M4 - third transistor, 40 - first initialization module, S3 - third scan signal, V1 - first initialization signal, S4 - fourth scan signal, M5 - fourth transistor, 50 - second initialization module, V2 - second initialization signal, M6 - fifth transistor, M7 - writing transistor, M8 - sixth transistor, M9 - seventh transistor, Emit - light emitting control signal, 100 - pixel circuit, 200 - display panel, 201 - data signal line, 202 - compensation signal line, 300 - display device. DETAILED DESCRIPTION

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0043] As described in the background section, display panels in the related art suffer from a technical problem where flickering occurs during low-frequency display. For example... Figure 1 The diagram shows a pixel circuit of a display panel in the related art, which includes a storage capacitor C. During the light-emitting phase, the potential stored in the storage capacitor C is provided to the gate of the driving transistor T1. However, due to leakage current during the light-emitting phase, when the brightness of the display panel is high, the potential of the gate of the driving transistor T1 is lower than the potential of the transistor T4. The leakage current flows through the transistor T4 to the gate of the driving transistor T1, causing the gate potential of the driving transistor T1 to increase. Conversely, when the brightness of the display panel is low, the potential of the gate of the driving transistor T1 is higher than the potential of the transistor T5. This results in leakage current flowing from the gate of the driving transistor T1 to the transistor T5, causing the gate potential of the driving transistor T1 to decrease. Therefore, the gate potential of the driving transistor T1 is unstable during the light-emitting phase. Existing display panels typically include multiple pixel circuits, each including a driving transistor that drives the light-emitting device to emit light. The driving transistor controls the brightness of the light-emitting device by controlling the driving current flowing through it. To extend the standby time of display panels and reduce power consumption, it is necessary to control the display panel to operate at low frequencies. Low-frequency display increases the duration of the light-emitting device's operation in the light-emitting phase within a single frame, leading to a prolonged leakage time at the gate of the driving transistor. Excessive leakage time at the driving transistor gate causes instability in the gate voltage. Generally, the gate voltage of the driving transistor is related to the driving current it generates; therefore, unstable gate voltage leads to unstable driving current for the light-emitting device, causing flickering. Thus, display panels in related technologies exhibit flickering during low-frequency display.

[0044] Based on the above technical problems, the inventors have found that by compensating the gate voltage of the driving transistor, the potential change of the gate of the driving transistor can be reduced, thereby keeping the luminance of the light emitting element stable, reducing the luminance fluctuation of the light emitting element, and improving the display effect. Based on this, the inventors have further researched and developed the technical scheme of the embodiments of the present application. Specifically, the embodiments of the present application provide a pixel circuit, comprising: a driving transistor, a data writing module, and a storage module; wherein the driving transistor is used to generate a driving current to drive a light emitting element to emit light; the first end of the data writing module is used to receive a data signal and a compensation signal in time division in a data writing stage, and the data writing module is used to write the received data signal and compensation signal to a driving node respectively; the storage module is connected with the gate of the driving transistor and is used to store a first potential of the driving node when the data signal is written and a second potential of the driving node when the compensation signal is written. The first potential is the potential provided to the gate of the driving transistor in a light emitting stage. The second potential is the potential provided to the gate of the driving transistor in a preset time period of the light emitting stage.

[0045] By adopting the above technical scheme, by setting the driving transistor, a driving current can be generated to drive the light emitting element to emit light. By setting the data writing module to receive the data signal and the compensation signal in time division in the data writing stage, and writing the received data signal and the compensation signal to the driving node between the data writing module and the gate of the driving transistor respectively, the storage module can store the first potential of the driving node when the data signal is written and the second potential of the driving node when the compensation signal is written. The threshold compensation module is connected with the gate and the second end of the driving transistor respectively, and short-circuits the gate and the second end of the driving transistor when turned on, thereby eliminating the influence of the threshold voltage of the driving transistor on the gate potential of the driving transistor. In the light emitting stage, the first potential stored by the storage module can be provided to the gate of the driving transistor, and the size of the driving current generated by the driving transistor can be controlled to control the luminance of the light emitting element. However, due to the existence of the threshold compensation module, there will be a leakage current flowing from the threshold compensation module to the gate of the driving transistor, causing the potential of the gate of the driving transistor to change. Therefore, in the preset time period of the light emitting stage, the second potential stored by the storage module can be provided to the gate of the driving transistor to compensate for the amount of change of the gate potential of the driving transistor. When the display panel displays at a low refresh rate, the leakage time of the gate of the driving transistor is prolonged, and the leakage time of the gate of the driving transistor is too long, which will cause the gate voltage of the driving transistor to be unstable. By compensating the amount of change of the gate potential of the driving transistor with the second potential, the gate potential of the driving transistor can be kept stable, so that the luminance of the light emitting element can be kept stable, the luminance fluctuation of the light emitting element can be reduced, and the display effect can be improved.

[0046] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0047] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present invention is shown below. Figure 2 As shown, the pixel circuit provided in this embodiment of the invention includes: a driving transistor M1, a data writing module 10, a storage module 20, and a threshold compensation module 30.

[0048] The driving transistor M1 is used to generate a driving current to drive the light-emitting element D1 to emit light. For details, please refer to [link to relevant documentation]. Figure 2 The source of driving transistor M1 is connected to the power supply signal PVDD, the drain of driving transistor M1 is connected to the anode of light-emitting element D1, and the gate of driving transistor M1 is connected to driving node N1. Thus, driving transistor M1 can generate a driving current under the control of its gate potential, driving light-emitting element D1 to emit light. The cathode of light-emitting element D1 is connected to the low-potential signal PVEE.

[0049] The first terminal of the data writing module 10 is used to receive data signals and compensation signals in a time-division multiplexing manner during the data writing stage. The data writing module 10 is used to write the received data signals and compensation signals to the driving node N1, which is the gate node of the driving transistor M1. In this embodiment, the operation of the pixel circuit includes at least a data writing stage and a light emission stage. In the data writing stage, the first terminal of the data writing module 10 receives data signals and compensation signals in a time-division multiplexing manner. The second terminal of the data writing module 10 is connected to the first terminal of the driving transistor M1. When a data signal is received, the data signal can flow through the first terminal of the driving transistor M1 to the second terminal of the driving transistor M1, and then be written to the driving node N1 through the threshold compensation module 30. When a compensation signal is received, the compensation signal is written to the driving node N1.

[0050] The storage module 20 is connected to the gate of the drive transistor M1, that is, the storage module 20 is connected to the drive node N1. The storage module 20 is used to store the first potential Vdata-|Vth| of the drive node N1 when the data signal is written, that is, the data signal includes the first potential Vdata-|Vth|, and store the second potential Vcomp-|Vth| of the drive node N1 when the compensation signal is written, that is, the compensation signal includes the second potential Vcomp-|Vth|. The first potential Vdata-|Vth| is the potential provided to the gate of the drive transistor M1 in the light-emitting stage. The second potential Vcomp-|Vth| is the potential provided to the gate of the drive transistor M1 in the preset time period of the light-emitting stage. When the data write module 10 writes the data signal to the drive node N1, the storage module 20 stores the first potential Vdata-|Vth| of the drive node N1, and when the data write module 10 writes the compensation signal to the drive node N1, the storage module 20 stores the second potential Vcomp-|Vth| of the drive node N1. The |Vth| is the threshold voltage of the drive transistor M1.

[0051] In the light-emitting stage, the first potential Vdata-|Vth| stored by the storage module 20 is provided to the gate of the drive transistor M1, so that the size of the drive current generated by the drive transistor M1 is controlled by the first potential Vdata-|Vth|, and the luminance of the light-emitting element is controlled. Due to the existence of the threshold compensation module 30, the leakage current flowing from the threshold compensation module 30 to the gate of the drive transistor M1 will cause the potential of the gate of the drive transistor M1 to change. Therefore, the second potential Vcomp-|Vth| stored by the storage module 20 is provided to the gate of the drive transistor M1 in the preset time period of the light-emitting stage, so that the change of the potential of the gate of the drive transistor M1 is compensated by the second potential Vcomp-|Vth|, so that the potential of the gate of the drive transistor M1 remains unchanged, and the luminance of the light-emitting element D1 remains stable, thereby reducing the luminance fluctuation of the light-emitting element D1.

[0052] The principle of the present application is illustrated by the pixel circuit shown in FIG. 1. Figure 12 The formula of the drive current is as follows:

[0053] I=k(PVDD-Vdata1) 2

[0054] Wherein, I is the driving current, k is the characteristic coefficient of the driving transistor M1, PVDD is the power voltage, Vdata1 is the gate voltage of the driving transistor M1, and in an ideal state, Vdata1 is equal to the first potential Vdata-|Vth|, but due to the existence of the leakage current in the light-emitting stage, when the brightness of the light-emitting element D1 is high, the potential of the gate of the driving transistor M1 is lower than the potential of the third transistor M4, the leakage current flows to the gate of the driving transistor M1 through the third transistor M4, so that the potential of the gate of the driving transistor M1 becomes larger, and / or when the brightness of the light-emitting element D1 is low, the potential of the gate of the driving transistor M1 is higher than the potential of the fourth transistor M5, the leakage current of the gate of the driving transistor M1 flows to the fourth transistor M5, so that the potential of the gate of the driving transistor M1 becomes smaller. As can be seen from the above formula, when the leakage phenomenon occurs in the pixel circuit, the gate voltage Vdata1 of the driving transistor M1 decreases, and I increases, so that the brightness of the light-emitting element D1 increases. When the leakage phenomenon occurs in the pixel circuit, the gate voltage Vdata1 of the driving transistor M1 increases, and I decreases, so that the brightness of the light-emitting element D1 decreases. Further, the brightness of the light-emitting element D1 fluctuates, and after the second potential Vcomp-|Vth| is provided to the gate of the driving transistor M1, the change of Vdata1 can be compensated, so that Vdata1 is equal to Vdata-|Vth|, and the brightness of the light-emitting element D1 remains stable.

[0055] The threshold compensation module 30 is connected with the gate and the second end of the driving transistor M1 and the storage module 20, and is used for short-circuiting the gate and the second end of the driving transistor M1 when turned on.

[0056] Specifically, in the data writing stage, the threshold compensation module 30 can be turned on to short-circuit the gate and the second end of the driving transistor M1, so that the gate potential of the driving transistor M1 is not affected by the threshold voltage of the driving transistor M1.

[0057] It should be noted that the source of the driving transistor M1 is the first end of the driving transistor M1, and the drain of the driving transistor M1 is the second end of the driving transistor M1.

[0058] In one embodiment, as shown in FIG. 2, the storage module 20 includes a first storage unit 21 and a second storage unit 22. Figure 3 The first storage unit 21 is connected with the gate of the driving transistor M1, and is used for storing the first potential of the driving node N1 when the data signal is written. The second storage unit 22 is connected with the gate of the driving transistor M1, and is used for storing the second potential of the driving node N1 when the compensation signal is written.

[0059] In the embodiment, the first storage unit 21 is configured to store the first potential, and the second storage unit 22 is configured to store the second potential, so that the first potential and the second potential can be stored separately, and the first potential and the second potential can be provided to the gate of the driving transistor M1 in the light-emitting stage, and then the driving current generated by the driving transistor is controlled by the first potential, and the light-emitting brightness of the light-emitting element is controlled, and the variation of the gate potential of the driving transistor is compensated by the second potential, so that the gate potential of the driving transistor is kept stable, the brightness of the light-emitting element is kept stable, the brightness fluctuation of the light-emitting element is reduced, and the display effect is improved.

[0060] In one embodiment, as shown in Figure 4 The first storage unit 21 includes a first storage capacitor C1 and a first transistor M2. The first end of the first storage capacitor C1 is configured to be connected to the first power supply signal PVDD1. The first end of the first transistor M2 is connected to the second end of the first storage capacitor C1, the second end of the first transistor M2 is connected to the gate of the driving transistor M1, and the control end of the first transistor M2 is configured to be connected to the first scan signal S1.

[0061] In the process of writing the data signal to the driving node N1, the first transistor M2 is turned on under the action of the first scan signal S1, the first storage capacitor C1 is connected to the driving node N1, and the first potential is stored in the first storage capacitor C1.

[0062] In the embodiment, the first storage unit 21 includes the first storage capacitor C1 and the first transistor M2, the first transistor M2 can be turned on to connect the path between the first storage capacitor C1 and the driving node N1 under the action of the first scan signal S1, the first potential can be stored in the first storage capacitor C1, and then the first potential can be provided to the gate of the driving transistor in the light-emitting stage, the size of the driving current generated by the driving transistor is controlled by the first potential, and the light-emitting brightness of the light-emitting element is controlled.

[0063] In one embodiment, as shown in Figure 5 The second storage unit 22 includes a second storage capacitor C2 and a second transistor M3. The first end of the second storage capacitor C2 is configured to be connected to the second power supply signal PVDD. The first end of the second transistor M3 is connected to the second end of the second storage capacitor C2, the second end of the second transistor M3 is connected to the gate of the driving transistor M1, and the control end of the second transistor M3 is configured to be connected to the second scan signal S2. When the second transistor M3 is turned on under the action of the second scan signal S2, the second storage capacitor C2 is configured to store the second potential of the driving node N1 when the compensation signal is written. The first transistor M2 and the second transistor M3 are turned on at different times in the data writing stage.

[0064] Specifically, the second transistor M3 is turned on under the action of the second scan signal S2 in the process that the data writing module 10 writes the compensation signal, so that the second storage capacitor C2 can be connected with the driving node N1 when the data writing module 10 writes the compensation signal to the driving node N1, and then the second potential is stored on the second storage capacitor C2. Since the data writing module 10 is to receive the data signal and the compensation signal in time division and write the data signal and the compensation signal to the driving node N1 in time division, the first transistor M2 and the second transistor M3 are turned on in time division in the data writing stage, so as to store the first potential on the first storage capacitor C1 and store the second potential on the second storage capacitor C2, respectively.

[0065] In the embodiment, by setting the second transistor M3, the second storage capacitor C2 can be controlled to keep connected with the driving node N1 in the process that the data writing module 10 writes the compensation signal under the action of the second scan signal S2, so as to store the second potential on the second storage capacitor C2, so as to provide the gate of the driving transistor in the preset time period of the light emitting stage and compensate the change of the gate potential of the driving transistor.

[0066] In one embodiment, as shown in Figure 6 The second power signal is the same signal as the first power signal.

[0067] In the embodiment, by setting the second power signal as the same signal as the first power signal, the potentials of the first ends of the first storage capacitor C1 and the second storage capacitor C2 are kept consistent.

[0068] Please continue to refer to Figure 5 In one embodiment, the second transistor M2 is further used to be turned on under the action of the second scan signal S2 in the preset time period of the light emitting stage, so as to provide the second potential stored on the second storage capacitor C2 to the gate of the driving transistor.

[0069] In the light emitting stage, the first potential stored in the first storage capacitor C1 is provided to the gate of the driving transistor M1 by controlling the first transistor M2 to be turned on. However, due to the leakage phenomenon of the pixel circuit, the potential of the gate of the driving transistor M1 changes, which causes the light emitting brightness of the light emitting element to fluctuate. Therefore, in the preset time period in the light emitting stage, the second potential stored in the second storage capacitor C2 is provided to the gate of the driving transistor M1 by controlling the second transistor M3 to be turned on, so that the change of the potential of the gate of the driving transistor M1 is compensated by the second potential, the potential of the gate of the driving transistor M1 remains unchanged, and the brightness of the light emitting element D1 remains stable, thereby reducing the brightness fluctuation of the light emitting element. The preset time period in the light emitting stage can be any time period after the initial time when the first potential is provided to the gate of the driving transistor. Since the leakage phenomenon occurs after the first potential is provided to the gate of the driving transistor M1, the second potential is provided to the gate of the driving transistor M1 after the first potential is provided to the gate of the driving transistor in the light emitting stage.

[0070] In the present embodiment, the second transistor M3 is turned on under the action of the second scan signal S2 in the preset time period in the light emitting stage, so that the second potential stored in the second storage capacitor C2 is provided to the gate of the driving transistor M1 in the preset time period in the light emitting stage, and the change of the potential of the gate of the driving transistor M1 is compensated, so that the light emitting of the light emitting element D1 is more stable.

[0071] In one embodiment, the initial time when the second potential is provided to the gate of the driving transistor is later than the initial time when the first potential is provided to the gate of the driving transistor. Specifically, please continue to refer to Figure 5 In the light emitting stage, the first potential is first provided to the gate of the driving transistor M1, so that the size of the driving current generated by the driving transistor M1 is controlled by the first potential, and the light emitting brightness of the light emitting element is controlled. Then, due to the leakage phenomenon of the pixel circuit, the potential of the gate of the driving transistor M1 changes, at this time, the second potential is provided to the gate of the driving transistor M1 again, the change of the potential of the gate of the driving transistor M1 is compensated, so that the potential of the gate of the driving transistor M1 remains unchanged, and the brightness of the light emitting element D1 remains stable.

[0072] In the present embodiment, the second potential is used to compensate the change of the potential of the gate of the driving transistor M1 caused by the leakage phenomenon of the pixel circuit. Therefore, by setting the initial time when the second potential is provided to the gate of the driving transistor M1 to be later than the initial time when the first potential is provided to the gate of the driving transistor M1, it can be avoided that the second potential affects the potential of the gate of the driving transistor M1 when the leakage phenomenon of the pixel circuit has not yet occurred. Avoiding the occurrence of false compensation.

[0073] In one embodiment, the first potential and the second potential are simultaneously stopped from being provided to the gate of the driving transistor.

[0074] Specifically, the first potential and the second potential are simultaneously stopped from being provided to the gate of the driving transistor, which means that the second potential is continuously provided to the gate of the driving transistor until the light emitting stage ends.

[0075] In the present embodiment, in the light emitting stage, by setting the first potential and the second potential to be simultaneously stopped from being provided to the gate of the driving transistor, which means that the second potential is continuously provided to the gate of the driving transistor until the light emitting stage ends, so that the continuous compensation of the potential of the gate of the driving transistor by the second potential continuously compensates the leakage of the gate of the driving transistor, so that the potential of the gate of the driving transistor is maintained unchanged in the light emitting stage, which ensures that the brightness of the light emitting element is unchanged, and improves the display effect. In one embodiment, the data writing stage includes a data writing sub-stage and a compensation writing sub-stage. For details, please refer to Figure 5 In the data writing sub-stage, the data writing module 10 is configured to write the received data signal to the driving node N1, and the storage module 20 is configured to store the first potential. In the compensation writing sub-stage, the data writing module 10 is configured to write the received compensation signal to the driving node N1, and the storage module 20 is configured to store the second potential.

[0076] In one embodiment, the data writing sub-stage is before the compensation writing sub-stage. Alternatively, the data writing sub-stage is after the compensation writing sub-stage. In this way, the data writing stage is divided into the data writing sub-stage for writing the data signal to the driving node N1 and the compensation writing sub-stage for writing the compensation signal to the driving node N1, so that the time-sharing writing of the data signal and the compensation signal can be realized.

[0077] For example, the above-mentioned embodiments can be combined, and for details, please refer to Figure 7The following explanation uses the data writing sub-stage before the compensation writing sub-stage as an example. The data writing stage T1 includes a data writing sub-stage T11 and a compensation writing sub-stage T12. In data writing sub-stage T11, the voltage source Source provides Vdata-|Vth| to the data writing module 10. The first scan signal S1 is low, and the second scan signal S2 is high. Therefore, when the first potential Vdata-|Vth| is written to the driving node N1, the first transistor M2 is turned on, the second transistor M3 is turned off, and the first storage capacitor C1 stores the first potential Vdata-|Vth|. In compensation writing sub-stage T12, the voltage source Source provides Vcomp-|Vth| to the data writing module 10. Then, the first scan signal S1 is high, and the second scan signal S2 is low. Therefore, when the second potential Vcomp-|Vth| is written to the driving node N1, the first transistor M2 is turned off, the second transistor M3 is turned on, and the second storage capacitor C2 stores the second potential Vcomp-|Vth|.

[0078] Optionally, such as Figure 8 As shown, another driving timing diagram for a pixel circuit is provided. In the data writing stage T1, there are two sub-stages: a data writing sub-stage T11 and a compensation writing sub-stage T12, with the compensation writing sub-stage T12 preceding the data writing sub-stage T11. In the compensation writing sub-stage T12, the voltage source Source provides Vcomp-|Vth| to the data writing module 10. Then, the first scan signal S1 is high and the second scan signal S2 is low. Therefore, when the second potential Vcomp-|Vth| is written to the driving node N1, the first transistor M2 is turned off, the second transistor M3 is turned on, and the second storage capacitor C2 stores the second potential Vcomp-|Vth|. In the data writing sub-stage T11, the voltage source Source provides Vdata-|Vth| to the data writing module 10. The first scan signal S1 is low and the second scan signal S2 is high. Therefore, when the first potential Vdata-|Vth| is written to the driving node N1, the first transistor M2 is turned on, the second transistor M3 is turned off, and the first storage capacitor C1 stores the first potential Vdata-|Vth|.

[0079] In this embodiment, the data writing stage is divided into a data writing sub-stage for writing data signals to driver node N1 and a compensation writing sub-stage for writing compensation signals to driver node N1. This achieves time-division multiplexing of the data and compensation signals. The data writing sub-stage can be set before or after the compensation writing sub-stage, allowing for flexible setting of the order of the data writing and compensation writing sub-stages according to actual needs and conditions.

[0080] In one embodiment, as shown in Figure 9 On the basis of the above embodiment, the first end of the threshold compensation module 30 is connected with the gate of the driving transistor M1, the second end of the first transistor M2 and the second end of the second transistor M3 respectively, the second end of the threshold compensation module 30 is connected with the drain of the driving transistor M1, and the control end of the threshold compensation module 30 is used for receiving the third scan signal S3.

[0081] Exemplarily, as shown in Figure 10 The threshold compensation module 30 can include a third transistor M4, which is turned on under the action of the third scan signal S3 to short the gate and the drain of the driving transistor M1, at this time, the driving transistor M1 becomes a diode. In the data writing sub-stage, the driving transistor M1 is turned on until the gate potential of the driving transistor M1 becomes Vdata-|Vth|-||Vth||, and then the driving transistor M1 is turned off, wherein Vdata-|Vth| is the first potential, and |Vth| is the turn-on threshold potential of the driving transistor M1. In the compensation writing sub-stage, the driving transistor M1 is turned on until the gate potential of the driving transistor M1 becomes Vcomp-|Vth|-||Vth||, and then the driving transistor M1 is turned off, wherein Vcomp-|Vth| is the second potential, and |Vth| is the turn-on threshold potential of the driving transistor M1.

[0082] In the embodiment, by setting the threshold compensation module 30, the gate potential of the driving transistor M1 can be compensated when writing the data signal or the compensation signal to the gate of the driving transistor M1, and the threshold voltage of the driving transistor M1 is eliminated, so that the gate potential of the driving transistor M1 is not affected by the threshold voltage of the driving transistor M1.

[0083] In one embodiment, as shown in Figure 11 On the basis of the above embodiment, the pixel circuit further includes a first initialization module 40. The first end of the first initialization module 40 is used for receiving a first initialization signal V1, the second end of the first initialization module 40 is connected with the gate of the driving transistor M1, the second end of the first transistor M2 and the second end of the second transistor M3 respectively, and the control end of the first initialization module 40 is used for receiving a fourth scan signal S4.

[0084] Specifically, the first initialization module 40 provides the first initialization signal V1 to the gate of the driving transistor M1, the second end of the first transistor M2 and the second end of the second transistor M3 under the action of the fourth scan signal S4, and resets the gate of the driving transistor M1, the first storage capacitor C1 and the second storage capacitor C2.

[0085] Exemplarily, as shown in Figure 12As shown, the first initialization module 40 can include a fourth transistor M5, which is turned on under the action of the fourth scan signal S4, and provides the first initialization signal V1 to the gate of the driving transistor M1, the second end of the first transistor M2, and the second end of the second transistor M3, and resets the gate of the driving transistor M1, the first storage capacitor C1, and the second storage capacitor C2.

[0086] In this embodiment, by providing the first initialization module 40, the first initialization signal V1 can be provided to the gate of the driving transistor M1, the second end of the first transistor M2, and the second end of the second transistor M3, and the gate of the driving transistor M1, the first storage capacitor C1, and the second storage capacitor C2 are reset, which ensures that the potentials on the gate of the driving transistor M1, the first storage capacitor C1, and the second storage capacitor C2 are the same at the initial moment of each frame of picture, and the potentials on the gate of the driving transistor M1, the first storage capacitor C1, and the second storage capacitor C2 are forcibly reset to the potential of the first initialization signal V1, avoiding the influence of the previous frame of picture on the next frame of picture, and further improving the accuracy of the light-emitting element emitting light.

[0087] In one embodiment, as shown in Figure 13 Based on the above embodiment, the pixel circuit further includes a second initialization module 50. The first end of the second initialization module 50 is used to receive a second initialization signal V2, the second end of the second initialization module 50 is connected to the anode of the light-emitting element D1, and the control end of the second initialization module 50 is used to receive a fourth scan signal S4. Wherein, the second initialization module 50 provides the second initialization signal V2 to the anode of the light-emitting element D1 under the action of the fourth scan signal S4, and resets the light-emitting element D1.

[0088] Exemplarily, as shown in Figure 14 The second initialization module 50 can include a fifth transistor M6, which is turned on under the action of the fourth scan signal S4, and provides the second initialization signal V2 to the anode of the light-emitting element D1, and resets the light-emitting element D1.

[0089] In this embodiment, by providing the second initialization module 50, the second initialization signal V2 can be provided to the anode of the light-emitting element D1, and the light-emitting element D1 is reset, and further the potential of the anode of the light-emitting element D1 in each frame of picture is the same, and the light-emitting brightness of the light-emitting element D1 in each frame of picture is consistent.

[0090] In one embodiment, as shown in Figure 15As shown, the data writing module 10 comprises a writing transistor M7. A first end of the writing transistor M7 is configured to receive the data signal and the compensation signal in time in the data writing stage, a second end of the writing transistor M7 is connected with the first end of the driving transistor M1, and a gate of the writing transistor M7 is configured to receive the third scan signal S3.

[0091] Specifically, the first end of the writing transistor M7 is configured to receive the data signal and the compensation signal in time in the data writing stage, and the writing transistor M7 is turned on under the control of the third scan signal S3, so as to write the data signal and the compensation signal to the driving node N1 in time.

[0092] In the embodiment, by setting the writing transistor M7, the writing transistor M7 can be turned on under the control of the third scan signal S3, so as to write the data signal and the compensation signal to the driving node N1 in time through the threshold compensation module 30, and the writing of the data signal and the compensation signal is realized.

[0093] In one embodiment, as shown in FIG. 6, the pixel circuit further comprises a sixth transistor M8 and a seventh transistor M9. The sixth transistor M8 is arranged between the source of the driving transistor M1 and the power supply signal PVDD, and the seventh transistor M9 is arranged between the drain of the driving transistor M1 and the anode of the light emitting element D1. The gates of the sixth transistor M8 and the seventh transistor M9 are configured to receive the light emitting control signal Emit. The sixth transistor M8 and the seventh transistor M9 are turned on under the control of the light emitting control signal Emit, so that the driving transistor M1 can generate the driving current and drive the light emitting element D1 to emit light. Figure 16 In the embodiment, by setting the sixth transistor and the seventh transistor, the sixth transistor and the seventh transistor are turned on under the control of the light emitting control signal, so that the driving transistor can generate the driving current and drive the light emitting element to emit light, thereby the light emitting element can be controlled to emit light or not.

[0094] In one embodiment, as shown in FIG. 7, a driving timing diagram of the pixel circuit in another embodiment is provided, which is applied to the pixel circuit as shown in FIG. 6. The working process of the pixel circuit comprises a reset stage T0, a data writing stage T1, and a light emitting stage T2. When each transistor is a P-type transistor, each stage is described.

[0095] Figure 17 Figure 16

[0096] ​​​In the reset stage T0, the first scan signal S1, the second scan signal S2 and the fourth scan signal S4 are low, the third scan signal S3 and the light emitting control signal Emit are high, the first transistor M2, the second transistor M3, the fourth transistor M5 and the fifth transistor M6 are turned on, the rest of the transistors are turned off, the first initialization signal V1 is provided to the first storage capacitor C1, the second storage capacitor C2 and the gate of the driving transistor M1, and the first storage capacitor C1, the second storage capacitor C2 and the gate of the driving transistor M1 are reset. The second initialization signal V2 is provided to the anode of the light emitting element D1, and the anode of the light emitting element D1 is reset.

[0097] In the data writing stage T1, including a data writing sub-stage T11 and a compensation writing sub-stage T12. In the data writing sub-stage T11, the first scan signal S1 and the third scan signal S3 are low, the second scan signal S2 and the fourth scan signal S4 and the light emitting control signal Emit are high, the first transistor M2 is turned on, the writing transistor M7 is turned on, the third transistor M4 is turned on, and the rest of the transistors are turned off. The voltage source Source provides Vdata-|Vth| for the data writing module 10, so that when the first potential Vdata-|Vth| is written to the driving node N1, the first storage capacitor C1 stores the first potential Vdata-|Vth|. In the compensation writing sub-stage T12, the second scan signal S2 and the third scan signal S3 are low, the first scan signal S1, the fourth scan signal S4 and the light emitting control signal Emit are high, the second transistor M3 is turned on, the writing transistor M7 is turned on, the third transistor M4 is turned on, and the rest of the transistors are turned off. The voltage source Source provides Vcomp-|Vth| for the data writing module 10, and when the second potential Vcomp-|Vth| is written to the driving node N1, the second storage capacitor C2 stores the second potential Vcomp-|Vth|.

[0098] In the light emitting stage T2, the first scan signal S1 and the light emitting control signal Emit are low, the second scan signal S2, the third scan signal S3 and the fourth scan signal S4 are high, the first transistor M2, the sixth transistor M8 and the seventh transistor M9 are turned on, the rest of the transistors are turned off, the first potential Vdata-|Vth| stored in the first storage capacitor C1 is provided to the gate of the driving transistor M1, the driving transistor M1 generates a driving current to drive the light emitting element D1 to emit light. In the preset time period in the light emitting stage T2, the second scan signal S2 is low, the second transistor M3 is turned on, the second potential Vcomp-|Vth| stored in the second storage capacitor C2 is provided to the gate of the driving transistor M1, the change of the potential of the gate of the driving transistor M1 is compensated, so that the potential of the gate of the driving transistor M1 remains unchanged, and then the brightness of the light emitting element D1 remains stable, and the brightness fluctuation of the light emitting element D1 is reduced. Alternatively, the second scan signal S2 can remain low until the end of the light emitting stage.

[0099] In the embodiment, by setting the sixth transistor and the seventh transistor, the sixth transistor and the seventh transistor are turned on under the control of the light emitting control signal, so that the driving transistor can generate a driving current and drive the light emitting element to emit light, thereby controlling whether the light emitting element emits light, the write transistor receives the data signal and the compensation signal in the data writing stage in time, and writes the received data signal and the compensation signal to the driving node respectively, the first storage capacitor can store the first potential of the driving node when the data signal is written, and the second storage capacitor stores the second potential of the driving node when the compensation signal is written. And in the light emitting stage, the first potential stored in the first storage capacitor can be provided to the gate of the driving transistor, and the size of the driving current generated by the driving transistor can be controlled to control the light emitting brightness of the light emitting element; in the preset time period in the light emitting stage, the second potential stored in the second storage capacitor can be provided to the gate of the driving transistor to compensate the amount of change of the gate potential of the driving transistor, and when the display panel displays at a low refresh rate, the number of frames displayed by the display panel per second is small, which increases the length of time that the light emitting element works in the light emitting stage in a frame, and prolongs the leakage time of the gate of the driving transistor. If the leakage time of the gate of the driving transistor is too long, the gate voltage of the driving transistor will be unstable, and the compensation of the amount of change of the gate potential of the driving transistor by the second potential can keep the gate potential of the driving transistor stable, so as to keep the brightness of the light emitting element stable and reduce the brightness fluctuation of the light emitting element, thereby improving the display effect.

[0100] Based on the same inventive concept, the embodiment of the present application also provides a display panel. Figure 18 The structure schematic diagram of the display device 200 provided by the embodiment of the present application is shown in Figure 18As shown, the display panel 200 comprises any one of the pixel circuits 100 provided in the above embodiments. Therefore, the display panel 200 also has the beneficial effects of the pixel circuit 100 in the above embodiments, and the same can be understood with reference to the above explanation of the display panel.

[0101] In one embodiment, as shown in Figure 19 The display panel 200 further comprises a data signal line 201. The data signal line 201 is connected with the first end of the data writing module 10, for transmitting the data signal and the compensation signal in time in the data writing stage.

[0102] In this embodiment, by providing the data signal line, the data signal and the compensation signal can be transmitted in time for the data writing module, so that the data writing module can receive the data signal and the compensation signal in time.

[0103] In one embodiment, as shown in Figure 20 The display panel 200 further comprises a data signal line 201 and a compensation signal line 202. The data signal line 201 is connected with the first end of the data writing module 10, for transmitting the data signal in the data writing sub-stage. The compensation signal line 202 is connected with the first end of the data writing module 10, for transmitting the compensation signal in the compensation writing sub-stage. The display panel 20 comprises a display area and a non-display area, and the data signal line 201 and the compensation signal line 202 are arranged in the non-display area.

[0104] In this embodiment, by providing the data signal line, the data signal can be transmitted for the data writing module in the data writing sub-stage, and by providing the compensation signal line, the compensation signal can be transmitted for the data writing module in the compensation writing sub-stage, so that the data writing module can receive the data signal and the compensation signal in time.

[0105] Based on the same inventive concept, the embodiment of the present application also provides a display device. Figure 21 The structural schematic diagram of the display device 300 provided by the embodiment of the present application is shown in Figure 21 The display device 300 comprises any one of the display panels 200 provided in the above embodiments. For example, as shown in Figure 21 The display device 300 comprises the display panel 200. Therefore, the display device 300 also has the beneficial effects of the display panel 200 in the above embodiments, and the same can be understood with reference to the above explanation of the display panel 200, which will not be repeated hereinafter.

[0106] The display device 300 provided by the embodiment of the present application can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, industrial control equipment, medical display screen, touch interactive terminal, etc., and the embodiment of the present application does not make special limitation thereto.

[0107] The embodiment of the present application further provides a driving method of the pixel circuit, which comprises a data writing stage and a light emitting stage, and can be applied to any pixel circuit provided by the above embodiments. Figure 22 The driving method specifically comprises the following steps:

[0108] In step 2200, in the data writing stage, the data writing module receives the data signal and the compensation signal in time, and writes the received data signal and compensation signal into the driving node respectively, the storage module stores the first potential of the driving node when the data signal is written, and stores the second potential of the driving node when the compensation signal is written. The driving node is the gate node of the driving transistor.

[0109] In step 2210, in the light emitting stage, the storage module provides the stored first potential to the gate of the driving transistor, and in a preset time period of the light emitting stage, the storage module provides the stored second potential to the gate of the driving transistor.

[0110] The driving method of the pixel circuit provided in the embodiment of the present application comprises the following steps: in a data writing stage, a data writing module receives a data signal and a compensation signal in time division manner, and writes the received data signal and compensation signal into a driving node between the data writing module and a gate of a driving transistor, so that the data writing module receives the data signal and the compensation signal in the data writing stage, and writes the data signal and the compensation signal into the driving node in time division manner, facilitating storage of a storage module. The storage module can store a first voltage of the driving node when the data signal is written, and a second voltage of the driving node when the compensation signal is written, and a threshold compensation module short-circuits the gate and the drain of the driving transistor when turned on, so as to eliminate the influence of the threshold voltage of the driving transistor on the gate voltage of the driving transistor. The storage module stores the first voltage corresponding to the data signal and the second voltage corresponding to the compensation signal in time division manner. However, due to the existence of the threshold compensation module, there is a leakage current flowing from the threshold compensation module to the gate of the driving transistor, so that the voltage of the gate of the driving transistor changes. Therefore, the first voltage stored in the storage module is provided to the gate of the driving transistor in a light emitting stage, so as to control the size of the driving current generated by the driving transistor through the first voltage, and further control the light emitting brightness of a light emitting element. The second voltage stored in the storage module is provided to the gate of the driving transistor in a preset time period in the light emitting stage, so as to compensate for the change of the voltage of the gate of the driving transistor through the second voltage, so that the voltage of the gate of the driving transistor remains unchanged, and further so that the brightness of the light emitting element remains stable, the brightness fluctuation of the light emitting element is reduced, and the display effect is improved.

[0111] In one embodiment, the data writing stage comprises a data writing sub-stage and a compensation writing sub-stage.

[0112] As shown in Figure 23 , the driving method further comprises:

[0113] In step 2300, in the data writing sub-stage, the data writing module receives the data signal and writes the received data signal into the driving node, and the storage module stores the first voltage.

[0114] In step 2310, in the compensation writing sub-stage, the data writing module receives the compensation signal and writes the received compensation signal into the driving node, and the storage module stores the second voltage.

[0115] In the embodiment, the data writing stage is divided into the data writing sub-stage for writing the data signal into the driving node and the compensation writing sub-stage for writing the compensation signal into the driving node, so as to realize time-division writing of the data signal and the compensation signal.

[0116] In one embodiment, please continue to refer to Figure 5The storage module 20 comprises a first storage capacitor C1, a first transistor M2, a second storage capacitor C2, and a second transistor M3. The first end of the first storage capacitor C1 is connected to the first power supply signal PVDD1. The second end of the first storage capacitor C1 is connected to the first end of the first transistor M2. The second end of the first transistor M2 is connected to the gate of the driving transistor M1. The control end of the first transistor M2 is connected to the first scanning signal S1. The first end of the second storage capacitor C2 is connected to the second power supply signal PVDD. The second end of the second storage capacitor C2 is connected to the first end of the second transistor M3. The second end of the second transistor M3 is connected to the gate of the driving transistor. The control end of the second transistor M3 is connected to the second scanning signal S2. As shown in FIG. 8, the driving method of the pixel circuit comprises the following steps. Figure 24

[0117] In step 2400, in the data writing sub-stage, the first transistor is controlled to be turned on by the first scanning signal, so that the first storage capacitor stores the first potential.

[0118] In step 2410, in the compensation writing sub-stage, the second transistor is controlled to be turned on by the second scanning signal, so that the second storage capacitor stores the second potential. The first transistor and the second transistor are turned on at different times in the data writing stage.

[0119] In the data writing sub-stage, the first transistor is controlled to be turned on by the first scanning signal, so that the first storage capacitor is kept connected with the driving node in the process of writing the data signal by the data writing module, thereby storing the first potential on the first storage capacitor. In the compensation writing sub-stage, the second transistor is controlled to be turned on by the second scanning signal, so that the second storage capacitor is kept connected with the driving node in the process of writing the compensation signal by the data writing module, thereby storing the second potential on the second storage capacitor.

[0120] In the description of the present specification, the description of the terms “some embodiments”, “other embodiments”, “ideal embodiments”, and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0121] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, and as long as the combinations of the technical features do not exist, they should be considered as the scope of the present specification.

[0122] ​The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific and detailed manner, but should not be construed as limiting the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are all within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A pixel circuit, characterized by comprising: The application relates to an organic light emitting diode (OLED) and a driving method thereof. The OLED comprises: a driving transistor for generating a driving current to drive a light emitting element to emit light; a data writing module, a first end of the data writing module being used for receiving a data signal and a compensation signal in a time-sharing manner in a data writing stage, the data writing module being used for writing the received data signal and compensation signal into a driving node, the driving node being a gate node of the driving transistor; a storage module, connected with the gate of the driving transistor, for storing a first potential of the driving node when the data signal is written and storing a second potential of the driving node when the compensation signal is written; wherein the first potential is a potential provided to the gate of the driving transistor in a light emitting stage; the second potential is a potential provided to the gate of the driving transistor in a preset time period of the light emitting stage; the storage module comprises a first storage unit and a second storage unit, the first storage unit comprises a first storage capacitor and a first transistor, a first end of the first storage capacitor being used for accessing a first power signal; a first end of the first transistor is connected with a second end of the first storage capacitor, a second end of the first transistor is connected with the gate of the driving transistor, and a control end of the first transistor is used for accessing a first scanning signal; when the first transistor is turned on under the action of the first scanning signal, the first storage capacitor is used for storing the first potential of the driving node when the data signal is written; the second storage unit is connected with the gate of the driving transistor, and the second storage unit is used for storing the second potential of the driving node when the compensation signal is written; a threshold compensation module, connected with the gate and a second end of the driving transistor respectively, for short-circuiting the gate and the second end of the driving transistor when the threshold compensation module is turned on. The second storage unit comprises: a second storage capacitor, a first end of the second storage capacitor being used for accessing a second power signal; a second transistor, a first end of the second transistor being connected with a second end of the second storage capacitor, a second end of the second transistor being connected with the gate of the driving transistor, and a control end of the second transistor being used for accessing a second scanning signal; when the second transistor is turned on under the action of the second scanning signal, the second storage capacitor is used for storing the second potential of the driving node when the compensation signal is written; wherein the first transistor and the second transistor are turned on in a time-sharing manner in the data writing stage. The second transistor is also used for being turned on under the action of the second scanning signal in a preset time period of the light emitting stage, so as to provide the stored second potential to the gate of the driving transistor. The second power signal is the same as the first power signal.

2. The pixel circuit of claim 1, wherein, The data writing stage comprises a data writing sub-stage and a compensation writing sub-stage; wherein, in the data writing sub-stage, the data writing module is used for writing the received data signal into the driving node, and the storage module is used for storing the first potential; in the compensation writing sub-stage, the data writing module is used for writing the received compensation signal into the driving node, and the storage module is used for storing the second potential. ​ ​ ​ 3. The pixel circuit of claim 2, wherein, ​ 4. The pixel circuit of claim 2, wherein, ​ 5. The pixel circuit of claim 1, wherein, ​ ​ In the compensation writing sub-stage, the data writing module is configured to write the received compensation signal to the driving node, and the storage module is configured to store the second potential.

6. The pixel circuit of claim 5, wherein, The data writing sub-stage is before the compensation writing sub-stage, or the data writing sub-stage is after the compensation writing sub-stage.

7. The pixel circuit of claim 2, wherein, The first end of the threshold compensation module is connected with the gate of the driving transistor, the second end of the first transistor, and the second end of the second transistor, respectively; the second end of the threshold compensation module is connected with the second end of the driving transistor; and the control end of the threshold compensation module is configured to receive a third scan signal.

8. The pixel circuit of claim 2, wherein, The threshold compensation module comprises a third transistor, the first end of the third transistor is connected with the gate of the driving transistor, the second end of the first transistor, and the second end of the second transistor, respectively; the second end of the third transistor is connected with the second end of the driving transistor; and the control end of the third transistor is configured to receive a third scan signal; and the third transistor is configured to be turned on under the action of the third scan signal to short the gate and the drain of the driving transistor.

9. The pixel circuit of claim 2, wherein, The pixel circuit further comprises: The first initialization module is configured to receive a first initialization signal at the first end thereof, and is connected with the gate of the driving transistor, the second end of the first transistor, and the second end of the second transistor at the second end thereof, respectively; and the control end of the first initialization module is configured to receive a fourth scan signal.

10. The pixel circuit of claim 1, wherein, The pixel circuit further comprises a second initialization module, the first end of the second initialization module is configured to receive a second initialization signal, the second end of the second initialization module is connected with the anode of the light emitting element, and the control end of the second initialization module is configured to receive a fourth scan signal; wherein the second initialization module is configured to provide the second initialization signal to the anode of the light emitting element under the action of the fourth scan signal to reset the light emitting element.

11. The pixel circuit of claim 1, wherein, The initial time of providing the second potential to the gate of the driving transistor is later than the initial time of providing the first potential to the gate of the driving transistor.

12. The pixel circuit of claim 11, wherein, The first potential and the second potential are simultaneously stopped from being provided to the gate of the driving transistor.

13. The pixel circuit of claim 1, wherein, The data writing module comprises: The first end of the writing transistor is configured to receive the data signal and the compensation signal in time division manner in the data writing stage; the second end of the writing transistor is connected with the first end of the driving transistor; and the gate of the writing transistor is configured to receive a third scan signal.

14. A display panel, characterized by The display panel further comprises:

15. The display panel of claim 14, wherein, The data signal line is connected with the first end of the data writing module, and is configured to transmit the data signal and the compensation signal in time division manner in the data writing stage. The data writing stage comprises a data writing sub-stage and a compensation writing sub-stage; wherein the display panel further comprises:

16. The display panel of claim 14, wherein, The data signal line is connected with the first end of the data writing module, and is configured to transmit the data signal in the data writing sub-stage. The data signal line is connected with the first end of the data writing module, and is configured to transmit the data signal in the data writing sub-stage. A compensation signal line is connected with a first end of the data writing module, and is used for transmitting the compensation signal in the compensation writing sub-stage.

17. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 14-16.

18. A driving method of a pixel circuit, characterized by, The driving method comprises a data writing stage and a light emitting stage; wherein, In the data writing stage, the data writing module receives the data signal and the compensation signal in time, and writes the received data signal and compensation signal into the driving node respectively, the storage module stores a first potential of the driving node when the data signal is written, and stores a second potential of the driving node when the compensation signal is written; wherein, the driving node is a gate node of a driving transistor; In the light emitting stage, the storage module provides the stored first potential to the gate of the driving transistor, and provides the stored second potential to the gate of the driving transistor in a preset time period of the light emitting stage; The storage module comprises a first storage unit and a second storage unit, the first storage unit comprises a first storage capacitor and a first transistor, a first end of the first storage capacitor is used for accessing a first power signal; a first end of the first transistor is connected with a second end of the first storage capacitor, a second end of the first transistor is connected with the gate of the driving transistor, and a control end of the first transistor is used for accessing a first scan signal; when the first transistor is turned on under the action of the first scan signal, the first storage capacitor is used for storing the first potential of the driving node when the data signal is written; the second storage unit is connected with the gate of the driving transistor, and the second storage unit is used for storing the second potential of the driving node when the compensation signal is written.

19. The driving method of the pixel circuit according to claim 18, wherein The data writing stage comprises a data writing sub-stage and a compensation writing sub-stage; In the data writing sub-stage, the data writing module receives the data signal, and writes the received data signal into the driving node, and the storage module stores the first potential; In the compensation writing sub-stage, the data writing module receives the compensation signal, and writes the received compensation signal into the driving node, and the storage module stores the second potential.

20. The driving method of the pixel circuit according to claim 19, wherein The second storage unit comprises a second storage capacitor and a second transistor, wherein: a first end of the second storage capacitor is used for accessing a second power signal, a second end of the second storage capacitor is connected with a first end of the second transistor, a second end of the second transistor is connected with the gate of the driving transistor, and a control end of the second transistor is used for accessing a second scan signal; In the data writing sub-stage, the first transistor is turned on by the first scan signal, so that the first storage capacitor stores the first potential; In the compensation writing sub-stage, the second transistor is turned on by the second scan signal, so that the second storage capacitor stores the second potential, wherein, the first transistor and the second transistor are turned on in time in the data writing stage.

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