Organic light-emitting diode display device including compensation unit and driving method thereof

Abstract

This disclosure relates to an organic light-emitting diode (OLED) display device including a compensation unit and a driving method thereof. An OLED display device includes: a driving transistor; a first transistor connected to the driving transistor; a second transistor connected between a data voltage and the driving transistor; a third transistor connected between a high-level voltage and the driving transistor; a fourth transistor connected to the driving transistor; a fifth transistor connected between an initial voltage and the driving transistor; a sixth transistor connected to the initial voltage; a seventh transistor connected to the high-level voltage; an eighth transistor connected to a reference voltage; a storage capacitor connected between the driving transistor and the eighth transistor; and a light-emitting diode connected between a low-level voltage and the fourth transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0188005, filed on December 27, 2021, in the Republic of Korea, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to organic light-emitting diode (OLED) display devices, and more specifically, to OLED display devices including compensation units and methods for driving OLED display devices, wherein sufficient sensing time is obtained by independently driving two transistors connected to the gate electrode and source electrode of a driving transistor. Background Technology

[0004] Recently, with the advent of the information society and the increasing focus on information displays for processing and displaying large amounts of information, as well as the growing demand for portable information media, the display field has developed rapidly. Consequently, various thin and light flat panel display devices have been developed and have become prominent.

[0005] Among various flat panel display devices, organic light-emitting diode (OLED) display devices are light-emitting devices and do not include the backlight unit used in non-light-emitting devices such as liquid crystal displays (LCDs). Therefore, OLED display devices have advantages in terms of viewing angle, contrast ratio, and power consumption, making them suitable for a wide range of applications.

[0006] In OLED displays, each subpixel includes a compensation unit of various structures to compensate for the threshold voltage of the driving transistor. A 10T1C structure compensation unit has been researched and developed, in which each subpixel includes eight transistors and one capacitor, and pixels with red, green, and blue subpixels typically include two transistors.

[0007] In OLED display devices with compensation units featuring a 10T1C structure, image quality degradation is minimized by compensating for the threshold voltage. However, since the two transistors connected to the driving transistor and the one transistor connected to the storage capacitor switch according to a gate voltage, data voltage writing and threshold voltage sensing are performed within a single horizontal time period. Therefore, the sensing time for high-frequency driving is reduced. Summary of the Invention

[0008] Therefore, this disclosure relates to an organic light-emitting diode (OLED) display device that substantially eliminates one or more problems caused by limitations and disadvantages of related technologies, and a method for driving the OLED display device.

[0009] The purpose of this disclosure is to provide an organic light-emitting diode display device including a compensation unit, wherein a sensing time equal to or greater than two horizontal time periods is obtained, two transistors connected to two electrodes of a storage capacitor are driven with an additional gate voltage, thereby minimizing the degradation of image display quality and performing high-speed driving with high resolution and high frequency, and providing a method for driving the organic light-emitting diode display device.

[0010] Another object of this disclosure is to provide an organic light-emitting diode display device including a compensation unit, wherein leakage current through the gate electrode of the driving transistor is reduced by reducing the number of transistors connected to the gate electrode of the driving transistor, and flickering in low-speed driving is minimized, and a method for driving the organic light-emitting diode display device is provided.

[0011] Further features and advantages of this disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained through the written description and the structures particularly pointed out in the claims herein and the accompanying drawings.

[0012] As specifically embodied and broadly described herein, in order to achieve these and other advantages and for the purposes of this disclosure, an organic light-emitting diode (OLED) display device includes: a driving transistor; a first transistor switched according to a gate 3 voltage and connected to the driving transistor; a second transistor switched according to a gate 2 voltage and connected between a data voltage and the driving transistor; a third transistor switched according to an emitt voltage and connected between a high-level voltage and the driving transistor; a fourth transistor switched according to an emitt voltage and connected to the driving transistor; a fifth transistor switched according to a gate 1 voltage and connected between an initial voltage and the driving transistor; a sixth transistor switched according to a gate 2 voltage and connected to the initial voltage; a seventh transistor switched according to an emitt voltage and connected to a high-level voltage; an eighth transistor switched according to a gate 3 voltage and connected to a reference voltage; a storage capacitor connected between the driving transistor and the eighth transistor; and a light-emitting diode connected between a low-level voltage and the fourth transistor.

[0013] In another aspect, a method for driving an organic light-emitting diode (OLED) display device including a first to an eighth transistor, a storage capacitor, and a light-emitting diode includes: during a first time period, turning on the first, fifth, and eighth transistors and turning off the second, third, fourth, sixth, and seventh transistors, and providing an initial voltage and a reference voltage to a first and second electrode of the storage capacitor, respectively; during a second time period, turning on the first, second, sixth, and eighth transistors and turning off the third, fourth, fifth, and seventh transistors, and providing a data voltage to the first electrode of the storage capacitor; during a third time period, turning on the first and eighth transistors and turning off the second, third, fourth, fifth, sixth, and seventh transistors; and during a fourth time period, turning off the first, second, fifth, sixth, and eighth transistors, turning on the third, fourth, and seventh transistors, and providing a high-level voltage to the second electrode of the storage capacitor and a driving transistor.

[0014] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0015] The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. In the drawings:

[0016] Figure 1 This is a diagram illustrating an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0017] Figure 2 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0018] Figure 3 This is a plan view showing the pixels of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0019] Figure 4 This is a diagram illustrating multiple signals of a display frame of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0020] Figures 5A to 5D This is a diagram showing the operation of sub-pixels during the first to fourth time periods of a display frame of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0021] Figure 6 This is a diagram illustrating multiple signals of a reset frame of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0022] Figure 7 This is a diagram illustrating the operation of sub-pixels during the fifth time period of a reset frame in an organic light-emitting diode display device according to a first embodiment of this disclosure; and

[0023] Figure 8 This is a plan view showing the pixels of an organic light-emitting diode display device according to a second embodiment of the present disclosure. Detailed Implementation

[0024] The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0025] The shapes, dimensions, ratios, angles, and numbers disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples. Therefore, this disclosure is not limited to the details shown. Throughout the document, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations may be omitted when it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure. Where the terms “comprising,” “having,” and “including” are used as described in this specification, additional components may be added unless more restrictive terms, such as “only,” are used. Unless otherwise stated, singular terms may include plural forms.

[0026] When interpreting a component, the component is interpreted as including a range of errors or tolerances, even if there is no explicit description of such a range of errors or tolerances.

[0027] When describing positional relationships, if the positional relationship between two components is described as "on," "above," "below," or "next to," one or more other components may be positioned between the two components unless more restrictive terms such as "only" or "directly" are used.

[0028] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from other elements. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may be interoperable with and technically driven by each other in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0030] In the following description, an organic light-emitting diode display device including a compensation unit according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the description, similar reference numerals indicate similar elements. Detailed descriptions of known functions or configurations relevant to this document will be omitted or simplified where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept.

[0031] Figure 1 This is a diagram illustrating an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0032] exist Figure 1 In the first embodiment of the present disclosure, the organic light-emitting diode (OLED) display device 110 includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, and a display panel 150.

[0033] The timing control unit 120 uses image signals and multiple timing signals to generate image data, data control signals, and gate control signals. These multiple timing signals include a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal transmitted from an external system such as a graphics card or television system. The image data and data control signals are transmitted to the data drive unit 130, and the gate control signals are transmitted to the gate drive unit 140.

[0034] The data drive unit 130 uses the data control signal and image data transmitted from the timing control unit 120 to generate a data voltage (data signal) and transmits the data voltage to the data line DL of the display panel 150.

[0035] The gate driving unit 140 uses the gate control signal transmitted from the timing control unit 120 to generate a gate voltage (gate signal) and an emitter voltage (emit signal), and applies the gate voltage and emitter voltage to the gate line GL of the display panel 150.

[0036] The gate driving unit 140 may have an in-board gate (GIP) type to be formed in the non-display area NDA of the substrate of the display panel 150 having gate lines GL, data lines DL and pixels P.

[0037] Display panel 150 includes a display area DA in its central portion and a non-display area NDA surrounding the display area DA. Display panel 150 displays images using gate voltage, emitter voltage, and data voltage. To display images, display panel 150 includes multiple pixels P, multiple gate lines GL, and multiple data lines DL in the display area DA.

[0038] For example, each of the multiple pixels P may include a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, and gate line GL and data line DL intersect each other to define the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb. Each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb may be connected to gate line GL and data line DL.

[0039] The structure of each subpixel of the display panel 150 of the OLED display device 110 will be described with reference to the accompanying drawings.

[0040] Figure 2 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure, and Figure 3 This is a plan view showing the pixels of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0041] exist Figure 2 and Figure 3 In the first embodiment of the OLED display device 110 according to the present disclosure, each pixel P of the display panel 150 includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, as well as a common block CB. Each sub-pixel SP includes a driving transistor Td, a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, and a light-emitting diode De, and the common block CB includes a seventh transistor T7 and an eighth transistor T8.

[0042] A driving transistor Td, first transistors T1 to sixth transistors T6, storage capacitor Cst and light-emitting diode De are disposed in each sub-pixel SP, and a seventh transistor T7 and an eighth transistor T8 are disposed in a pixel P composed of red sub-pixel SPr, green sub-pixel SPg and blue sub-pixel SPb.

[0043] For example, the driving transistor Td and the second transistors T2 to the seventh transistor T7 can be positive type polycrystalline silicon thin film transistors, while the first transistor T1 and the eighth transistor T8 can be negative type oxide semiconductor thin film transistors.

[0044] exist Figure 2 In this circuit, the driving transistor Td switches (turns on and off) according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the driving transistor Td is connected to the first electrode of the storage capacitor Cst and the drain electrode of the first transistor T1. The source electrode of the driving transistor Td is connected to the drain electrode of the second transistor T2 and the source electrode of the third transistor T3. Furthermore, the drain electrode of the driving transistor Td is connected to the source electrode of the first transistor T1, the source electrode of the fourth transistor T4, and the drain electrode of the fifth transistor T5.

[0045] The first transistor T1 is switched (on and off) according to the nth gate3 voltage Scan3(n). The gate electrode of the first transistor T1 is connected to the nth gate3 voltage Scan3(n), the source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor Td, the source electrode of the fourth transistor T4 and the drain electrode of the fifth transistor T5, and the drain electrode of the first transistor T1 is connected to the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst.

[0046] The second transistor T2 of the switching transistor is switched (on and off) according to the nth gate2 voltage Scan2(n). The gate electrode of the second transistor T2 is connected to the nth gate2 voltage Scan2(n), the source electrode of the second transistor T2 is connected to the data voltage Vdata, and the drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor Td and the source electrode of the third transistor T3.

[0047] The third transistor T3 is switched (on and off) according to the nth emitter voltage Em(n). The gate electrode of the third transistor T3 is connected to the nth emitter voltage Em(n), the source electrode of the third transistor T3 is connected to the drain electrode of the second transistor T2 and the source electrode of the driving transistor Td, and the drain electrode of the third transistor T3 is connected to the high-level voltage Vdd and the source electrode of the seventh transistor T7.

[0048] The fourth transistor T4, which is the emitter transistor, is switched (on and off) according to the nth emitter voltage Em(n). The gate electrode of the fourth transistor T4 is connected to the nth emitter voltage Em(n), the source electrode of the fourth transistor T4 is connected to the drain electrode of the driver transistor Td, the source electrode of the first transistor T1, and the drain electrode of the fifth transistor T5, and the drain electrode of the fourth transistor T4 is connected to the drain electrode of the sixth transistor T6 and the anode of the light-emitting diode De.

[0049] The fifth transistor T5 is switched (on and off) according to the nth gate1 voltage Scan1(n). The gate electrode of the fifth transistor T5 is connected to the nth gate1 voltage Scan1(n), the source electrode of the fifth transistor T5 is connected to the initial voltage Vini and the source electrode of the sixth transistor T6, and the drain electrode of the fifth transistor T5 is connected to the drain electrode of the driving transistor Td, the source electrode of the first transistor T1, and the source electrode of the fourth transistor T4.

[0050] The sixth transistor T6 is switched (on and off) according to the (n+1)th gate2 voltage Scan2(n+1). The gate electrode of the sixth transistor T6 is connected to the (n+1)th gate2 voltage Scan2(n+1), the source electrode of the sixth transistor T6 is connected to the initial voltage Vini and the source electrode of the fifth transistor T5, and the drain electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode De and the drain electrode of the fourth transistor T4.

[0051] The seventh transistor T7 is switched (on and off) according to the nth emitter voltage Em(n). The gate electrode of the seventh transistor T7 is connected to the nth emitter voltage Em(n), the source electrode of the seventh transistor T7 is connected to the high-level voltage Vdd and the drain electrode of the third transistor T3, and the drain electrode of the seventh transistor T7 is connected to the source electrode of the eighth transistor T8 and the second electrode of the storage capacitor Cst.

[0052] The eighth transistor T8 is switched (on and off) according to the nth gate3 voltage Scan3(n). The gate electrode of the eighth transistor T8 is connected to the nth gate3 voltage Scan3(n), the source electrode of the eighth transistor T8 is connected to the drain electrode of the seventh transistor T7 and the second electrode of the storage capacitor Cst, and the drain electrode of the eighth transistor T8 is connected to the reference voltage Vref.

[0053] The storage capacitor Cst stores the data voltage Vdata, the threshold voltage Vth, and the high-level voltage Vdd. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor Td and the drain electrode of the first transistor T1, and the second electrode of the storage capacitor Cst is connected to the drain electrode of the seventh transistor T7 and the source electrode of the eighth transistor T8.

[0054] The light-emitting diode De is connected between the fourth transistor T4 and the sixth transistor T6 and the low-level voltage Vss, and emits light with a brightness proportional to the current driving the transistor Td. The anode of the light-emitting diode De is connected to the drain electrode of the fourth transistor T4 and the drain electrode of the sixth transistor T6, and the cathode of the light-emitting diode De is connected to the low-level voltage Vss.

[0055] exist Figure 3 In the first embodiment of the present disclosure, the OLED display device 110 includes multiple gate1 lines G1L for transmitting gate1 voltage Scan1, multiple gate2 lines G2L for transmitting gate2 voltage Scan2, multiple gate3 lines G3L for transmitting gate3 voltage Scan3, multiple initial lines IL for transmitting initial voltage Vini, multiple emission lines EL for transmitting emission voltage Em, multiple data lines DL for transmitting data voltage Vdata, multiple power lines PL for transmitting high-level voltage Vdd, and multiple reference lines RL for transmitting reference voltage Vref.

[0056] Multiple gate1 lines G1L, multiple gate2 lines G2L, multiple gate3 lines G3L, multiple initial lines IL, and multiple emission lines EL are arranged parallel to the horizontal direction along the long side of the OLED display device 110, and multiple data lines DL and multiple reference lines RL are arranged parallel to the vertical direction along the short side of the OLED display device 110. Multiple power lines PL are arranged parallel to both the horizontal and vertical directions.

[0057] Vertical data lines DL and PL are set in each sub-pixel SP, and reference lines RL are set in a common block CB. Horizontal gate2 lines G2L and PL intersect with the vertical data lines DL and PL to define each sub-pixel SP.

[0058] For example, in each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb, the horizontal gate2 line G2L, initial line IL, gate1 line G1L, gate3 line G3L, emission line EL, and power line PL can be arranged sequentially along the vertical direction, and the vertical data line DL and power line PL can be arranged sequentially along the horizontal direction.

[0059] Each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb includes a driving transistor Td, first transistors T1 through sixth transistors T6, a storage capacitor Cst, and a light-emitting diode De, and the common block CB includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 may overlap with the reference line RL to be disposed within the reference line RL.

[0060] Figure 3 The sub-pixels of the nth horizontal pixel line are shown. Figure 3 The sixth transistor T6 can belong to the sub-pixel of the (n-1)th horizontal pixel line, and the sixth transistor T6 of the nth horizontal pixel line can be set in the sub-pixel of the (n+1)th horizontal pixel line.

[0061] During a display frame of an image displayed on the OLED display device 110, the second transistor T2, connected between the data voltage Vdata and the driving transistor Td, switches according to the gate2 voltage Scan2, and the first transistor T1 and the eighth transistor T8, respectively connected to the first and second electrodes of the storage capacitor Cst, switch according to the gate3 voltage Scan3. Therefore, a sensing time equal to or longer than two horizontal time periods (2H) of threshold voltage is obtained.

[0062] During the reset frame of resetting the anode of the light-emitting diode De in the OLED display device 110, an initial voltage Vini is provided to the anode of the light-emitting diode De to initialize the anode of the light-emitting diode De.

[0063] The driving method for the OLED display device will be described with reference to the accompanying drawings.

[0064] Figure 4 This is a diagram illustrating multiple signals of a display frame of an organic light-emitting diode display device according to a first embodiment of the present disclosure, and Figures 5A to 5D This is a diagram illustrating the operation of sub-pixels during the first to fourth time periods of a display frame of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0065] exist Figure 4 In the image display frame DF, the first time period TP1 is used to initialize the gate electrode of the driving transistor Td, the second time period TP2 is used to initialize the anode of the light-emitting diode De and the data voltage to the gate electrode of the driving transistor Td, the third time period TP3 is used to sense the threshold voltage Vth of the driving transistor Td, and the fourth time period TP4 is used to emit light from the light-emitting diode De.

[0066] For example, the period during which the nth transmit voltage Em(n) has a high logic voltage Vh (excluding the fourth time period TP4, the display frame DF) can be approximately 64 horizontal time periods (64H).

[0067] exist Figure 4 and Figure 5ADuring the first time period TP1, the nth emitter voltage Em(n), the nth gate3 voltage Scan3(n), the nth gate2 voltage Scan2(n), and the (n+1)th gate2 voltage Scan2(n+1) become high logic voltages Vh, while the nth gate1 voltage Scan1(n) becomes low logic voltage Vl. The first transistor T1, the fifth transistor T5, and the eighth transistor T8 are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off. Therefore, the first and second electrodes of the storage capacitor Cst become the initial voltage Vini and the reference voltage Vref, respectively, thus initializing the gate electrode of the driving transistor Td.

[0068] For example, the first time period TP1 can be divided into two separate parts to increase the initialization period. The first time period can be approximately eight horizontal periods (8H), and the first voltage V1 of the initial voltage Vini can be approximately -5V.

[0069] exist Figure 4 and Figure 5B During the second time period TP2, the nth emitter voltage Em(n), the nth gate3 voltage Scan3(n), and the nth gate1 voltage Scan1(n) become high logic voltages Vh, while the nth gate2 voltage Scan2(n) and the (n+1)th gate2 voltage Scan2(n+1) become low logic voltages Vl. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned on, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. Therefore, the first electrode of the storage capacitor Cst becomes the data voltage Vdata, causing the data voltage Vdata to be stored in the storage capacitor Cst.

[0070] For example, the second time period TP2 can be approximately a horizontal time period (1H).

[0071] exist Figure 4 and Figure 5CDuring the third time period TP3, the nth emitter voltage Em(n), the nth gate3 voltage Scan3(n), the nth gate2 voltage Scan2(n), the (n+1)th gate2 voltage Scan2(n+1), and the nth gate1 voltage Scan1(n) become high logic voltages Vh. The first transistor T1 and the eighth transistor T8 are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. Therefore, the first electrode of the storage capacitor Cst becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), such that (Vdata+Vth) is stored in the storage capacitor Cst.

[0072] For example, the third time period TP3 can be approximately seven horizontal time periods (7H).

[0073] exist Figure 4 and Figure 5D During the fourth time period TP4, the nth emitter voltage Em(n) and the nth gate3 voltage Scan3(n) become low logic voltage Vl, while the nth gate2 voltage Scan2(n), the (n+1)th gate2 voltage Scan2(n+1), and the nth gate1 voltage Scan1(n) become high logic voltage Vh. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off, while the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on. Therefore, the second electrode of the storage capacitor Cst becomes a high-level voltage Vdd, and the first electrode of the storage capacitor Cst becomes a value obtained by adding the difference between the high-level voltage Vdd and the reference voltage Vref (Vdd-Vref) to the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth) (Vdata+Vth), such that a current flows in the driving transistor Td proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage (Vgs=(Vg-Vs)=(Vdd-Vref+Vdata+Vth)-Vdd=Vdata-Vef+Vth) (Vdata-Vref+Vth), and the light-emitting diode De emits light with a brightness corresponding to the current flowing through the driving transistor Td.

[0074] Figure 6 This is a diagram illustrating multiple signals of a reset frame in an organic light-emitting diode display device according to a first embodiment of the present disclosure, and Figure 7 This is a diagram illustrating the operation of sub-pixels during the fifth time period of a reset frame in an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0075] exist Figure 6 In the process, the reset frame RF used to reset the light-emitting diode De includes the fifth time period TP5 of the reset period of the anode of the light-emitting diode De.

[0076] For example, the nth emitter voltage Em(n) has a high logic voltage Vh for a period of approximately 64 horizontal periods (64H), and the fifth period TP5 can be approximately 1 horizontal period (1H).

[0077] exist Figure 6 and Figure 7 During the fifth time period TP5, the nth emitter voltage Em(n) and the nth gate1 voltage Scan1(n) become high logic voltages Vh, while the nth gate3 voltage Scan3(n), the nth gate2 voltage Scan2(n), and the (n+1)th gate2 voltage Scan2(n+1) become low logic voltages Vl. The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off, while the second transistor T2 and the sixth transistor T6 are turned on. Therefore, the anode of the light-emitting diode De is initialized to the initial voltage Vini. The second voltage V2 of the initial voltage Vini can be greater than the first voltage V1 of the initial voltage Vini of the display frame DF.

[0078] For example, the second voltage V2 of the initial voltage Vini can be approximately 0V.

[0079] The data voltage Vdata can be changed to a constant third voltage V3, so that the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td remain at the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth).

[0080] For example, the third voltage V3 of the data voltage Vdata can be the maximum voltage that the data driving unit 130 can provide based on the gate-source voltage Vgs of the driving transistor Td.

[0081] Therefore, in the OLED display device according to the first embodiment of this disclosure, the light-emitting diode De emits light to display an image based on the operation of the driving transistor Td, the first transistor T1 to the eighth transistor T8, and the storage capacitor Cst. Variations in the threshold voltage Vth, high-level voltage Vdd, and degradation of the light-emitting diode De over time are compensated using sub-pixels SP, and the brightness can be adjusted by driving the light-emitting diode De according to the duty cycle corresponding to the emission time.

[0082] Furthermore, during the display frame DF of the image displayed on the OLED display device 110, the second transistor T2, connected between the data voltage Vdata and the driving transistor Td, switches according to the gate2 voltage Scan2, and the first transistor T1 and the eighth transistor T8, respectively connected to the first and second electrodes of the storage capacitor Cst, switch according to the gate3 voltage Scan3. Therefore, since the sensing time of the threshold voltage is equal to or longer than two horizontal time periods (2H), the degradation of the image display quality is minimized, and high-resolution and high-frequency high-speed driving is achieved.

[0083] Furthermore, during the reset frame RF during which the anode of LED De is reset, the anode of LED De is initialized by providing an initial voltage Vini to the anode of LED De.

[0084] In addition, since only the first transistor T1 is connected to the gate electrode of the driving transistor Td, the leakage current through the gate electrode of the driving transistor Td is reduced, and the flickering of low-speed driving is minimized.

[0085] Furthermore, since each subpixel includes nine transistors such as the driving transistor Td and the first transistor T1 through the eighth transistor T8, the number of transistors in each subpixel is reduced and the design freedom is increased.

[0086] In another embodiment, the first transistor T1 to the eighth transistor T8 can be formed of polysilicon.

[0087] Figure 8 This is a plan view showing the pixels of an organic light-emitting diode display device according to a second embodiment of the present disclosure. Descriptions of portions identical to those in the first embodiment will be omitted.

[0088] exist Figure 8 In the second embodiment of the organic light-emitting diode (OLED) display device according to this disclosure, the display panel includes a plurality of pixels, and each pixel includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, as well as a common block CB. Each sub-pixel SPr, SPg, and SPb includes a driving transistor Td, a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, and a light-emitting diode De, and the common block CB includes a seventh transistor T7 and an eighth transistor T8.

[0089] In addition, the display panel includes: multiple gate1 lines G1L for transmitting gate1 voltage Scan1, multiple gate2 lines G2L for transmitting gate2 voltage Scan2, multiple gate3 lines G3L for transmitting gate3 voltage Scan3, multiple initial lines IL for transmitting initial voltage Vini, multiple transmit lines EL for transmitting transmit voltage Em, multiple data lines DL for transmitting data voltage Vdata, multiple power lines PL for transmitting high-level voltage Vdd, and multiple reference lines RL for transmitting reference voltage Vref.

[0090] Multiple gate1 lines G1L, multiple gate2 lines G2L, multiple gate3 lines G3L, multiple initial lines IL, and multiple emission lines EL are arranged parallel to the horizontal direction along the long side of the OLED display device, while multiple data lines DL and multiple reference lines RL are arranged parallel to the vertical direction along the short side of the OLED display device. Multiple power lines PL are arranged parallel to both the horizontal and vertical directions.

[0091] Vertical data lines DL and PL are set in each sub-pixel SP, and reference lines RL are set in a common block CB. Horizontal gate2 lines G2L and PL intersect with the vertical data lines DL and PL to define each of the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb.

[0092] For example, in each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb, the horizontal gate2 line G2L, initial line IL, gate1 line G1L, gate3 line G3L, emission line EL, and power line PL can be arranged sequentially along the vertical direction, and the vertical data line DL and power line PL can be arranged sequentially along the horizontal direction.

[0093] Each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb includes a driving transistor Td, first transistors T1 through T6, a storage capacitor Cst, and a light-emitting diode De, and the common block CB includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 may overlap with the reference line RL to be disposed within the reference line RL. The driving transistor Td and the first transistors T1 through T8 may be positive-type polycrystalline silicon thin-film transistors.

[0094] Despite Figure 8In the second embodiment, the first transistor T1 of each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb is exemplary of having a dual-gate type and is configured to overlap with the gate3 line G3L together with the eighth transistor T8 of the common block CB. However, in another embodiment as in the first embodiment, the first transistor T1 may have a single-gate type and may be configured to protrude from the gate3 line G3L.

[0095] Figure 8 The sub-pixels of the nth horizontal pixel line are shown. Figure 8 The sixth transistor T6 can belong to the sub-pixel of the (n-1)th horizontal pixel line, and the sixth transistor T6 of the nth horizontal pixel line can be set in the sub-pixel of the (n+1)th horizontal pixel line.

[0096] Except that the first transistor T1 and the eighth transistor T8 are positive-type polysilicon thin-film transistors, the circuit structure of each sub-pixel SP in the second embodiment is the same as that in the first embodiment. The gate3 voltage Scan3 supplied to the gate electrodes of the first transistor T1 and the eighth transistor T8 can have the same characteristics as in the first embodiment. Figure 4 and Figure 6 The gate3 voltage Scan3 has the opposite polarity.

[0097] During the display frame of an image displayed in the OLED display device, the second transistor T2, connected between the data voltage Vdata and the driving transistor Td, switches according to the gate2 voltage Scan2, and the first transistor T1 and the eighth transistor T8, respectively connected to the first and second electrodes of the storage capacitor Cst, switch according to the gate3 voltage Scan3. Therefore, a sensing time equal to or longer than two horizontal time periods (2H) of the threshold voltage is obtained.

[0098] During the reset frame of resetting the anode of the light-emitting diode De in the OLED display device, an initial voltage Vini is provided to the anode of the light-emitting diode De to initialize the anode of the light-emitting diode De.

[0099] Therefore, in the OLED display device according to this disclosure, since the two transistors connected to the first and second electrodes of the storage capacitor are driven by an additional gate voltage, the degradation of the image display quality is minimized and high-speed driving with high resolution and high frequency is obtained because the threshold voltage sensing time is equal to or longer than two horizontal time periods (2H).

[0100] In addition, the reduced number of transistors connected to the gate electrode of the driving transistor reduces leakage current through the gate electrode of the driving transistor and minimizes flickering during low-speed driving.

[0101] Furthermore, since the threshold voltage and high-level voltage are charged to the gate electrode of the driving transistor during the light-emitting period, the high-level voltage and threshold voltage are compensated.

[0102] In addition, the design freedom of each sub-pixel is increased because the number of transistors in the sub-pixels and pixels is reduced.

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover modifications and variations that fall within the scope of the appended claims.

Claims

1. An organic light-emitting diode (OLED) display device, comprising: Drive transistors; The first transistor is switched according to the gate3 voltage and is connected between the gate electrode and the drain electrode of the driving transistor. The second transistor is switched according to the gate2 voltage and is connected between the data voltage and the source electrode of the driving transistor; A third transistor, which is switched according to the emitter voltage and connected between the high-level voltage and the source electrode of the driving transistor; A fourth transistor, which switches according to the emission voltage and is connected between the drain electrode of the driving transistor and the light-emitting diode; The fifth transistor, which switches according to the gate1 voltage and is connected between the initial voltage and the drain electrode of the driving transistor; The sixth transistor, which switches according to the gate2 voltage and is connected between the initial voltage and the light-emitting diode; A seventh transistor, which is switched according to the emitter voltage and connected between the high-level voltage and the storage capacitor; The eighth transistor, which is switched according to the gate3 voltage and connected between the reference voltage and the storage capacitor; The storage capacitor is connected between the driving transistor and the eighth transistor; as well as The light-emitting diode is connected between the low-level voltage and the fourth transistor.

2. The display device according to claim 1, wherein, The driving transistor and the second to seventh transistors are positive type polycrystalline silicon thin film transistors, and the first transistor and the eighth transistor are either negative type oxide semiconductor thin film transistors or positive type polycrystalline silicon thin film transistors.

3. The display device according to claim 1, wherein, The seventh transistor and the eighth transistor overlap with the reference line that transmits the reference voltage and are disposed within the reference line.

4. The display device according to claim 1, wherein, The first transistor and the eighth transistor are positive type polycrystalline silicon thin film transistors, and the first transistor and the eighth transistor are configured to overlap with the gate3 line that transmits the gate3 voltage.

5. The display device according to claim 1, wherein, The display frames used to display the image include a first time period to a fourth time period, and in: During the first time period, the transmit voltage, the gate3 voltage, and the gate2 voltage have high logic voltages, while the gate1 voltage has a low logic voltage. During the second time period, the transmit voltage, the gate3 voltage, and the gate1 voltage have high logic voltages, while the gate2 voltage has a low logic voltage. During the third time period, the transmit voltage, the gate3 voltage, the gate2 voltage, and the gate1 voltage have high logic voltages; and During the fourth time period, the transmit voltage and the gate3 voltage have low logic voltages, while the gate2 voltage and the gate1 voltage have high logic voltages.

6. The display device according to claim 5, wherein, The third time period is equal to or longer than two horizontal time periods.

7. The display device according to claim 5, wherein: During the first time period, the first transistor, the fifth transistor, and the eighth transistor are turned on, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor are turned off, and the first electrode and the second electrode of the storage capacitor have the initial voltage and the reference voltage, respectively. During the second time period, the first transistor, the second transistor, the sixth transistor, and the eighth transistor are turned on, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor are turned off, and the first electrode of the storage capacitor has the data voltage; During the third time period, the first transistor and the eighth transistor are turned on, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are turned off, and the first electrode of the storage capacitor has the sum of the data voltage and the threshold voltage; as well as During the fourth time period, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are off, the third transistor, the fourth transistor, and the seventh transistor are on, the second electrode of the storage capacitor has the high-level voltage, and the first electrode of the storage capacitor has a value obtained by adding the difference between the high-level voltage and the reference voltage to the sum of the data voltage and the threshold voltage.

8. The display device according to claim 1, wherein, The reset frame used to reset the light-emitting diode includes a fifth time period, and During the fifth time period, the transmit voltage and the gate1 voltage have high logic voltages, while the gate2 voltage and the gate3 voltage have low logic voltages.

9. The display device according to claim 8, wherein, During the fifth time period, the first transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are off, the second transistor and the sixth transistor are on, and the anode of the light-emitting diode has the initial voltage.

10. The display device according to claim 1, further comprising: The gate2 line transmits the gate2 voltage, the initial line transmits the initial voltage, the gate1 line transmits the gate1 voltage, the gate3 line transmits the gate3 voltage, and the transmission line transmits the transmission voltage; as well as The data line that transmits the data voltage, the power line that transmits the high-level voltage, and the reference line that transmits the reference voltage.

11. The display device according to claim 10, wherein, The gate2 line, the initial line, the gate1 line, the gate3 line, and the emission line are arranged parallel to each other in a horizontal direction, and The data line, the power line, and the reference line are arranged parallel to each other in a vertical direction.

12. A method for driving an organic light-emitting diode display device according to any one of claims 1 to 11, comprising: During the first time period, the first, fifth, and eighth transistors are turned on, and the second, third, fourth, sixth, and seventh transistors are turned off, and an initial voltage and a reference voltage are provided to the first and second electrodes of the storage capacitor, respectively. During the second time period, the first transistor, the second transistor, the sixth transistor, and the eighth transistor are turned on, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor are turned off, and a data voltage is provided to the first electrode of the storage capacitor; During the third time period, the first transistor and the eighth transistor are turned on, and the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are turned off. as well as During the fourth time period, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor are turned off, the third transistor, the fourth transistor, and the seventh transistor are turned on, and a high-level voltage is provided to the second electrode of the storage capacitor and the driving transistor.

13. The method of claim 12, further comprising: During the fifth time period, the first transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are turned off, the second transistor and the sixth transistor are turned on, and the initial voltage is provided to the anode of the light-emitting diode.

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