A method and apparatus in a node for wireless communication

Abstract

The application discloses a method and device in a node for wireless communication. The node receives a first information block; the node transmits a first PUCCH; the first information block determines a first scrambling sequence; the first PUCCH carries a first bit block and a second bit block; the number of bits included in the first bit block is not greater than 2; the sum of the number of bits included in the first bit block and the second bit block is greater than 2; the priority index of the first bit block is equal to a first level index, the priority index of the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block jointly generate a first bit sequence; the first bit sequence includes a placeholder bit, and the non-placeholder bit included in the first bit sequence is scrambled by the first scrambling sequence. The application improves the PUCCH link performance.

Description

[0001] This application is a divisional application of the following original application:

[0002] -- Original application filing date: April 26, 2021

[0003] -- Original application number: 202110463733.9

[0004] -- Original application title: Method and apparatus in a node for wireless communication TECHNICAL FIELD

[0005] The present application relates to a transmission method and apparatus in a wireless communication system, and more particularly, to a transmission scheme and apparatus for information with different priority levels in a wireless communication. BACKGROUND

[0006] The application scenarios of future wireless communication systems are increasingly diversified, and different application scenarios put forward different performance requirements for the system. In order to meet the different performance requirements of various application scenarios, it is decided at the 72nd plenary meeting of 3GPP (3rd Generation Partnership Project) RAN (Radio Access Network) to study the new radio technology (NR, New Radio) (or 5G), and the new radio technology (NR, New Radio) WI (Work Item) is passed at the 75th plenary meeting of 3GPP RAN, and the standardization work of NR is started. It is decided at the 86th plenary meeting of 3GPP RAN to start the SI (Study Item) and WI (Work Item) work of NR Rel-17.

[0007] In the new radio technology, enhanced mobile broadband (eMBB, enhanced Mobile BroadBand), ultra-reliable low-latency communication (URLLC, Ultra-reliable and Low Latency Communications), and massive machine type communication (mMTC, massive Machine Type Communications) are three main application scenarios. SUMMARY

[0008] In URLLC communication, there are transmissions of data or control information with different priority levels. In NR Rel-16, when UCI (Uplink Control Information) with different priority levels collide in time domain, the UCI with low priority is dropped to guarantee the transmission of UCI with high priority. In NR Rel-17, multiplexing of UCI with different priority levels onto the same PUCCH or the same PUSCH is supported.

[0009] For the multiplexing problem of UCI associated with different priority levels, a solution is disclosed in the present application. It should be noted that in the description of the present application, URLLC is only taken as a typical application scenario or example; the present application is also applicable to other scenarios facing similar problems (for example, scenarios where multiple services coexist, or other scenarios of multiplexing of information with different priority levels, or scenarios of multiplexing of services with different QoS requirements, or for different application scenarios such as V2X and eMBB multiplexing, etc.), and similar technical effects can be achieved. In addition, the use of a unified solution in different scenarios (including but not limited to the scenario of URLLC) also helps to reduce hardware complexity and cost. In the case of no conflict, the embodiments in the first node device and the features in the embodiments can be applied to the second node device, and vice versa. In particular, the explanation of the terms (Terminology), nouns, functions, and variables in the present application (if not specially specified) can refer to the definitions in the specification protocols TS36 series, TS38 series, and TS37 series of 3GPP.

[0010] The present application discloses a method in a first node for wireless communication, characterized in that it comprises:

[0011] receiving a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer greater than 1 of sequentially indexed bits;

[0012] transmitting a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block comprising at least 1 control information bit, the second bit block comprising at least 1 control information bit;

[0013] The number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are used together to generate a first bit sequence, the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having the same index.

[0014] As an embodiment, the placeholder bit is introduced into the scrambling process of the PUCCH, so that when different priority levels of uplink control information (UCI) bits are multiplexed on the PUCCH, and respectively encoded for high-priority UCI and low-priority UCI, the link transmission performance of the PUCCH transmission of 1 to 2 bits of high-priority UCI or low-priority UCI is guaranteed.

[0015] According to an aspect of the present application, the above method is characterized in that the modulation order of the modulation mode used by the first PUCCH is equal to a first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit.

[0016] As an embodiment, the placeholder bit is introduced only when the modulation order is greater than the number of information bits, so that the Euclidean distance can be maximized and the transmission robustness can be improved.

[0017] According to an aspect of the present application, the above method is characterized in that the first bit sequence and the first scrambling sequence are used together to generate a first output sequence, the first output sequence includes a positive integer greater than 1 of sequentially indexed bits, the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of a placeholder bit included in the first bit sequence, the bit whose index is equal to the first index included in the first output sequence is a first bit, a second bit is a bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, the bit value of the first bit and the bit value of the second bit are equal.

[0018] As an embodiment, when scrambling the placeholder bits, only the placeholder bits of the repeated transmission are introduced, considering the limitation of the modulation of the PUCCH and the limitation of the number of UCI bits, which simplifies the standardization work.

[0019] According to an aspect of the present application, the above method is characterized in that it comprises:

[0020] receiving a second information block;

[0021] wherein the second information block is used to determine X1 resource sets, X1 being a positive integer greater than 1; any one of the X1 resource sets comprises at least one PUCCH resource, the resource occupied by the first PUCCH belonging to a target PUCCH resource, the target PUCCH resource being one PUCCH resource comprised in a target resource set; the target resource set being one of the X1 resource sets, a target quantity value being used to determine the target resource set from the X1 resource sets, the target quantity value being a positive integer; at least one of the number of control information bits comprised in the first bit block or the number of control information bits comprised in the second bit block being used to determine the target quantity value.

[0022] According to an aspect of the present application, the above method is characterized in that it comprises:

[0023] receiving a first signaling;

[0024] wherein when the target resource set comprises more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

[0025] According to an aspect of the present application, the above method is characterized in that whether the number of control information bits comprised in the second bit block is used to determine the target quantity value is related to the second rank index.

[0026] As an embodiment, according to the priority level, it is determined whether the number of bits of the corresponding UCI is counted in the PUCCH resource determination process, which guarantees the robustness of the transmission of high-priority UCI in the case of multiplexing of high-priority and low-priority.

[0027] According to an aspect of the present application, the above method is characterized in that the second information block is used to determine a first code rate, the first code rate being a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain is equal to a first quantity value; the first code rate is used to determine the first quantity value, the number of bits comprised in the first bit sequence being in a positive proportional relationship with the first quantity value; the type of UCI carried by the first PUCCH is used to determine the first code rate.

[0028] As an embodiment, the code rate at the time of dynamically selecting the rate matching for the type of UCI is selected, so as to further ensure the robustness of the transmission of the high-priority UCI, while ensuring backward compatibility.

[0029] A method in a second node for wireless communication is disclosed, comprising:

[0030] transmitting a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer greater than 1 of sequentially indexed bits;

[0031] receiving a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block comprising at least 1 control information bit, the second bit block comprising at least 1 control information bit;

[0032] wherein the number of control information bits comprised in the first bit block is not greater than 2; the sum of the number of control information bits comprised in the first bit block and the number of control information bits comprised in the second bit block is greater than 2; the priority level index of the control information bits comprised in the first bit block is equal to a first level index, the priority level index of the control information bits comprised in the second bit block is equal to a second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence comprising an integer greater than 1 of sequentially indexed bits; at least one placeholder bit is comprised in the first bit sequence, the non-placeholder bits comprised in the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index.

[0033] According to an aspect of the present application, the above method is characterized in that the modulation order of the modulation mode adopted by the first PUCCH is equal to a first order, the first order being a positive integer greater than 1; the number of control information bits comprised in the first bit block is less than the first order, which is used to determine that the first bit sequence comprises at least one placeholder bit.

[0034] According to an aspect of the present application, the above method is characterized in that the first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence comprises a positive integer greater than 1 of sequentially indexed bits, and the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of one placeholder bit included in the first bit sequence, the bit equal to the first index included in the first output sequence is a first bit, the second bit is one bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, and the bit value of the first bit is equal to the bit value of the second bit.

[0035] According to an aspect of the present application, the above method is characterized in that it comprises:

[0036] sending a second information block;

[0037] wherein the second information block is used to determine X1 resource sets, X1 is a positive integer greater than 1, any one of the X1 resource sets comprises at least one PUCCH resource, the first PUCCH occupies a resource belonging to a target PUCCH resource, the target PUCCH resource is one PUCCH resource included in a target resource set, the target resource set is one of the X1 resource sets, a target quantity value is used to determine the target resource set from the X1 resource sets, the target quantity value is a positive integer, and at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the target quantity value.

[0038] According to an aspect of the present application, the above method is characterized in that it comprises:

[0039] sending a first signaling;

[0040] wherein when the target resource set comprises more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

[0041] According to an aspect of the present application, the above method is characterized in that whether the number of control information bits included in the second bit block is used to determine the target quantity value is related to the second level index.

[0042] According to an aspect of the present application, the method is characterized in that: the second information block is used to determine a first code rate, the first code rate is a non-negative number; the first PUCCH occupies a first number of physical resource blocks in the frequency domain; the first code rate is used to determine the first number, the first bit sequence includes a number of bits in a positive correlation with the first number; and a type of UCI carried by the first PUCCH is used to determine the first code rate.

[0043] The present application discloses a first node device for wireless communication, characterized in that comprising:

[0044] a first receiver, configured to receive a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, and the first scrambling sequence including an integer number of sequentially indexed bits greater than 1;

[0045] a first transmitter, configured to transmit a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block including at least one control information bit, and the second bit block including at least one control information bit;

[0046] wherein: the first bit block includes no more than two control information bits; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than two; the first bit block includes control information bits with a priority index equal to a first level index, and the second bit block includes control information bits with a priority index equal to a second level index, the first level index and the second level index being different; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence including an integer number of sequentially indexed bits greater than 1; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by the bits in the first scrambling sequence with the same index.

[0047] The present application discloses a second node device for wireless communication, characterized in that comprising:

[0048] a second transmitter, configured to transmit a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, and the first scrambling sequence including an integer number of sequentially indexed bits greater than 1;

[0049] The second receiver receives the first PUCCH, which is used to carry a first bit block and a second bit block, the first bit block includes at least one control information bit, and the second bit block includes at least one control information bit.

[0050] The number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having the same index.

[0051] As an embodiment, the method in the present application has the following advantages:

[0052] The method in the present application introduces placeholder bits into the scrambling process of PUCCH, thereby ensuring the link transmission performance of PUCCH transmitting 1 to 2 bits of high-priority UCI or low-priority UCI when different priority levels of UCI bits are multiplexed on the PUCCH and respectively encoded for high-priority UCI and low-priority UCI;

[0053] The method in the present application introduces placeholder bits only when the modulation order is greater than the number of information bits, thereby maximizing the Euclidean distance and improving transmission robustness;

[0054] When the method in the present application scrambles the placeholder bits, only repeated transmission placeholder bits are introduced considering the modulation limit of PUCCH and the number limit of UCI bits, thereby simplifying standardization work;

[0055] The method in the present application determines whether the number of bits of UCI corresponding to the priority level is included in the PUCCH resource determination process according to the priority level, thereby ensuring the robustness of transmission of high-priority UCI in the case of multiplexing of high-priority UCI and low-priority UCI;

[0056] The method in the present application supports dynamically selecting the code rate when rate matching for the type of UCI, thereby further ensuring the robustness of transmission of high-priority UCI and ensuring backward compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0057] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in connection with the following accompanying drawings:

[0058] Figure 1 A flowchart of a first information block and a first PUCCH is shown in accordance with an embodiment of the present application;

[0059] Figure 2 A schematic diagram of a network architecture is shown in accordance with an embodiment of the present application;

[0060] Figure 3 A schematic diagram of a radio protocol architecture for the user and control planes is shown in accordance with an embodiment of the present application;

[0061] Figure 4 A schematic diagram of a first node device and a second node device is shown in accordance with an embodiment of the present application;

[0062] Figure 5 A flowchart of a wireless signal transmission is shown in accordance with an embodiment of the present application;

[0063] Figure 6 A schematic diagram of a relationship between a first order and a first bit block is shown in accordance with an embodiment of the present application;

[0064] Figure 7 A schematic diagram of a relationship between a first bit and a second bit is shown in accordance with an embodiment of the present application;

[0065] Figure 8 A schematic diagram of a relationship between a target number value and a target resource set is shown in accordance with an embodiment of the present application;

[0066] Figure 9 A schematic diagram of a relationship between a target number value and a second rank index is shown in accordance with an embodiment of the present application;

[0067] Figure 10 A schematic diagram of a first number value is shown in accordance with an embodiment of the present application;

[0068] Figure 11 A block diagram of a structure of a processing device in a first node device is shown in accordance with an embodiment of the present application;

[0069] Figure 12 A block diagram of a structure of a processing device in a second node device is shown in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0070] With reference to the drawings, the technical solutions of the present application will be further described in detail below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0071] Example 1

[0072] Embodiment 1 illustrates a flowchart 100 of a first information block and a first PUCCH according to an embodiment of the present application, as shown in the accompanying drawings. Figure 1 As shown in the accompanying drawings, each block represents a step. In particular, the order of the blocks in the drawings does not represent the time sequence of the steps represented by the blocks. Figure 1

[0073] In Embodiment 1, the first node device in the present application receives a first information block in step 101; the first node device in the present application transmits a first PUCCH in step 102; the first information block is used to determine a first parameter value, the first parameter value is used to generate a first scrambling sequence, the first parameter value is a non-negative integer, and the first scrambling sequence includes an integer greater than 1 of sequentially indexed bits; the first PUCCH is used to carry a first bit block and a second bit block, the first bit block includes at least 1 control information bit, and the second bit block includes at least 1 control information bit; the number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, and the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index.

[0074] As an embodiment, the first information block is transmitted through an air interface or a wireless interface.

[0075] As an embodiment, the first information block includes all or part of a high layer signaling or a physical layer signaling.

[0076] ​As an embodiment, the first information block includes all or part of a Radio Resource Control (RRC) layer signaling or a Medium Access Control (MAC) layer signaling.

[0077] As an embodiment, the first information block is carried by a Physical Downlink Shared Channel (PDSCH).

[0078] As an embodiment, the first information block is carried by a Synchronization / Physical Broadcast Channel (SS / PBCH) block.

[0079] As an embodiment, the first information block is carried by a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS).

[0080] As an embodiment, the first information block is Cell Specific or UE-specific.

[0081] As an embodiment, the first information block is Per BWP Configured.

[0082] As an embodiment, the first information block includes all or part of a field in a Downlink Control Information (DCI) format.

[0083] As an embodiment, the first information block includes more than one sub-information block, each of the sub-information blocks included in the first information block is an Information Element (IE) or a field in the RRC signaling to which the first information block belongs; and one or more of the sub-information blocks included in the first information block are used to determine the first parameter.

[0084] As one embodiment, the first information block comprises all or part of fields in an IE (Information Element) "dataScramblingIdentityPUSCH" in an RRC signaling.

[0085] As one embodiment, the first information block comprises all or part of fields in an IE (Information Element) "PUSCH-Config" in an RRC signaling.

[0086] As one embodiment, the first information block comprises all or part of fields in an IE (Information Element) "PUCCH-Config" in an RRC signaling.

[0087] As one embodiment, the first information block comprises all or part of fields in an IE (Information Element) "BWP-UplinkDedicated" in an RRC signaling.

[0088] As one embodiment, the expression "the first information block is used to determine the first parameter value" in the claim comprises the following meaning: the first information block is used by the first node device in the present application to determine the first parameter value.

[0089] As one embodiment, the expression "the first information block is used to determine the first parameter value" in the claim comprises the following meaning: the first information block is used to explicitly indicate the first parameter value.

[0090] As one embodiment, the expression "the first information block is used to determine the first parameter value" in the claim comprises the following meaning: the first information block is used to implicitly indicate the first parameter value.

[0091] As one embodiment, the first parameter value is equal to the physical cell ID (PCID, Physical Cell ID) of the serving cell (Serving Cell) to which the first information block belongs.

[0092] As one embodiment, the first parameter value is equal to one of 0, 1, 2, …, 1023.

[0093] As one embodiment, the first parameter value is greater than 1023.

[0094] As one embodiment, the first scrambling sequence is a pseudo-random sequence.

[0095] As an embodiment, the first scrambling sequence is a Gold sequence of length 31.

[0096] As an embodiment, the first scrambling sequence is a m-sequence.

[0097] As an embodiment, the expression "the first parameter value is used to generate the first scrambling sequence" in the claim comprises the meaning that the first parameter value is used to calculate an initial value of a generator of the first scrambling sequence.

[0098] As an embodiment, the expression "the first parameter value is used to generate the first scrambling sequence" in the claim comprises the meaning that the first parameter value is used to initialize a generator of the first scrambling sequence.

[0099] As an embodiment, the expression "the first parameter value is used to generate the first scrambling sequence" in the claim comprises the meaning that the first parameter value is used to initialize a register of a generator of the first scrambling sequence.

[0100] As an embodiment, the expression "the first parameter value is used to generate the first scrambling sequence" in the claim comprises the meaning that the first parameter value is used to calculate a first initial value, which is used to initialize a generator of the first scrambling sequence. As an dependent embodiment of the above embodiment, the C-RNTI to which the first node device is configured is also used to calculate the first initial value.

[0101] As an embodiment, the first scrambling sequence comprises the same number of bits as the first bit sequence.

[0102] As an embodiment, the first scrambling sequence comprises a different number of bits than the first bit sequence.

[0103] As an embodiment, the bits of the first scrambling sequence are indexed in the order 0, 1, 2,...

[0104] As an embodiment, the first PUCCH comprises a radio frequency signal of a PUCCH (Physical Uplink Control Channel).

[0105] As an embodiment, the first PUCCH comprises a baseband signal of a PUCCH.

[0106] As an embodiment, the first PUCCH carries UCI (Uplink Control Information).

[0107] As one embodiment, a UCI payload in a UCI format (Format) is used to generate the first PUCCH.

[0108] As one embodiment, the first PUCCH is in PUCCH Format 2.

[0109] As one embodiment, the first PUCCH is in PUCCH Format 3 or 4.

[0110] As one embodiment, the first PUCCH occupies only one PRB (Physical Resource Block) in frequency domain.

[0111] As one embodiment, the first PUCCH occupies more than one PRB (Physical Resource Block) in frequency domain.

[0112] As one embodiment, the first bit block includes information bits and CRC bits.

[0113] As one embodiment, the first bit block includes only information bits.

[0114] As one embodiment, the second bit block includes information bits and CRC bits.

[0115] As one embodiment, the second bit block includes only information bits.

[0116] As one embodiment, the first bit block includes only 1 HARQ-ACK bit.

[0117] As one embodiment, the first bit block includes more than 1 HARQ-ACK bit.

[0118] As one embodiment, the first bit block includes bits other than HARQ-ACK bits.

[0119] As one embodiment, the first bit block is a UCI payload.

[0120] As one embodiment, the second bit block includes only 1 HARQ-ACK bit.

[0121] As one embodiment, the second bit block includes more than 1 HARQ-ACK bit.

[0122] As one embodiment, the second bit block includes bits other than HARQ-ACK bits.

[0123] As one embodiment, the second block of bits is UCI payload.

[0124] As one embodiment, the first block of bits includes only HARQ-ACK bits.

[0125] As one embodiment, the second block of bits includes only HARQ-ACK bits.

[0126] As one embodiment, the first block of bits includes CSI bits.

[0127] As one embodiment, the first block of bits does not include CSI bits.

[0128] As one embodiment, the second block of bits includes CSI bits.

[0129] As one embodiment, the second block of bits does not include CSI bits.

[0130] As one embodiment, the expression "the first PUCCH is used to carry the first block of bits and the second block of bits" in a claim includes the following meaning: the first PUCCH is used by the first node device in the present application to carry the first block of bits and the second block of bits.

[0131] As one embodiment, the expression "the first PUCCH is used to carry the first block of bits and the second block of bits" in a claim includes the following meaning: the first block of bits and the second block of bits are used to generate the first PUCCH.

[0132] As one embodiment, the expression "the first PUCCH is used to carry the first block of bits and the second block of bits" in a claim includes the following meaning: the first block of bits and the second block of bits are transmitted on the first PUCCH.

[0133] As one embodiment, the expression "the first PUCCH is used to carry the first block of bits and the second block of bits" in a claim includes the following meaning: the first block of bits and the second block of bits are used to generate a codeword of the first PUCCH.

[0134] As an embodiment, the expression "the first PUCCH is used to carry the first block of bits and the second block of bits" in a claim includes the following meaning: the first block of bits and the second block of bits together are used to generate the first PUCCH.

[0135] As an embodiment, the second block of bits includes a number of control information bits not greater than 2.

[0136] As an embodiment, the second block of bits includes a number of control information bits greater than 2.

[0137] As an embodiment, the second block of bits includes a number of control information bits equal to 1.

[0138] As an embodiment, the second block of bits includes a number of control information bits equal to 2.

[0139] As an embodiment, the first block of bits includes a number of control information bits equal to 1.

[0140] As an embodiment, the first block of bits includes a number of control information bits equal to 2.

[0141] As an embodiment, the first rank index is a non-negative integer.

[0142] As an embodiment, the first rank index is equal to one of 0 or 1.

[0143] As an embodiment, the first rank index is a positive integer.

[0144] As an embodiment, the second rank index is a non-negative integer.

[0145] As an embodiment, the second rank index is equal to one of 0 or 1.

[0146] As an embodiment, the second rank index is a positive integer.

[0147] As an embodiment, the first rank index is greater than the second rank index.

[0148] As an embodiment, the first rank index is smaller than the second rank index.

[0149] As an embodiment, the priority rank index of the control information bits included in the first block of bits is the priority rank index of the PDSCH to which the control information bits included in the first block of bits are associated.

[0150] As one embodiment, the priority index of the control information bits comprised in the first bit block is a priority index (Priority index) indicated by a DCI format carried by a PDCCH to which the control information bits comprised in the first bit block are associated.

[0151] As one embodiment, the priority index of the control information bits comprised in the first bit block is a value of a priority indicator (Priority indicator) carried by a PDCCH to which the control information bits comprised in the first bit block are associated.

[0152] As one embodiment, the priority index of the control information bits comprised in the second bit block is a priority index of a PDSCH to which the control information bits comprised in the second bit block are associated.

[0153] As one embodiment, the priority index of the control information bits comprised in the second bit block is a priority index (Priority index) indicated by a DCI format carried by a PDCCH to which the control information bits comprised in the second bit block are associated.

[0154] As one embodiment, the priority index of the control information bits comprised in the second bit block is a value of a priority indicator (Priority indicator) carried by a PDCCH to which the control information bits comprised in the second bit block are associated.

[0155] As one embodiment, the first PUCCH corresponds to the first index.

[0156] As one embodiment, a priority index associated with the first PUCCH is equal to the first index.

[0157] As one embodiment, a priority index (Priority index) indicated by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the first index.

[0158] As one embodiment, a value of a priority indicator (Priority indicator) carried by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the first index.

[0159] As one embodiment, a priority index (Priority index) indicated by a DCI format carrying a PRI (PUCCH Resource Indicator) for the first PUCCH is equal to the first index.

[0160] As one embodiment, a value of a priority indicator carried by a DCI format carrying a PRI for the first PUCCH is equal to the first priority index.

[0161] As one embodiment, the first PUCCH corresponds to the second priority index.

[0162] As one embodiment, a priority index associated with the first PUCCH is equal to the second priority index.

[0163] As one embodiment, a priority index indicated by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the second priority index.

[0164] As one embodiment, a value of a priority indicator carried by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the second priority index.

[0165] As one embodiment, a priority index indicated by a DCI format carrying a PRI (PUCCH Resource Indicator) for the second PUCCH is equal to the first priority index.

[0166] As one embodiment, a value of a priority indicator carried by a DCI format carrying a PRI for the second PUCCH is equal to the first priority index.

[0167] As one embodiment, the first PUCCH corresponds to a larger one of the first priority index and the second priority index.

[0168] As one embodiment, a priority index associated with the first PUCCH is equal to a larger one of the first priority index and the second priority index.

[0169] As one embodiment, the first PUCCH corresponds to a smaller one of the first priority index and the second priority index.

[0170] As one embodiment, a priority index associated with the first PUCCH is equal to a smaller one of the first priority index and the second priority index.

[0171] As one embodiment, a priority index indicated by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the larger of the first priority index and the second priority index when compared.

[0172] As one embodiment, a value of a priority indicator carried by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the larger of the first priority index and the second priority index when compared.

[0173] As one embodiment, a priority index indicated by a DCI format carrying a PRI (PUCCH Resource Indicator) for the first PUCCH is equal to the larger of the first priority index and the second priority index when compared.

[0174] As one embodiment, a value of a priority indicator carried by a DCI format carrying a PRI for the first PUCCH is equal to the larger of the first priority index and the second priority index when compared.

[0175] As one embodiment, a priority index indicated by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the smaller of the first priority index and the second priority index when compared.

[0176] As one embodiment, a value of a priority indicator carried by a DCI format indicating time-frequency resources occupied by the first PUCCH is equal to the smaller of the first priority index and the second priority index when compared.

[0177] As one embodiment, a priority index indicated by a DCI format carrying a PRI (PUCCH Resource Indicator) for the first PUCCH is equal to the smaller of the first priority index and the second priority index when compared.

[0178] As one embodiment, a value of a priority indicator carried by a DCI format carrying a PRI for the first PUCCH is equal to the smaller of the first priority index and the second priority index when compared.

[0179] As an embodiment, the expression "the first bit block and the second bit block are used together to generate the first bit sequence" in the claims includes the following meaning: the first bit block and the second bit block are used together by the first node device in the present application to generate the first bit sequence.

[0180] As an embodiment, the expression "the first bit block and the second bit block are used together to generate the first bit sequence" in the claims includes the following meaning: the bit block obtained by channel encoding the first bit block and the bit block obtained by channel encoding the second bit block are used together to generate the first bit sequence.

[0181] As an embodiment, the expression "the first bit block and the second bit block are used together to generate the first bit sequence" in the claims includes the following meaning: the bit block obtained by channel encoding the first bit block and then rate matching, and the bit block obtained by channel encoding the second bit block and then rate matching are concatenated to generate the first bit sequence.

[0182] As an embodiment, the expression "the first bit block and the second bit block are used together to generate the first bit sequence" in the claims includes the following meaning: the first bit block is sequentially subjected to channel encoding and rate matching to generate a first target bit sequence, the second bit block is sequentially subjected to channel encoding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

[0183] As an embodiment, the expression "the first bit block and the second bit block are used together to generate the first bit sequence" in the claims includes the following meaning: the first bit block is sequentially subjected to channel encoding and rate matching to generate a first target bit sequence, the second bit block is sequentially subjected to CRC insertion, channel encoding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

[0184] As an embodiment, the expression "the first bit block and the second bit block are jointly used to generate a first bit sequence" in the claims includes the following meaning: the first bit block is sequentially subjected to channel coding and rate matching to generate a first target bit sequence, the second bit block is used to generate a third bit block, the third bit block includes less bits than the second bit block, the third bit block is sequentially subjected to channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

[0185] As an embodiment, the expression "the first bit block and the second bit block are jointly used to generate a first bit sequence" in the claims includes the following meaning: the first bit block is sequentially subjected to channel coding and rate matching to generate a first target bit sequence, the second bit block is used to generate a third bit block, the third bit block includes less bits than the second bit block, the third bit block is sequentially subjected to channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

[0186] As an embodiment, the expression "the first bit block and the second bit block are jointly used to generate a first bit sequence" in the claims includes the following meaning: the first bit block is sequentially subjected to channel coding and rate matching to generate a first target bit sequence, the second bit block is subjected to compression or dropping or bundling to generate a third bit block, the third bit block includes less bits than the second bit block, the third bit block is sequentially subjected to channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

[0187] As an embodiment, the first bit sequence is sequentially indexed as 0, 1, 2, ….

[0188] As an embodiment, the placeholder bit is a placeholder bit in repetition coding.

[0189] As an embodiment, the placeholder bit is a placeholder bit in Simplex coding.

[0190] As one embodiment, the placeholder bit is a bit marked as "x" in repetition coding or Simplex coding.

[0191] As one embodiment, the placeholder bit is a bit marked as "y" in repetition coding or Simplex coding.

[0192] As one embodiment, the placeholder bit is a bit marked as "x" or a bit marked as "y" in repetition coding or Simplex coding.

[0193] As one embodiment, the placeholder bit is a bit that is not scrambled in a scrambling process.

[0194] As one embodiment, the placeholder bit is a bit that needs special handling.

[0195] As one embodiment, the placeholder bit is a bit that is used to maximize Euclidean distance.

[0196] As one embodiment, the expression "non-placeholder bits comprised in the first bit sequence are scrambled by bits having the same index in the first scrambling sequence" in the claims includes the following meaning: any one of the non-placeholder bits comprised in the first bit sequence is scrambled by the bit having the same index in the first scrambling sequence.

[0197] As one embodiment, the expression "non-placeholder bits comprised in the first bit sequence are scrambled by bits having the same index in the first scrambling sequence" in the claims includes the following meaning: the non-placeholder bits comprised in the first bit sequence and the bits having the same index in the first scrambling sequence are subjected to an AND operation.

[0198] As one embodiment, the expression "non-placeholder bits comprised in the first bit sequence are scrambled by bits having the same index in the first scrambling sequence" in the claims includes the following meaning: the non-placeholder bits comprised in the first bit sequence and the bits having the same index in the first scrambling sequence are subjected to an OR operation.

[0199] As one embodiment, the expression "non-placeholder bits comprised in the first bit sequence are scrambled by bits having the same index in the first scrambling sequence" in the claims includes the following meaning: the bits comprised in the first bit sequence and the bits comprised in the first scrambling sequence are in one-to-one correspondence, and any one of the non-placeholder bits comprised in the first bit sequence and the corresponding bit in the first scrambling sequence are subjected to an AND operation.

[0200] As an embodiment, the expression "non-occupation bits comprised in the first bit sequence are scrambled by bits having the same index in the first scrambling sequence" in the claims comprises the following meaning: the first scrambling sequence scrambles the non-occupation bits comprised in the first bit sequence.

[0201] As an embodiment, the bit sequence obtained by scrambling the non-occupation bits comprised in the first bit sequence by bits having the same index in the first scrambling sequence and the occupation bits comprised in the first bit sequence after processing are used together to generate the first PUCCH.

[0202] As an embodiment, the first bit sequence and the first scrambling sequence are used together to generate the first PUCCH.

[0203] As an embodiment, the first bit sequence and the first scrambling sequence are used together to generate the first PUCCH in sequence by Scrambling, Modulation, Spreading, Mapping to physical resources, OFDM baseband signal generation, and Modulation and upconversion.

[0204] As an embodiment, the first bit sequence and the first scrambling sequence are used together to generate the first PUCCH in sequence by Scrambling, Modulation, Spreading, Mapping to physical resources, and OFDM baseband signal generation.

[0205] As an embodiment, the first bit sequence and the first scrambling sequence are used together to generate the first PUCCH in sequence by Scrambling, Modulation, Block-wise Spreading, Transform Precoding, Mapping to physical resources, OFDM baseband signal generation, and Modulation and upconversion.

[0206] As an embodiment, the first bit sequence and the first scrambling sequence together go through, in sequence, Scrambling, Modulation, Block-wise Spreading, Transform Precoding, Mapping to physical resources, OFDM baseband signal generation to generate the first PUCCH.

[0207] Example 2

[0208] Embodiment 2 illustrates a schematic diagram of a network architecture according to the present application, as shown in FIG. 2. FIG. 2 shows a network architecture 200 according to the present application. The network architecture 200 includes a network 202, a network node 204, and a UE 206. Figure 2 As shown in FIG. 2, the network node 204 is connected to the network 202. The network node 204 is configured to transmit a PUCCH to the UE 206 via the network 202. The UE 206 is configured to receive the PUCCH from the network node 204 via the network 202. Figure 2A diagram illustrating a network architecture 200 for 5G NR, LTE (Long-Term Evolution), and LTE-A (Long-Term Evolution Advanced) systems is shown. The 5G NR or LTE network architecture 200 can be referred to as a 5GS (5G System) / EPS (Evolved Packet System) 200 or some other suitable terminology. The 5GS / EPS 200 can include one or more UEs (User Equipment) 201, NG-RAN (Next Generation Radio Access Network) 202, 5GC (5G Core Network, 5G Core Network) / EPC (Evolved Packet Core) 210, HSS (Home Subscriber Server) / UDM (Unified Data Management) 220, and Internet services 230. The 5GS / EPS can interconnect with other access networks, but these entities / interfaces are not shown for simplicity. As shown, the 5GS / EPS provides packet-switched services, however, those skilled in the art will readily appreciate that the various concepts presented throughout this application can be extended to networks providing circuit-switched services or other cellular networks. The NG-RAN includes NR / evolved Node-Bs (gNBs / eNBs) 203 and other gNBs (eNBs) 204. The gNBs (eNBs) 203 provide user and control plane protocol terminations toward the UEs 201. The gNBs (eNBs) 203 can be connected to other gNBs (eNBs) 204 via an Xn / X2 interface (e.g., backhaul). The gNBs (eNBs) 203 can also be referred to as base stations, base transceiver stations, radio base stations, radio transceivers, transceiver functions, basic service sets (BSSs), extended service sets (ESSs), TRPs (Transmission and Reception Points), or some other suitable terminology. The gNBs (eNBs) 203 provide access to the 5GC / EPC 210 for the UEs 201. Examples of UEs 201 include cellular phones, smart phones, session initiation protocol (SIP) phones, laptop computers, personal digital assistants (PDAs), satellite radios, non-terrestrial base station communications, satellite mobile communications, global positioning systems, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, drones, unmanned aerial vehicles, narrowband internet of things devices, machine type communication devices, land vehicles, automobiles, wearable devices, test equipment, test instruments, test tools, or any other similar functional devices.A UE 201 can also be referred to as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communication device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. A gNB (eNB) 203 is connected to a 5GC / EPC 210 by an S1 / NG interface. The 5GC / EPC 210 includes a MME (Mobility Management Entity) / AMF (Authentication Management Field) / SMF (Session Management Function) 211, other MME / AMF / SMF 214, a S-GW (Service Gateway) / UPF (User Plane Function) 212, and a P-GW (Packet Data Network Gateway) / UPF 213. The MME / AMF / SMF 211 is a control node that handles signaling between the UE 201 and the 5GC / EPC 210. Generally, the MME / AMF / SMF 211 provides bearer and connection management. All user IP (Internet Protocal) packets are transferred through the S-GW / UPF 212, which itself is connected to the P-GW / UPF 213. The P-GW provides UE IP address allocation as well as other functions. The P-GW / UPF 213 is connected to Internet services 230. The Internet services 230 include operator corresponding Internet protocol services, which can include the Internet, an intranet, IMS (IP Multimedia Subsystem), and packet switched streaming services, among others.

[0209] As an embodiment, the UE 201 corresponds to the first node device in the present application.

[0210] As an embodiment, the UE 201 supports multiplexing transmission of UCIs associated to different priority levels.

[0211] As an embodiment, the gNB (eNB) 201 corresponds to the second node device in the present application.

[0212] As an embodiment, the gNB (eNB) 201 supports multiplexing transmission of UCIs associated to different priority levels.

[0213] Example 3

[0214] Figure 3 shows a schematic diagram illustrating an embodiment of a radio protocol architecture for the user plane and control plane of a wireless communication system according to an embodiment of the application, in accordance with Figure 2. Figure 3 Figure 3 shows a schematic diagram illustrating an embodiment of a radio protocol architecture for the user plane and control plane of a wireless communication system according to an embodiment of the application, in accordance with Figure 2. Figure 3 Figure 3 shows a schematic diagram illustrating an embodiment of a radio protocol architecture for the user plane and control plane of a wireless communication system according to an embodiment of the application, in accordance with Figure 2. Figure 3The radio protocol architecture for the control plane 300 of a first node device (UE or gNB) and a second node device (gNB or UE) is shown with three layers: Layer 1, Layer 2, and Layer 3. Layer 1 (L1 layer) is the lowest layer and implements various PHY (Physical layer) signal processing functions. The L1 layer will be referred to as the PHY 301 herein. Layer 2 (L2 layer) 305 is above the PHY 301 and is responsible for the link between the first node device and the second node device using the PHY 301. The L2 layer 305 includes a MAC (Medium Access Control) sublayer 302, a RLC (Radio Link Control) sublayer 303, and a PDCP (Packet Data Convergence Protocol) sublayer 304, which are terminated at the second node device. The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. The PDCP sublayer 304 also provides security functions that include the ciphering service to protect the data and the integrity protection service to detect any manipulation of the data. The RLC sublayer 303 provides segmentation and reassembly of upper layer data packets, retransmission of lost data packets, and reordering of data packets to compensate for out-of-order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical and transport channels. The MAC sublayer 302 is also responsible for allocating the various radio resources (e.g., resource blocks) in one cell among the UEs. The MAC sublayer 302 is also responsible for HARQ operations. The RRC (Radio Resource Control) sublayer 306 in Layer 3 (L3 layer) in the control plane 300 is responsible for obtaining radio resources (i.e., radio bearers) and configuring the lower layers using RRC signaling between the second node device and the first node device. The radio protocol architecture for the user plane 350 includes Layer 1 (L1 layer) and Layer 2 (L2 layer), which are substantially the same as the corresponding layers and sublayers in the control plane 300 for the physical layer 351, the PDCP sublayer 354 in the L2 layer 355, the RLC sublayer 353 in the L2 layer 355, and the MAC sublayer 352 in the L2 layer 355 for the first node device and the second node device, but the PDCP sublayer 354 also provides header compression for upper layer data packets to reduce radio transmission overhead. The SDAP (Service Data Adaptation Protocol) sublayer 356 is also included in the L2 layer 355 in the user plane 350, which is responsible for mapping between QoS flows and data radio bearers (DRBs) to support diverse traffic.Although not shown, the first node device can have several upper layers above the L2 layer 355, including a network layer (e.g., IP layer) that terminates at a P-GW on the network side and an application layer that terminates at the other end of the connection (e.g., a remote UE, a server, etc.).

[0215] As one embodiment, the wireless protocol architecture in FIG. 3A is applicable to the first node device in the present application. Figure 3

[0216] As one embodiment, the wireless protocol architecture in FIG. 3A is applicable to the first node device in the present application. Figure 3

[0217] As one embodiment, the first information block in the present application is generated at the RRC 306, or the MAC 302, or the MAC 352, or the PHY 301, or the PHY 351.

[0218] As one embodiment, the first PUCCH in the present application is generated at the PHY 301, or the PHY 351.

[0219] As one embodiment, the first signaling in the present application is generated at the PHY 301, or the PHY 351.

[0220] As one embodiment, the second information block in the present application is generated at the RRC 306, or the MAC 302, or the MAC 352, or the PHY 301, or the PHY 351.

[0221] Example 4

[0222] Embodiment 4 shows a schematic diagram of a first node device and a second node device according to one embodiment of the present application, as shown in FIG. 4. Figure 4

[0223] In the first node device (450) can include a controller / processor 490, a data source / buffer 480, a receive processor 452, a transmitter / receiver 456 including antenna 460, and a transmit processor 455.

[0224] In the second node device (410) can include a controller / processor 440, a data source / buffer 430, a receive processor 412, a transmitter / receiver 416 including antenna 420, and a transmit processor 415.

[0225] ​​​In the DL, the upper layer packets, such as the upper layer information carried by the first information block and the second information block in the present application (when the first information block includes the upper layer information) are provided to the controller / processor 440. The controller / processor 440 implements functionality of higher layer, such as the layer 2. In the DL, the controller / processor 440 provides header compression, ciphering, packet segmentation and reordering, multiplexing between logical and transport channels, and radio resource allocations for the first node device 450 based on various priority metrics. The controller / processor 440 is also responsible for HARQ operations, retransmission of lost packets, and signaling to the first node device 450, such as the high layer information included in the first information block and the second information block in the present application are generated in the controller / processor 440. The transmit processor 415 implements various signal processing functions for the layer 1 (i.e., physical layer) such as encoding, interleaving, scrambling, modulation, power control / assignment, precoding, and physical layer control signaling generation, etc., such as the generation of the physical layer signals carrying the first information block and the second information block and the first signaling is done in the transmit processor 415. The generated modulation symbols are then split into parallel streams, one for each transmit antenna 420, and each stream is mapped to a respective sub-carrier, and / or a respective multi-carrier symbol, and then the stream is further mapped to an antenna 420 via a transmit processor 415 to be transmitted via a transmitter 416 in the form of a radio frequency signal. At the receiver side, each receiver 456 receives the radio frequency signal through its respective antenna 460, each receiver 456 recovers the baseband information modulated onto the radio frequency carrier, and provides the baseband information to the receive processor 452. The receive processor 452 implements various signal processing functions of the layer 1. The signal processing functions include the reception of the physical layer signals carrying the first information block in the present application and the physical layer signals carrying the second information block in the present application and the first signaling, demodulation based on various modulation schemes (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK)) through the multi-carrier symbols in the multi-carrier symbol stream, followed by descrambling, decoding, and de-interleaving to recover the data or control transmitted by the second node device 410 on the physical channel, followed by providing the data and control signals to the controller / processor 490. The controller / processor 490 is responsible for the layer 2 and above, the controller / processor 490 interprets the high layer information included in the first information block in the present application and the high layer information carried by the second information block. The controller / processor can be associated with a memory that stores program codes and data. The memory can be referred to as a computer readable medium.

[0226] In the uplink (UL), similar to the downlink transmission, high layer information is first generated at the controller / processor 490 and then subjected to various signal processing functions at the transmit processor 455 for the LI layer (i.e., physical layer). The first PUCCH in this application is generated at the transmit processor 455 and then mapped to the antennas 460 via the transmitter 456 for transmission as radio frequency signals. The receiver 416 receives the radio frequency signals through its respective antennas 420, and each receiver 416 recovers the baseband information modulated onto the radio frequency carrier and provides the baseband information to the receive processor 412. The receive processor 412 implements various signal processing functions for the LI layer (i.e., physical layer) and then provides data and / or control signals to the controller / processor 440. The controller / processor 440 implements the functionality of the L2 layer, including the interpretation of high layer information. The controller / processor can be associated with a memory that stores program codes and data. The memory can be a computer readable medium.

[0227] As one embodiment, the first node device 450 apparatus includes at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured to, with the at least one processor, cause the first node device 450 apparatus at least to: receive a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence including an integer number of sequentially indexed bits greater than 1; transmit a first PUCCH, the first PUCCH being used to carry a first block of bits and a second block of bits, the first block of bits including at least 1 control information bit, the second block of bits including at least 1 control information bit; wherein a number of control information bits included in the first block of bits is no greater than 2; a sum of the number of control information bits included in the first block of bits and the number of control information bits included in the second block of bits is greater than 2; a priority index of the control information bits included in the first block of bits is equal to a first index, a priority index of the control information bits included in the second block of bits is equal to a second index, the first index and the second index being not equal; the first block of bits and the second block of bits are collectively used to generate a first bit sequence, the first bit sequence including an integer number of sequentially indexed bits greater than 1; the first bit sequence includes at least one placeholder bit, non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having a same index.

[0228] As an embodiment, the first node device 450 device comprises: a memory storing a computer readable program of instructions which, when executed by at least one processor, results in actions comprising: receiving a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer number of sequentially indexed bits greater than 1; transmitting a first PUCCH, the first PUCCH being used to carry a first block of bits and a second block of bits, the first block of bits comprising at least 1 control information bit, the second block of bits comprising at least 1 control information bit; wherein the number of control information bits comprised by the first block of bits is not greater than 2; the sum of the number of control information bits comprised by the first block of bits and the number of control information bits comprised by the second block of bits is greater than 2; the priority index of the control information bits comprised by the first block of bits is equal to a first index, the priority index of the control information bits comprised by the second block of bits is equal to a second index, the first index and the second index being not equal; the first block of bits and the second block of bits are collectively used to generate a first bit sequence, the first bit sequence comprising an integer number of sequentially indexed bits greater than 1; at least one placeholder bit is comprised in the first bit sequence, the non-placeholder bits comprised by the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index.

[0229] As an embodiment, the second node device 410 apparatus comprises at least one processor and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the second node device 410 apparatus at least to: transmit a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer number of sequentially indexed bits greater than 1 ; receive a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block comprising at least 1 control information bit, the second bit block comprising at least 1 control information bit; wherein a number of control information bits comprised by the first bit block is not greater than 2; a sum of the number of control information bits comprised by the first bit block and a number of control information bits comprised by the second bit block is greater than 2; a priority index of control information bits comprised by the first bit block is equal to a first level index, a priority index of control information bits comprised by the second bit block is equal to a second level index, the first level index and the second level index being not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence comprising an integer number of sequentially indexed bits greater than 1 ; at least one placeholder bit is comprised in the first bit sequence, non-placeholder bits comprised by the first bit sequence are scrambled by bits having a same index in the first scrambling sequence.

[0230] As an embodiment, the second node device 410 comprises: a memory storing a computer readable program, the computer readable program, when executed by at least one processor, produces actions comprising: sending a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to generate a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer number of sequentially indexed bits greater than 1; receiving a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block comprising at least 1 control information bit, the second bit block comprising at least 1 control information bit; wherein the number of control information bits comprised by the first bit block is no more than 2; the sum of the number of control information bits comprised by the first bit block and the number of control information bits comprised by the second bit block is greater than 2; the priority index of the control information bits comprised by the first bit block is equal to a first level index, the priority index of the control information bits comprised by the second bit block is equal to a second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence comprising an integer number of sequentially indexed bits greater than 1; at least one placeholder bit is comprised in the first bit sequence, the non-placeholder bits comprised by the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index.

[0231] As an embodiment, the first node device 450 is a user equipment (UE).

[0232] As an embodiment, the first node device 450 is a user equipment supporting information multiplexing transmission associated to different priority levels.

[0233] As an embodiment, the second node device 410 is a base station device (gNB / eNB).

[0234] As an embodiment, the second node device 410 is a base station device supporting information multiplexing transmission associated to different priority levels.

[0235] As an embodiment, the receiver 456 (including the antenna 460), the receiving processor 452 and the controller / processor 490 are used to receive the first information block in the present application.

[0236] As an embodiment, the transmitter 456 (including the antenna 460) and the transmitting processor 455 are used to send the first PUCCH in the present application.

[0237] As an embodiment, the receiver 456 (including the antenna 460), the receive processor 452 and the controller / processor 490 are used to receive the second information block in the present application.

[0238] As an embodiment, the receiver 456 (including the antenna 460) and the receive processor 452 are used to receive the first signaling in the present application.

[0239] As an embodiment, the transmitter 416 (including the antenna 420), the transmit processor 415 and the controller / processor 440 are used to transmit the first information block in the present application.

[0240] As an embodiment, the receiver 416 (including the antenna 420) and the receive processor 412 are used to receive the first PUCCH in the present application.

[0241] As an embodiment, the transmitter 416 (including the antenna 420), the transmit processor 415 and the controller / processor 440 are used to transmit the second information block in the present application.

[0242] As an embodiment, the transmitter 416 (including the antenna 420) and the transmit processor 415 are used to transmit the first signaling in the present application.

[0243] Example 5

[0244] Embodiment 5 illustrates a flow chart of wireless signal transmission according to an embodiment of the present application, as shown in FIG. 5. In FIG. 5, the second node device N 500 is a serving cell of the first node device U 550, and the steps in the dashed box Optl represent optional steps. It is particularly pointed out that the sequence in the present example does not limit the sequence of signal transmission and implementation in the present application. Figure 5 As an embodiment, the transmitter 416 (including the antenna 420), the transmit processor 415 and the controller / processor 440 are used to transmit the second information block in the present application. Figure 5 As an embodiment, the transmitter 416 (including the antenna 420), the transmit processor 415 and the controller / processor 440 are used to transmit the second information block in the present application.

[0245] For the first node device U 550, in step S501, the first information block is transmitted, in step S502, the second information block is transmitted, in step S503, the first signaling is transmitted, and in step S504, the first PUCCH is received. Second node device N 500 For the first node device U 550, in step S551, the first information block is received, in step S552, the second information block is received, in step S553, the first signaling is received, and in step S554, the first PUCCH is transmitted.

[0246] First node device U 550 For the first node device U 550, in step S551, the first information block is received, in step S552, the second information block is received, in step S553, the first signaling is received, and in step S554, the first PUCCH is transmitted.

[0247] ​In Embodiment 5, the first information block is used to determine a first parameter value, the first parameter value is used to generate a first scrambling sequence, the first parameter value is a non-negative integer, the first scrambling sequence includes an integer number of sequentially indexed bits greater than 1; the first PUCCH is used to carry a first bit block and a second bit block, the first bit block includes at least 1 control information bit, the second bit block includes at least 1 control information bit; the number of control information bits included in the first bit block is no greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer number of sequentially indexed bits greater than 1; the first bit sequence includes at least one placeholder bit, the non-placeholder bits included in the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index; the second information block is used to determine X1 resource sets, X1 is a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH belongs to a target PUCCH resource, the target PUCCH resource is one PUCCH resource included in a target resource set; the target resource set is one of the X1 resource sets, a target number value is used to determine the target resource set from the X1 resource sets, the target number value is a positive integer; at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the target number value; when the target resource set includes more than 1 PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

[0248] As an embodiment, the second information block is transmitted through an air interface or a wireless interface.

[0249] As an embodiment, the second information block includes all or part of a high layer signaling or a physical layer signaling.

[0250] As an embodiment, the second information block includes all or part of a RRC (Radio Resource Control) layer signaling or a MAC (Medium Access Control) layer signaling.

[0251] As an embodiment, the second information block comprises all or part of a system information block (SIB).

[0252] As an embodiment, the second information block is cell specific or UE-specific.

[0253] As an embodiment, the second information block is per BWP configured.

[0254] As an embodiment, the second information block comprises all or part of fields of a DCI (Downlink Control Information) signaling.

[0255] As an embodiment, the second information block comprises a priority indication field in a DCI (Downlink Control Information) format.

[0256] As an embodiment, the first information block and the second information block are two different IEs in the same RRC layer signaling.

[0257] As an embodiment, the first information block and the second information block are two different fields in the same IE.

[0258] As an embodiment, the first information block and the second information block are two different fields in the same DCI format.

[0259] As an embodiment, the second information block comprises more than one sub-information block, and each sub-information block included in the first information block is an IE (Information Element) or a field in the RRC signaling to which the second information block belongs; one or more sub-information blocks included in the second information block are used to determine the X1 resource sets.

[0260] As an embodiment, the second information block comprises all or part of fields in an IE (Information Element) “PUCCH-Config” in an RRC signaling.

[0261] As an embodiment, the second information block comprises all or part of fields in an IE (Information Element) “PDSCH-Config” in an RRC signaling.

[0262] As an embodiment, the second information block comprises all or part of fields in an IE (Information Element) “PUCCH-ConfigCommon” in an RRC signaling.

[0263] As an embodiment, the second information block comprises all or part of fields in an IE (Information Element) “BWP-UplinkDedicated” in an RRC signaling.

[0264] As an embodiment, the second information block comprises all or part of fields in an IE (Information Element) “pucch-ConfigurationList” in an RRC signaling.

[0265] As an embodiment, the second information block comprises all or part of fields in a second “PUCCH-Config” IE in an IE (Information Element) “pucch-ConfigurationList” in an RRC signaling.

[0266] As an embodiment, the second information block comprises all or part of fields in a “PUCCH-Config” IE corresponding to a priority index of “1” in an IE (Information Element) “pucch-ConfigurationList” in an RRC signaling.

[0267] As an embodiment, the second information block comprises all or part of fields in a “PUCCH-Config” IE corresponding to a priority index of “0” in an IE (Information Element) “pucch-ConfigurationList” in an RRC signaling.

[0268] As an embodiment, the second information block comprises all or part of fields in a "PUCCH-Config" IE corresponding to a large priority index in an IE "pucch-ConfigurationList" in an RRC signaling.

[0269] As an embodiment, the second information block comprises all or part of fields in a "PUCCH-Config" IE corresponding to a small priority index in an IE "pucch-ConfigurationList" in an RRC signaling.

[0270] As an embodiment, the expression "the second information block is used to determine X1 resource sets" in the claims comprises the following meaning: the second information block is used by the first node device in the present application to determine the X1 resource sets.

[0271] As an embodiment, the expression "the second information block is used to determine X1 resource sets" in the claims comprises the following meaning: the second information block is used to explicitly or implicitly indicate the X1 resource sets.

[0272] As an embodiment, the expression "the second information block is used to determine X1 resource sets" in the claims comprises the following meaning: one or more fields included in the second information block are used to explicitly or implicitly indicate the X1 resource sets.

[0273] As an embodiment, the first signaling is transmitted through an air interface or a wireless interface.

[0274] As an embodiment, the first signaling comprises all or part of a high layer signaling or a physical layer signaling.

[0275] As an embodiment, the first signaling comprises all or part of an RRC (Radio Resource Control) layer signaling or a MAC (Medium Access Control) layer signaling.

[0276] As an embodiment, the first signaling is cell-specific (Cell Specific) or user equipment-specific (UE-specific).

[0277] As an embodiment, the first signaling is per BWP (Bandwidth Part) configured (Per BWP Configured).

[0278] As one embodiment, the first signaling comprises all or part of fields of a DCI (Downlink Control Information) signaling.

[0279] As one embodiment, the first signaling comprises a PRI (PUCCH Resource Indicator) field in a DCI (Downlink Control Information) format.

[0280] As one embodiment, the first signaling is carried by a PDCCH.

[0281] As one embodiment, the first signaling is carried by a latest PDCCH associated to the first PUCCH.

[0282] As one embodiment, the expression "the first signaling is used to determine the target PUCCH resource from the target resource set" in the claims comprises the following meaning: the first signaling is used by the first power saving device in the present application to determine the target PUCCH resource from the target resource set.

[0283] As one embodiment, the expression "the first signaling is used to determine the target PUCCH resource from the target resource set" in the claims comprises the following meaning: the first signaling is used to explicitly or implicitly indicate the target PUCCH resource from the target resource set.

[0284] As one embodiment, the expression "the first signaling is used to determine the target PUCCH resource from the target resource set" in the claims comprises the following meaning: the first signaling is used to explicitly or implicitly indicate an index or ID of the target PUCCH resource in the target resource set.

[0285] As one embodiment, the expression "the first signaling is used to determine the target PUCCH resource from the target resource set" in the claims comprises the following meaning: a PRI field carried by the first signaling and an index of a starting CCE (Control Channel Element) occupied by a PDCCH carrying the first signaling are used together to determine an index or ID of the target PUCCH resource in the target resource set.

[0286] Example 6

[0287] Embodiment 6 illustrates a diagram of the relationship between the first order and the first bit block according to one embodiment of the present application, as shown in FIG. 6. In FIG. 6, the first column from the left represents the modulation order, the second column from the left represents the number of control information bits, and the third column from the left represents whether there is a placeholder bit. The black rows represent the first order, the number of control information bits included in the first bit block, respectively. Figure 6 Figure 6

[0288] In Embodiment 6, the modulation order of the modulation scheme adopted by the first PUCCH in the present application is equal to the first order, and the first order is a positive integer greater than 1. The number of control information bits included in the first bit block in the present application is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit.

[0289] As one embodiment, the modulation scheme adopted by the first PUCCH is QPSK.

[0290] As one embodiment, the modulation scheme adopted by the first PUCCH is 16QAM.

[0291] As one embodiment, when the modulation scheme adopted by the first PUCCH is QPSK, the first order is equal to 2.

[0292] As one embodiment, when the modulation scheme adopted by the first PUCCH is 16QAM, the first order is equal to 4.

[0293] As one embodiment, the first order is equal to a positive integer power of 2.

[0294] As one embodiment, the first order is equal to one of 2, 4, 8, and 16.

[0295] As one embodiment, the expression "the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit" in the claims includes the following meaning: the number of control information bits included in the first bit block is less than the first order, which is used by the first node device in the present application to determine that the first bit sequence includes at least one placeholder bit.

[0296] As one embodiment, the expression "the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit" in the claims includes the following meaning: only when the number of control information bits included in the first bit block is less than the first order, the first bit sequence includes at least one placeholder bit. ​​

[0297] As one embodiment, the expression "the number of control information bits included in the first bit block is less than the first order number" in the claims includes the following meaning: when the number of control information bits included in the first bit block is greater than or equal to the first order number, the first bit sequence does not include any placeholder bit.

[0298] As one embodiment, the expression "the number of control information bits included in the first bit block is less than the first order number" in the claims includes the following meaning: when the number of control information bits included in the first bit block is less than the first order number, the first bit sequence includes at least one placeholder bit; when the number of control information bits included in the first bit block is greater than or equal to the first order number, the first bit sequence does not include any placeholder bit.

[0299] As one embodiment, the expression "the number of control information bits included in the first bit block is less than the first order number" in the claims includes the following meaning: the number of control information bits included in the first bit block is less than the first order number.

[0300] Example 7

[0301] Embodiment 7 illustrates a schematic diagram of the relationship between the first bit and the second bit according to one embodiment of the present application, as shown in FIG. 7. Figure 7 In FIG. 7, each small square represents a bit, each cross-line filled small square represents a placeholder bit in the first bit sequence, each diagonal-line filled small square represents a first bit, each dot-filled small square represents a second bit, and each arrow represents that the bit values are equal. Figure 7

[0302] In embodiment 7, the first bit sequence in the present application and the first scrambling sequence in the present application are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 sequentially indexed bits, the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of a placeholder bit included in the first bit sequence, the bit at the index equal to the first index included in the first output sequence is a first bit, the second bit is a bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, the bit value of the first bit and the bit value of the second bit are equal. ​

[0303] As one embodiment, the first output sequence is a bit sequence obtained after scrambling the first bit sequence.

[0304] As one embodiment, the first output sequence is used to generate the first PUCCH.

[0305] As one embodiment, the first output sequence is used to generate the first PUCCH.

[0306] As one embodiment, the first output sequence is used to generate the first PUCCH.

[0307] As one embodiment, the first output sequence is used to generate the first PUCCH.

[0308] As one embodiment, the first output sequence is used to generate the first PUCCH.

[0309] As an embodiment, the expression "the first bit sequence and the first scrambling sequence are used together to generate the first output sequence" in the claims includes the following meaning: the first bit sequence and the first scrambling sequence are used together by the first node device in the present application to generate the first output sequence.

[0310] As an embodiment, the expression "the first bit sequence and the first scrambling sequence are used together to generate the first output sequence" in the claims includes the following meaning: the first bit sequence and the first scrambling sequence are used together to generate the first output sequence.

[0311] As an embodiment, the expression "the first bit sequence and the first scrambling sequence are used together to generate the first output sequence" in the claims includes the following meaning: the first bit sequence and the first scrambling sequence are used together to generate the first output sequence.

[0312] As an embodiment, the first index is the index of a placeholder bit included in the first bit sequence in the first bit sequence.

[0313] As an embodiment, the first index can be the index of any placeholder bit included in the first bit sequence in the first bit sequence.

[0314] As an embodiment, the index of the first bit in the first output sequence is equal to the first index.

[0315] As an embodiment, the first bit is the bit of a corresponding placeholder bit in the first output sequence.

[0316] As an embodiment, the second bit is the bit of a corresponding non-placeholder bit in the first output sequence.

[0317] As an embodiment, the bit value of the second bit is equal to the result of the logical AND between the bit value of a bit included in the first bit sequence and the bit value of a bit included in the first scrambling sequence.

[0318] As an embodiment, the second bit is equal to the result of the logical AND between the bit value of a bit included in the first bit sequence and the bit value of a bit included in the first scrambling sequence.

[0319] As an example, the statement "the second index and the first index are two adjacent indices" in the claim includes the following meaning: the second index is equal to the first index minus 1.

[0320] As an example, the statement "the second index and the first index are two adjacent indices" in the claim includes the following meaning: the second index is equal to the first index plus 1.

[0321] As an example, the statement "the second index and the first index are two adjacent indices" in the claim includes the following meaning: the second index and the first index are the indices of two adjacent bits in the first output sequence.

[0322] As an example, the statement "the second index and the first index are two adjacent indexes" in the claim includes the following meaning: the second index is an index that precedes the first index.

[0323] As an example, the statement "the second index and the first index are two adjacent indexes" in the claim includes the following meaning: the second index is an index that is later than the first index.

[0324] Example 8

[0325] Example 8 illustrates a schematic diagram of the relationship between a target quantity value and a target resource set according to an embodiment of this application, as shown in the attached diagram. Figure 8 As shown. In the appendix Figure 8 In the diagram, the horizontal axis represents time, the vertical axis represents frequency, each rectangle represents one PUCCH resource included in the X1 resource sets, each rectangle filled with diagonal lines represents one PUCCH resource included in the target resource set, and each line end on the right represents a numerical range, with the target quantity value belonging to a numerical range.

[0326] In embodiment 8, the second information block in this application is used to determine X1 resource sets, where X1 is a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH in this application belongs to a target PUCCH resource, and the target PUCCH resource is a PUCCH resource included in the target resource set; the target resource set is one of the X1 resource sets, and a target quantity value is used to determine the target resource set from the X1 resource sets, where the target quantity value is a positive integer; at least one of the number of control information bits included in the first bit block in this application or the number of control information bits included in the second bit block in this application is used to determine the target quantity value.

[0327] As one embodiment, any one of the X1 resource sets is a PUCCH resource set (PUCCH resource set).

[0328] As one embodiment, any one of the X1 resource sets includes any one PUCCH resource (PUCCH Resource) including at least one of frequency domain resource, time domain resource, code domain resource.

[0329] As one embodiment, any one of the X1 resource sets includes any one PUCCH resource (PUCCH Resource) including at least one of frequency domain resource, time domain resource, sequence resource.

[0330] As one embodiment, the resource occupied by the first PUCCH is the target PUCCH resource.

[0331] As one embodiment, the resource occupied by the first PUCCH is part of the target PUCCH resource.

[0332] As one embodiment, the target PUCCH resource only includes the resource occupied by the first PUCCH.

[0333] As one embodiment, the target PUCCH resource further includes resources other than the resource occupied by the first PUCCH.

[0334] As one embodiment, the resource occupied by the first PUCCH includes at least one of frequency domain resource, time domain resource, code domain resource.

[0335] As one embodiment, the resource occupied by the first PUCCH includes at least one of frequency domain resource, time domain resource, sequence resource.

[0336] As one embodiment, the expression "the target quantity value is used to determine the target resource set from the X1 resource sets" in the claim includes the following meanings: the target quantity value is used by the first node device in this application to determine the target resource set from the X1 resource sets.

[0337] As one embodiment, the expression "the target quantity value is used to determine the target resource set from the X1 resource sets" in the claim includes the following meanings: the target quantity value is used to determine the target resource set from the X1 resource sets according to the corresponding relationship.

[0338] As one embodiment, the expression "the target quantity value is used to determine the target resource set from the X1 resource sets" in a claim comprises the following meaning: the target quantity value is used to determine the target resource set from the X1 resource sets according to a mapping relationship.

[0339] As one embodiment, the expression "the target quantity value is used to determine the target resource set from the X1 resource sets" in a claim comprises the following meaning: the X1 resource sets respectively correspond to X1 value intervals, the target quantity value belongs to a target value interval, the target value interval is one of the X1 value intervals, and the target resource set is a resource set corresponding to the target value interval among the X1 resource sets. As one subembodiment of the above embodiment, the X1 value intervals are configurable. As one subembodiment of the above embodiment, the X1 value intervals are predefined. As one subembodiment of the above embodiment, the X1 value intervals are configured by one or more fields included in the second information block.

[0340] As one embodiment, the expression "at least one of the quantity of control information bits included in the first bit block or the quantity of control information bits included in the second bit block is used to determine the target quantity value" in a claim comprises the following meaning: at least one of the quantity of control information bits included in the first bit block or the quantity of control information bits included in the second bit block is used by the first node device in the present application to determine the target quantity value.

[0341] As one embodiment, the expression "at least one of the quantity of control information bits included in the first bit block or the quantity of control information bits included in the second bit block is used to determine the target quantity value" in a claim comprises the following meaning: the quantity of control information bits included in the first bit block is used to determine the target quantity value.

[0342] As one embodiment, the expression "at least one of the quantity of control information bits included in the first bit block or the quantity of control information bits included in the second bit block is used to determine the target quantity value" in a claim comprises the following meaning: the quantity of control information bits included in the second bit block is used to determine the target quantity value.

[0343] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: both the number of control information bits comprised by the first bit block and the number of control information bits comprised by the second bit block are used for determining the target number value.

[0344] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: the target number value is equal to the number of control information bits comprised by the first bit block.

[0345] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: the target number value is equal to the number of control information bits comprised by the second bit block.

[0346] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: the target number value is equal to the sum of the number of control information bits comprised by the first bit block and the number of control information bits comprised by the second bit block.

[0347] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: the target number value is equal to the number of control information bits comprised by the bit block with the higher priority index among the first bit block and the second bit block.

[0348] As one embodiment, the expression "at least one of the number of control information bits comprised by the first bit block or the number of control information bits comprised by the second bit block is used for determining the target number value" in a claim comprises the following meaning: the second bit block is used for generating a fourth bit block, and the target number value is equal to the sum of the number of control information bits comprised by the first bit block and the number of bits comprised by the fourth bit block.

[0349] As one embodiment, the expression "at least one of the number of control information bits comprised in the first bit block, or the number of control information bits comprised in the second bit block is used to determine the target number value" in the claims comprises the following meaning: the second bit block is used to generate a fourth bit block, the number of control information bits comprised in the second bit block is used to determine the number of bits comprised in the fourth bit block, the target number value is equal to the sum of the number of control information bits comprised in the first bit block and the number of bits comprised in the fourth bit block.

[0350] As one embodiment, the expression "at least one of the number of control information bits comprised in the first bit block, or the number of control information bits comprised in the second bit block is used to determine the target number value" in the claims comprises the following meaning: the second bit block is used to generate a fourth bit block, the number of control information bits comprised in the second bit block is used to determine the number of bits comprised in the fourth bit block, the target number value is equal to the sum of the number of control information bits comprised in the first bit block and the number of bits comprised in the fourth bit block.

[0351] Example 9

[0352] Embodiment 9 illustrates a diagram of the relationship between the target number value and the second level index according to one embodiment of the present application, as shown in FIG. 9. In FIG. 9, starting from 901, in 902 whether the second level index is equal to "1", in 903 the number of control information bits comprised in the second bit block is used to determine the target number value, in 904 a value other than the number of control information bits comprised in the second bit block is used to determine the target number value. Figure 9 Figure 9

[0353] In embodiment 9, whether the number of control information bits comprised in the second bit block in the present application is used to determine the target number value in the present application is related to the second level index in the present application.

[0354] As one embodiment, the expression "whether the number of control information bits comprised in the second bit block is used to determine the target number value and the second level index" in the claims comprises the following meaning: when the second level index is equal to 1, the number of control information bits comprised in the second bit block is used to determine the target number value; when the second level index is equal to 0, the number of control information bits comprised in the second bit block is not used to determine the target number value.

[0355] ​​As one embodiment, the expression "whether the number of control information bits included in the second block of bits is used to determine the target number value and the second level index" in a claim comprises the following meaning: when the second level index is equal to 0, the number of control information bits included in the second block of bits is used to determine the target number value; when the second level index is equal to 1, the number of control information bits included in the second block of bits is not used to determine the target number value.

[0356] As one embodiment, the expression "whether the number of control information bits included in the second block of bits is used to determine the target number value and the second level index" in a claim comprises the following meaning: when the second level index is greater than the first level index, the number of control information bits included in the second block of bits is used to determine the target number value; when the second level index is less than the first level index, the number of control information bits included in the second block of bits is not used to determine the target number value.

[0357] As one embodiment, the expression "whether the number of control information bits included in the second block of bits is used to determine the target number value and the second level index" in a claim comprises the following meaning: when the second level index is less than the first level index, the number of control information bits included in the second block of bits is used to determine the target number value; when the second level index is greater than the first level index, the number of control information bits included in the second block of bits is not used to determine the target number value.

[0358] As one embodiment, the expression "whether the number of control information bits included in the second block of bits is used to determine the target number value and the second level index" in a claim comprises the following meaning: when the second level index is equal to 1, the number of control information bits included in the second block of bits is used to determine the target number value; when the second level index is equal to 0 and the number of control information bits included in the second block of bits is greater than a first threshold, the first threshold is used to determine the target number value. As one dependent embodiment of the above embodiment, the first threshold is configurable. As one dependent embodiment of the above embodiment, the first threshold is predefined.

[0359] As an embodiment, the expression "whether the number of control information bits included in the second bit block is used to determine the target number value and the second level index" in the claims includes the following meanings: when the second level index is equal to 1, the number of control information bits included in the second bit block is used to determine the target number value; when the second level index is equal to 0 and the number of control information bits included in the second bit block is greater than a first threshold value, the first threshold value is used to determine the target number value; when the second level index is equal to 0 and the number of control information bits included in the second bit block is not greater than the first threshold value, the number of control information bits included in the second bit block is used to determine the target number value. As an embodiment of the above embodiment, the first threshold value is configurable. As an embodiment of the above embodiment, the first threshold value is predefined.

[0360] As an embodiment, the expression "whether the number of control information bits included in the second bit block is used to determine the target number value and the second level index" in the claims includes the following meanings: when the second level index is equal to 1, the target number value is equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block; when the second level index is equal to 0 and the number of control information bits included in the second bit block is greater than a first threshold value, the target number value is equal to the sum of the number of control information bits included in the first bit block and the first threshold value; when the second level index is equal to 0 and the number of control information bits included in the second bit block is not greater than the first threshold value, the target number value is equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block. As an embodiment of the above embodiment, the first threshold value is configurable. As an embodiment of the above embodiment, the first threshold value is predefined.

[0361] Example 10

[0362] Embodiment 10 illustrates a schematic diagram of the first number value according to an embodiment of the present application, as shown in FIG. 10. In FIG. 10, each rectangular box represents a variable or state, and the arrow represents a determination relationship. Figure 10 Figure 10

[0363] ​​In Embodiment 10, the second information block in the present application is used to determine a first code rate, the first code rate is a non-negative number; the first PUCCH in the present application occupies a first number of physical resource blocks in the frequency domain; the first code rate is used to determine the first number, the first bit sequence in the present application includes a number of bits proportional to the first number; and the type of UCI carried by the first PUCCH is used to determine the first code rate.

[0364] As an embodiment, the expression "the second information block is used to determine a first code rate" in the claims includes the following meaning: the second information block is used by the first node device in the present application to determine the first code rate.

[0365] As an embodiment, the expression "the second information block is used to determine a first code rate" in the claims includes the following meaning: the second information block is used to explicitly or implicitly indicate the first code rate.

[0366] As an embodiment, the expression "the second information block is used to determine a first code rate" in the claims includes the following meaning: one or more fields included in the second information block are used to explicitly or implicitly indicate the first code rate.

[0367] As an embodiment, the first code rate is a configured maximum PUCCH code rate.

[0368] As an embodiment, the first code rate is the code rate of the first bit block when rate matching.

[0369] As an embodiment, the first code rate is the expected code rate of the first bit block when rate matching.

[0370] As an embodiment, the first code rate is the code rate of the second bit block when rate matching.

[0371] As an embodiment, the first code rate is the expected code rate of the second bit block when rate matching.

[0372] As an embodiment, the first number is a positive integer.

[0373] As an embodiment, the first number is not greater than the number of physical resource blocks (PRBs) included in the target PUCCH resource in the present application in the frequency domain.

[0374] As one embodiment, the first PUCCH occupies a number of physical resource blocks in the frequency domain equal to the first number value in one OFDM symbol.

[0375] As one embodiment, the first PUCCH occupies a number of physical resource blocks in the frequency domain equal to the first number value in one hop.

[0376] As one embodiment, the expression "the first code rate is used to determine the first number value" in the claim includes the following meaning: the first code rate is used by the first node device in the present application to determine the first number value.

[0377] As one embodiment, the expression "the first code rate is used to determine the first number value" in the claim includes the following meaning: the first code rate is used to calculate the first number value.

[0378] As one embodiment, the expression "the first code rate is used to determine the first number value" in the claim includes the following meaning: the first code rate and a characteristic number value are used together to calculate the first number value, at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the characteristic number value, and the characteristic number value is a positive integer.

[0379] As one embodiment, the expression "the first code rate is used to determine the first number value" in the claim includes the following meaning: the first code rate and a characteristic number value are used together to calculate the first number value, at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the characteristic number value, and the characteristic number value is a positive integer; when the number of information bits is equal to the characteristic number value, the first number value is equal to the smallest number of physical resource blocks that satisfy the rate matching after the code rate is not greater than the first code rate.

[0380] As one embodiment, the number of bits included in the first bit sequence is also in a positive proportional relationship with the number of OFDM symbols occupied by the first PUCCH.

[0381] As one embodiment, the number of bits included in the first bit sequence is also in a positive proportional relationship with the number of OFDM symbols (excluding OFDM symbols occupied by reference signals) occupied by the first PUCCH.

[0382] As one embodiment, the number of bits included in the first bit sequence is also in direct proportion to the number of OFDM symbols (including OFDM symbols occupied by reference signals) occupied by the first PUCCH.

[0383] As one embodiment, the number of bits included in the first bit sequence is also in inverse proportion to the spreading factor adopted by the first PUCCH.

[0384] As one embodiment, the number of bits included in the first bit sequence is equal to the result calculated by the following formula:

[0385]

[0386] wherein, represents the first quantity value, represents the number of OFDM symbols occupied by the first PUCCH, represents the spreading factor of the first PUCCH.

[0387] As one embodiment, the number of bits included in the first bit sequence is equal to the result calculated by the following formula:

[0388]

[0389] wherein, represents the first quantity value, represents the number of OFDM symbols (excluding OFDM symbols occupied by reference signals) occupied by the first PUCCH, represents the spreading factor of the first PUCCH.

[0390] As one embodiment, the number of bits included in the first bit sequence is equal to the result calculated by the following formula:

[0391]

[0392] wherein, represents the first quantity value, represents the number of OFDM symbols (excluding OFDM symbols occupied by reference signals) occupied by the first PUCCH, represents the spreading factor of the first PUCCH.

[0393] As one embodiment, the first code rate equals to one of X2 alternative code rates, X2 is a positive integer greater than 1; a specific code rate equals to a predefined one of the X2 alternative code rates, the first code rate and the specific code rate are not equal are used to determine that the first bit block and the second bit block are jointly used to generate the first PUCCH.

[0394] As one embodiment, the type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type is UCI including CSI, the second UCI type is UCI not including CSI.

[0395] As one embodiment, the type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type is UCI including control information of different priorities, the second UCI type is UCI including only control information of same priority.

[0396] As one embodiment, the type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type is UCI including HARQ-ACK of different priorities, the second UCI type is UCI including only HARQ-ACK of same priority or HARQ-ACK of same priority and CSI of same priority.

[0397] As one embodiment, the type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type is UCI including HARQ-ACK of different priorities, the second UCI type is a UCI type other than the first UCI type.

[0398] As one embodiment, the expression "the type of UCI carried by the first PUCCH is used to determine the first code rate" in the claims includes the following meaning: the type of UCI carried by the first PUCCH is used by the first node device in the present application to determine the first code rate.

[0399] As an embodiment, the expression "a type of UCI carried by the first PUCCH is used to determine the first code rate" in the claims includes the following implications: the first code rate is equal to one of two alternative code rates, the two alternative code rates respectively correspond to a first UCI type and a second UCI type, the type of UCI carried by the first PUCCH is one of the first UCI type and the second UCI type; the first code rate is equal to the alternative code rate of the two alternative code rates and corresponds to the type of UCI carried by the first PUCCH. As an embodiment of the above embodiment, the first UCI type is UCI including CSI, and the second UCI type is UCI not including CSI. As an embodiment of the above embodiment, the first UCI type is UCI including control information of different priorities, and the second UCI type is UCI including only control information of the same priority. As an embodiment of the above embodiment, the first UCI type is UCI including HARQ-ACK of different priorities, and the second UCI type is UCI including only HARQ-ACK of the same priority or HARQ-ACK of the same priority and CSI of the same priority. As an embodiment of the above embodiment, the first UCI type is UCI including HARQ-ACK of different priorities, and the second UCI type is a UCI type other than the first UCI type. As an embodiment of the above embodiment, the two alternative code rates are configurable. As an embodiment of the above embodiment, the two alternative code rates are predefined. As an embodiment of the above embodiment, the two alternative code rates are both configured by the second information block.

[0400] Example 11

[0401] Embodiment 11 illustrates a structural block diagram of a processing device in a first node device of an embodiment, as shown in FIG. 11. In FIG. 11, the first node device processing device 1100 includes a first receiver 1101 and a first transmitter 1102. The first receiver 1101 includes the transmitter / receiver 456 (including the antenna 460), the reception processor 452, and the controller / processor 490 in the first node device 1000 in the present application; the first transmitter 1102 includes the transmitter / receiver 456 (including the antenna 460) and the transmission processor 455 in the first node device 1000 in the present application. Figure 11 Figure 11 Figure 4 Figure 4

[0402] ​​​​In embodiment 11, the first receiver 1101 receives a first information block, the first information block is used to determine a first parameter value, the first parameter value is used to generate a first scrambling sequence, the first parameter value is a non-negative integer, the first scrambling sequence includes an integer greater than 1 sequentially indexed bits; the first transmitter 1102 sends the first PUCCH, the first PUCCH is used to carry the first bit block and the second bit block, the first bit block includes at least 1 control information bit, the second bit block includes at least 1 control information bit; wherein, the number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to the first level index, the priority index of the control information bits included in the second bit block is equal to the second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 sequentially indexed bits; the first bit sequence includes at least one placeholder bit, the non-placeholder bits included in the first bit sequence are scrambled by the bits with the same index in the first scrambling sequence.

[0403] As an embodiment, the modulation order of the modulation mode adopted by the first PUCCH is equal to the first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit.

[0404] As an embodiment, the first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 sequentially indexed bits, the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of one placeholder bit included in the first bit sequence, the bit included in the first output sequence whose index is equal to the first index is the first bit, the second bit is one bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, the bit value of the first bit and the bit value of the second bit are equal.

[0405] As an embodiment, a first receiver 1101 receives a second information block; wherein, the second information block is used to determine X1 resource sets, where X1 is a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH belongs to a target PUCCH resource, and the target PUCCH resource is a PUCCH resource included in the target resource set; the target resource set is one of the X1 resource sets, and a target quantity value is used to determine the target resource set from the X1 resource sets, where the target quantity value is a positive integer; at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the target quantity value.

[0406] As one embodiment, the first receiver 1101 receives a first signaling; wherein, when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

[0407] As one embodiment, the number of control information bits included in the second bit block is used to determine the target quantity value and the second level index.

[0408] As an example, the second information block is used to determine a first code rate, which is a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain is equal to a first quantity value; the first code rate is used to determine the first quantity value, and the number of bits included in the first bit sequence is proportional to the first quantity value; the type of UCI carried by the first PUCCH is used to determine the first code rate.

[0409] Example 12

[0410] Example 12 illustrates a structural block diagram of a processing device in a second node device according to an embodiment, as shown in the attached diagram. Figure 12 As shown. In the appendix Figure 12 In the second node device processing unit 1200, there are a second transmitter 1201 and a second receiver 1202. The second transmitter 1201 includes the components specified in the appendix of this application. Figure 4 The transmitter / receiver 416 (including antenna 460), the transmitter processor 415, and the controller / processor 440 are included; the second receiver 1202 includes the appendix to this application. Figure 4 The transmitter / receiver 416 (including antenna 460) and receiver processor 412 are included.

[0411] In embodiment 12, the second transmitter 1201 sends a first information block, sends the first information block, the first information block is used to indicate a first parameter value, the first parameter value is used to generate a first scrambling sequence, the first parameter value is a non-negative integer, the first scrambling sequence includes an integer greater than 1 sequentially indexed bits; the second receiver 1202 receives the first PUCCH, the first PUCCH is used to carry the first bit block and the second bit block, the first bit block includes at least 1 control information bit, the second bit block includes at least 1 control information bit; wherein, the number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to the first level index, the priority index of the control information bits included in the second bit block is equal to the second level index, the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by the bits with the same index in the first scrambling sequence. The second receiver 1202 receives the first PUCCH,

[0412] As an embodiment, the modulation order of the modulation mode adopted by the first PUCCH is equal to the first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order is used to determine that the first bit sequence includes at least one placeholder bit.

[0413] As an embodiment, the first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 sequentially indexed bits, the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of one placeholder bit included in the first bit sequence, the bit included in the first output sequence whose index is equal to the first index is the first bit, the second bit is one bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, the bit value of the first bit and the bit value of the second bit are equal.

[0414] As one embodiment, the second transmitter 1201 transmits a second information block; wherein the second information block is used to determine X1 resource sets, X1 is a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the first PUCCH occupies a target PUCCH resource, the target PUCCH resource is one PUCCH resource included in a target resource set; the target resource set is one of the X1 resource sets, a target quantity value is used to determine the target resource set from the X1 resource sets, the target quantity value is a positive integer; at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the target quantity value.

[0415] As one embodiment, the second transmitter 1201 transmits a first signaling; wherein when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

[0416] As one embodiment, whether the number of control information bits included in the second bit block is used to determine the target quantity value is related to the second rank index.

[0417] As one embodiment, the second information block is used to determine a first code rate, the first code rate is a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain is equal to a first quantity value; the first code rate is used to determine the first quantity value, the number of bits included in the first bit sequence is in a positive proportional relationship with the first quantity value; the type of UCI carried by the first PUCCH is used to determine the first code rate.

[0418] Those skilled in the art can understand that all or part of the steps in the foregoing method can be instructed by a program to the relevant hardware, and the program can be stored in a computer readable storage medium, such as a read-only memory, a hard disk, an optical disk or the like. Alternatively, all or part of the steps of the foregoing embodiments can also be implemented using one or more integrated circuits. Correspondingly, each module unit in the foregoing embodiments can be implemented in the form of hardware or in the form of a software function module, and the present application is not limited to any specific form of combination of software and hardware. The first node device or the second node device or the UE or the terminal in the present application includes but is not limited to a mobile phone, a tablet computer, a notebook computer, a network card, a low-power device, an eMTC device, an NB-IoT device, a vehicle-mounted communication device, a flying vehicle, an airplane, a drone, a remote control airplane, a test device, a test equipment, a test instrument, and the like. The base station device or the base station or the network side device in the present application includes but is not limited to a macro cellular base station, a micro cellular base station, a home base station, a relay base station, an eNB, a gNB, a transmission reception point TRP, a relay satellite, a satellite base station, an air base station, a test device, a test equipment, a test instrument, and the like.

[0419] The above only describes the preferred embodiments of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A first node device for wireless communication, the first node device comprising: Comprising: a first receiver, receiving a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to calculate a first initial value, the first initial value being used to initialize a generator of a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence comprising an integer number of sequentially indexed bits greater than 1; a first transmitter, transmitting a first PUCCH, the first PUCCH being used to carry a first block of bits and a second block of bits, the first block of bits comprising at least 1 control information bit, the second block of bits comprising at least 1 control information bit, the first PUCCH adopting PUCCH format 2 or 3 or 4; wherein, the first block of bits comprises no more than 2 control information bits; the sum of the number of control information bits comprised by the first block of bits and the number of control information bits comprised by the second block of bits is greater than 2; the priority index of the control information bits comprised by the first block of bits is equal to a first index, the priority index of the control information bits comprised by the second block of bits is equal to a second index, the first index and the second index are not equal; the first block of bits and the second block of bits are collectively used to generate a first bit sequence, the first bit sequence comprising an integer number of sequentially indexed bits greater than 1; the first bit sequence comprises at least one placeholder bit, the non-placeholder bits comprised by the first bit sequence are scrambled by the bits in the first scrambling sequence having the same index; the C-RNTI configured for the transmitter of the first PUCCH is also used to calculate the first initial value, the priority index associated with the first PUCCH is equal to the larger index between the first index and the second index when compared.

2. The first node device of claim 1, wherein, the modulation order of the modulation scheme adopted by the first PUCCH is equal to a first order, the first order being a positive integer greater than 1; the number of control information bits comprised by the first block of bits is less than the first order, which is used to determine that the first bit sequence comprises at least one placeholder bit; the modulation scheme adopted by the first PUCCH is QPSK, and the first order is equal to 2.

3. The first node device of claim 1 or 2, wherein, the first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence comprising a positive integer number of sequentially indexed bits greater than 1, the number of bits comprised by the first output sequence being equal to the number of bits comprised by the first bit sequence; a first index is the index of one placeholder bit comprised by the first bit sequence, the bit at the index equal to the first index comprised by the first output sequence is a first bit, a second bit is one bit comprised by the first output sequence, a second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, the bit value of the first bit and the bit value of the second bit are equal.

4. The first node device of claim 3, wherein, The bit value of the second bit is equal to the result of logical AND between the bit value of one bit included in the first bit sequence and the bit value of one bit included in the first scrambling sequence, and the second index is equal to the first index minus 1.

5. The first node device of claim 1, wherein, The first receiver receives a second information block; wherein the second information block is used to determine X1 resource sets, X1 being a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the first PUCCH occupies a target PUCCH resource, the target PUCCH resource being one PUCCH resource included in a target resource set, the target resource set being one of the X1 resource sets, a target quantity value being used to determine the target resource set from the X1 resource sets, the target quantity value being a positive integer; the target quantity value being equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block.

6. The first node device of claim 5, wherein, The second information block includes all or part of the fields in the information unit "PUCCH-Config" in an RRC signaling.

7. The first node device of claim 5, wherein, The X1 resource sets correspond to X1 value intervals respectively, the target quantity value belongs to a target value interval, the target value interval being one of the X1 value intervals, the target resource set being the resource set corresponding to the target value interval among the X1 resource sets; the X1 value intervals being configured by one or more fields included in the second information block.

8. The first node device of claim 5, wherein, The first receiver receives a first signaling; wherein when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

9. The first node device of claim 8, wherein, The first signaling includes a PUCCH resource indication field in a DCI format, and the first signaling is carried by the latest PDCCH associated with the first PUCCH.

10. The first node device of claim 8, wherein, The PUCCH resource indication field carried by the first signaling and the index of the starting CCE occupied by the PDCCH carrying the first signaling are used together to determine the index or ID of the target PUCCH resource in the target resource set.

11. The first node device of claim 5, wherein, The second information block is used to determine a first code rate, the first code rate being a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain being equal to a first quantity value; The first code rate is used to determine the first quantity value, the number of bits included in the first bit sequence being in a positive proportional relationship with the first quantity value; the type of UCI carried by the first PUCCH being used to determine the first code rate.

12. The first node device of claim 11, wherein, The first quantity value is not greater than the number of physical resource blocks included in the target PUCCH resource in the frequency domain; and the first code rate is the maximum PUCCH code rate configured.

13. The first node device of claim 11, wherein, The first code rate and the feature quantity value are used together to calculate the first quantity value, at least one of a quantity of control information bits included in the first bit block or a quantity of control information bits included in the second bit block is used to determine the feature quantity value, and the feature quantity value is a positive integer.

14. The first node device of claim 11, wherein, The quantity of bits included in the first bit sequence is also in a positive proportional relationship with a quantity of OFDM symbols occupied by the first PUCCH, and the quantity of bits included in the first bit sequence is also in an inverse proportional relationship with a spreading factor adopted by the first PUCCH.

15. The first node device of claim 11, wherein, The type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type is UCI including control information of different priorities, and the second UCI type is UCI including only control information of the same priority.

16. The first node device of claim 1, wherein, The first bit sequence and the first scrambling sequence are used together to sequentially undergo scrambling, modulation, spreading, mapping to a physical resource, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH, or the first bit sequence and the first scrambling sequence are used together to sequentially undergo scrambling, modulation, block spreading, transform precoding, mapping to a physical resource, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH.

17. The first node device of claim 1, wherein, A priority index of a control information bit included in the first bit block is a value of a priority indication carried by a PDCCH to which the control information bit included in the first bit block is associated, and a priority index of a control information bit included in the second bit block is a value of a priority indication carried by a PDCCH to which the control information bit included in the second bit block is associated.

18. The first node device of claim 1, wherein, The first bit block includes only HARQ-ACK bits, the first bit block sequentially undergoes channel coding and rate matching to generate a first target bit sequence, the second bit block sequentially undergoes channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

19. The first node device of claim 1, wherein, The placeholder bit is a bit used to maximize a Euclidean distance, and any one non-placeholder bit included in the first bit sequence is scrambled by a bit having a same index in the first scrambling sequence. 20.A second node device for wireless communication, comprising: Comprise: a second transmitter that transmits a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to calculate a first initial value, the first initial value being used to initialize a generator of a first scrambling sequence, the first parameter value being a non-negative integer, and the first scrambling sequence including an integer number of sequentially indexed bits greater than 1; a second receiver that receives a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block including at least one control information bit, the second bit block including at least one control information bit, and the first PUCCH adopting a PUCCH format 2 or 3 or 4; and The number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having the same index; the C-RNTI configured for the sender of the first PUCCH is also used to calculate the first initial value, and the priority index associated with the first PUCCH is equal to the larger level index compared between the first level index and the second level index.

21. The second node device of claim 20, wherein, The modulation order of the modulation mode used by the first PUCCH is equal to a first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit; the modulation mode used by the first PUCCH is QPSK, and the first order is equal to 2.

22. The second node device of claim 20 or 21, wherein, The first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 of sequentially indexed bits, and the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of a placeholder bit included in the first bit sequence, the bit included in the first output sequence whose index is equal to the first index is a first bit, the second bit is a bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, and the bit value of the first bit is equal to the bit value of the second bit.

23. The second node device of claim 22, wherein, The bit value of the second bit is equal to the result of the logical AND between the bit value of a bit included in the first bit sequence and the bit value of a bit included in the first scrambling sequence, and the second index is equal to the first index minus 1.

24. The second node device of claim 20, wherein, The second transmitter transmits a second information block; wherein the second information block is used to determine X1 resource sets, X1 is a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH belongs to a target PUCCH resource, the target PUCCH resource is one PUCCH resource included in a target resource set; the target resource set is one of the X1 resource sets, a target quantity value is used to determine the target resource set from the X1 resource sets, the target quantity value is a positive integer; the target quantity value is equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block.

25. The second node device of claim 24, wherein, The second information block includes all or part of the domains in the information unit "PUCCH-Config" in the RRC signaling.

26. The second node device of claim 24, wherein, The X1 resource sets correspond to X1 value intervals respectively, the target quantity value belongs to a target value interval, the target value interval is one of the X1 value intervals, and the target resource set is the resource set corresponding to the target value interval in the X1 resource sets; the X1 value intervals are configured by one or more domains included in the second information block.

27. The second node device of claim 24, wherein, The second transmitter transmits a first signaling; wherein when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

28. The second node device of claim 27, wherein, The first signaling includes a PUCCH resource indication domain in a DCI format, and the first signaling is carried by the latest PDCCH associated with the first PUCCH.

29. The second node device of claim 27, wherein, The PUCCH resource indication domain carried by the first signaling and the index of the starting CCE occupied by the PDCCH carrying the first signaling are used together to determine the index or ID of the target PUCCH resource in the target resource set.

30. The second node device of claim 24, wherein, The second information block is used to determine a first code rate, the first code rate is a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain is equal to a first quantity value; The first code rate is used to determine the first quantity value, and the number of bits included in the first bit sequence is in a proportional relationship with the first quantity value; the type of UCI carried by the first PUCCH is used to determine the first code rate.

31. The second node device of claim 30, wherein, The first quantity value is not greater than the number of physical resource blocks included in the target PUCCH resource in the frequency domain; and the first code rate is the maximum PUCCH code rate configured.

32. The second node device of claim 30, wherein, The first code rate and a feature quantity value are used together to calculate the first quantity value, at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block is used to determine the feature quantity value, and the feature quantity value is a positive integer.

33. The second node device of claim 30, wherein, The number of bits included in the first bit sequence is also in a positive proportional relationship with the number of OFDM symbols occupied by the first PUCCH; and the number of bits included in the first bit sequence is also in an inverse proportional relationship with a spreading factor adopted by the first PUCCH.

34. The second node device of claim 30, wherein, The type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type being UCI including control information of different priorities, and the second UCI type being UCI including only control information of the same priority.

35. The second node device of claim 20, wherein, The first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, spreading, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH, or the first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, block spreading, transform precoding, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH.

36. The second node device of claim 20, wherein, The priority index of the control information bits included in the first bit block is a value of a priority indication carried by a PDCCH to which the control information bits included in the first bit block are associated; and the priority index of the control information bits included in the second bit block is a value of a priority indication carried by a PDCCH to which the control information bits included in the second bit block are associated.

37. The second node device of claim 20, wherein, The first bit block only includes HARQ-ACK bits; the first bit block sequentially undergoes channel coding and rate matching to generate a first target bit sequence, and the second bit block sequentially undergoes channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

38. The second node device of claim 20, wherein, The placeholder bit is a bit used to maximize the Euclidean distance, and any non-placeholder bit included in the first bit sequence is scrambled by a bit having the same index in the first scrambling sequence.

39. A method in a first node for wireless communication, the method comprising: Comprise: receiving a first information block, the first information block being used to determine a first parameter value, the first parameter value being used to calculate a first initial value, the first initial value being used to initialize a generator of a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence including an integer number of sequentially indexed bits greater than 1; sending a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block including at least one control information bit, the second bit block including at least one control information bit, the first PUCCH adopting PUCCH format 2 or 3 or 4; The number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having the same index; the C-RNTI configured for the sender of the first PUCCH is also used to calculate the first initial value, and the priority index associated with the first PUCCH is equal to the larger level index compared between the first level index and the second level index.

40. A method in a first node according to claim 39, characterised by, The modulation order of the modulation mode used by the first PUCCH is equal to a first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit; the modulation mode used by the first PUCCH is QPSK, and the first order is equal to 2.

41. A method in a first node according to claim 39 or 40, characterized by, The first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 of sequentially indexed bits, and the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of one placeholder bit included in the first bit sequence, the bit included in the first output sequence whose index is equal to the first index is a first bit, the second bit is one bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, and the bit value of the first bit and the bit value of the second bit are equal.

42. A method in a first node according to claim 41, characterised by, The bit value of the second bit is equal to the result of the logical AND between the bit value of one bit included in the first bit sequence and the bit value of one bit included in the first scrambling sequence, and the second index is equal to the first index minus 1.

43. A method in a first node according to claim 39, characterised by, Comprise: Receiving a second information block; The second information block is used to determine X1 resource sets, X1 being a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH being a target PUCCH resource, the target PUCCH resource being one PUCCH resource included in a target resource set; the target resource set being one of the X1 resource sets, a target quantity value being used to determine the target resource set from the X1 resource sets, the target quantity value being a positive integer; the target quantity value being equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block.

44. A method in a first node according to claim 43, characterised by, The second information block includes all or part of the domains in the information unit "PUCCH-Config" in the RRC signaling.

45. A method in a first node according to claim 43, characterised by, The X1 resource sets respectively correspond to X1 value intervals, the target quantity value belonging to a target value interval, the target value interval being one of the X1 value intervals, the target resource set being the resource set corresponding to the target value interval in the X1 resource sets; the X1 value intervals being configured by one or more domains included in the second information block.

46. A method in a first node according to claim 43, characterised by, Comprise: Receiving a first signaling; Wherein, when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

47. A method in a first node according to claim 46, characterised by, The first signaling includes a PUCCH resource indication domain in a DCI format, and the first signaling is carried by the latest PDCCH associated with the first PUCCH.

48. A method in a first node according to claim 46, characterised by, The PUCCH resource indication domain carried by the first signaling and the index of the starting CCE occupied by the PDCCH carrying the first signaling are used together to determine the index or ID of the target PUCCH resource in the target resource set.

49. A method in a first node according to claim 43, characterised by, The second information block is used to determine a first code rate, the first code rate being a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain being equal to a first quantity value; The first code rate is used to determine the first quantity value, the number of bits included in the first bit sequence being in a positive proportional relationship with the first quantity value; the type of UCI carried by the first PUCCH being used to determine the first code rate.

50. A method in a first node according to claim 49, characterised by, The first quantity value is not greater than the number of physical resource blocks included in the target PUCCH resource in the frequency domain; the first code rate being the maximum PUCCH code rate configured.

51. A method in a first node according to claim 49, characterised by, The first code rate and a feature quantity value are used together to calculate the first quantity value, at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block being used to determine the feature quantity value, the feature quantity value being a positive integer.

52. A method in a first node according to claim 49, characterised by, The number of bits included in the first bit sequence is also in a positive proportional relationship with the number of OFDM symbols occupied by the first PUCCH; and the number of bits included in the first bit sequence is also in an inverse proportional relationship with the spreading factor adopted by the first PUCCH.

53. A method in a first node according to claim 49, characterised by, The type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type being UCI including control information of different priorities, and the second UCI type being UCI including only control information of the same priority.

54. The method in a first node according to claim 39, characterised by, The first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, spreading, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH, or the first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, block spreading, transform precoding, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH.

55. The method in a first node according to claim 39, characterised by, The priority index of the control information bits included in the first bit block is a value of a priority indication carried by a PDCCH to which the control information bits included in the first bit block are associated; and the priority index of the control information bits included in the second bit block is a value of a priority indication carried by a PDCCH to which the control information bits included in the second bit block are associated.

56. The method in a first node according to claim 39, characterised by, The first bit block only includes HARQ-ACK bits; the first bit block sequentially undergoes channel coding and rate matching to generate a first target bit sequence, and the second bit block sequentially undergoes channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

57. The method in a first node according to claim 39, characterised by, The placeholder bit is a bit used to maximize the Euclidean distance, and any non-placeholder bit included in the first bit sequence is scrambled by a bit having the same index in the first scrambling sequence.

58. A method in a second node for wireless communication, the method comprising: Comprise: transmitting a first information block, the first information block being used to indicate a first parameter value, the first parameter value being used to calculate a first initial value, the first initial value being used to initialize a generator of a first scrambling sequence, the first parameter value being a non-negative integer, the first scrambling sequence including an integer number of sequentially indexed bits greater than 1; receiving a first PUCCH, the first PUCCH being used to carry a first bit block and a second bit block, the first bit block including at least one control information bit, the second bit block including at least one control information bit, the first PUCCH adopting PUCCH format 2 or 3 or 4; The number of control information bits included in the first bit block is not greater than 2; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2; the priority index of the control information bits included in the first bit block is equal to a first level index, the priority index of the control information bits included in the second bit block is equal to a second level index, and the first level index and the second level index are not equal; the first bit block and the second bit block are collectively used to generate a first bit sequence, the first bit sequence includes an integer greater than 1 of sequentially indexed bits; the first bit sequence includes at least one placeholder bit, and the non-placeholder bits included in the first bit sequence are scrambled by bits in the first scrambling sequence having the same index; the C-RNTI configured for the sender of the first PUCCH is also used to calculate the first initial value, and the priority index associated with the first PUCCH is equal to the larger level index compared between the first level index and the second level index.

59. A method in a second node according to claim 58, characterised by, The modulation order of the modulation mode used by the first PUCCH is equal to a first order, the first order is a positive integer greater than 1; the number of control information bits included in the first bit block is less than the first order, which is used to determine that the first bit sequence includes at least one placeholder bit; the modulation mode used by the first PUCCH is QPSK, and the first order is equal to 2.

60. A method in a second node according to claim 58 or 59, characterized by, The first bit sequence and the first scrambling sequence are collectively used to generate a first output sequence, the first output sequence includes a positive integer greater than 1 of sequentially indexed bits, and the number of bits included in the first output sequence is equal to the number of bits included in the first bit sequence; the first index is the index of one placeholder bit included in the first bit sequence, the bit included in the first output sequence whose index is equal to the first index is a first bit, the second bit is one bit included in the first output sequence, the second index is the index of the second bit in the first output sequence, the second index and the first index are two adjacent indexes, and the bit value of the first bit and the bit value of the second bit are equal.

61. A method in a second node according to claim 60, characterised by, The bit value of the second bit is equal to the result of the logical AND between the bit value of one bit included in the first bit sequence and the bit value of one bit included in the first scrambling sequence, and the second index is equal to the first index minus 1.

62. A method in a second node according to claim 58, characterised by, Comprising: sending a second information block; The second information block is used to determine X1 resource sets, X1 being a positive integer greater than 1; any one of the X1 resource sets includes at least one PUCCH resource, the resource occupied by the first PUCCH being a target PUCCH resource, the target PUCCH resource being one PUCCH resource included in a target resource set; the target resource set being one of the X1 resource sets, a target quantity value being used to determine the target resource set from the X1 resource sets, the target quantity value being a positive integer; the target quantity value being equal to the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block.

63. A method in a second node according to claim 62, characterized by, The second information block includes all or part of the domains in the information unit "PUCCH-Config" in the RRC signaling.

64. A method in a second node according to claim 62, characterised by, The X1 resource sets respectively correspond to X1 value intervals, the target quantity value belonging to a target value interval, the target value interval being one of the X1 value intervals, and the target resource set being the resource set corresponding to the target value interval in the X1 resource sets; the X1 value intervals being configured by one or more domains included in the second information block.

65. A method in a second node according to claim 62, characterised by, Comprise: sending a first signaling; wherein, when the target resource set includes more than one PUCCH resource, the first signaling is used to determine the target PUCCH resource from the target resource set.

66. A method in a second node according to claim 65, characterised by, The first signaling includes a PUCCH resource indication domain in a DCI format, and the first signaling is carried by the latest PDCCH associated with the first PUCCH.

67. A method in a second node according to claim 65, characterised by, The PUCCH resource indication domain carried by the first signaling and the index of the starting CCE occupied by the PDCCH carrying the first signaling are used together to determine the index or ID of the target PUCCH resource in the target resource set.

68. The method in a second node according to claim 62, characterised by, The second information block is used to determine a first code rate, the first code rate being a non-negative number; the number of physical resource blocks occupied by the first PUCCH in the frequency domain being equal to a first quantity value; The first code rate is used to determine the first quantity value, the number of bits included in the first bit sequence being in a positive proportional relationship with the first quantity value; and the type of UCI carried by the first PUCCH being used to determine the first code rate.

69. A method in a second node according to claim 68, characterized by, The first quantity value is not greater than the number of physical resource blocks included in the target PUCCH resource in the frequency domain; and the first code rate is the maximum PUCCH code rate configured.

70. A method in a second node according to claim 68, characterised by, The first code rate and a feature quantity value are used together to calculate the first quantity value, at least one of the number of control information bits included in the first bit block or the number of control information bits included in the second bit block being used to determine the feature quantity value, the feature quantity value being a positive integer.

71. A method in a second node according to claim 68, characterised by, The number of bits included in the first bit sequence is also in direct proportion to the number of OFDM symbols occupied by the first PUCCH, and is in inverse proportion to the spreading factor adopted by the first PUCCH.

72. A method in a second node according to claim 68, characterised by, The type of UCI carried by the first PUCCH is one of a first UCI type or a second UCI type, the first UCI type being UCI including control information of different priorities, and the second UCI type being UCI including only control information of the same priority.

73. A method in a second node according to claim 58, characterised by, The first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, spreading, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH, or the first bit sequence and the first scrambling sequence together sequentially undergo scrambling, modulation, block spreading, transform precoding, mapping to physical resources, OFDM baseband signal generation, and modulation and up-conversion to generate the first PUCCH.

74. The method in a second node according to claim 58, characterized by, The priority index of the control information bits included in the first bit block is the value of the priority indication carried by the PDCCH to which the control information bits included in the first bit block are associated, and the priority index of the control information bits included in the second bit block is the value of the priority indication carried by the PDCCH to which the control information bits included in the second bit block are associated.

75. A method in a second node according to Claim 58, characterised by, The first bit block only includes HARQ-ACK bits, the first bit block sequentially undergoes channel coding and rate matching to generate a first target bit sequence, the second bit block sequentially undergoes channel coding and rate matching to generate a second target bit sequence, and the first target bit sequence and the second target bit sequence are concatenated to obtain the first bit sequence.

76. The method in a second node according to claim 58, characterised by, The placeholder bit is a bit used to maximize the Euclidean distance, and any non-placeholder bit included in the first bit sequence is scrambled by a bit having the same index in the first scrambling sequence.

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