A domain controller and a vehicle

Abstract

This invention discloses a domain controller and a vehicle. The domain controller includes a multi-input detection chip, a main control chip, a wake-up source classification and processing module, and an analog wake-up module. The wake-up source classification and processing module classifies externally input wake-up sources according to their type and sends them to the multi-input detection chip. The multi-input detection chip monitors the wake-up sources and sends wake-up signals to the main control chip. The main control chip controls the domain controller to enter sleep or wake-up mode based on the received wake-up signals. The analog wake-up module processes externally input analog wake-up signals and sends them to the main control chip through the multi-input detection chip. The main control chip controls the domain controller to enter sleep or wake-up mode based on the received analog wake-up signals. The wake-up signals and analog wake-up signals are different types of signals. The domain controller of this invention can identify and respond to multiple wake-up sources.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and more particularly to a domain controller and a vehicle. Background Technology

[0002] With the development of automotive electronics technology, some small controllers in automobiles are gradually being replaced by integrated domain controllers. Major OEMs are also committed to the design and development of integrated domain controllers with new architectures. Integrated architectures are accelerating the development of intelligent, connected, and lightweight vehicles. However, the development of new architecture integrated domain controllers inevitably brings some technical challenges, one of which is the response and recognition of wake-up signals in sleep mode.

[0003] Domain controllers have a variety of wake-up sources. Small controllers have limited functionality and require relatively simple wake-up signals, such as edge or level recognition, to identify and respond to wake-up sources. However, domain controllers involve various types of wake-up signals, such as voltage analog change wake-up, signal edge wake-up, and bus wake-up. A single domain controller may have dozens of wake-up source inputs, and due to the limited number of wake-up pins on the main control chip, existing domain controllers cannot convert different types of wake-up source signals into signals that the domain controller can recognize, cannot classify wake-up signals, and cannot effectively identify and respond to multiple wake-up sources. Summary of the Invention

[0004] This invention provides a domain controller and a vehicle, which convert wake-up signals from different types of wake-up sources into signals that the domain controller can recognize, classify the wake-up signals, and achieve effective identification and response to multiple wake-up sources.

[0005] According to one aspect of the present invention, a domain controller is provided, comprising: a multi-input detection chip, a main control chip, a wake-up source classification and processing module, and an analog wake-up module;

[0006] The wake-up source classification and processing module is connected to the multi-input detection chip, and the multi-input detection chip is connected to the main control chip. The wake-up source classification and processing module is used to classify and process external wake-up sources according to their type and send them to the multi-input detection chip. The multi-input detection chip is used to monitor wake-up sources and send wake-up signals to the main control chip. The main control chip is used to control the domain controller to go into sleep or wake up according to the received wake-up signal.

[0007] The analog wake-up module is connected to the multi-input detection chip. The analog wake-up module is used to process the externally input analog wake-up signal and send it to the main control chip through the multi-input detection chip. The main control chip is used to control the domain controller to go into sleep or wake up according to the received analog wake-up signal.

[0008] The wake-up signal and the analog type wake-up signal are different types of signals.

[0009] Optionally, the wake-up source classification and processing module includes at least one of the following circuits: a first wake-up source classification and processing circuit, a second wake-up source classification and processing circuit, and a third wake-up source classification and processing circuit.

[0010] Optionally, the first wake-up source classification and processing circuit includes a first CAN wake-up circuit and an electronic parking signal detection circuit. The first CAN wake-up circuit is directly connected to the multi-input detection chip, and the electronic parking signal detection circuit is directly connected to the multi-input detection chip.

[0011] The second wake-up source classification and processing circuit includes a second CAN wake-up circuit, an electronic fuse detection circuit, and a first wake-up circuit. The second CAN wake-up circuit and the first AND gate are connected to the multi-input detection chip. The electronic fuse detection circuit and the second AND gate are connected to the multi-input detection chip. The first wake-up circuit and the third AND gate are connected to the multi-input detection chip.

[0012] The third wake-up source classification and processing circuit includes a LIN wake-up circuit, an Ethernet wake-up circuit, an Ethernet conversion circuit, and a second wake-up circuit. The LIN wake-up circuit is connected to the first OR gate and then to the multi-input detection chip. The Ethernet wake-up circuit is connected to the second OR gate and then to the multi-input detection chip. The Ethernet conversion circuit is connected to the third OR gate and then to the multi-input detection chip. The second wake-up circuit is connected to the fourth OR gate and then to the multi-input detection chip.

[0013] Optionally, the analog wake-up module includes a first low-power comparison unit and a second low-power comparison unit;

[0014] The first terminal of the first low-power comparison unit is connected to the AC charging gun, and the second terminal of the first low-power comparison unit is connected to the multi-input detection chip.

[0015] The first terminal of the second low-power comparison unit is connected to the DC charging gun, and the second terminal of the second low-power comparison unit is connected to the multi-input detection chip.

[0016] Optionally, the first low-power comparison unit is used to identify at least one of the first wake-up mode, the second wake-up mode, and the third wake-up mode of the AC charging gun.

[0017] Optionally, the first low-power comparison unit includes a first resistor, a first capacitor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first comparator, a second comparator, a sixth resistor, a seventh resistor, a second capacitor, a third capacitor, an eighth resistor, a ninth resistor, a first diode, a second diode, and a fourth capacitor;

[0018] The first end of the first resistor is connected to the first power supply terminal. The second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded. The first end of the first capacitor is also connected to the first end of the fourth capacitor, and the first end of the fourth capacitor is connected to the main control chip. The second end of the fourth capacitor is grounded. The first end of the second resistor is connected to the first power supply terminal. The second end of the second resistor and the first end of the third resistor are connected and then connected to the non-inverting input terminal of the first comparator. The second end of the third resistor is grounded. The second end of the first resistor and the first end of the first capacitor are connected and then connected to the inverting input terminal of the first comparator. The inverting input terminal of the first comparator is connected to the non-inverting input terminal of the second comparator. The first end of the fourth resistor is connected to the first power supply terminal. The second end of the fourth resistor and the first end of the fifth resistor are connected... After connection, it is connected to the inverting input terminal of the second comparator. The second terminal of the fifth resistor is grounded. The output terminal of the first comparator is connected to the first terminal of the sixth resistor and the first terminal of the second capacitor. The second terminal of the sixth resistor is connected to the second power supply terminal. The second terminal of the second capacitor is connected to the first terminal of the eighth resistor, the cathode of the first diode, and the multiplexer detection chip. The second terminal of the eighth resistor is connected to the second power supply terminal. The anode of the first diode is grounded. The output terminal of the second comparator is connected to the first terminal of the seventh resistor and the first terminal of the third capacitor. The second terminal of the seventh resistor is connected to the second power supply terminal. The second terminal of the third capacitor is connected to the first terminal of the ninth resistor, the cathode of the second diode, and the multiplexer detection chip. The second terminal of the ninth resistor is connected to the second power supply terminal. The anode of the second diode is grounded.

[0019] Optionally, the second CAN wake-up circuit includes at least one third diode, a tenth resistor, an eleventh resistor, a twelfth resistor, a first transistor, a fifth capacitor, a thirteenth resistor, a second transistor, and a fourteenth resistor;

[0020] The cathode of the third diode serves as the input terminal of the second CAN wake-up circuit, used to input multiple non-specific frame wake-up signals. The anode of the third diode is connected in parallel and then connected to the first terminal of the tenth resistor. The second terminal of the tenth resistor is connected to the base of the first transistor. The eleventh and twelfth resistors are connected in series between the base and emitter of the first transistor. The collector of the first transistor is connected to the first terminal of the fifth capacitor and the emitter of the second transistor and then grounded. The emitter of the first transistor is connected to the second terminal of the fifth capacitor and the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor is connected to the base of the second transistor. The collector of the second transistor is connected to the first terminal of the fourteenth resistor and then serves as the output terminal of the second CAN wake-up circuit. The second terminal of the fourteenth resistor is connected to the logic power supply terminal.

[0021] Optionally, the first CAN wake-up circuit includes a fourth diode, a fifteenth resistor, a sixteenth resistor, a third transistor, and a seventeenth resistor;

[0022] The anode of the fourth diode serves as the input terminal of the first CAN wake-up circuit for inputting a specific frame wake-up signal. The cathode of the fourth diode is connected to the first terminal of the fifteenth resistor. The second terminal of the fifteenth resistor is connected to the base of the third transistor. The sixteenth resistor is connected between the base and emitter of the third transistor. The collector of the third transistor is connected to the first terminal of the seventeenth resistor and serves as the output terminal of the first CAN wake-up circuit. The second terminal of the seventeenth resistor is connected to the logic power supply terminal.

[0023] Optionally, the domain controller further includes a power supply chip, which is connected to the wake-up source classification and processing module, the analog wake-up module, the multi-input detection chip and the main control chip, respectively, and the power supply chip is used to provide logic power.

[0024] According to another aspect of the invention, a vehicle is provided that includes a domain controller as described in any of the preceding aspects.

[0025] The domain controller in this embodiment of the invention includes: a multi-input detection chip, a main control chip, a wake-up source classification and processing module, and an analog wake-up module. The wake-up source classification and processing module is connected to the multi-input detection chip, which is connected to the main control chip. The wake-up source classification and processing module is used to classify and process externally input wake-up sources according to their type and send them to the multi-input detection chip. The multi-input detection chip is used to monitor the wake-up sources and send wake-up signals to the main control chip. The main control chip is used to control the domain controller to enter sleep mode or wake up according to the received wake-up signals. The analog wake-up module is connected to the multi-input detection chip. The analog wake-up module is used to process externally input analog wake-up signals and send them to the main control chip through the multi-input detection chip. The main control chip is used to control the domain controller to enter sleep mode or wake up according to the received analog wake-up signals. The wake-up signals and analog wake-up signals are signals of different types. The technical solution of this embodiment converts the wake-up signal from the wake-up source into a signal that the domain controller can recognize by using different types of logic processing circuits, thereby realizing the recognition and response to multiple wake-up sources; it also classifies the wake-up signal to achieve effective recognition of multiple wake-up sources. In summary, the technical solution of this embodiment solves the problems in the prior art where the domain controller cannot convert wake-up signals from different types of wake-up sources into signals that the domain controller can recognize, cannot classify the wake-up signal, and cannot achieve effective recognition and response to multiple wake-up sources.

[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a domain controller according to an embodiment of the present invention;

[0029] Figure 2 This is a flowchart of a domain controller sleep and wake-up process according to an embodiment of the present invention;

[0030] Figure 3 This is a flowchart of another domain controller sleep and wake-up process provided by an embodiment of the present invention;

[0031] Figure 4This is a schematic diagram of the structure of another domain controller provided according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the structure of a wake-up source classification and processing module provided in an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the structure of an analog signal wake-up module according to an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the overall structure of a domain controller according to an embodiment of the present invention;

[0035] Figure 8 This is a circuit schematic diagram of a first low-power comparison unit provided according to an embodiment of the present invention;

[0036] Figure 9 This is a circuit diagram of a second CAN wake-up circuit provided according to an embodiment of the present invention;

[0037] Figure 10 This is a circuit schematic diagram of a first CAN wake-up circuit provided according to an embodiment of the present invention;

[0038] Figure 11 This is a circuit schematic diagram of a first wake-up circuit provided according to an embodiment of the present invention;

[0039] Figure 12 This is a circuit diagram of a second wake-up circuit provided according to an embodiment of the present invention;

[0040] Figure 13 This is a circuit schematic diagram of a LIN wake-up circuit according to an embodiment of the present invention;

[0041] Figure 14 This is a circuit diagram of an electronic fuse detection circuit according to an embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] Figure 1 This is a schematic diagram of a domain controller according to an embodiment of the present invention, with reference to... Figure 1 This invention provides a domain controller, comprising: a multiplexer detection chip 10, a main control chip 20, a wake-up source classification and processing module 30, and an analog wake-up module 40. The wake-up source classification and processing module 30 is connected to the multiplexer detection chip 10, which is connected to the main control chip 20. The wake-up source classification and processing module 30 classifies externally input wake-up sources according to their type and sends them to the multiplexer detection chip 10. The multiplexer detection chip 10 monitors the wake-up sources and sends wake-up signals to the main control chip 20. The main control chip 20 controls the domain controller to enter sleep or wake-up mode based on the received wake-up signals. The analog wake-up module 40 is connected to the multiplexer detection chip 10. The analog wake-up module 40 processes externally input analog wake-up signals and sends them to the main control chip 20 via the multiplexer detection chip 10. The main control chip 20 controls the domain controller to enter sleep or wake-up mode based on the received analog wake-up signals. The wake-up signals and analog wake-up signals are different types of signals.

[0045] Specifically, the main control chip 20 is an MCU chip with a sleep function and a wake-up pin. The main control chip 20 can use the E3 series chip from SemiDrive Technology, which has a sleep mode. In sleep mode, the SYS-WAKEUP0, SYS-WAKEUP1, and SYS-BUTTON pins are used to respond to wake-up source requests. The multi-input detection chip 10 supports multiple inputs and low power consumption. The main control chip 20 only has three pins supporting wake-up in sleep mode, which cannot support the recognition of all wake-up types of the domain controller. Therefore, the multi-input detection chip 10 is used to monitor the wake-up source and output a wake-up signal to wake up the main control chip 20. The main control chip 20 reads the wake-up source by reading the registers of the multi-input detection chip 10 via SPI for wake-up source calibration. The multi-input detection chip 10 can use an NXP MC33978 multiplexer chip. Valid wake-up signal: The input pins of the multi-input detection chip 10 have built-in comparators that can identify level changes across 4V. Wake-up signals are output through the INT-B and WAKE-B pins to wake up the main control chip 20 and the power supply chip. The wake-up source classification and processing module 30 classifies wake-up sources according to their type. For multi-input signals, high-active-signal signals are ORed, and low-active-signal signals are ANDed. If the wake-up source level does not meet the detection level requirements of the multi-input detection chip, level conversion is required before sending the signal to the multi-input detection chip 10. The multi-input detection chip 10 then sends a wake-up signal to the main control chip 20, thereby controlling the domain controller to enter sleep or wake-up mode.

[0046] The analog wake-up source of the analog wake-up module 40 mainly refers to the wake-up signal of the AC / DC charging gun connection status. Specifically, the AC / DC charging gun insertion wake-up occurs when the charging gun is inserted. The built-in resistor of the charging gun and the domain controller resistor required by the charging standard are used to divide the voltage and input it to the main control chip 20 to identify the charging gun type. At the same time, plugging and unplugging the charging gun will change the voltage division value, thereby generating a wake-up signal. The analog wake-up module 40 processes the analog wake-up signal accordingly and sends it to the main control chip 20 through the multi-input detection chip 10 to control the domain controller to go into sleep or wake up.

[0047] The types and quantities of wake-up sources for domain controllers are listed in Table 1 below:

[0048]

[0049] Figure 2 This is a flowchart of a domain controller sleep and wake-up process according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating another domain controller sleep and wake-up process according to an embodiment of the present invention, see reference. Figure 2 and Figure 3Due to the high static power consumption of domain controllers, and the existence of sleep current loss since the system is not powered down in sleep mode, as well as the current consumption required for wake-up source identification, this invention maintains the system's static power consumption at a low level through the selection of logic circuit components and low-power circuit design. MCUs from major international manufacturers such as Infineon have sleep domains, with multiple GPIOs and AD ports available for responding to wake-up sources in sleep mode. However, most main control chips have a limited number of pins supporting wake-up source reception in sleep mode, insufficient to meet the wake-up source requirements of domain controllers. This invention addresses these issues through a sleep-wake-up scheme, component selection, and the construction of discrete logic circuits. The domain controller in this embodiment of the invention includes: a multi-input detection chip, a main control chip, a wake-up source classification and processing module, and an analog wake-up module. The wake-up source classification and processing module is connected to the multi-input detection chip, which is connected to the main control chip. The wake-up source classification and processing module is used to classify and process externally input wake-up sources according to their type and send them to the multi-input detection chip. The multi-input detection chip is used to monitor the wake-up sources and send wake-up signals to the main control chip. The main control chip is used to control the domain controller to enter sleep mode or wake up according to the received wake-up signals. The analog wake-up module is connected to the multi-input detection chip. The analog wake-up module is used to process externally input analog wake-up signals and send them to the main control chip through the multi-input detection chip. The main control chip is used to control the domain controller to enter sleep mode or wake up according to the received analog wake-up signals. The wake-up signals and analog wake-up signals are signals of different types. The technical solution of this embodiment converts the wake-up signal from the wake-up source into a signal that the domain controller can recognize by using different types of logic processing circuits, thereby realizing the recognition and response to multiple wake-up sources; it also classifies the wake-up signal to achieve effective recognition of multiple wake-up sources. In summary, the technical solution of this embodiment solves the problems in the prior art where the domain controller cannot convert wake-up signals from different types of wake-up sources into signals that the domain controller can recognize, cannot classify the wake-up signal, and cannot achieve effective recognition and response to multiple wake-up sources.

[0050] Figure 4 This is a schematic diagram of another domain controller provided according to an embodiment of the present invention, with reference to... Figure 4 Optionally, the domain controller also includes a power supply chip 50, which is connected to the wake-up source classification and processing module 30, the analog wake-up module 40, the multi-input detection chip 10 and the main control chip 20, respectively. The power supply chip 50 is used to provide logic power.

[0051] Specifically, power supply chip 50, using NXP's VR5510, provides logic power to the domain controller in sleep mode. Upon receiving a sleep command, power supply chip 50 retains the HV LDO (3.3V) and HV BUCK (5V) power supplies, shuts down other power supplies, and enters sleep standby mode. It only resumes normal operation after receiving a wake-up signal from the main control chip 20 or the multiplexer detection chip 10.

[0052] Figure 5 This is a schematic diagram of the structure of a wake-up source classification and processing module according to an embodiment of the present invention, with reference to... Figure 5 Optionally, the wake-up source classification and processing module 30 includes at least one of the following circuits: a first wake-up source classification and processing circuit 31, a second wake-up source classification and processing circuit 32, and a third wake-up source classification and processing circuit 33.

[0053] Continue to refer to Figure 5 Optionally, the first wake-up source classification and processing circuit 31 includes a first CAN wake-up circuit 311 and an electronic parking signal detection circuit 312. The first CAN wake-up circuit 311 is directly connected to the multi-input detection chip 10, and the electronic parking signal detection circuit 312 is directly connected to the multi-input detection chip 10. The second wake-up source classification and processing circuit 32 includes a second CAN wake-up circuit 321, an electronic fuse detection circuit 322, and a first wake-up circuit 323. The second CAN wake-up circuit 321 is connected to the first AND gate and then to the multi-input detection chip 10. The electronic fuse detection circuit 322 is connected to the second AND gate and then to the multi-input detection chip 10. The circuit consists of a 0-connection, a first wake-up circuit 323 and a third AND gate, which are then connected to a multiplexer detection chip 10. The third wake-up source classification and processing circuit 33 includes a LIN wake-up circuit 331, an Ethernet wake-up circuit 332, an Ethernet conversion circuit 333 and a second wake-up circuit 334. The LIN wake-up circuit 331 and the first OR gate are connected to the multiplexer detection chip 10. The Ethernet wake-up circuit 332 and the second OR gate are connected to the multiplexer detection chip 10. The Ethernet conversion circuit 333 and the third OR gate are connected to the multiplexer detection chip 10. The second wake-up circuit 334 and the fourth OR gate are connected to the multiplexer detection chip 10.

[0054] Specifically, the first CAN wake-up circuit 311 is a specific frame wake-up circuit. The electronic parking signal detection circuit 312 includes an EPB processing chip, using ST's L93XX series chip. When a valid EPB button change is detected, the EPB chip generates a high-level pulse of 0V-12V-0V. The processing circuit can handle digital high-validity wake-up sources, meeting the recognition requirements of multi-input detection chips. The second CAN wake-up circuit 321 is a non-specific frame wake-up circuit. The electronic fuse detection circuit 322 is used when the current flowing through the bypass MOSFET in the EFuse chip with wake-up function increases, i.e., when a power-on demand is detected at the power distribution end, the MOSFET will report desaturation information. At the same time, the EFuse chip output DIAG pin level changes from 12V to 0V. The wake-up function is achieved through logic AND processing and level conversion. The first wake-up circuit 323 can be a digital type low active circuit, specifically used to identify digital type low active wake-up sources. The LIN wake-up circuit 331 is used when a message appears on the LIN bus; the INH pin of a LIN chip with wake-up function (e.g., chip model SIT1021) will generate a voltage change of 0V-12V. A processing circuit such as a specific frame CAN wake-up can meet the identification requirements of the multi-input detection chip. The Ethernet wake-up circuit 332 is used when an Ethernet PHY or switch chip with wake-up function receives Ethernet data and reports wake-up information. If the wake-up signal is of OD structure, the processing circuit is the same as the EFuse wake-up circuit; if the wake-up signal is of push-pull structure, the processing circuit is the same as the digital type high active circuit. The Ethernet conversion circuit 333 is mainly used for data signal reception and conversion, facilitating identification and detection by the multi-input detection chip. The second wake-up circuit 334 can be a digital type high active circuit, specifically used to identify digital type high active wake-up sources.

[0055] Figure 6 This is a schematic diagram of an analog wake-up module according to an embodiment of the present invention. (Refer to...) Figure 6 Optionally, the analog wake-up module 40 includes a first low-power comparison unit 41 and a second low-power comparison unit 42; the first end of the first low-power comparison unit 41 is connected to the AC charging gun, and the second end of the first low-power comparison unit 41 is connected to the multi-input detection chip 10; the first end of the second low-power comparison unit 42 is connected to the DC charging gun, and the second end of the second low-power comparison unit 42 is connected to the multi-input detection chip 10.

[0056] Specifically, the first low-power comparison unit 41 mainly relates to the insertion wake-up of the AC charging gun. After the charging gun is inserted, the built-in resistor of the charging gun and the domain controller resistor required by the charging standard are used to divide the voltage and input it to the main control chip to identify the charging gun type. At the same time, plugging and unplugging the charging gun will cause the voltage division value to change, thereby generating a wake-up signal. The second low-power comparison unit 42 mainly relates to the insertion wake-up of the DC charging gun. After the charging gun is inserted, the built-in resistor of the charging gun and the domain controller resistor required by the charging standard are used to divide the voltage and input it to the main control chip to identify the charging gun type. At the same time, plugging and unplugging the charging gun will cause the voltage division value to change, thereby generating a wake-up signal.

[0057] Figure 7 This is a schematic diagram of the overall structure of a domain controller according to an embodiment of the present invention, with reference to... Figure 7 The domain controller also includes a reverse connection protection diode, one end of which is connected to an external 12V power supply, and the other end of which is connected to a power supply chip.

[0058] Optionally, the first low-power comparison unit is used to identify at least one of the first wake-up mode, the second wake-up mode, and the third wake-up mode of the AC charging gun.

[0059] Specifically, the first wake-up mode refers to identifying the AC charging gun as not connected to the half-connected state, the second wake-up mode refers to identifying the AC charging gun as not connected to the fully connected state, and the third wake-up mode refers to identifying the AC charging gun as being half-connected to the fully connected state.

[0060] Figure 8 This is a circuit schematic diagram of a first low-power comparator unit according to an embodiment of the present invention, with reference to... Figure 8Optionally, the first low-power comparator unit includes a first resistor R1, a first capacitor C1, a second resistor R2, a third resistor R3, a fourth resistor R5, a fifth resistor R6, a first comparator U1, a second comparator U2, a sixth resistor R7, a seventh resistor R8, a second capacitor C3, a third capacitor C4, an eighth resistor R9, a ninth resistor R10, a first diode D1, a second diode D2, and a fourth capacitor C2; the first terminal of the first resistor R1 is connected to the first power supply terminal 3.3V, and the second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1. The second terminal of capacitor C1 is grounded. The first terminal of the first capacitor C1 is also connected to the first terminal of the fourth capacitor C2. The first terminal of the fourth capacitor C2 is connected to the main control chip 20. The second terminal of the fourth capacitor C2 is grounded. The first terminal of the second resistor R2 is connected to the first power supply terminal 3.3V. The second terminal of the second resistor R2 and the first terminal of the third resistor R3 are connected and then connected to the non-inverting input terminal of the first comparator U1. The second terminal of the third resistor R3 is grounded. The second terminal of the first resistor R1 and the first terminal of the first capacitor C1 are connected and then connected to the inverting input terminal of the first comparator U1. The inverting input of comparator U1 is connected to the non-inverting input of comparator U2. The first terminal of the fourth resistor R5 is connected to the first power supply terminal (3.3V). The second terminal of the fourth resistor R5 and the first terminal of the fifth resistor R6 are connected and then connected to the inverting input of comparator U2. The second terminal of the fifth resistor R6 is grounded. The output of comparator U1 is connected to the first terminal of the sixth resistor R7 and the first terminal of the second capacitor C3. The second terminal of the sixth resistor R7 is connected to the second power supply terminal (5V). The second terminal of the second capacitor C3 is connected to the first terminal of the eighth resistor R9 and the first diode D1. The cathode of the first diode D1 is connected to the multiple input detection chip 10. The second end of the eighth resistor R9 is connected to the second power supply terminal 5V. The anode of the first diode D1 is grounded. The output terminal of the second comparator U2 is connected to the first end of the seventh resistor R8 and the first end of the third capacitor C4. The second end of the seventh resistor R8 is connected to the second power supply terminal 5V. The second end of the third capacitor C4 is connected to the first end of the ninth resistor R10, the cathode of the second diode D2, and the multiple input detection chip 10. The second end of the ninth resistor R10 is connected to the second power supply terminal 5V. The anode of the second diode D2 is grounded.

[0061] Specifically, since the multi-input detection chip can only recognize wake-up signals that cross 4V and maintain a level greater than 19µs after the change (other multi-input detection chips can be designed according to actual conditions), and the signal after voltage division when the charging gun is inserted may be lower than 4V and cannot be recognized, it is necessary to process the analog wake-up signal accordingly to meet the recognition conditions. This embodiment of the invention uses a comparator scheme. The comparator reference threshold is determined according to the range of analog input signal level changes. A pulse generation circuit is also added to prevent a wake-up signal from being generated when the charging gun is removed, simplifying the system software scheme. The comparator should be a low-power open-drain output comparator, for example, the BU7233YF model. The specific circuit implementation is as follows:

[0062] The charging gun includes switch S3, a first charging gun resistor RC, and a second charging gun resistor R4. After the charging gun is disconnected and then connected, the CC port of the domain controller is connected to a pull-down resistor RC (fully connected state) or RC+R4 (half-connected state). The first low-power comparator needs to identify the following three wake-up modes: not connected to half-connected ①, not connected to fully connected ②, and half-connected to fully connected ③.

[0063] The second resistor R2, the third resistor R3, the fourth resistor R5, and the fifth resistor R6 are used for threshold setting; the sixth resistor R7 and the seventh resistor R8 are used for open-drain pull-up of the comparator; the second capacitor C3 and the eighth resistor R9 are used to generate pulse signals; the third capacitor C4 and the ninth resistor R10 serve the same function. The Zener diodes at the ports of the multi-input detection chip are used to protect the ports when high pulses are generated. The voltage divider values ​​of the second resistor R2 and the third resistor R3 are set to be less than the unconnected state and greater than the half-connected and fully connected states. When the charging gun changes from an unconnected state to a fully connected state or from an unconnected state to a half-connected state, the output terminal OUT1 of the first comparator U1 changes from high to low, and CC-WAKE1 outputs a 5V-0V-5V low-level pulse, which meets the recognition conditions of the multi-input detection chip. The voltage divider values ​​of the fourth resistor R5 and the fifth resistor R6 are set to be greater than the fully connected state and less than the half-connected state. When the charging gun changes from a half-connected to a fully connected state, the output terminal OUT2 of the second comparator U2 changes from high to low, and CC-WAKE2 outputs a 5V-0V-5V low-level pulse, which meets the recognition conditions of the multi-input detection chip. After entering sleep mode and being fully charged, when the charging gun is unplugged, a 5V-10V-5V high-level pulse is generated at CC-WAKE1 and CC-WAKE2, which does not meet the recognition conditions of the multi-input detection chip, and the controller is not woken up, thus meeting the set conditions. The DC charging gun wake-up scheme is similar to that of the AC charging gun, and it is also implemented through a comparator. The principle is the same as above, so it will not be repeated here.

[0064] Figure 9 This is a circuit schematic diagram of a second CAN wake-up circuit according to an embodiment of the present invention, for reference. Figure 9 Optionally, the second CAN wake-up circuit includes at least one third diode D3, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, a first transistor Q1, a fifth capacitor C5, a thirteenth resistor R14, a second transistor Q2, and a fourteenth resistor R15. The cathode of the third diode D3 serves as the input terminal of the second CAN wake-up circuit, used to input multiple non-specific frame wake-up signals. The anodes of the third diode D3 are connected in parallel to the first terminal of the tenth resistor R11, and the second terminal of the tenth resistor R11 is connected to the base b of the first transistor Q1. The eleventh resistor R12 and the twelfth resistor... R13 is connected in series between the base (b) and emitter (e) of the first transistor Q1. The collector (c) of the first transistor Q1 is connected to the first terminal of the fifth capacitor C5 and the emitter (e) of the second transistor Q2, and then grounded. The emitter (e) of the first transistor Q1 is connected to the second terminal of the fifth capacitor C5 and the first terminal of the thirteenth resistor R14. The second terminal of the thirteenth resistor R14 is connected to the base (b) of the second transistor Q2. The collector (c) of the second transistor Q2 is connected to the first terminal of the fourteenth resistor R15, which serves as the output terminal of the second CAN wake-up circuit. The second terminal of the fourteenth resistor R15 is connected to the logic power supply terminal VBUCK-5V.

[0065] Specifically, the second CAN wake-up circuit is a non-specific frame wake-up circuit. It is woken up by the RX signal output by the CAN chip (e.g., the chip model could be SIT1044). When a CAN message is received, the RX signal generates a 3.3V-0V-3.3V low-level pulse. Since the duration of the RX signal low level is relatively short (<5µs), it does not meet the time requirement for recognition by the multi-channel input detection chip. Therefore, the low-level pulse needs to be delayed. The specific implementation circuit is as follows: The second CAN wake-up circuit includes N third diodes D3. The N third diodes D3 perform AND logic processing on the multiple CAN-RX signals. The first transistor Q1, the tenth resistor R11, the eleventh resistor R12, the twelfth resistor R13, and the fifth capacitor C5 constitute a delay circuit. The second transistor Q2 and the fourteenth resistor R15 constitute a level conversion circuit. Simulation results of the second CAN wake-up circuit show that it can convert a 3µs 3.3V low-level pulse into a >50µs 5V low-level pulse, which meets the recognition requirements of the multi-channel input detection chip.

[0066] Figure 10 This is a circuit schematic diagram of a first CAN wake-up circuit according to an embodiment of the present invention, for reference. Figure 10Optionally, the first CAN wake-up circuit includes a fourth diode D4, a fifteenth resistor R16, a sixteenth resistor R17, a third transistor Q3, and a seventeenth resistor R18. The anode of the fourth diode D4 serves as the input terminal of the first CAN wake-up circuit for inputting a specific frame wake-up signal. The cathode of the fourth diode D4 is connected to the first terminal of the fifteenth resistor R16. The second terminal of the fifteenth resistor R16 is connected to the base b of the third transistor Q3. The sixteenth resistor R17 is connected between the base b and the emitter c of the third transistor Q3. The collector e of the third transistor Q3 is connected to the first terminal of the seventeenth resistor R18 and serves as the output terminal of the first CAN wake-up circuit. The second terminal of the seventeenth resistor R18 is connected to the logic power supply terminal VBUCK-5V.

[0067] Specifically, the first CAN wake-up circuit is a specific frame wake-up circuit, implemented by a chip with specific frame wake-up function, such as the TJA1145A. The chip is constantly powered by a 12V battery. After recognizing a specific frame CAN message that meets the requirements, the wake-up indicator signal INH changes from 0V to 12V. A level conversion is required; after the conversion, the wake-up signal changes from 0V to 5V to meet the recognition conditions of the multi-input detection chip.

[0068] Figure 11 This is a circuit schematic diagram of a first wake-up circuit according to an embodiment of the present invention, with reference to... Figure 11 The first wake-up circuit includes at least one fifth diode D5 and an eighteenth resistor R19; the cathode of the fifth diode D5 serves as the input terminal of the first wake-up circuit, used to input multiple digital active-low wake-up source signals; the anodes of the fifth diode D5 are connected in parallel and connected to the first terminal of the eighteenth resistor R19; the second terminal of the eighteenth resistor R19 is connected to the logic power supply terminal VBUCK-5V; and the first terminal of the eighteenth resistor R19 serves as the output terminal of the first wake-up circuit.

[0069] Specifically, the first wake-up circuit is a digital type low-active wake-up source processing circuit. The definition of a digital type low-active wake-up source is: the default level is high, and at least one signal must be low to wake up the domain controller. Digital signals are mostly 12V. A level conversion circuit and AND gates are built using discrete components to identify digital type low-active wake-up sources. The first wake-up circuit includes N fifth diodes D5, which are used for multiplexed input AND logic. The eighteenth resistor R19 is pulled up to a constant 5V to provide the default state for the circuit. After the input wake-up source is valid, the IO-L-WAKE level changes from 5V to 0V, which can be recognized by the multiplexed input detection chip.

[0070] Figure 12 This is a circuit schematic diagram of a second wake-up circuit according to an embodiment of the present invention, with reference to... Figure 12The second wake-up circuit includes at least one sixth diode D6, a nineteenth resistor R20, a twentieth resistor R21, a fourth transistor Q4, and a twenty-first resistor R22. The cathode of the sixth diode D6 serves as the input terminal of the second wake-up circuit, used to input multiple digital active-high wake-up source signals. The anodes of the sixth diode D6 are connected in parallel and then connected to the first terminal of the nineteenth resistor R20. The second terminal of the nineteenth resistor R20 is connected to the base b of the fourth transistor Q4. The twentieth resistor R21 is connected between the base b and the emitter c of the fourth transistor Q4. The collector c of the fourth transistor Q4 is connected to the first terminal of the twenty-first resistor R22 and serves as the output terminal of the second wake-up circuit. The second terminal of the twenty-first resistor R22 is connected to the logic power supply terminal VBUCK-5V.

[0071] Specifically, the second wake-up circuit is a digital high-active-to-wake-up-source processing circuit. The definition of a digital high-active-to-wake-up-source is: the default level is low, and at least one input must be high to wake up the domain controller. The digital signal is 12V, and a level conversion circuit and an OR gate are built using discrete components to identify the digital high-active-to-wake-up-source. The second wake-up circuit includes N sixth diodes D6, which are used for multiplexed input OR logic. The twenty-first resistor R22 is pulled up to a constant 5V to provide the default state for the circuit. After the input wake-up source is valid, the IO-H-WAKE level changes from 5V to 0V, which can be recognized by the multiplexed input detection chip.

[0072] Figure 13 This is a circuit schematic diagram of a LIN wake-up circuit according to an embodiment of the present invention, for reference. Figure 13 The LIN wake-up circuit includes a seventh diode D7, a twenty-second resistor R23, a twenty-third resistor R24, a fifth transistor Q5, and a twenty-fourth resistor R25. The anode of the seventh diode D7 serves as the input terminal of the LIN wake-up circuit for inputting the wake-up signal. The cathode of the seventh diode D7 is connected to the first terminal of the twenty-second resistor R23. The second terminal of the twenty-second resistor R23 is connected to the base (b) of the fifth transistor Q5. The twenty-third resistor R24 ​​is connected between the base (b) and emitter (e) of the fifth transistor Q5. The collector (c) of the fifth transistor Q5 is connected to the first terminal of the twenty-fourth resistor R25 and serves as the output terminal of the LIN wake-up circuit. The second terminal of the twenty-fourth resistor R25 is connected to the logic power supply terminal VBUCK-5V.

[0073] Specifically, the LIN wake-up circuit is used when a message appears on the LIN bus. The INH pin of the LIN chip with wake-up function (e.g., the chip model can be SIT1021) will generate a voltage change of 0V-12V. The recognition requirements of the multi-input detection chip can be met by using a processing circuit such as a specific frame CAN wake-up.

[0074] Figure 14 This is a circuit schematic diagram of an electronic fuse detection circuit according to an embodiment of the present invention, with reference to... Figure 14 The electronic fuse detection circuit includes at least one eighth diode D8 and a twenty-fifth resistor R26. The cathode of the eighth diode D8 serves as the input terminal of the electronic fuse detection circuit, used to input multiple wake-up source signals. The anode of the eighth diode D8 is connected in parallel to the first terminal of the twenty-fifth resistor R26. The second terminal of the twenty-fifth resistor R26 is connected to the logic power supply terminal. The first terminal of the twenty-fifth resistor R26 serves as the output terminal of the electronic fuse detection circuit.

[0075] Specifically, the electronic fuse detection circuit is used when the current flowing through the bypass MOSFET in the EFuse chip with wake-up function increases, indicating a power-on demand at the power distribution end. The MOSFET then reports desaturation information, and simultaneously, the DIAG pin output of the EFuse chip changes from 12V to 0V. The wake-up function is achieved through logic AND processing and level conversion.

[0076] In this embodiment of the invention, the circuit of the wake-up source classification and processing module selects a low static current chip and sets a pull-up resistor to ensure that the static current is at a relatively small level, which can reduce power consumption and is beneficial to energy saving.

[0077] This invention also provides a vehicle that includes a domain controller provided in any embodiment of this invention.

[0078] Since the vehicle includes the domain controller provided in any embodiment of the present invention, the beneficial effects of the vehicle and the domain controller are the same as described above, and will not be repeated here.

[0079] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A domain controller, characterized by, The application relates to a multi-channel input detection chip, a main control chip, a wake-up source classification and processing module and an analog quantity wake-up module. The wake-up source classification and processing module is connected with the multi-channel input detection chip, the multi-channel input detection chip is connected with the main control chip, the wake-up source classification and processing module is used for classifying and processing external input wake-up sources according to types and sending the wake-up sources to the multi-channel input detection chip, the multi-channel input detection chip is used for monitoring wake-up sources and sending a wake-up signal to the main control chip, and the main control chip is used for controlling the domain controller to sleep or wake up according to the received wake-up signal. The analog quantity wake-up module is connected with the multi-channel input detection chip, the analog quantity wake-up module is used for processing external input analog quantity type wake-up signals and sending the analog quantity type wake-up signals to the main control chip through the multi-channel input detection chip, and the main control chip is used for controlling the domain controller to sleep or wake up according to the received analog quantity type wake-up signals. The wake-up signal and the analog quantity type wake-up signal are different types of signals. The wake-up source classification and processing module comprises at least one of the following circuits: a first wake-up source classification and processing circuit, a second wake-up source classification and processing circuit and a third wake-up source classification and processing circuit.

2. The domain controller of claim 1, wherein, The first wake-up source classification and processing circuit comprises a first CAN wake-up circuit and an electronic parking signal detection circuit, the first CAN wake-up circuit is directly connected with the multi-channel input detection chip, and the electronic parking signal detection circuit is directly connected with the multi-channel input detection chip.

3. The domain controller of claim 2, wherein, The second wake-up source classification and processing circuit comprises a second CAN wake-up circuit, an electronic fuse detection circuit and a first wake-up circuit, the second CAN wake-up circuit is connected with the multi-channel input detection chip through a first AND gate, the electronic fuse detection circuit is connected with the multi-channel input detection chip through a second AND gate, and the first wake-up circuit is connected with the multi-channel input detection chip through a third AND gate. The third wake-up source classification and processing circuit comprises a LIN wake-up circuit, an Ethernet wake-up circuit, an Ethernet conversion circuit and a second wake-up circuit, the LIN wake-up circuit is connected with the multi-channel input detection chip through a first OR gate, the Ethernet wake-up circuit is connected with the multi-channel input detection chip through a second OR gate, the Ethernet conversion circuit is connected with the multi-channel input detection chip through a third OR gate, and the second wake-up circuit is connected with the multi-channel input detection chip through a fourth OR gate. The analog quantity wake-up module comprises a first low-power consumption comparison unit and a second low-power consumption comparison unit.

4. The domain controller of claim 1, wherein, A first end of the first low-power consumption comparison unit is connected with an alternating current charging gun, and a second end of the first low-power consumption comparison unit is connected with the multi-channel input detection chip. A first end of the second low-power consumption comparison unit is connected with a direct current charging gun, and a second end of the second low-power consumption comparison unit is connected with the multi-channel input detection chip. ​ 5. The domain controller of claim 4, wherein, The first low-power consumption comparison unit is configured to identify at least one of a first wake-up mode, a second wake-up mode, and a third wake-up mode of the alternating current charging gun.

6. The domain controller of claim 4, wherein, The first low-power consumption comparison unit comprises a first resistor, a first capacitor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first comparator, a second comparator, a sixth resistor, a seventh resistor, a second capacitor, a third capacitor, an eighth resistor, a ninth resistor, a first diode, a second diode, and a fourth capacitor. The first end of the first resistor is connected to a first power supply end, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the first capacitor is also connected to the first end of the fourth capacitor, the first end of the fourth capacitor is connected to the master control chip, and the second end of the fourth capacitor is grounded. The first end of the second resistor is connected to the first power supply end, the second end of the second resistor and the first end of the third resistor are connected and then connected to the positive input end of the first comparator, the second end of the third resistor is grounded, the second end of the first resistor and the first end of the first capacitor are connected and then connected to the negative input end of the first comparator, the negative input end of the first comparator is connected to the positive input end of the second comparator, the first end of the fourth resistor is connected to the first power supply end, the second end of the fourth resistor and the first end of the fifth resistor are connected and then connected to the negative input end of the second comparator, the second end of the fifth resistor is grounded, the output end of the first comparator is connected to the first end of the sixth resistor and the first end of the second capacitor, the second end of the sixth resistor is connected to a second power supply end, the second end of the second capacitor is connected to the first end of the eighth resistor, the cathode of the first diode, and the multi-input detection chip, the second end of the eighth resistor is connected to the second power supply end, the anode of the first diode is grounded, the output end of the second comparator is connected to the first end of the seventh resistor and the first end of the third capacitor, the second end of the seventh resistor is connected to the second power supply end, the second end of the third capacitor is connected to the first end of the ninth resistor, the cathode of the second diode, and the multi-input detection chip, the second end of the ninth resistor is connected to the second power supply end, and the anode of the second diode is grounded.

7. The domain controller of claim 3, wherein, The second CAN wake-up circuit comprises at least one third diode, a tenth resistor, an eleventh resistor, a twelfth resistor, a first triode, a fifth capacitor, a thirteenth resistor, a second triode, and a fourteenth resistor. The cathode of the third diode is used as the input end of the second CAN wake-up circuit for inputting a plurality of non-specific frame wake-up signals, the anode of the third diode is connected to the first end of the tenth resistor in parallel, the second end of the tenth resistor is connected to the base of the first triode, the eleventh resistor and the twelfth resistor are connected in series between the base and the emitter of the first triode, the collector of the first triode is connected to the first end of the fifth capacitor and the emitter of the second triode and then grounded, the emitter of the first triode is connected to the second end of the fifth capacitor and the first end of the thirteenth resistor, the second end of the thirteenth resistor and the base of the second triode are connected, the collector of the second triode and the first end of the fourteenth resistor are connected and then used as the output end of the second CAN wake-up circuit, and the second end of the fourteenth resistor is connected to the logic power supply end.

8. The domain controller of claim 3, wherein, The first CAN wake-up circuit comprises a fourth diode, a fifteenth resistor, a sixteenth resistor, a third triode and a seventeenth resistor. The anode of the fourth diode is used as the input end of the first CAN wake-up circuit for inputting a specific frame wake-up signal, the cathode of the fourth diode is connected to the first end of the fifteenth resistor, the second end of the fifteenth resistor is connected to the base of the third triode, the sixteenth resistor is connected between the base and the emitter of the third triode, the collector of the third triode is connected to the first end of the seventeenth resistor and then used as the output end of the first CAN wake-up circuit, and the second end of the seventeenth resistor is connected to the logic power supply end.

9. The domain controller of claim 1, wherein, The power supply chip is further connected with the wake-up source classification and processing module, the analog quantity wake-up module, the multi-input detection chip and the main control chip respectively, and is used for providing logic power supply.

10. A vehicle characterized by comprising: The domain controller of any one of claims 1-9 is included.

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