Debugging system, microprocessing device and debugging method

Abstract

A debugging system, a microprocessing device and a debugging method are provided. The debugging system includes a debugger and a target device. The debugger is configured to output an output signal. The output signal is a first encoded signal or a reset signal. The first encoded signal is generated from a first data signal and a first clock signal. The target device includes a serial debug interface circuit and a serial debug access port. The serial debug interface circuit is coupled to the debugger to receive the output signal. The serial debug interface circuit is configured to decode the first encoded signal to generate the first data signal and the first clock signal. The serial debug access port is coupled to the serial debug interface circuit. The serial debug access port is configured to receive the data signal and the clock signal from the serial debug interface circuit to perform debugging of the target device.

Description

Technical Field

[0001] The embodiments of the present invention are mainly related to a debugging technique, and more particularly to a debugging technique that transmits reset signals, data signals and clock signals by means of only one pin, including a debugging system, a microprocessor device and a debugging method. Background Technology

[0002] Serial wire debug (SWD) interfaces are a type of debugging interface. They can be used for debugging chips or processors. Traditional SWD interfaces require SWDIO pins, SWDCLC pins, and RESET pins to receive data signals, clock signals, and reset signals, respectively.

[0003] In the design of microcontroller units (MCUs), reducing the number of pins can reduce the routing complexity of external devices. Therefore, how to reduce the number of pins configured in the serial line error detection interface of the microcontroller unit is a topic worthy of research. Summary of the Invention

[0004] In view of the problems of the prior art described above, embodiments of the present invention provide a debugging system, a microprocessor device, and a debugging method.

[0005] According to an embodiment of the present invention, a debugging system is provided. The debugging system includes a debugger and a target device. The debugger is configured to output an output signal. The output signal is a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal. The target device includes a serial wire debug interface circuit (SWD interface circuit) and a serial wire debug access port (SWD debug access port). The serial debug interface circuit is coupled to the debugger to receive the output signal. Furthermore, the serial debug interface circuit can decode the first encoded signal to generate the first data signal and the first clock signal. The debug access port is coupled to the serial debug interface circuit. The debug access port receives the data signal and the clock signal from the serial debug interface circuit to perform debugging on the target device.

[0006] In some embodiments, the serial debugging interface circuit further includes a determination circuit. The determination circuit determines whether the period of the output signal is greater than a threshold value to determine whether the output signal is the first encoded signal or the reset signal. When the period of the output signal is greater than the threshold value, the determination circuit determines that the output signal is the reset signal; and when the period of the output signal is not greater than the threshold value, the determination circuit determines that the output signal is the first encoded signal.

[0007] In some embodiments, the serial debugging interface circuit further includes a decoder. The decoder is coupled to a judgment circuit. The decoder can decode the first encoded signal to generate the first data signal and the first clock signal.

[0008] In some embodiments, the serial debugging interface circuit further includes an analysis circuit. The analysis circuit is coupled to the decoder and the debugging access port. Based on the first data signal, the analysis circuit determines a first transmission direction of the first data signal and the first clock signal, and transmits the first data signal and the first clock signal to the debugging access port. The analysis circuit also receives a second data signal and a second clock signal from the debugging access port, and determines a second transmission direction of the second data signal and the second clock signal based on the first data signal.

[0009] In some embodiments, the serial debugging interface circuit further includes an encoding circuit. The encoding circuit is coupled to the analysis circuit. The encoding circuit can receive the second data signal and the second clock signal, and encode the second data signal and the second clock signal to generate second encoded data.

[0010] In some embodiments, the first encoded data and the second encoded data are generated via Manchester encoding.

[0011] According to an embodiment of the present invention, a microprocessor device is provided. The microprocessor device includes a serial debugging interface circuit and a debugging access port. The serial debugging interface circuit is coupled to a debugger to receive an output signal. Furthermore, the serial debugging interface circuit decodes a first encoded signal to generate a first data signal and a first clock signal. The output signal is either the first encoded signal or a reset signal, and the first encoded signal is generated by encoding the first data signal and the first clock signal. The debugging access port is coupled to the serial debugging interface circuit. The debugging access port can receive the data signal and the clock signal from the serial debugging interface circuit to perform debugging of the microprocessor device.

[0012] According to an embodiment of the present invention, a debugging method is provided. The debugging method is applicable to a debugging system, wherein the debugging system includes a debugger and a target device. The steps of the debugging method include: outputting an output signal by the debugger, wherein the output signal is a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal; receiving the output signal by a serial debugging interface circuit of the target device; when the output signal is the first encoded signal, decoding the first encoded signal by the serial debugging interface circuit to generate the first data signal and the first clock signal; and receiving the data signal and the clock signal from the serial debugging interface circuit by a debugging access port of the target device to perform debugging of the target device.

[0013] Other additional features and advantages of the present invention can be obtained by those skilled in the art through modifications and refinements based on the debugging system, microprocessor device and debugging method disclosed in the embodiments of this invention, without departing from the spirit and scope of the present invention. Attached Figure Description

[0014] Figure 1 This shows a block diagram of a debugging system 100 according to an embodiment of the present invention.

[0015] Figure 2 A flowchart of a debugging method according to an embodiment of the present invention.

[0016] Icon labels:

[0017] 100: Debugging System

[0018] 110: Debugger

[0019] 120: Target device

[0020] 210: Serial debugging interface circuit

[0021] 211: Judgment Circuit

[0022] 212: Decoder

[0023] 213: Encoder

[0024] 214: Circuit Analysis

[0025] 220: Serial debugging access port

[0026] 230: Processor core

[0027] S out Output signal

[0028] S encode S'encode Encoded signal

[0029] S reset Reset signal

[0030] S data Data signal

[0031] S clock Clock signal

[0032] S210~S240: Steps Detailed Implementation

[0033] This section describes preferred embodiments of the invention and is intended to illustrate the spirit of the invention rather than to limit its scope of protection. The scope of protection of the invention shall be determined by the scope of the claims in this application.

[0034] Figure 1 This shows a block diagram of a debugging system 100 according to an embodiment of the present invention. Figure 1 As shown, the debugging system 100 may include a debugger 110 and a target device 120. Note that, in Figure 1 The block diagrams shown are for illustrative purposes only and are not intended to represent embodiments of the present invention. Figure 1 Limited to.

[0035] According to one embodiment of the present invention, the target device 120 may be a microcontroller unit (MCU) or a chip. For example... Figure 1 As shown, according to an embodiment of the present invention, the target device 120 may include a serial debugging interface circuit 210, a serial wire debug (SWD) debug access port (DAP) 220, and a processor core 230. According to an embodiment of the present invention, the target device 120 may be coupled to the debugger 110 via the serial debugging interface circuit 210 to perform serial debugging. The serial debugging interface circuit 210 may be coupled to the serial debugging access port 220 and the processor core 230. Furthermore, the serial debugging access port 220 may be coupled to the processor core 230. Note that in... Figure 1 The target device 120 shown is merely for illustrative purposes and is not intended to represent an embodiment of the present invention. Figure 1 This is a limitation. Other components may also be included in the target device 120.

[0036] According to an embodiment of the present invention, the serial debugging interface circuit 210 can be applied to serial debugging technology. For example... Figure 1As shown, according to an embodiment of the present invention, the serial debugging interface circuit 210 may include a judgment circuit 211, a decoder 212, an encoder 213 and an analysis circuit 214.

[0037] According to one embodiment of the present invention, the determination circuit 211 may utilize a timer. According to one embodiment of the present invention, when the debugger 110 needs to perform debugging on the target device 120, the debugger 110 sends an output signal S. out The serial debugging interface circuit 210 of the target device 120 is connected. When the judgment circuit 211 of the serial debugging interface circuit 210 receives the output signal S... out Then, the judgment circuit 211 determines whether the period of the currently received output signal is greater than a threshold value (e.g., 100 microseconds (μs), but this invention is not limited thereto). Specifically, in this invention, the period represents the output signal S. out The time elapsed from a high level to a low level or from a low level to a high level.

[0038] When the judgment circuit 211 determines that the period of the currently received output signal is greater than a threshold value, the judgment circuit 211 will determine the output signal S out It is a reset signal S reset And reset signal S reset The signal is transmitted to the processor core 230. According to one embodiment of the present invention, the determination circuit 211 may first reset the signal S... reset The signal is transmitted to processor core 230. According to one embodiment of the present invention, when the reset signal S... reset It is a high-level timing, the target device 120 will not enter the reset, and when the reset signal S reset At a low-level time, the target device 120 enters a reset state.

[0039] When the judgment circuit 211 judges the currently received output signal S out When the period time is not greater than a critical value, the judgment circuit 211 will judge the output signal S. out It is a coded signal S encode Next, the judgment circuit 211 will convert the encoded signal S encode The signal is transmitted to decoder 212. According to one embodiment of the present invention, the encoded signal S output by debugger 110... encode A data signal S is pre-encoded using an encoding technique. data and a clock signal S clock This is generated. According to one embodiment of the present invention, the encoding technique used in the present invention may be Manchester Coding. The decoder 212 will decode the encoded signal S according to the adopted encoding technique. encodeTo generate the data signal S to be transmitted by the debugger 110. data and clock signal S clock Next, the decoder 212 will output the data signal S. data and clock signal S clock The signal is transmitted to the analysis circuit 214.

[0040] According to one embodiment of the present invention, the analysis circuit 214 will analyze the data signal S from the decoder 212. data The command bit (e.g., RnW bit) is used to determine the subsequent data signal S. data and clock signal S clock The transmission direction. That is, the analysis circuit 214 will determine the transmission direction based on the data signal S from the decoder 212. data The command bit (e.g., RnW bit) is used to determine whether the operation requested by the debugger 110 is a write operation (i.e., writing data from the debugger 110 to the target device 120) or a read operation (i.e., reading data from the target device 120 to the debugger 110). According to one embodiment of the present invention, when the command bit is a first value (e.g., 0), the analysis circuit 214 determines the data signal S. data and clock signal S clock To write to target device 120 from debugger 110; and when the command bit is a second value (e.g., 1), analysis circuit 214 determines that data signal S needs to be read from target device 120. data and clock signal S clock To debugger 110. Furthermore, according to one embodiment of the present invention, analysis circuit 214 will analyze the data signal S... data The acknowledgment bit (e.g., ACK bit) in the data signal S indicates whether the data signal S has been successfully received. data When the analysis circuit 214 successfully receives the data signal S data The analysis circuit 214 will be able to analyze the data signal S data The direction of transmission is used to transmit data signal S. data .

[0041] According to an embodiment of the present invention, when the analysis circuit 214 receives the data signal S from the decoder 212 data Determine the data signal S data and clock signal S clock When the transmission direction is to be written from the debugger 110 to the target device 120, the analysis circuit 214 will convert the data signal S decoded by the decoder 212 into a data signal S. data and clock signal S clock The data is transmitted to the serial debugging access port 220. According to one embodiment of the present invention, the analysis circuit 214 can transmit the data signal S via a data path. dataThe serial error-detection access port 220 is provided with a clock signal S transmitted via a clock path. clock Serial debugging access port 220 is provided. Serial debugging access port 220 receives data signal S. data and clock signal S clock Then, the data signal S will be sent. data and clock signal S clock The program is sent to processor core 230 for debugging.

[0042] According to an embodiment of the present invention, when the analysis circuit 214 receives the data signal S from the decoder 212 data Determine the data signal S data and clock signal S clock When the transmission direction needs to be read from the target device 120 to the debugger 110, the analysis circuit 214 will read the data signal S received from the serial debugging access port 220. data and clock signal S clock The data is transmitted to encoder 213. According to one embodiment of the present invention, analysis circuit 214 can receive data signal S from serial debugging access port 220 via a data path. data and clock signal S clock Encoder 213 will transmit the data signal S via an encoding technique (e.g., Manchester Coding). data and clock signal S clock Encode into a coded signal S ’ encode Next, encoder 213 will encode the signal S. ’ encode The signal is transmitted to the judgment circuit 211. The judgment circuit 211 will then transmit the encoded signal S. ’ encode Send to debugger 110.

[0043] According to one embodiment of the present invention, the debugger 110 may also include a decoder and an encoder to decode the encoded signal S. ’ encode and generate coded signal S encode .

[0044] According to the debugging system 100 proposed by the present invention, the target device 120 can transmit the reset signal S to be transmitted by the serial debugging interface by connecting to the debugger 110 via only one pin. reset Data signal S data and clock signal S clockIn other words, the debugging system 100 proposed in this invention can integrate the SWDIO pin, SWDCLC pin, and RESET pin of the serial debugging interface into a single pin. Therefore, the debugging system 100 proposed in this invention can reduce the number of pins required for the target device 120 to perform serial debugging.

[0045] Figure 2 This is a flowchart of a debugging method according to an embodiment of the present invention. The debugging method is applicable to a debugging system 100. Figure 2 As shown, in step S210, an output signal is output by the debugger of the debugging system 100, wherein the output signal is a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal.

[0046] In step S220, the output signal is received by a series of debugging interface circuits of the target device of the debugging system 100.

[0047] In step S230, when the output signal is the first encoded signal, the first encoded signal is decoded by the serial error-detecting interface circuit to generate the first data signal and the first clock signal.

[0048] In step S240, data signals and clock signals are received from the serial debugging interface circuit through a serial debugging access port of the target device to perform debugging of the target device.

[0049] According to an embodiment of the present invention, the debugging method further includes determining, by means of a judgment circuit of the serial debugging interface circuit, whether a period of the output signal is greater than a threshold value, so as to determine whether the output signal is a first encoded signal or a reset signal. When the period of the output signal is greater than the threshold value, the judgment circuit determines that the output signal is a reset signal, and when the period of the output signal is not greater than the threshold value, the judgment circuit determines that the output signal is a first encoded signal.

[0050] According to an embodiment of the present invention, step S230 of the debugging method further includes decoding the first encoded signal by a decoder of a serial debugging interface circuit to generate the first data signal and the first clock signal.

[0051] According to one embodiment of the present invention, the debugging method further includes determining a first transmission direction of the first data signal and the first clock signal based on the first data signal using an analysis circuit of the serial debugging interface circuit, so as to transmit the first data signal and the first clock signal to the serial debugging access port. Furthermore, the debugging method further includes determining, based on the first data signal, that a second data signal and a second clock signal are received from the serial debugging access port from a second transmission direction using the analysis circuit of the serial debugging interface circuit.

[0052] According to an embodiment of the present invention, the debugging method further includes receiving a second data signal and a second clock signal via an encoding circuit of a serial debugging interface circuit, and encoding the second data signal and the second clock signal to generate a second encoded data.

[0053] According to one embodiment of the present invention, in the debugging method, the first encoded data and the second encoded data are generated via Manchester encoding.

[0054] According to the debugging method proposed in this invention, the target device of the debugging system 100 can transmit the reset signal S by simply connecting to the debugger of the debugging system 100 via a single pin. reset Data signal S data and clock signal S clock Therefore, the debugging method proposed in this invention can reduce the number of pins required for serial debugging.

[0055] The serial numbers in this specification and in the scope of the patent application, such as "first," "second," etc., are for illustrative purposes only and there is no sequential relationship between them.

[0056] The steps of the methods and algorithms disclosed in this specification can be directly applied to hardware and software modules or a combination of both by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data memory, such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, optical disc read-only memory (CD-ROM), DVDs, or any other computer-readable storage media format known in the art. A storage media can be coupled to a machine device, for example, such as a computer / processor (referred to as processor in this specification for convenience), through which the processor can read information (such as program code) and write information to the storage media. A storage media can integrate a processor. An application-specific integrated circuit (ASIC) includes a processor and a storage media. A user equipment includes an application-specific integrated circuit. In other words, the processor and storage media are included in the user equipment in a manner that is not directly connected to the user equipment. Furthermore, in some embodiments, any product suitable for computer programs includes a readable storage medium, wherein the readable storage medium includes program code associated with one or more of the disclosed embodiments. In some embodiments, the product of computer programs may include packaging material.

[0057] The preceding paragraphs use multiple levels of description. Clearly, the teachings herein can be implemented in various ways, and any particular architecture or functionality disclosed in the examples is merely a representative case. Based on the teachings herein, any person skilled in the art should understand that the various levels disclosed herein can be implemented independently or that two or more levels can be implemented in combination.

[0058] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the invention shall be determined by the scope of protection defined in the claims of this application.

Claims

1. A debugging system characterized by, include: A debugger outputs an output signal, wherein the output signal is a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal; as well as A target device, comprising: A series of debugging interface circuits, coupled to the debugger via a pin, to receive the first encoded signal or the reset signal via the pin; and to decode the first encoded signal to generate the first data signal and the first clock signal; and A serial debugging access port is coupled to the serial debugging interface circuit, and receives the data signal and the clock signal from the serial debugging interface circuit to perform debugging of the target device; The serial debugging interface circuit further includes: A judgment circuit determines whether the one-cycle time of the output signal is greater than a threshold value, so as to determine whether the output signal is the first encoded signal or the reset signal; When the period of the output signal is greater than a threshold value, the determination circuit determines that the output signal is the reset signal; and when the period of the output signal is not greater than the threshold value, the determination circuit determines that the output signal is the first encoded signal.

2. The debugging system of claim 1, wherein, The serial debugging interface circuit also includes: A decoder, coupled to the judgment circuit, decodes the first encoded signal to generate the first data signal and the first clock signal.

3. The debugging system of claim 2, wherein, The serial debugging interface circuit also includes: An analysis circuit, coupled to the decoder and the serial debugging access port, determines a first transmission direction of the first data signal and the first clock signal based on the first data signal, so as to transmit the first data signal and the first clock signal to the serial debugging access port. The analysis circuit further determines, based on the first data signal, that a second data signal and a second clock signal are received from the serial debugging access port from a second transmission direction.

4. The debugging system according to claim 3, characterized in that, The serial debugging interface circuit also includes: An encoding circuit, coupled to the analysis circuit, receives the second data signal and the second clock signal, and encodes the second data signal and the second clock signal to generate a second encoded data.

5. A microprocessor device, characterized in that, include: A series of debugging interface circuits, coupled to a debugger, are used to receive an output signal and decode a first encoded signal to generate a first data signal and a first clock signal, wherein the output signal is either the first encoded signal or a reset signal; and the first encoded signal is generated by encoding the first data signal and the first clock signal. as well as A serial debugging access port is coupled to the serial debugging interface circuit, and receives the data signal and the clock signal from the serial debugging interface circuit to perform debugging of the microprocessor. The microprocessor device further includes: A judgment circuit determines whether the one-cycle time of the output signal is greater than a threshold value, so as to determine whether the output signal is the first encoded signal or the reset signal; When the period of the output signal is greater than a threshold value, the determination circuit determines that the output signal is the reset signal; and when the period of the output signal is not greater than the threshold value, the determination circuit determines that the output signal is the first coded signal.

6. The microprocessor device according to claim 5, characterized in that, Also includes: A decoder, coupled to the judgment circuit, decodes the first encoded signal to generate the first data signal and the first clock signal.

7. A debugging method, applicable to a debugging system, characterized in that, The debugging system includes a debugger and a target device, and the debugging method includes: The debugger outputs an output signal, wherein the output signal is a first encoded signal or a reset signal, and the first encoded signal is generated by encoding a first data signal and a first clock signal. The output signal is received via a series of debugging interface circuits in the target device; Determine whether the period of the output signal is greater than a threshold value to determine whether the output signal is the first encoded signal or the reset signal, wherein when the period of the output signal is greater than the threshold value, the output signal is determined to be the reset signal, and when the period of the output signal is not greater than the threshold value, the output signal is determined to be the first encoded signal; When the output signal is the first encoded signal, the first encoded signal is decoded by the serial debugging interface circuit to generate the first data signal and the first clock signal; and The data signal and the clock signal are received from the serial debugging interface circuit via a serial debugging access port of the target device in order to perform debugging of the target device.

8. The debugging method according to claim 7, characterized in that, Also includes: An analysis circuit of the serial debugging interface circuit determines a first transmission direction of the first data signal and the first clock signal based on the first data signal, so as to transmit the first data signal and the first clock signal to the serial debugging access port. or The analysis circuit of the serial debugging interface circuit determines, based on the first data signal, that a second data signal and a second clock signal are received from the serial debugging access port from a second transmission direction.

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