Tiled display device

Abstract

A tiled display apparatus includes a setting plate configured to generate a control command signal, and a plurality of display modules connected to each other through a first interface circuit based on a serial communication scheme for performing a target operation corresponding to the control command signal, and the first interface circuit is implemented through a bidirectional serial interface having a feedback loop type between adjacent display modules of the plurality of display modules.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194683, filed on December 31, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to scalable tiled display devices. Background Technology

[0004] Large-size displays can be used in various fields such as indoor and outdoor digital advertising. To meet the demand for large-size displays, expandable tiled display devices have been proposed. In tiled display devices, a single screen is configured by connecting multiple display modules, and the desired screen size can be achieved by adjusting the number of interconnected display modules.

[0005] In such tiled display devices, the reliability and speed of data communication may be reduced because multiple display modules are interconnected over long distances, and the synchronization between clock and data may be difficult, leading to a decrease in data reliability. Summary of the Invention

[0006] To overcome the above problems, this disclosure is intended to provide a tiled display device for performing large-scale communication with fast data communication speed and high reliability, and a driving method for the tiled display device.

[0007] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, a tiled display device includes: a setting board configured to generate control command signals; and a plurality of display modules interconnected via a first interface circuit based on a serial communication scheme for performing target operations corresponding to the control command signals, wherein the first interface circuit is implemented using a bidirectional serial interface having a feedback loop type between adjacent display modules of the plurality of display modules. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] In the attached diagram:

[0010] Figure 1 This is a schematic diagram illustrating a tiled display device according to one aspect of this disclosure;

[0011] Figure 2 This is a diagram showing the connection configuration of the display module;

[0012] Figure 3 and Figure 4 This is a diagram showing a display panel based on miniature light-emitting diodes (LEDs);

[0013] Figure 5 It is a schematic equivalent circuit diagram of the pixels included in the display panel;

[0014] Figures 6 to 8 This is a diagram illustrating the connection structure of a tiled display device according to one aspect of this disclosure;

[0015] Figures 9 to 11 This is a diagram illustrating an example of the operation of a tiled display device according to one aspect of this disclosure;

[0016] Figure 12 This is a diagram illustrating the operation of a tiled display device in basic communication mode according to one aspect of this disclosure;

[0017] Figure 13A and Figure 13B This is a diagram illustrating the operation of a tiled display device in bypass communication mode according to one aspect of this disclosure;

[0018] Figure 14 This is a diagram illustrating the operation of a tiled display device in an asynchronous overlapping communication mode according to one aspect of this disclosure;

[0019] Figure 15 This diagram illustrates the operation when a check flag error occurs in bypass communication mode;

[0020] Figure 16 This is a diagram illustrating the operation when a check flag error occurs in asynchronous overlapping communication mode;

[0021] Figure 17 This is a diagram illustrating the operation when a check flag error occurs in synchronous overlapping communication mode;

[0022] Figure 18 and Figure 19 This is a diagram illustrating the operation of a tiled display device in synchronous overlapping communication mode according to an embodiment of the present disclosure;

[0023] Figure 20 This is a diagram illustrating the configuration of a timing controller for implementing multiple communication modes in a tiled display device according to an embodiment of the present disclosure; and

[0024] Figure 21This is a diagram illustrating an example of the implementation of a multi-channel synchronization signal for realizing a synchronous overlapping communication mode in a tiled display device, according to one aspect of this disclosure. Detailed Implementation

[0025] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary aspects of the disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the aspects set forth herein; rather, these aspects are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art.

[0026] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0027] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to describe various aspects of this disclosure are merely exemplary, and this disclosure is not limited thereto. Similar reference numerals always refer to similar elements. Throughout this specification, the same elements are represented by the same reference numerals. As used herein, the terms “comprising,” “having,” “including,” etc., indicate that additional parts may be added, unless the term “only” is used. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0028] Even in the absence of explicit statement, elements in various aspects of this disclosure should be interpreted as including error margins.

[0029] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "below," and "next to," one or more other parts may be arranged between the two parts, unless "exactly" or "directly" is used.

[0030] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0031] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where such descriptions would unnecessarily obscure the focus of this disclosure. Aspects of this disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic diagram of a tiled display device 100 according to one aspect of this disclosure. Figure 2 This is a diagram showing the connection configuration of the display module.

[0033] Reference Figure 1 and Figure 2 According to one aspect of this disclosure, the tiled display device 100 may include a setup board SET and a plurality of display modules CB. Each of the display modules CB may be referred to as a cabinet.

[0034] Display modules (CBs) can be interconnected via a serial interface circuit to configure a large screen. The total resolution of the large screen can be determined by the sum of the unit resolutions of each display module (CB). For example, in the case of configuring a screen with eight display modules each having a unit resolution of 960*1080, the total screen resolution can be 3840*2160.

[0035] Each display module CB can be implemented as an electroluminescent display type or a liquid crystal display type, and in the following aspects, it is shown that the display module CB is implemented as an electroluminescent display type based on micro light-emitting diodes (LEDs). However, the spirit of this disclosure is not limited to the implementation type of the display module CB.

[0036] The display modules CB can be interconnected via a first interface circuit based on a bidirectional serial communication scheme to execute target operations corresponding to control command signals input from the setting board SET. The first interface circuit can be implemented as a bidirectional multi-link port with a feedback loop type between adjacent display modules CB.

[0037] Individual bidirectional serial communication can be performed between display modules CB via the first interface circuit, and therefore, short communication lines can be ensured, and the reliability and speed of large-scale data communication performed via short communication lines can be enhanced.

[0038] The first display module CB can be connected to the setting board SET via a second interface circuit. The second interface circuit can be implemented as a unidirectional serial interface for compatibility with the setting board SET. However, the second interface circuit can also be implemented as a bidirectional serial interface, increasing the communication speed between the setting board SET and the first display module CB.

[0039] The first interface circuit can be implemented as a bidirectional dual serial peripheral interface (SPI), and the second interface circuit can be implemented as a unidirectional single SPI. The first and second interface circuits can be implemented via wired or wireless connections.

[0040] Specifically, in the first interface circuit (i.e., bidirectional dual SPI), each SPI can use only unidirectional TX (SCLK, MOSI, and SS) to reliably transmit large amounts of data. Based on this characteristic, wireless schemes can be applied efficiently without considering the delay difference between RX (MISO) and TX (SCLK, MOSI, and SS).

[0041] Each display module CB may include: multiple display panels PNL; multiple panel driving circuits for driving the display panels PNL; and multiple timing controllers TCON, the multiple timing controllers TCON controlling the operation timing of the control panel driving circuit.

[0042] The timing controller TCON can be connected to one or more of the first interface circuit and the second interface circuit. The timing controller TCON included in the first display module of the display module CB can be connected to the setting board SET via the second interface circuit, and can also be connected to an adjacent display module via the first interface circuit. The timing controller TCON included in each of the other display modules CB besides the first display module can be connected to an adjacent display module via the first interface circuit.

[0043] The timing controller TCON for each display module CB can be mounted on the control printed circuit board CPCB and can be connected in parallel to the panel drive circuit of the corresponding display module CB via a branch cable CBL.

[0044] The panel driving circuit can be independently included in each of the multiple display panels PNL configured with the same display module CB. The panel driving circuit may include: a source printed circuit board SPCB connected to the timing controller TCON via a cable CBL; a memory circuit MEM mounted on the source printed circuit board SPCB; a conductive film COF electrically connecting the source printed circuit board SPCB to the display panel PNL; a data driver SIC bonded to the conductive film COF; and a gate driver and power supply circuit electrically connected to the source printed circuit board SPCB.

[0045] The memory circuit MEM can be a non-volatile memory storing panel characteristic information, and can be flash memory and / or electrically erasable programmable read-only memory (EEPROM). The panel characteristic information may include correction values ​​for gamma settings, first compensation values ​​for compensating for drive characteristic deviations / color deviations between pixels, second compensation values ​​for compensating for boundary deviations between adjacent display panel PNLs, and various image quality and drive control data. A large portion of the panel characteristic information can be stored in flash memory, and a small portion can be stored in EEPROM.

[0046] The timing controller TCON can operate the panel drive circuit based on control command signals received through a control interface circuit, such as a Serial Peripheral Interface (SPI), to execute target operations corresponding to the control command signals. Therefore, it can generate a control response signal that includes the execution result of the target operation. Target operations may include reset, squelch (dark field transition), average image level (APL) range change, gamma change, image quality compensation value update, and firmware update. Target operations may also include writing and storing control command data in a specific memory and reading control execution data from a specific memory. The control response signal may include control execution data and check flag signals for sending / receiving error checks, thus increasing operational reliability.

[0047] Figure 3 and Figure 4 This is a diagram showing a display panel based on miniature light-emitting diodes (LEDs). Figure 5 It is a schematic equivalent circuit diagram of the pixels included in the display panel.

[0048] Reference Figure 3 and Figure 4 A pixel array for reproducing the input image can be set in each of the display panel PNLs. Multiple pixels can be arranged in the pixel array, and signal lines for driving the pixels can be arranged in the pixel array. The signal lines may include: multiple data lines DL for supplying a data voltage Vdata to the pixel; multiple gate lines GL for supplying a gate signal GSIG to the pixel; and multiple power lines for supplying a source voltage to the pixel.

[0049] Each pixel may include a micro LED chip (μLED chip) as a light-emitting device (EL). Multiple micro LED chips (μLED chips) may include a red chip (μLED chip_R), a green chip (μLED chip_G), and a blue chip (μLED chip_B) disposed on a thin-film transistor (TFT) backplane. A red (R) pixel may include a red chip (μLED chip_R) as a light-emitting device (EL), a green (G) pixel may include a green chip (μLED chip_G) as a light-emitting device (EL), and a blue (B) pixel may include a blue chip (μLED chip_B) as a light-emitting device (EL).

[0050] Micro-LED chips (μLED chips) can be transferred from R donors / G donors / B donors and thus can be mounted on a TFT backplane. Red chips (μLED chip_R) can be transferred from R donors, green chips (μLED chip_G) from G donors, and blue chips (μLED chip_B) from B donors. Transfer techniques can utilize electrostatic forces, lasers, velocity-dependent viscous forces, and load-dependent viscous forces. Transfer techniques are not limited to these and electrostatic force-based self-assembly can also be used.

[0051] TFT backplanes can be implemented as active matrix structures for efficient driving. In a TFT backplane, pixels can be defined by the intersections of data lines (DL), gate lines (GL), and power lines.

[0052] Multiple pixels can be configured into a single unit pixel. For example, adjacent R, G, and B pixels can be configured into a single unit pixel along the extension direction of the gate line GL or the data line DL.

[0053] As in Figure 5 In this process, the pixel PXL may include a light-emitting device EL, a driving TFT DT, and a node circuit NCON.

[0054] The node circuit NCON can be connected to the gate line GL and the data line DL. A data voltage Vdata can be supplied to the node circuit NCON via the data line DL, and a gate signal GSIG can be supplied to the node circuit NCON via the gate line GL. The node circuit NCON can synchronously apply the data voltage Vdata and the gate signal GSIG to the gate electrode of the driving TFT DT, and therefore, the gate-source voltage of the driving TFT DT can be set based on the conditions used to generate the drive current. The node circuit NCON may include internal compensation circuitry that senses the threshold voltage and / or electron mobility of the driving TFT DT to compensate for the gate voltage of the driving TFT DT.

[0055] A driving TFT DT can be a driving element that generates a driving current based on its gate-source voltage. The gate electrode of the driving TFT DT can be connected to the node circuit NCON, its first electrode (drain electrode) can be connected to the high-level pixel power supply VDD, and its second electrode (source electrode) can be connected to the light-emitting device EL.

[0056] A light-emitting device (EL) can be a device that emits light with an intensity corresponding to the driving current input from a driving TFT DT. The EL can be implemented using a micro-LED comprising an inorganic light-emitting layer. The first electrode of the EL can be connected to the driving TFT DT, and its second electrode can be connected to a low-level pixel power supply VSS.

[0057] The connection configuration and operation of a pixel PXL can be merely one implementation method, and the spirit of this disclosure is not limited thereto. For example, each of the driving TFT DT and the node circuit NCON can be implemented based on a PMOS transistor, or it can be implemented based on an NMOS transistor. Furthermore, multiple gate lines GL connected to the node circuit NCON can be configured.

[0058] Figures 6 to 8 This is a diagram illustrating the connection structure of a tiled display device according to one aspect of this disclosure.

[0059] Reference Figures 6 to 8 The SET board and the first timing controller TCON1 of the first display module can be connected to each other via a single SPI.

[0060] A single SPI can be a second interface circuit IF2, and can be configured as a unidirectional serial interface.

[0061] In a single SPI configuration, the master can be a setup board (SET), and the slave can be a first timing controller (TCON1). The master port (MA) of the setup board (SET) can be connected to the first slave port (SL1) of the first timing controller (TCON1), thus enabling a single SPI configuration.

[0062] The transmit / receive operation of a single SPI can be synchronized based on the clock CLK, which is the master output. The attribute used to set the basic state of the clock CLK can be called clock polarity CPOL. The attribute used to set the edge of the clock CLK from which the data to be transmitted can be called clock phase CPHA. For example, when CPOL or CPHA is logic low (0), data (i.e., control command signals) can be transmitted from the master port MA to the first slave port SL1 when the clock CLK switches from a low state to a high state (i.e., the rising edge of the clock). On the other hand, when CPOL or CPHA is logic high (1), data (i.e., control command signals) can be transmitted from the master port MA to the first slave port SL1 when the clock CLK switches from a high state to a low state (i.e., the falling edge of the clock).

[0063] In a single SPI, the Master Output Slave Input (MOSI) represents data output from the master (SET) and input to the slave (TCON1) (i.e., a control command signal), and the Master Input Slave Output (MISO) represents data output from the slave (TCON1) and input to the master (SET) (i.e., a control response signal). The Slave Select (SS) in a single SPI configuration can be a signal that selects the slave (TCON1).

[0064] The master (SET) and slave (TCON1) can serially send or receive data bits via the MOSI port. In the data transmitted from the master (SET) to the slave (TCON1), the most significant bit can be transmitted first. The slave (TCON1) and master (SET) can serially transmit and receive data bits between each other via the MOSI port. In the data transmitted from the slave (TCON1) to the master (SET), the least significant bit can be transmitted first.

[0065] Reference Figures 6 to 8 The first timing controllers TCON1 to TCONm of the first display module to the m-th display module can be interconnected via dual SPI. The dual SPI can be a first interface circuit IF1, and can be configured with a bidirectional serial interface of the feedback loop type.

[0066] Each of the first timing controllers TCON1 to the m-th timing controller TCONm can include a first master port MA1, a first slave port SL1, a second master port MA2, and a second slave port SL2, thereby enabling dual SPI among the first timing controllers TCON1 to the m-th timing controller TCONm.

[0067] The first master port MA1 and the first slave port SL1 included in each of the first timing controllers TCON1 to the m-th timing controller TCONm can be used to transmit control command signals to the adjacent timing controller via forward SPI (F-SPI).

[0068] The second master port MA2 and the second slave port SL2 included in each of the first timing controllers TCON1 to the m-th timing controller TCONm can be used to transmit control response signals to the adjacent timing controller via reverse SPI (R-SPI).

[0069] For example, in a forward SPI (F-SPI) between a first timing controller TCON1 and a second timing controller TCON2, the master can be the first timing controller TCON1, and the slave can be the second timing controller TCON2. In this case, the first master port MA1 of the first timing controller TCON1 can be connected to the first slave port SL1 of the second timing controller TCON2 via a forward SPI (F-SPI).

[0070] In a forward F-SPI, the Master Output / Slave Input (MOSI) can represent data (i.e., control command signals) output from the master TCON1 and input to the slave TCON2. The data can be transferred to the target slave's memory circuit MEM and can bypass the slave TCON2. The Master Input / Slave Output (MISO) can be excluded from use in a forward F-SPI.

[0071] MISO is not used for forward SPI (F-SPI) because it is unsuitable for high-speed, large-scale communication in a structure where multiple timing controllers (TCONs) are serially connected to each other over long distances. Data must be synchronized with the clock CLK to be read via MISO, and therefore, the speed can be slowed down whenever data passes through a timing controller (TCON), and it can be difficult to determine the timing of data reading from the slave in the master, regardless of the communication between adjacent timing controllers (TCONs). On the other hand, the problems described above can be easily solved by transferring data from the master to the slave via MOSI using reverse SPI (R-SPI).

[0072] In the reverse SPI (R-SPI) between the first timing controller TCON1 and the second timing controller TCON2, the master can be the second timing controller TCON2, and the slave can be the first timing controller TCON1. ​​In this case, the second master port MA2 of the second timing controller TCON2 can be connected to the second slave port SL2 of the first timing controller TCON1 via the reverse SPI (R-SPI). The master output / slave input MOSI of the reverse SPI (R-SPI) can represent data output from the master TCON2 and input to the slave TCON1 (i.e., control response signal). The control response signal can be data read from the memory circuit MEM of the target slave, or it can be a check flag signal used to determine whether the data transmitted to the forward SPI (F-SPI) (i.e., control command signal) is normal. The master input / slave output MISO can be not used for the reverse SPI (R-SPI). The slave select SS of the reverse SPI (R-SPI) can be a signal used to select the slave TCON1.

[0073] The SET board can transmit multiple synchronization signals SYNC to the timing controllers TCON1 to TCONm via a separate third interface circuit IF3. The multiple synchronization signals SYNC can be used in the overlapping communication scheme described below, and can ensure that the execution time of the target operation is matched across all display modules, thereby reducing screen flicker caused by communication time differences. The multiple synchronization signals SYNC can also be transmitted to the timing controllers TCON1 to TCONm via the first interface circuit IF1 and the second interface circuit IF2, in which case the third interface circuit IF3 can be omitted.

[0074] The setup board SET can transmit image data used to implement the input image to the timing controllers TCON1 to TCONm via a separate fourth interface circuit IF4. The fourth interface circuit IF4 can be implemented based on a V x 1 scheme that enables high-speed and high-capacity interfaces, but is not limited to this.

[0075] The dual SPI described above cannot be replaced by a feedback-type V x 1 (Vx1). In the feedback-type V x 1 (Vx1) model, when a problem occurs in one of the timing controllers TCON1 to TCONm, the feedback signal may fail to be transmitted to the corresponding timing controller, and therefore, overall communication may fail. In the dual SPI model according to this aspect, the preceding timing controller TCONn-1 can perform normal communication in both directions until the timing controller TCONn that has the problem occurs, and therefore, the location of the timing controller TCONn that has the problem can be accurately detected. In this case, n can be a natural number greater than 1 and less than m.

[0076] Figures 9 to 11This is a diagram illustrating an example of the operation of a tiled display device according to one aspect of this disclosure.

[0077] Reference Figure 9 The control command signals generated by the SET board can be transmitted via forward SPI (F-SPI) to the Nth TCON of the timing controller of the target display module. A single data transmission packet of the control command signal can be divided into a header area H, a data area D, and an information area I. The header area H may include location information about the target display module and a command signal CMD indicating the type of control command (e.g., memory read command, memory write command, reset command, automatic identification (ID) generation command, etc.). The data area D may include the control command data. The information area I may include check flag signals for sending / receiving error checking.

[0078] Reference Figure 9 The control response signal generated by the Nth TCON of the timing controller of the target display module can be fed back to the setup board SET via reverse SPI (R-SPI). A single data transmission packet of the control response signal can be divided into a header area H, a data area D, and an information area I. The header area H may include location information about the target display module (the first timing controller or setup board) and an ACK command indicating whether the command signal CMD is functioning correctly. The data area D may include control execution data (values ​​read from a specific memory circuit MEM). The information area I may include a check flag signal CFG for sending / receiving error checking.

[0079] For example, as in Figure 10 and Figure 11 In this configuration, the control command signal generated by the SET board can bypass display modules #1 to #3 via the MOSI of the forward SPI F-SPI and can be transmitted up to display module #4, which serves as the target display module. The timing controller TCON included in display modules #1 to #3 can analyze the header area included in the control command signal to transmit the control command signal to the adjacent display module in the forward direction without executing the control command data.

[0080] The timing controller TCON included in display module #4 can analyze the header area to execute control command data. That is, it can read information from the flash memory of display module #4 and store the read information in any buffer to generate a check flag signal. The read information and the check flag signal can be control response signals.

[0081] The control response signal generated by the timing controller TCON included in display module #4 can bypass display modules #3 and #2 via the MOSI of the reverse SPIR-SPI and can be transmitted up to display module #1.

[0082] The SET board can receive and store control response signals from the display module #4 via the MISO of the second interface circuit (single SPI), and can check whether an error has occurred in the check flag signal included in the control response signal. The control process can end when no error has occurred in the check flag signal.

[0083] exist Figure 11 In this context, "M / C" can represent the memory controller, and "R-EN" can represent the read enable signal. Figure 11 In this context, "Y" can be a shorter time than "X," and therefore, burst data read commands can be transmitted and executed between the setup board SET and the target display module #4. Regardless of the location of the target display module, the communication time for burst data read commands can be nearly equal through bypass operation. As can be seen from this example, even when multiple display modules are arranged between the setup board SET and the target display module #4, the communication time can be significantly reduced through bypass operation.

[0084] Figure 12 This is a diagram illustrating the operation of a tiled display device in basic communication mode according to one aspect of this disclosure.

[0085] Reference Figure 12 In basic communication mode, the SET board can individually check the communication results from each of the timing controllers TCON1 to TCON4 (i.e., check the flag signal CFG), and then can execute the next-level timing controller (one of the timing controllers TCON2 to TCON5).

[0086] In basic communication mode, when memory data needs to be changed for timing controllers TCON1 to TCON5, a total communication time of "15X" may be required.

[0087] Figure 13A and Figure 13B This is a diagram illustrating the operation of a tiled display device in bypass communication mode according to one aspect of this disclosure.

[0088] Reference Figure 13A and Figure 13B In bypass communication mode, the setting board SET can sequentially change the memory data of the first memory display module to the fifth memory display module through five bypass communications for each of the timing controllers TCON1 to TCON5. In this case, the overall communication can be completed in a relatively short time (e.g., about 5X) based on the bypass scheme.

[0089] The bypass scheme can be as follows, wherein the control command signal is transmitted rapidly to the target timing controller via a forward SPI through one or more interconnected timing controllers, and the control response signal (e.g., check flag signal CFG) generated by the target timing controller is transmitted rapidly to the first timing controller TCON1 via a reverse SPI through one or more interconnected timing controllers.

[0090] One or more timing controllers transmitting control command signals can store and analyze only the header area of ​​the control command signal, and can transmit the control command signal to the adjacent timing controller in the forward direction without executing the control command data. Similarly, one or more timing controllers transmitting control response signals can analyze only the header area of ​​the control response signal, and can feed the control response signal back to the adjacent timing controller in the reverse direction. When the control response signal is stored in a specific register of the first timing controller TCON1 through the feedback process, the setup board SET can receive the control response signal from that specific register via a single SPI MISO. Furthermore, when the first timing controller TCON1 is connected to the setup board SET via dual SPIs, the setup board SET can receive the control response signal via a dual SPI reverse MOSI.

[0091] To provide a detailed description, the setup board SET can change the memory data of the first display module via the first bidirectional communication with the first timing controller TCON1, and can receive the check flag signal CFG generated by the first timing controller TCON1, where the communication time spent can be "X".

[0092] The setting board SET can change the memory data of the second display module via the second bidirectional communication with the second timing controller TCON2, and can receive the check flag signal CFG generated by the second timing controller TCON2. In this case, the communication time spent can be "X+Y1". Here, "Y1" can be the time spent in the bypass operation (i.e., header area analysis) performed in the first timing controller TCON1, and can be much shorter than "X". Therefore, the time spent in the second bidirectional communication can be approximately "X". The first timing controller TCON1 may not generate the check flag signal CFG, and only the second timing controller TCON2 may generate the check flag signal CFG.

[0093] The SET board can change the memory data of the third display module via the third bidirectional communication with the third timing controller TCON3, and can receive the check flag signal CFG generated by the third timing controller TCON3. In this case, the communication time spent can be "X + Y2". Here, "Y2" can be the time spent in the bypass operation (i.e., header area analysis) performed by the first timing controller TCON1 and the second timing controller TCON2, and can be much shorter than "X". Therefore, the time spent in the third bidirectional communication can be approximately "X". The first timing controller TCON1 and the second timing controller TCON2 may not generate the check flag signal CFG, and only the third timing controller TCON3 may generate the check flag signal CFG.

[0094] The SET board can change the memory data of the fourth display module via the fourth bidirectional communication with the fourth timing controller TCON4, and can receive the check flag signal CFG generated by the fourth timing controller TCON4. In this case, the communication time spent can be "X + Y3". Here, "Y3" can be the time spent in the bypass operation (i.e., header area analysis) performed by the first timing controller TCON1 to the third timing controller TCON3, and can be much shorter than "X". Therefore, the time spent in the fourth bidirectional communication can be approximately "X". The first timing controller TCON1 to the third timing controller TCON3 may not generate the check flag signal CFG, and only the fourth timing controller TCON4 may generate the check flag signal CFG.

[0095] The SET board can change the memory data of the fifth display module via the fifth bidirectional communication with the fifth timing controller TCON5, and can receive the check flag signal CFG generated by the fifth timing controller TCON5. In this case, the communication time spent can be "X + Y4". Here, "Y4" can be the time spent in the bypass operation (i.e., header area analysis) performed by the first timing controller TCON1 to the fourth timing controller TCON4, and can be much shorter than "X". Therefore, the time spent in the fifth bidirectional communication can be approximately "X". The first timing controller TCON1 to the fourth timing controller TCON4 may not generate the check flag signal CFG, and only the fifth timing controller TCON5 may generate the check flag signal CFG.

[0096] Therefore, in bypass communication mode, the time spent changing memory data for the first timing controller TCON1 to the fifth timing controller TCON5 can be approximately "5X". Thus, compared to the basic communication mode, bypass communication mode can reduce communication time and increase communication speed.

[0097] Figure 14 This is a diagram illustrating the operation of a tiled display device in an asynchronous overlapping communication mode according to one aspect of this disclosure.

[0098] Reference Figure 14 In asynchronous overlapping communication mode, the setting board SET can sequentially change the memory data of the first to fifth display modules through one bypass communication with all timing controllers TCON1 to TCON5, and therefore, the overall communication can be completed in a very short time (e.g., about X) through the asynchronous overlapping communication scheme.

[0099] The asynchronous overlapping communication scheme can be as follows, wherein control command signals are rapidly transmitted to each of the timing controllers TCON1 to TCON5 via forward SPI, and control response signals (e.g., check flag signal CFG) generated by each of the timing controllers TCON2 to TCON5 are rapidly fed back to the first timing controller TCON1 via reverse SPI.

[0100] Each of the timing controllers TCON1 through TCON4 can analyze the header area of ​​the control command signal and store the control command data in the target memory while simultaneously transmitting the control command signal to the adjacent timing controller in the forward direction. Each of the timing controllers TCON1 through TCON5 can generate a control response signal that includes the execution result of the control command. The control response signal (e.g., the check flag signal CFG) can be transmitted to the adjacent timing controller via reverse SPI and updated, and then fed back to the first timing controller TCON1. ​​When all control response signals generated by the timing controllers TCON1 through TCON5 are stored in a specific register of the first timing controller TCON1 through a feedback process based on the update scheme, the setup board SET can receive the control response signals from the specific register via the MISO of a single SPI.

[0101] To provide a detailed description, the setup board SET can change the memory data of the display module for all timing controllers TCON1 to TCON5 via a single bidirectional communication, and can receive the check flag signal CFG generated by timing controllers TCON1 to TCON5 from the first timing controller TCON1. ​​In this case, the communication time spent can be "X + Y4". Here, "Y4" can be the time spent in the bypass operation (i.e., header area analysis) performed by timing controllers TCON1 to TCON4, and can be much shorter than "X". Therefore, the time spent in a single bidirectional communication can be approximately "X".

[0102] Therefore, in asynchronous overlapping communication mode, the time spent changing memory data for timing controllers TCON1 to TCON5 can be approximately "X". Thus, compared to the basic communication mode, asynchronous overlapping communication mode can significantly reduce communication time and greatly improve communication speed.

[0103] Figure 15 This is a diagram illustrating the operation when a check flag error occurs in bypass communication mode. Figure 16 This is a diagram illustrating the operation when a check flag error occurs in asynchronous overlapping communication mode. Figure 17 This is a diagram illustrating the operation when a check flag error occurs in synchronous overlapping communication mode.

[0104] exist Figures 15 to 17 In the diagram, the area with diagonal stripes represents the screen of the display module executing control commands (APL and gamma changes of specific colors), while the area shown in white represents the screen of the display module not executing control commands.

[0105] Reference Figure 15 In bypass communication mode, because each of the timing controllers TCON1 through TCON5 is set to the target sequentially, the image quality of the first through fifth display modules can be changed sequentially. For example, when operating in bypass communication mode, if an error occurs in the check flag signal generated by a specific timing controller (e.g., TCON4), the SET board can re-execute the bypass communication process from the timing controller TCON4 where the error occurred. In this case, the time spent changing the image quality of all the first through fifth display modules can be approximately 6X.

[0106] In bypass communication mode, since the image quality of the first to fifth display modules is changed sequentially, the screen flicker caused by the change in image quality can be detected by the eye, and continuous screen flicker may occur when the error of the check flag signal is repeated.

[0107] Reference Figure 16 In asynchronous overlapping communication mode, timing controllers TCON1 to TCON5 can be simultaneously set as targets, and the image quality of the first to fifth display modules can be changed sequentially with a small time difference. For example, when operating in asynchronous overlapping communication mode, if an error occurs in the check flag signal generated by a specific timing controller (e.g., TCON4), the setting board SET can re-execute the overlapping communication process of timing controllers TCON1 to TCON5. In this case, the time spent changing the image quality of all display modules from the first to the fifth display module can be approximately 2X.

[0108] In asynchronous overlapping communication mode, since the image quality of the first to fifth display modules changes sequentially with a small time difference, screen flicker caused by the change in image quality may not cause much inconvenience. However, continuous screen flicker may occur when the check flag signal is repeatedly erroneously checked.

[0109] Reference Figure 17 In synchronous overlapping communication mode, timing controllers TCON1 to TCON5 can be simultaneously set as targets, and the image quality of the first to fifth display modules can be changed simultaneously based on the multi-channel synchronization signal SYNC. For example, when operating in synchronous overlapping communication mode, if an error occurs in the check flag signal generated by a specific timing controller (e.g., TCON4), the setting board SET can re-execute the overlapping communication process of timing controllers TCON1 to TCON5. In this case, the time spent changing the image quality of all display modules from the first to the fifth display module can be approximately 2X.

[0110] In synchronous overlapping communication mode, control command signals can be stored sequentially in temporary buffers of the first to fifth display modules with a small time difference. Then, the target memory of the first to fifth display modules can be updated simultaneously based on the multi-channel synchronization signal SYNC. Therefore, since the image quality of the first to fifth display modules is changed simultaneously based on the multi-channel synchronization signal SYNC, screen flicker caused by image quality changes can be prevented, and continuous screen flicker will not occur when the check flag signal is checked for error repetition.

[0111] Figure 18 and Figure 19 This is a diagram illustrating the operation of a tiled display device in synchronous overlapping communication mode according to one aspect of this disclosure.

[0112] Reference Figure 18 and Figure 19 In synchronous overlapping communication mode, the setting board SET can simultaneously change the memory data of the first to fifth display modules through one bypass communication for all timing controllers TCON1 to TCON5, and therefore, the overall communication can be completed in a very short time (e.g., about X) through the synchronous overlapping communication scheme.

[0113] Compared to the asynchronous overlapping scheme, the synchronous overlapping scheme may differ in that the execution time of the target operation corresponding to the control command signal is equal in response to the multi-channel synchronization signal SYNC transmitted from the setting board SET, across the first to fifth display modules. Therefore, in the synchronous overlapping scheme, timing controllers TCON1 to TCON5 can sequentially store the control command signal in a temporary buffer, and then simultaneously update the target memory of the first to fifth display modules based on the multi-channel synchronization signal SYNC. According to the synchronous overlapping scheme, screen flicker caused by the time difference Td during the sequential storage of control command signals in the temporary buffer can be prevented.

[0114] Similar to the asynchronous overlapping communication scheme, the synchronous overlapping communication scheme can be as follows, wherein control command signals are rapidly transmitted to each of the timing controllers TCON1 to TCON5 via forward SPI, and control response signals (e.g., check flag signal CFG) generated by each of the timing controllers TCON2 to TCON5 are rapidly fed back to the first timing controller TCON1 via reverse SPI.

[0115] Each of the timing controllers TCON1 through TCON4 can analyze the header area of ​​the control command signal and store the control command data in a temporary buffer while transmitting the control command signal to the adjacent timing controller in the forward direction. Each of the timing controllers TCON1 through TCON5 can generate a control response signal that includes the execution result of the control command. The control response signal (e.g., the check flag signal CFG) can be transmitted to the adjacent timing controller via reverse SPI for updating, and then fed back to the first timing controller TCON1. ​​When all the control response signals generated by the timing controllers TCON1 through TCON5 are stored in a specific register of the first timing controller TCON1 through a feedback process based on the update scheme, the setup board SET can receive the control response signals in the specific register via the MISO of a single SPI.

[0116] The SET board can determine whether an error has occurred in the control response signal, and when no error is found, it can transmit the multi-channel synchronization signal SYNC to the timing controllers TCON1 to TCON5. The timing controllers TCON1 to TCON5 can simultaneously update the control command data stored in the temporary buffer in each specific memory based on the multi-channel synchronization signal SYNC, and therefore, control commands can be executed simultaneously in the first to fifth display modules.

[0117] Figure 20This is a diagram illustrating the configuration of a timing controller for implementing multiple communication modes in a tiled display device, according to one aspect of this disclosure. Figure 21 This is a diagram illustrating an example of the implementation of a multi-channel synchronization signal for realizing a synchronous overlapping communication mode in a tiled display device, according to one aspect of this disclosure.

[0118] Reference Figure 20 and Figure 21 , such as in Figure 8 In this configuration, the SYNC signal can be transmitted from the SET board to the timing controller TCON of each display module via the third interface circuit IF3. In this case, the third interface circuit IF3 can be implemented using transistor logic (TTL).

[0119] It is possible Figure 8 During the idle interval between the first interface circuit IF1 and the second interface circuit IF2, the multi-channel synchronization signal SYNC is transmitted from the setting board SET to the timing controller TCON of each display module via MOSI. This is due to the control command signal (shown as...) Figure 21 The valid data is transmitted via MOSI to the timing controller TCON of each display module during the SPI intervals of the first interface circuit IF1 and the second interface circuit IF2. Therefore, the idle intervals between SPI intervals can be used to transmit the multi-channel synchronization signal SYNC. Thus, the third interface circuit IF3 can be omitted.

[0120] Reference Figure 20 The timing controller TCON may include an SPI receiver RX connected to one of the first interface circuit IF1 and the second interface circuit IF2, a multiplexer MUX, a controller, a temporary buffer, and a mode selector MDS.

[0121] The Mode Selector (MDS) can activate one of the following modes—bypass communication mode, synchronous overlapping communication mode, and asynchronous overlapping communication mode—based on control by the SET board.

[0122] The multiplexer (MUX), controller, and temporary buffer can be activated in synchronous overlapping communication mode and deactivated in other communication modes.

[0123] A temporary buffer can temporarily store control command data received via SPI.

[0124] The multiplexer MUX can select and output one of the multiple synchronization signals SYNC received through the third interface circuit IF3 and the multiple synchronization signals SYNC received through the first interface circuit IF1 and the second interface circuit IF2.

[0125] The controller can update the control command data stored in the temporary buffer to the target memory based on the multi-channel synchronization signal SYNC.

[0126] This aspect can achieve the following effects.

[0127] In this aspect, multiple link ports with feedback loop type can be configured between adjacent display modules, allowing the setup board to individually control multiple display modules interconnected over long distances, and achieving reliable large-scale communication. That is, according to this aspect, multiple display modules can be interconnected via dual SPI interfaces capable of bidirectional communication between them.

[0128] According to this aspect, since each display module includes all master and slave ports for bidirectional dual SPI, all write and read functions can be performed, and therefore, convenience may be increased and maintenance and repair can be easy.

[0129] According to this approach, because each display module includes all master and slave ports for bidirectional dual SPI, individual bidirectional communication can be performed between adjacent display modules, and short communication lines can be ensured. According to this approach, although the number of tiled display modules increases, module select pins do not need to be added to the setup board, and connection lines between the setup board and the display modules do not need to be added; therefore, screen scalability can be easily achieved.

[0130] According to this aspect, since separate feedback bidirectional communication is performed between display modules via short communication lines, the reliability and speed of large-scale data communication can be improved.

[0131] According to this aspect, since separate feedback bidirectional communication is performed between display modules through short communication lines, synchronization between clock and data can be maintained, and data reliability can be greatly improved.

[0132] According to this aspect, based on the bypass communication scheme, the access speed from the setting board to the target display module can be almost equal regardless of the location of the target display module, and therefore, the data communication time can be reduced.

[0133] According to this aspect, the setup board can perform large-scale data communication with almost all display modules simultaneously based on the overlapping communication scheme, and therefore, the data communication time can be greatly reduced.

[0134] According to this aspect, the execution time of the target operation can be matched in all display modules because multiple synchronization signals are further applied to the overlapping communication scheme, thus effectively preventing screen flicker caused by communication time difference.

[0135] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0136] While this disclosure has been specifically shown and described with reference to its exemplary aspects, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A tiled display device, comprising: The settings board is configured to generate control command signals; as well as Multiple display modules are interconnected via a first interface circuit based on a serial communication scheme, and perform target operations corresponding to the control command signals. The first interface circuit is implemented through a bidirectional serial interface, which has a feedback loop type between adjacent display modules of the plurality of display modules. The first interface circuit differs from the separate interface circuit used to send input images between the adjacent display modules. The first interface circuit includes a first transmitting cable, and the separate interface circuit includes a separate transmitting cable that is physically separate from the first transmitting cable.

2. The tiled display device according to claim 1, wherein, The setting board is connected to the first display module of the plurality of display modules via a second interface circuit, and The second interface circuit is implemented through a unidirectional serial interface or the bidirectional serial interface.

3. The tiled display device according to claim 2, wherein, The bidirectional serial interface is implemented as a dual serial peripheral interface (SPI), and The unidirectional serial interface is implemented as a single SPI.

4. The tiled display device according to claim 2, wherein, Each of the plurality of display modules includes: A first master port and a first slave port, configured to transmit the control command signal to an adjacent display module via a serial interface in a first direction; and The second master port and the second slave port are configured to transmit a control response signal corresponding to the control command signal to an adjacent display module via a serial interface in a second direction opposite to the first direction.

5. The tiled display device according to claim 4, wherein, The control command signals include: The header area includes a command signal indicating the type of control command and location information of the target display module to perform the target operation based on the control command signal; This includes the data area for controlling command data; and The information area includes check flag signals used for sending / receiving error checks.

6. The tiled display device according to claim 5, wherein, In the predefined bypass communication mode At least one display module is defined as the target display module, and The control command signal is transmitted to the target display module based on a bypass scheme, in which the control command signal passes through at least one display module via the serial interface in the first direction to reach the target display module.

7. The tiled display device according to claim 6, wherein, The at least one display module transmitting the control command signal stores and analyzes the header area of ​​the control command signal, and transmits the control command signal to a display module adjacent to the at least one display module in the first direction without executing the control command data.

8. The tiled display device according to claim 6, wherein, The target display module generates the control response signal, which includes the execution result of the control command data, and The control response signal is fed back to the first display module based on a bypass scheme, in which the control response signal passes through at least one display module via the serial interface in the second direction to reach the first display module.

9. The tiled display device according to claim 8, wherein, The control response signal includes: This includes the data area that controls the execution of data; and The information area includes check flag signals used for sending / receiving error checks.

10. The tiled display device according to claim 5, wherein, In the predefined asynchronous overlapping communication mode All of the aforementioned display modules are defined as target display modules. Specifically, for each of the target display modules, the control command signal is transmitted to that target display module based on a bypass scheme. In this bypass scheme, the control command signal passes through each display module via the serial interface in the first direction to reach the target display module. The execution time of the target operation corresponding to the control command signal differs among the multiple display modules.

11. The tiled display device according to claim 10, wherein, Each of the plurality of display modules analyzes the header area of ​​the control command signal and transmits the control command signal to the display module adjacent to it in the first direction while storing the control command data in the target memory.

12. The tiled display device according to claim 10, wherein, Each of the plurality of display modules sequentially generates the control response signal, which includes the execution result of the control command data, and The control response signal is updated based on a bypass scheme, in which the control response signal passes through the serial interface in the second direction, through the adjacent display module connected to the display module, and is fed back to the first display module.

13. The tiled display device according to claim 12, wherein, The control response signal includes: This includes the data area for controlling response data; and The information area includes check flag signals used for sending / receiving error checks.

14. The tiled display device according to claim 13, wherein, The control response data and check flag signals of each of the other display modules besides the first display module are reflected in the control response signal that is updated and fed back to the first display module.

15. The tiled display device according to claim 5, wherein, In the predefined synchronous overlapping communication mode All of the aforementioned display modules are defined as target display modules. For each of the target display modules, the control command signal is transmitted to the target display module based on a bypass scheme, in which the control command signal passes through each display module via the serial interface in the first direction to reach the target display module. The execution time of the target operation corresponding to the control command signal is equal in response to the multiple synchronization signals transmitted from the setting board in the plurality of display modules.

16. The tiled display device according to claim 15, wherein, Each of the plurality of display modules analyzes the header area of ​​the control command signal and transmits the control command signal to the display module adjacent to it in the first direction while storing the control command data in a temporary buffer.

17. The tiled display device according to claim 16, wherein, Each of the plurality of display modules stores the control command data stored in the temporary buffer into the target memory based on the multi-channel synchronization signal, and The control command data is stored in the target memory at the same time across the plurality of display modules.

18. The tiled display device according to claim 16, wherein, Each of the plurality of display modules generates a control response signal including the result of receiving the control command data, and The control response signal is updated based on a bypass scheme, in which the control response signal passes through the serial interface in the second direction, through the adjacent display module connected to the display module, and is fed back to the first display module.

19. The tiled display device according to claim 18, wherein, The control response signal includes: This includes the data area for controlling response data; and The information area includes check flag signals used for sending / receiving error checks.

20. The tiled display device according to claim 19, wherein, The control response data and check flag signals of each of the other display modules besides the first display module are reflected in the control response signal transmitted to the first display module via the update.

21. The tiled display device according to claim 15, wherein, The multi-channel synchronization signal and the control command signal are transmitted to the plurality of display modules through the first interface circuit and the second interface circuit. The control command signal is transmitted to the plurality of display modules during the first communication interval between the first interface circuit and the second interface circuit, and The multi-channel synchronization signal is transmitted to the plurality of display modules in a second communication interval arranged between adjacent first communication intervals of the first interface circuit and the second interface circuit.

22. The tiled display device according to claim 15, wherein, The multi-channel synchronization signal is transmitted to the multiple display modules through a third interface circuit, which is different from the first interface circuit.

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