Display device

Abstract

Disclosed is a display device including a display panel on which a plurality of pixels are disposed, a data driver configured to receive a sensing voltage from a reference voltage line connected to the plurality of pixels, convert the sensing voltage into sensing data, and provide a data voltage to the plurality of pixels, a gate driver configured to provide a scan signal to the plurality of pixels, and a timing controller configured to output a data control signal for controlling an output timing of the data voltage, and output a gate control signal for controlling an output timing of the scan signal, wherein one of the output timing of the data voltage and the output timing of the scan signal is adjusted based on the sensing data.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device, and more particularly to a display device capable of compensating for degradation. BACKGROUND

[0002] As a display device for a monitor of a computer, a television (TV), a mobile phone, etc., there are an organic light emitting display (OLED) configured to emit light autonomously and a liquid crystal display (LCD) requiring a separate light source to emit light.

[0003] Among various display devices, an organic light emitting display device includes a display panel including a plurality of sub-pixels, and a driving unit configured to operate the display panel. The driving unit includes a gate driver configured to provide a scan signal to the display panel, and a data driver configured to provide a data voltage. When signals such as the scan signal and the data voltage are provided to the sub-pixels of the organic light emitting display device, the selected sub-pixels can emit light, thereby displaying an image. SUMMARY

[0004] As the operation time of each of the pixels increases, circuit elements such as a driving transistor are degraded. Accordingly, an intrinsic characteristic value of the circuit elements such as the driving transistor can change. Accordingly, the change in the characteristic value of the circuit elements can cause a change in the pixel brightness.

[0005] An object to be achieved by the disclosure is to provide a display device capable of compensating for degradation.

[0006] Another object to be achieved by the disclosure is to provide a display device capable of controlling a data charging rate according to a rate of change in a characteristic value of a circuit element.

[0007] The object of the disclosure is not limited to the above-described objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0008] In one embodiment, a display device includes a display panel on which a plurality of pixels are disposed, a data driver configured to receive a sensing voltage from a reference voltage line connected to the plurality of pixels, convert the sensing voltage into sensing data, and provide a data voltage to the plurality of pixels, a gate driver configured to provide a scan signal to the plurality of pixels, and a timing controller configured to output a data control signal for controlling an output timing of the data voltage, and output a gate control signal for controlling an output timing of the scan signal, wherein one of the output timing of the data voltage and the output timing of the scan signal is adjusted based on the sensing data.

[0009] In one embodiment, a display apparatus includes a display panel including a plurality of pixels, a data driver configured to provide a data voltage to the plurality of pixels and to generate sensing data indicating a characteristic value of a pixel based on a sensing voltage of the pixel received from a reference voltage line connected to the pixel among the plurality of pixels, a gate driver configured to provide a scan signal to the plurality of pixels, and a timing controller configured to generate compensation data compensating for the characteristic value of the pixel and to adjust an amount of overlap time during which the data voltage for the pixel is output while the scan signal is also output to the pixel based on the compensation data.

[0010] In one embodiment, a display apparatus includes a display panel including a plurality of first pixels configured not to emit light and a plurality of second pixels configured to emit light, a data driver configured to provide a data voltage to the plurality of first pixels and the plurality of second pixels and to generate first sensing data indicating a first characteristic value of the plurality of first pixels and to generate second sensing data indicating a second characteristic value of the plurality of second pixels, a gate driver configured to provide a scan signal to the plurality of first pixels and the plurality of second pixels, and a timing controller configured to determine an amount of overlap time during which a first data voltage for the plurality of first pixels is output while a first scan signal is also output to the plurality of first pixels based on the first sensing data, and to adjust an amount of overlap time during which a second data voltage for a second pixel among the plurality of second pixels is output while a scan signal is also output to the second pixel based on at least the determined amount of overlap time for the plurality of first pixels not to emit light.

[0011] Other matters of the exemplary embodiments include in the DETAILED DESCRIPTION and the drawings.

[0012] The present disclosure can compensate for deterioration by changing the on timing of a scan signal and the output timing of a data voltage.

[0013] The present disclosure can compensate for output luminance by controlling a data charging rate.

[0014] Effects according to the present disclosure are not limited to what has been described above with respect to the examples, and include various effects in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic view of a display apparatus according to an embodiment of the present disclosure;

[0017] Figure 2is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure;

[0018] Figure 3 is a block diagram illustrating a display panel of a display device according to an embodiment of the present disclosure;

[0019] Figure 4 is a block diagram illustrating a timing controller of a display device according to an embodiment of the present disclosure;

[0020] Figure 5 is a diagram for explaining an operation of a display device according to an embodiment of the present disclosure within each frame;

[0021] Figure 6 is a signal timing diagram for explaining a sensing process of a display device according to an embodiment of the present disclosure during a blanking period;

[0022] Figure 7A 、 Figure 7B 、 Figure 8A and Figure 8B is a signal timing diagram for explaining a compensation process of a display device according to an embodiment of the present disclosure during an operation time; and

[0023] Figure 9A and Figure 9B is a signal timing diagram for explaining a compensation process in pixels in a plurality of rows of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The advantages and features of the present disclosure and a method of achieving the same will become apparent by referring to exemplary embodiments described below in detail and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein and can be implemented in various forms. The exemplary embodiments are provided by way of example only, so that one of ordinary skill in the art can completely understand the disclosure and the scope of the present disclosure. Therefore, the present disclosure will only be limited by the scope of the claims.

[0025] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the drawings for describing the exemplary embodiments of the present disclosure are merely examples and the present disclosure is not limited thereto. The same reference numerals are generally used throughout the specification to refer to the same elements. Also, in the following description of the present disclosure, detailed descriptions of known related technologies can be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Unless the term is used with the term "only" together, the terms such as "include", "have", and "comprise" used herein are generally intended to allow addition of other components. Unless otherwise explicitly stated, any singular reference can include plural.

[0026] Components are to be interpreted in the broadest possible sense, even if not explicitly stated.

[0027] When a positional relationship between two components is described using terms such as "on", "above", "below", and "near", unless these terms are used together with the term "immediately" or "directly", one or more components can be positioned therebetween.

[0028] When an element or layer is disposed "on" another element or layer, the element or layer can be directly on the other element or layer or other elements or layers can be interposed therebetween.

[0029] Although the terms "first", "second", and the like are used to describe various components, the components are not limited by these terms. The terms are used only to distinguish one component from another. Thus, a first component mentioned below can be a second component in the technical concept of the disclosure.

[0030] The same reference numerals are used throughout the specification to generally designate the same elements.

[0031] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the disclosure is not limited to the size and thickness of the illustrated components.

[0032] The features of various embodiments of the disclosure can be partially or wholly adhered or combined to each other, and can be interlocked and operated in various technical ways, and the embodiments can be executed independently of or in association with each other.

[0033] The transistor for the display device according to the present disclosure can be implemented as one or more of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an active layer made of an oxide semiconductor or a low-temperature polysilicon (LTPS) transistor having an active layer made of low-temperature polysilicon (LTPS). The transistor can include at least a gate, a source, and a drain. The transistor can be implemented as a thin film transistor (TFT) on a display panel. In the transistor, carriers flow from the source to the drain. Since the carriers are electrons in the n-channel transistor (NMOS), the source voltage is lower than the drain voltage, so that the electrons flow from the source to the drain. In the n-channel transistor (NMOS), current can flow from the drain to the source, and the source can be an output terminal. Since the carriers are positive holes in the p-channel transistor (PMOS), the source voltage is higher than the drain voltage, so that the positive holes flow from the source to the drain. Since the positive holes in the p-channel transistor (PMOS) flow from the source to the drain, current can flow from the source to the drain, and the drain can be an output terminal. Thus, it should be noted that the source and the drain of the transistor are not fixed, because the source and the drain can be changed depending on the applied voltage. The present specification is described on the assumption that the transistor is an n-channel transistor (NMOS). However, the present disclosure is not limited thereto. A p-channel transistor can be used as the transistor. Thus, the circuit configuration can be changed.

[0034] The gate signal of the transistor using the switching element swings between an on voltage and an off voltage. The on voltage is set to a voltage greater than the threshold voltage Vth of the transistor. The off voltage is set to a voltage less than the threshold voltage Vth of the transistor. The transistor is turned on in response to the on voltage. In contrast, the transistor is turned off in response to the off voltage. In the case of an NMOS, the on voltage can be a high voltage, and the off voltage can be a low voltage. In the case of a PMOS, the on voltage can be a low voltage, and the off voltage can be a high voltage.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a schematic view of a display device according to an embodiment of the present disclosure.

[0037] Referring to Figure 1 , the display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0038] The display panel 110 is a panel configured to display an image. The display panel 110 can include various circuits, lines, and light emitting elements disposed on a substrate. The display panel 110 can include a plurality of pixels PX defined by a plurality of data lines DL and a plurality of gate lines GL crossing each other. The plurality of pixels PX are connected to the plurality of data lines DL and the plurality of gate lines GL. The display panel 110 can include a display area defined by the plurality of pixels PX and a non-display area in which various types of signal lines or various pads are formed. The display panel 110 can be implemented as a display panel 110 for various display apparatuses such as a liquid crystal display apparatus, an organic light emitting display apparatus, and an electrophoretic display apparatus. Hereinafter, a configuration in which the display panel 110 is a panel for an organic light emitting display apparatus will be described. However, the present disclosure is not limited thereto.

[0039] The timing controller 140 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock signal through a receiving circuit such as an LVDS or TMDS interface connected to a host system. Based on the input timing signals, the timing controller 140 generates a data control signal DCS for controlling the data driver 130 and a gate control signal GCS for controlling the gate driver 120.

[0040] For example, to control the gate driver 120, the timing controller 140 outputs various gate control signals (GCS) including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal.

[0041] In this case, the gate start pulse controls an operation start timing of one or more gate circuits constituting the gate driver 120. The gate shift clock is a clock signal commonly input to the one or more gate circuits and controls a shift timing of a scan signal (gate pulse). The gate output enable signal assigns timing information of the one or more gate circuits.

[0042] In addition, to control the data driver 130, the timing controller 140 outputs various data control signals (DCS) including a source start pulse (SSP), a source sample clock (SSC), and a source output enable (SOE) signal.

[0043] In this case, the source start pulse controls a data sample start timing of one or more data circuits constituting the data driver 130. The source sample clock is a clock signal for controlling a sample timing of data of each data circuit. The source output enable signal controls an output timing of the data driver 130.

[0044] Further, the timing controller 140 processes frame data inputted from the outside so that the frame data are suitable for the size and resolution of the display panel 110. The timing controller 140 converts the frame data into image data RGB and provides the image data RGB to the data driver 130.

[0045] Further, the timing controller 140 senses characteristic values (mobility, threshold voltage) of the driving transistor provided on each of the plurality of pixels PX and generates compensation data for the characteristic values (mobility, threshold voltage) of the driving transistor. Further, the timing controller 140 can generate the data control signal DCS and the gate control signal GCS by using the compensation data.

[0046] The data driver 130 can provide the data voltage Vdata to the plurality of pixels PX. The data driver 130 can include a source printed circuit board and a plurality of source driving integrated circuits. The plurality of source driving integrated circuits can each receive the image data RGB and the data control signal DCS from the timing controller 140 through the source printed circuit board.

[0047] The data driver 130 can generate the data voltage Vdata by converting the image data RGB into a gamma voltage in response to the data control signal DCS. The data driver 130 can provide the data voltage Vdata through the data line DL of the display panel 110.

[0048] Further, the data driver 130 can receive a sensing voltage from the plurality of pixels PX and convert the sensing voltage into sensing data about the characteristic values (mobility, threshold voltage) of the driving transistor. Further, the data driver 130 can output the sensing data to the timing controller 140.

[0049] The plurality of source driving integrated circuits can be provided in a form of a chip on film (COF) and connected to the data line DL of the display panel 110. More specifically, the plurality of source driving integrated circuits can each be provided in a form of a chip provided on a connection film. A line connected to the source driving integrated circuit in the form of a chip can be formed on the connection film. However, the arrangement shape of the plurality of source driving integrated circuits is not limited thereto. The plurality of source driving integrated circuits can be connected to the data line DL of the display panel 110 in a chip on glass (COG) or tape automated bonding (TAB) process.

[0050] The gate driver 120 provides a scan signal to the plurality of pixels PX. The gate driver 120 can include a level shifter and a shift register. The gate driver 120 can be formed in a non-display area of the display panel 110 by a gate-in-panel (GIP) method. However, the present disclosure is not limited thereto. The gate driver 120 can include a plurality of stages configured to shift a scan signal to correspond to a gate clock signal and a gate control signal GCS, and output the scan signal. The plurality of stages included in the gate driver 120 can sequentially output the scan signal through a plurality of output ports.

[0051] The display panel 110 can include a plurality of pixels PX. The plurality of pixels PX can include sub-pixels that emit light beams having different colors. For example, the plurality of sub-pixels can include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. However, the present disclosure is not limited thereto. The plurality of sub-pixels can constitute a pixel PX. That is, the red sub-pixels, the green sub-pixels, the blue sub-pixels, and the white sub-pixels can constitute a single pixel PX. The display panel 110 can include a plurality of pixels PX.

[0052] Further, in the display device according to the embodiment of the present disclosure, the display panel 110 includes a display area AA in which light-emitting pixels are disposed and a dummy area DA in which non-light-emitting pixels are disposed.

[0053] The display area AA is an area in which light-emitting pixels among the plurality of pixels PX are disposed and in which an image is implemented. Further, the dummy area DA indicates an area in which non-light-emitting pixels among the plurality of pixels PX are disposed and in which an image is not implemented. However, sensing data can be calculated by sampling a sensing voltage from the non-light-emitting pixels disposed in the dummy area DA. Further, Figure 1 It is exemplified that the dummy area DA is an area in which the pixels PX in the uppermost row of the display panel 110 and the pixels PX in the lowermost row of the display panel 110 are disposed. However, the present disclosure is not limited thereto. The area of the dummy area DA can be variously changed.

[0054] Hereinafter, a description will be given of a display device according to an embodiment of the present disclosure with reference to Figure 2 A driving circuit for operating one pixel will be described in more detail.

[0055] Figure 2 is a circuit diagram exemplifying a pixel of a display device according to an embodiment of the present disclosure.

[0056] Figure 2 is a circuit diagram exemplifying one pixel among a plurality of pixels of the display device 100.

[0057] Reference will be made to Figure 2In one embodiment, the pixel can include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC, and a light emitting element LED.

[0058] The light emitting element LED can include an anode, an organic layer, and a cathode. The organic layer can include various organic layers such as a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer. The anode of the light emitting element LED can be connected to the output terminal of the driving transistor DT. The low potential voltage VSS can be applied to the cathode through the low potential voltage line VSSL. Figure 2 It is exemplified that the light emitting element LED is an organic light emitting element. However, the disclosure is not limited thereto. The light emitting element LED can be changed to various elements configured to emit light.

[0059] The low potential voltage line VSSL is a constant potential line for applying a constant electric power of a low potential voltage. The low potential voltage line VSSL can be referred to as a ground terminal.

[0060] Referring to Figure 2 , the switching transistor SWT is a transistor for transferring a data voltage Vdata to a first node N1 corresponding to a gate of the driving transistor DT. The switching transistor SWT can include a drain connected to a data line DL, a gate connected to a gate line GL, and a source connected to the gate of the driving transistor DT. The switching transistor SWT can be turned on in response to a scan signal SCAN applied from the gate line GL, and transfer the data voltage Vdata provided from the data line DL to the first node N1 corresponding to the gate of the driving transistor DT.

[0061] Referring to Figure 2 , the driving transistor DT is a transistor for operating the light emitting element LED by providing a driving current to the light emitting element LED. The driving transistor DT can include a gate corresponding to the first node N1, a source corresponding to the second node N2 and an output terminal, and a drain corresponding to the third node N3 and an input terminal. The gate of the driving transistor DT can be connected to the switching transistor SWT. The drain can receive a high potential voltage VDD through a high potential voltage line VDDL. The source can be connected to the anode of the light emitting element LED.

[0062] Referring to Figure 2 , the storage capacitor SC is a capacitor for maintaining a voltage corresponding to the data voltage Vdata in one frame. The first electrode of the storage capacitor SC can be connected to the first node N1. The second electrode of the storage capacitor SC can be connected to the second node N2.

[0063] Further, in the case of the display device 100, circuit elements such as the drive transistor DT can deteriorate as the operation time of each of the pixels increases. Thus, the intrinsic characteristic values of the circuit elements such as the drive transistor DT can change. In this case, the intrinsic characteristic values of the circuit elements can include the threshold voltage Vth of the drive transistor DT, the mobility a of the drive transistor DT, and the like. The change in the characteristic values of the circuit elements can cause a change in the luminance of the corresponding pixel. Thus, the change in the characteristic values of the circuit elements can be used as the same concept as the pixel luminance change.

[0064] In addition, the degree of change in the characteristic values between the circuit elements of each of the pixels can vary depending on the difference in the degree of deterioration between the circuit elements. The difference in the degree of change in the characteristic values between the circuit elements can cause a luminance deviation between the pixels. Thus, the deviation in the characteristic values between the circuit elements can be used as the same concept as the luminance deviation between the pixels. The change in the characteristic values of the circuit elements such as the luminance change of the pixels and / or the deviation between the characteristic values between the circuit elements and / or the luminance deviation between the pixels can cause a problem such as degradation in the accuracy of the luminance expression of the pixels or a screen abnormality.

[0065] Thus, according to the embodiment of the present disclosure, the sensing function of sensing the characteristic values of the pixels and the compensation function of compensating for the characteristic values of the pixels by using the sensing result can be provided to the pixels of the display device 100.

[0066] Thus, as Figure 2 indicated, the pixel PX can include a sensing transistor SET for effectively controlling the voltage state of the source of the drive transistor DT in addition to the switching transistor SWT, the drive transistor DT, the storage capacitor SC, and the light emitting element LED.

[0067] Referring to Figure 2 , the sensing transistor SET is connected to a reference voltage line RVL for supplying a reference voltage Vref to the source of the drive transistor DT at the second node N2. The gate of the sensing transistor SET is connected to a gate line GL. Thus, the sensing transistor SET can be turned on in response to a sensing signal SENSE applied through the gate line GL and apply the reference voltage Vref supplied through the reference voltage line RVL to the source of the drive transistor DT. In addition, the sensing transistor SET can function as one of the voltage sensing paths for sensing the source of the drive transistor DT.

[0068] Referring to Figure 2 , a scan signal SCAN can be applied to the switching transistor SWT through the gate line GL. A sensing signal SENSE can be applied to the sensing transistor SET through a sensing line.

[0069] Accordingly, the reference voltage Vref is applied to the source of the driving transistor DT through the sensing transistor SET. Also, a sensing voltage for sensing the threshold voltage Vth of the driving transistor DT or the mobility a of the driving transistor DT is detected through the reference voltage line RVL. Also, the data driver 130 can compensate for the amount of change in the threshold voltage Vth of the driving transistor DT or the amount of change in the mobility a of the driving transistor DT detected according to the sensing voltage of the reference voltage line RVL.

[0070] Figure 3 is a block diagram of a display panel 110 of a display apparatus according to an embodiment of the disclosure.

[0071] As described above, the display apparatus 100 according to an embodiment of the disclosure can detect a characteristic value of the driving transistor DT in the pixel PX or a change in the characteristic value during a sensing period according to the sensing voltage of the reference voltage line RVL. Accordingly, the reference voltage line RVL can not only be used to transfer the reference voltage Vref, but also can be used as a sensing line for sensing the characteristic value of the driving transistor DT in the pixel PX. Accordingly, the reference voltage line RVL can be referred to as a sensing line.

[0072] In particular, referring to Figure 2 and Figure 3 In the sensing process of the display apparatus 100 according to an embodiment of the disclosure, the characteristic value of the driving transistor DT or the change in the characteristic value can be the voltage of the second node N2 of the driving transistor DT (e.g., Vdata-Vth).

[0073] When the sensing transistor SET is in the on state, the voltage of the second node N2 of the driving transistor DT can correspond to the sensing voltage of the reference voltage line RVL. Also, the line capacitor Cline on the reference voltage line RVL can be charged by the voltage of the second node N2 of the driving transistor DT. With the charged line capacitor Cline, the reference voltage line RVL can have the sensing voltage corresponding to the voltage of the second node N2 of the driving transistor DT.

[0074] The display apparatus 100 according to an embodiment of the disclosure performs ON-OFF control on the switching transistor SWT and the sensing transistor SET in the pixel PX to be sensed, and controls the provision of the data voltage Vdata and the reference voltage Vref. Accordingly, the display apparatus 100 can operate to achieve a voltage state in which the second node N2 of the driving transistor DT reflects the characteristic value (threshold voltage, mobility) of the driving transistor DT or the change in the characteristic value.

[0075] The data driver 130 of the display device 100 according to an embodiment of the present disclosure may include an analog-to-digital converter (ADC) 131 and switching circuits SAM and SPRE. The ADC 131 is configured to measure a sense voltage corresponding to the voltage of the second node N2 of the driving transistor DT on the reference voltage line RVL and convert the sense voltage into a digital value. The switching circuits SAM and SPRE are used to sense the characteristic value of the driving transistor DT.

[0076] The switching circuits SAM and SPRE for controlling the sensing operation may include: a sensing reference switch SPRE configured to control the connection between the reference voltage line RVL and the sensing reference voltage providing node Npres for providing the reference voltage Vref; and a sampling switch SAM configured to control the connection between the reference voltage line RVL and the ADC 131.

[0077] In this case, the sensing reference switch SPRE is a switch used to control the sensing operation. The reference voltage Vref supplied to the reference voltage line RVL through the sensing reference switch SPRE is the sensing reference voltage VpreS.

[0078] In addition, to realize the image, the data driver 130 may include a shift register 132, a latching unit 133, a digital-to-analog converter 134, and a switch RPRE for image operations during image display. Furthermore, the data driver 130 may also include buffer circuitry.

[0079] The image-driven reference switch RPRE controls the connection between the reference voltage line RVL and the image-driven reference voltage supply node Nprer, which provides the reference voltage Vref. The image-driven reference switch RPRE is a switch used for image operation. The reference voltage Vref supplied to the reference voltage line RVL via the image-driven reference switch RPRE corresponds to the image-driven reference voltage VpreR.

[0080] In other words, the sensing reference switch SPRE, acting as the first voltage switch, can apply the sensing reference voltage VpreS to the reference voltage line RVL to sense the driving transistor DT. Furthermore, the image driving reference switch RPRE, acting as the second voltage switch, can apply the image driving reference voltage VpreR to the reference voltage line RVL for image operation.

[0081] However, the ADC 131 and various types of switches SAM, SPRE, and RPRE can be located outside the data driver 130.

[0082] In this configuration, the sensing reference switch SPRE and the image driving reference switch RPRE can be configured individually or integrated. The sensing reference voltage VpreS and the image driving reference voltage VpreR can have the same voltage value or different voltage values.

[0083] Furthermore, shift register 132 shifts the sampled signal according to the source sampling clock SSC of the data control signal DCS. Additionally, when more data than the latching unit 133 can latch is provided, shift register 132 generates a carry signal Carry.

[0084] The latching unit 133 samples the image data RGB from the timing controller 140 in response to the sampling signals sequentially input from the shift register 132. The latching unit 133 latches the image data RGB through a horizontal line, and then simultaneously outputs the image data RGB for the horizontal line during the on-level segment of the source output enable signal SOE.

[0085] DAC 134 decodes the digital image data RGB input from latch unit 133 and outputs the analog gamma voltage Vgamma corresponding to the grayscale value of the image data RGB as the data voltage Vdata to the data line DL.

[0086] Through the above series of processes, the data driver 130 of the display device 100 according to the embodiments of the present disclosure can process image data RGB in response to the data control signal DSC and output the data voltage Vdata to multiple data lines DL.

[0087] More specifically, the data voltage Vdata can be output during the on-level segment of the source output enable signal SOE.

[0088] Furthermore, the gating driver 120 can sequentially output the scan signal SCAN during the on-level segment of the gating output enable signal GOE. That is, the gating driver 120 of the display device 100 according to the embodiment of this disclosure can output the scan signal SCAN in response to the gating control signal GCS.

[0089] Figure 4 This is a block diagram illustrating a timing controller 140 of a display device according to an embodiment of the present disclosure.

[0090] The timing controller 140 includes a data compensator 141 configured to compensate for data, a memory 142 configured to store data for multiple different time periods (e.g., a long time period or a short time period shorter than a long time period), and a signal generator 143 configured to generate a gating control signal GCS and a data control signal DCS.

[0091] The data compensator 141 can calculate the compensation data CD based on the sensing data SD output from the ADC 131. In one embodiment, the compensation data CD is calculated for both non-illuminating dummy pixels and illuminating pixels.

[0092] Specifically, the data compensator 141 can compare the sensed data SD and the reference data, and calculate the compensation data CD that reflects the difference between the sensed data SD and the reference data. In addition, the compensation data CD can be stored in the memory 142.

[0093] For example, when the reference data is greater than the sensed data SD, the data compensator 141 calculates the compensation data CD at a positive level. Conversely, when the reference data is less than the sensed data SD, the data compensator 141 calculates the compensation data CD at a negative level.

[0094] The memory 142 stores the sensing data SD output from the ADC 131 or the compensation data CD output from the data compensator 141.

[0095] Reference data can be stored in memory 142. For example, the reference data may include the mobility of the driving transistor in a base state without degradation.

[0096] Furthermore, the memory 142 can be located outside the timing controller 140 or implemented as a register inside the timing controller 140.

[0097] Signal generator 143 can generate gating control signal GCS and data control signal DCS based on compensation data CD in order to control the charging rate of data voltage Vdata.

[0098] The charging rate of the data voltage Vdata can be determined based on the extent to which the data voltage Vdata is applied during the on-level segment of the scan signal SCAN, which turns on at least one pixel of the scan signal SCN, which is at the on-level. In other words, the charging rate of the data voltage Vdata can increase with the increase of the overlap time between the on-level segment of the scan signal SCAN and the output segment of the data voltage Vdata.

[0099] Signal generator 143 can generate a gating control signal GCS and a data control signal DCS based on compensation data CD, so as to control the overlap time between the on-level segment of the scan signal SCAN that turns on at least one pixel of the receiving scan signal SCN and the output segment of the data voltage Vdata. That is, the amount of time for outputting the scan signal SCAN with the on-level that turns on at least one pixel is adjusted based on the compensation data.

[0100] Specifically, when the compensation data CD at a positive level is applied to the signal generator 143, the gating control signal GCS and the data control signal DCS can be generated to reduce the overlap time between the on-level segment of the scanning signal SCAN and the output segment of the data voltage Vdata while simultaneously outputting both the scanning signal SCAN and the data voltage Vdata.

[0101] Conversely, specifically, when the compensation data CD at a negative level is applied to the signal generator 143, the gating control signal GCS and the data control signal DCS can be generated to simultaneously increase the overlap time between the on-level segment of the scanning signal SCAN and the output segment of the data voltage Vdata, while simultaneously increasing both the output scanning signal SCAN and the data voltage Vdata.

[0102] The following will refer to Figures 7A to 8B Describe this configuration in detail.

[0103] Figure 5 This is a diagram illustrating the operation of a display device according to an embodiment of the present disclosure within each frame.

[0104] like Figure 5 As shown, the image operation data voltage Vdata is sequentially written to pixels PX in multiple rows during the operation time (effective time) of the Nth frame, so that multiple pixels PX can emit light (normal drive).

[0105] Subsequently, during the blanking period (blanking time) in the Nth frame, a process is performed to sense the deviation of the characteristic values ​​of the driving transistors in multiple pixels PX located in a specific row of the display panel. In this case, the sensed data voltage Vdata can be applied to the multiple pixels PX in the specific row. Furthermore, because the sensing process is performed, the multiple pixels PX do not emit light.

[0106] Subsequently, during the operation time (effective time) of the Nth frame, the data voltage Vdata used for recovery drive is written to multiple pixels PX in a specific row that has already undergone sensing processing, enabling the multiple pixels PX to emit light (recovery drive). The recovery drive data voltage Vdata can be equal to the image operation data voltage Vdata.

[0107] Furthermore, the image data voltage Vdata, which is compensated by reflecting the sensing processing, is sequentially written to the pixels PX in multiple rows during the operation time (effective time) of the (N+1)th frame, so that multiple pixels PX can emit light (normal drive).

[0108] Furthermore, sensing processing performed during the blanking period is referred to as real-time sensing processing.

[0109] Furthermore, a process for sensing the mobility value of the driving transistor DRT can be performed after the power-on signal is generated and before image operation begins. This sensing process is called power-on sensing and power-on sensing processing. Alternatively, a process for sensing the mobility value of the driving transistor DRT can be performed after the power-off signal is generated. This sensing and sensing process is called power-off sensing and power-off sensing processing.

[0110] In the following text, reference will be made to Figure 6 This describes an implementation of sensing processing during the blanking period (blanking time).

[0111] Figure 6 This is a signal timing diagram used to illustrate the sensing processing of a display device during a blanking period according to an embodiment of the present disclosure.

[0112] Reference Figure 2 , Figure 3 and Figure 6 In the display device according to the embodiments of the present disclosure, the process of sensing the mobility of the driving transistor DT during the blanking period (blanking time) can be performed by an initialization step, a tracking step, and a sampling step.

[0113] In the initialization step, the switching transistor SWT is turned on by the scan signal SCAN at the on level, and the first node N1 of the driving transistor DT is initialized to the sensing data voltage Vdata for mobility sensing.

[0114] Additionally, the sensing transistor SET is turned on by the sensing signal SENSE, which is at the on level, and the sensing reference switch SPRE is turned on. In this state, the second node N2 of the driving transistor DT is initialized to the sensing reference voltage VpreS.

[0115] The tracking step is the process of tracking the mobility of the driving transistor DT. The mobility of the driving transistor DT indicates its current driving capability. The tracking step tracks the voltage at the second node N2 of the driving transistor DT, which can be used to calculate the mobility of the driving transistor DT.

[0116] In the tracking step, the switching transistor SWT is turned off by the scan signal SCAN, which is at the cutoff level, and the sensing reference switch SPRE transitions to the off level. Therefore, both the first node N1 and the second node N2 of the driving transistor DT are floating, causing the voltages at both nodes to increase. Specifically, since the voltage at the second node N2 of the driving transistor DT has been initialized to the sensing reference voltage VpreS, the voltage begins to increase from the sensing reference voltage VpreS. In this case, because the sensing transistor SET is turned on, the increase in the voltage at the second node N2 of the driving transistor DT leads to an increase in the sensed voltage of the reference voltage line RVL.

[0117] In the sampling step, the sampling switch SAM is turned on at a predetermined time Δt after the point at which the voltage at the second node N2 of the driving transistor DT begins to increase. In this case, the ADC 131 can sense the sensed voltage of the reference voltage line RVL connected by the sampling switch SAM and convert the analog sensed voltage into second sensed data in the form of a digital signal. In this case, the sensed voltage applied to the ADC 131 corresponds to the level (VpreS+ΔV) of the increase in the sensed reference voltage VpreS by a predetermined voltage ΔV.

[0118] In this case, during the tracking step, the mobility of the driving transistor DT is proportional to the voltage change per unit time (ΔV / Δt) of the reference voltage line RVL, that is, proportional to the slope of the voltage waveform of the reference voltage line RVL.

[0119] In other words, when the sensing reference switch SPRE, which serves as the first voltage switch, is in the off state, and the sampling switch SAM, which serves as the second voltage switch, switches from the on state to the off state after the image driving reference switch RPRE, which serves as the second voltage switch, switches from the on state to the off state, the sensing voltage can be sampled during the blanking period.

[0120] Figures 7A to 8B This is a signal timing diagram used to illustrate the compensation processing during the operation (effective) time of the display device according to an embodiment of the present disclosure.

[0121] Specifically, Figures 7A to 7B This diagram illustrates the compensation process when the output is at a negative level (compensation data CD). Figures 8A to 8B This diagram illustrates the compensation process when the output is at a positive level and the compensation data CD is displayed.

[0122] Reference Figure 2 , Figure 3 , Figure 7A and Figure 7BIn the display device according to the embodiments of the present disclosure, an initialization step, a writing step, and an emission step can be performed during operation time.

[0123] In the initialization step, the sensing transistor SET is turned on by the sensing signal SENSE, which is at the on level, and the drive reference switch RPRE is turned on. In this state, the second node N2 of the drive transistor DT is initialized to the drive reference voltage VpreR.

[0124] In the writing step, the switching transistor SWT is turned on by the scan signal SCAN, which is at the on level, and the data voltage Vdata is written to the first node N1 of the driving transistor DT.

[0125] Furthermore, because the drive reference switch RPRE is turned off during the writing step, the second node N2 is charged with a voltage corresponding to the difference between the data voltage Vdata and the threshold voltage, based on the data voltage Vdata written to the first node N1.

[0126] In the emission step, the driving current flowing through the LED is determined based on the voltage of the second node N2, causing the LED to emit light.

[0127] However, because the sensed data SD is smaller than the reference data, when generating the compensation data CD at a negative level, the gating control signal GCS and the data control signal DCS can be generated to increase the overlap time between the on-level segment of the scan signal SCAN and the output segment of the data voltage Vdata. Therefore, in response to the compensation data CD being at a negative level, the scan signal SCAN is on-level, and the amount of time for outputting the data voltage Vdata increases simultaneously with the output of the scan signal SCAN.

[0128] Therefore, as Figure 7A As shown, the output timing of the data voltage Vdata can be delayed in response to the data control signal DCS.

[0129] Alternative locations, such as Figure 7B As shown, the turn-on timing of the scan signal SCAN can be advanced in response to the gating control signal GCS. In this case, the duty cycle of the scan signal SCAN can be constant. However, this disclosure is not limited thereto. The duty cycle of the scan signal SCAN can be increased.

[0130] Therefore, as described above, by controlling the gating control signal GCS and the data control signal DCS, the overlap time between the conduction level segment of the scan signal SCAN and the output segment of the data voltage Vdata can be increased.

[0131] Therefore, the charging rate of the data voltage Vdata applied to the second node N2 can be increased. Consequently, the driving current flowing through the light-emitting element LED increases, thereby increasing the output brightness.

[0132] In other words, in existing display devices, the turn-on timing of the scan signal and the output timing of the data voltage are fixed. Therefore, the following problem exists: when the mobility of the driving transistor decreases, the voltage charging the source of the driving transistor decreases (as shown by the dashed line), which reduces the output brightness.

[0133] Conversely, in the case of the display device 100 according to the embodiments of the present disclosure, when the mobility of the driving transistor decreases, the turn-on timing of the scan signal and the output timing of the data voltage are adjusted so that the output brightness can be compensated by increasing the voltage that charges the source of the driving transistor (as shown by the solid line).

[0134] Reference Figure 2 , Figure 3 , Figure 8A and Figure 8B In the display device according to the embodiments of the present disclosure, an initialization step, a writing step, and an emission step can be performed during operation time.

[0135] In the initialization step, the sensing transistor SET is turned on by the sensing signal SENSE, which is at the on level, and the drive reference switch RPRE is turned on. In this state, the second node N2 of the drive transistor DT is initialized to the drive reference voltage VpreR.

[0136] In the writing step, the switching transistor SWT is turned on by the scan signal SCAN, which is at the on level, and the data voltage Vdata is written to the first node N1 of the driving transistor DT.

[0137] Furthermore, because the drive reference switch RPRE is turned off during the writing step, the second node N2 is charged with a voltage corresponding to the difference between the data voltage Vdata and the threshold voltage, based on the data voltage Vdata written to the first node N1.

[0138] In the emission step, the driving current flowing through the LED is determined based on the voltage of the second node N2, causing the LED to emit light.

[0139] However, because the sensed data SD is larger than the reference data, when generating the compensation data CD at a positive level, the gating control signal GCS and the data control signal DCS can be generated to reduce the overlap time between the on-level segment of the scan signal SCAN and the output segment of the data voltage Vdata. Therefore, the amount of time that the scan signal SCAN is on-level and the data voltage Vdata is output simultaneously with the output of the scan signal SCAN is reduced in response to the compensation data CD being at a positive level.

[0140] Therefore, as Figure 8A As shown, the output timing of the data voltage Vdata can be advanced in response to the data control signal DCS.

[0141] Alternative locations, such as Figure 8B As shown, the on-time of the scan signal SCAN can be delayed in response to the gating control signal GCS. In this case, the duty cycle of the scan signal SCAN can be constant. However, this disclosure is not limited thereto. The duty cycle of the scan signal SCAN can be reduced.

[0142] Therefore, as described above, by controlling the gating control signal GCS and the data control signal DCS, the overlap time between the on-level segment of the scan signal SCAN and the output segment of the data voltage Vdata can be reduced.

[0143] Therefore, the charging rate of the data voltage Vdata applied to the second node N2 can be reduced. Consequently, the driving current flowing through the LED light-emitting element decreases, allowing for a reduction in output brightness.

[0144] In other words, in existing display devices, the turn-on timing of the scan signal and the output timing of the data voltage are fixed and cannot be adjusted. Therefore, the following problem exists: when the mobility of the driving transistor increases, the voltage required to charge the source of the driving transistor increases (as shown by the dashed line), which increases the output brightness.

[0145] Conversely, in the case of the display device according to the embodiments of the present disclosure, when the mobility of the driving transistor increases, the turn-on timing of the scan signal and the output timing of the data voltage change, so that the output brightness can be compensated by reducing the voltage that charges the source of the driving transistor (as shown by the solid line).

[0146] Figure 9A and Figure 9BThis is a signal timing diagram used to illustrate compensation processing in pixels in multiple rows of a display device according to an embodiment of the present disclosure.

[0147] Specifically, Figure 9A This diagram illustrates the compensation process set in pixels PX across multiple rows in the display area AA during the Nth frame. Figure 9B This diagram illustrates the compensation process set in the pixels PX of multiple rows in the display area AA in the (N+1)th frame.

[0148] However, Figure 9B This can be used not only to describe the (N+1)th frame, but also to describe the (N+k)th frame. Here, k is a natural number of 2 or greater.

[0149] also, Figure 9A and Figure 9B Examples of scan signals SCAN and data voltage Vdata applied to pixels in the first row, the 730th row, the 1460th row, and the 2190th row of pixels PX in multiple rows set in the display area AA.

[0150] like Figure 1 , Figure 9A and Figure 9B As shown, the pixel PX in the top row of the dummy area DA can be sensed, and the gating control signal GCS and the data control signal DCS can be controlled based on the compensation data for the pixel PX in the top row, so that the overlap time between the output segment of the data voltage Vdata output to the pixel in the first row and the on-level segment of the scan signal SCAN is 40%, which is the top row in the display area AA.

[0151] like Figure 1 , Figure 9A and Figure 9B As shown, the pixel PX in the bottom row of the dummy area DA can be sensed, and the gating control signal GCS and the data control signal DCS can be controlled based on the compensation data for the pixel PX in the bottom row, so that the overlap time between the output segment of the data voltage Vdata output to the pixel in the 2190th row and the on-level segment of the scan signal SCAN is 100%, and the 2190th row is the bottom row in the display area AA.

[0152] Furthermore, the overlap time between the output segment of the data voltage Vdata output to the pixels in the middle row of the display area AA and the on-level segment of the scan signal SCAN can be set between the overlap time between the output segment of the data voltage Vdata output to the pixels in the first row (e.g., the top row) and the on-level segment of the scan signal SCAN and the overlap time between the output segment of the data voltage Vdata output to the pixels in the 2190th row (e.g., the bottom row) and the on-level segment of the scan signal SCAN.

[0153] More specifically, the overlap time between the output segment of the data voltage Vdata of the pixels output to the middle row and the on-level segment of the scan signal SCAN can be calculated by linear interpolation based on the overlap time between the output segment of the data voltage Vdata of the pixels output to the first row (e.g., the top row) and the on-level segment of the scan signal SCAN, and the overlap time between the output segment of the data voltage Vdata of the pixels output to the 2190th row (e.g., the bottom row) and the on-level segment of the scan signal SCAN. Therefore, the overlap time for the pixels in the first row and the bottom row sets the boundary for the overlap time of the pixels set in the middle row of the display panel.

[0154] For example, such as Figure 9A As shown, the gating control signal GCS and the data control signal DCS can be controlled such that the overlap time between the output segment of the data voltage Vdata of the pixel output to the 730th row and the on-level segment of the scan signal SCAN is 60%.

[0155] Furthermore, the gating control signal GCS and the data control signal DCS can be controlled such that the overlap time between the output segment of the data voltage Vdata of the pixel output to the 1460th row and the on-level segment of the scan signal SCAN is 80%.

[0156] Furthermore, in multiple adjacent frames, the overlap time between the output segment of the data voltage Vdata of a pixel output to a row in one frame and the on-level segment of the scan signal SCAN can be different from the overlap time between the output segment of the data voltage Vdata of a pixel output to a row in another frame and the on-level segment of the scan signal SCAN.

[0157] For example, refer to Figure 9A The overlap time between the output segment of the data voltage Vdata of the pixel in the 730th row of the Nth frame and the on-level segment of the scan signal SCAN is 60%.

[0158] In comparison, refer to Figure 9BThe overlap time between the output segment of the data voltage Vdata of the pixel in the 730th row in the (N+1)th frame and the on-level segment of the scan signal SCAN can be adjusted to 80% within the boundary of the overlap time determined in the Nth frame.

[0159] For example, refer to Figure 9A The overlap time between the output segment of the data voltage Vdata of the pixel in the 1460th row in the Nth frame and the on-level segment of the scan signal SCAN is 80% within the boundary of the overlap time determined in the Nth frame.

[0160] In comparison, refer to Figure 9B The overlap time between the output segment of the data voltage Vdata of the pixel in the (N+1)th frame and the on-level segment of the scan signal SCAN can be adjusted to 60%.

[0161] Therefore, the display device according to the embodiments of the present disclosure can compensate for the data charging rate. However, the processing for compensating for the data charging rate of pixels in the middle row can be varied and is not limited thereto.

[0162] Exemplary embodiments of this disclosure may also be described as follows:

[0163] According to one aspect of this disclosure, a display device includes: a display panel having a plurality of pixels disposed thereon; a data driver configured to receive a sensed voltage from a reference voltage line connected to the plurality of pixels, convert the sensed voltage into sensed data, and provide a data voltage to the plurality of pixels; a gating driver configured to provide a scan signal to the plurality of pixels; and a timing controller configured to output a data control signal for controlling the output timing of the data voltage using the sensed data, and to output a gating control signal for controlling the output timing of the scan signal.

[0164] The timing controller may include: a data compensator configured to compare sensed data and reference data to output compensated data; and a signal generator configured to output a data control signal and a gating control signal based on the compensated data.

[0165] The timing controller may also include a memory configured to store compensation data.

[0166] When the sensed data is larger than the reference data, the overlap time between the on-level segment of the scan signal and the output segment of the data voltage can be reduced.

[0167] The activation timing of the scan signal can be delayed in response to the gating control signal.

[0168] The timing of the data voltage output can be advanced in response to the data control signal.

[0169] When the sensed data is smaller than the reference data, the overlap time between the on-level segment of the scan signal and the output segment of the data voltage can be increased.

[0170] The activation timing of the scan signal can be advanced in response to the gating control signal.

[0171] The timing of the data voltage output can be delayed in response to the data control signal.

[0172] The display panel may include: a display area having luminescent pixels among a plurality of pixels; and a dummy area having non-luminescent pixels among a plurality of pixels.

[0173] The sensed voltage can be sampled from a reference voltage line connected to a non-emitting pixel set in a dummy area.

[0174] The timing controller can calculate the sensing data from the non-light-emitting pixels set in the dummy area and output a gating control signal and a data control signal to control the overlap time between the output segment of the data voltage output to the light-emitting pixels set in the display area and the on-level segment of the scan signal.

[0175] The overlap time between the output segment of the data voltage output to the luminous pixels in the middle row of the display area and the conduction level segment of the scan signal can be calculated by linear interpolation based on the overlap time between the output segment of the data voltage output to the luminous pixels in the top row of the display area and the conduction level segment of the scan signal, as well as the overlap time between the output segment of the data voltage output to the luminous pixels in the bottom row of the display area and the conduction level segment of the scan signal.

[0176] The overlap time between the output segment of the data voltage output to the pixels in a row on the display panel and the on-level segment of the scan signal in the first frame can be different from the overlap time between the output segment of the data voltage output to the pixels in a row on the display panel and the on-level segment of the scan signal in the second frame.

[0177] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0178] Cross-references to related applications

[0179] This patent application claims priority to Korean Patent Application No. 10-2021-0194569, filed with the Korean Intellectual Property Office on December 31, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising: The display panel includes a plurality of pixels; A data driver configured to receive a sensing voltage from a reference voltage line connected to the plurality of pixels, convert the sensing voltage into sensing data, and provide a data voltage to the plurality of pixels; A gating driver configured to provide scan signals to the plurality of pixels; as well as A timing controller configured to output a data control signal that controls the output timing of the data voltage, and to output a gating control signal that controls the output timing of the scan signal. The timing of the data voltage output and the timing of the scan signal output are adjusted based on the sensing data. The display panel further includes: A display area is provided in which light-emitting pixels are disposed among the plurality of pixels, and the light-emitting pixels are configured to emit light; and A dummy region is provided, in which a non-light-emitting pixel is configured to not emit light. The sensed voltage is sampled from another reference voltage line connected to the non-emitting pixel disposed in the dummy region, and The timing controller receives sensing data from the non-light-emitting pixels in the dummy area based on the sampled sensing voltage, and outputs the gating control signal and the data control signal to control the overlap time between the output segment of the data voltage and the conduction level segment of the scan signal that turns on the light-emitting pixels in the display area.

2. The display device according to claim 1, wherein, The timing controller includes: A data compensator configured to compare the sensed data and reference data, and output compensated data based on the comparison; and A signal generator configured to output the data control signal and the gating control signal based on the compensation data.

3. The display device according to claim 2, wherein, The timing controller also includes: A memory configured to store the compensation data.

4. The display device according to claim 2, wherein, The overlap time between the on-level segment of the scanning signal that enables the plurality of pixels and the output segment of the data voltage decreases in response to the sensing data being larger than the reference data.

5. The display device according to claim 4, wherein, The timing of the output of the scanning signal is delayed in response to the gating control signal.

6. The display device according to claim 4, wherein, The output timing of the data voltage is advanced in response to the data control signal.

7. The display device according to claim 2, wherein, The overlap time between the on-level segment of the scanning signal that enables the plurality of pixels and the output segment of the data voltage increases in response to the sensing data being smaller than the reference data.

8. The display device according to claim 7, wherein, The timing of the output of the scanning signal is advanced in response to the gating control signal.

9. The display device according to claim 7, wherein, The timing of the data voltage output is delayed in response to the data control signal.

10. The display device according to claim 1, wherein, The overlap time between the output segment of the data voltage of the light-emitting pixels in the middle row of the display area and the conduction level segment of the scan signal is calculated by linear interpolation based on the overlap time between the output segment of the data voltage of the first light-emitting pixel in the top row of the display area and the conduction level segment of the scan signal, and the overlap time between the output segment of the data voltage of the second light-emitting pixel in the bottom row of the display area and the conduction level segment of the scan signal.

11. The display device according to claim 1, wherein, The overlap time between the output segment of the data voltage in the first frame and the on-level segment of the scan signal that enables the pixels in a row on the display panel to conduct is different from the overlap time between the output segment of the data voltage output to the pixels in the row and the on-level segment of the scan signal in a second frame different from the first frame.

12. A display device, the display device comprising: The display panel includes a plurality of pixels; A data driver configured to provide data voltages to the plurality of pixels and generate sensing data indicating feature values ​​of the pixels based on sensing voltages of the pixels received from reference voltage lines connected to the pixels among the plurality of pixels; A gating driver configured to provide scan signals to the plurality of pixels; as well as A timing controller configured to generate compensation data to compensate for the feature value of the pixel, and to adjust the overlap amount of the data voltage output to the pixel and the scan signal output to the pixel based on the compensation data. The display panel further includes: A display area is provided in which light-emitting pixels are disposed among the plurality of pixels, and the light-emitting pixels are configured to emit light; and A dummy region is provided, in which a non-light-emitting pixel is configured to not emit light. The sensed voltage is sampled from another reference voltage line connected to the non-emitting pixel disposed in the dummy region, and The timing controller receives sensing data from the non-light-emitting pixels in the dummy area based on the sampled sensing voltage, and outputs a gating control signal and a data control signal to control the overlap time between the output segment of the data voltage and the conduction level segment of the scan signal that turns on the light-emitting pixels in the display area.

13. The display device according to claim 12, wherein, The timing controller is configured to generate the compensation data by comparing the sensed data with reference data.

14. The display device according to claim 13, wherein, The timing controller is configured to reduce the overlap time amount at which the data voltage for the pixel is output while the scan signal is also output to the pixel in response to the sensing data being larger than the reference data.

15. The display device according to claim 13, wherein, The timing controller is configured to increase the overlap time amount at which the data voltage for the pixel is output while the scan signal is also output to the pixel in response to the sensing data being smaller than the reference data.

16. A display device, the display device comprising: The display panel includes a plurality of first pixels configured to not emit light and a plurality of second pixels configured to emit light; A data driver configured to provide data voltages to the plurality of first pixels and the plurality of second pixels, and to generate first sensing data indicating first feature values ​​of the plurality of first pixels, and to generate second sensing data indicating second feature values ​​of the plurality of second pixels; A gating driver configured to provide scan signals to the plurality of first pixels and the plurality of second pixels; as well as A timing controller configured to determine, based on the first sensing data, an overlap time at which a first data voltage is output to the plurality of first pixels while a first scan signal is also output to the plurality of first pixels, and to adjust, at least based on the determined overlap time for the plurality of non-emitting first pixels, the overlap time at which a second data voltage is output to the second pixel while a scan signal is also output to the second pixel.

17. The display device according to claim 16, wherein, The timing controller is configured to determine the amount of overlap time by: A first overlap time is determined when a first data voltage of one of the first data voltages is output to a first pixel of a first row of the plurality of first pixels, and a first scan signal of the first scan signal is also output to a first pixel of the first row. A second overlap time is determined when another first data voltage from the first data voltage is output to the first pixel of the second row of the plurality of first pixels, and simultaneously the second scan signal from the first scan signal is also output to the first pixel of the second row. The overlap time amount, in which the second data voltage for the second pixel is output while the scan signal is also output to the second pixel, is based on a linear interpolation of the first overlap time amount and the second overlap time amount.

18. The display device according to claim 17, wherein, The first pixel of the first row is the pixel of the top row in the display panel, and the second pixel of the second row is the pixel of the bottom row in the display panel.

Images