A control amplification method and circuit, a sensitive amplifier and a semiconductor memory

Abstract

The embodiment of the present disclosure provides a control amplification method and circuit, a sensitive amplifier and a semiconductor memory, the method comprises the following steps: receiving a preset instruction, determining an isolation power value and a control instruction signal according to the preset instruction; generating an isolation control signal according to the isolation power value and the control instruction signal; the amplification circuit receives the isolation control signal and a target signal to be processed according to the preset instruction, processes the signal to be processed, and completes the preset instruction. In this way, the specific voltage value of the isolation control signal is controlled through the isolation power value, the signal amplification process can be optimized, the signal amplification speed can be improved, and the problem of large circuit noise can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a control amplification method and circuit, a sensitive amplifier, and a semiconductor memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. During data reading, the read data signal for each memory cell is read sequentially via the local data line, global data line, and data bus; conversely, during data writing, the write data signal is written to the memory cell sequentially via the data bus, global data line, and local data line.

[0003] Currently, there is a sensitive amplifier between the storage unit and the local data line to improve the signal quality of the storage unit content. The stored data needs to be amplified by this sensitive amplifier before it can be read or written. However, the amplification process of the data signal in related technologies is still insufficient, which means that the performance of the sensitive amplifier needs to be improved. Summary of the Invention

[0004] This disclosure provides a control amplification method and circuit, a sensitive amplifier, and a semiconductor memory that can optimize the signal amplification process.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a control amplification method applied to an amplifier circuit; the method includes:

[0007] Receive a preset instruction and determine the isolation power value and control instruction signal according to the preset instruction;

[0008] An isolation control signal is generated based on the isolation power supply value and the control command signal;

[0009] The amplifier circuit receives the isolation control signal and the target signal to be processed according to the preset instruction, processes the signal to be processed, and completes the preset instruction.

[0010] In some embodiments, the preset instructions include at least one of the following: read instructions, refresh instructions, and write instructions;

[0011] The isolation power supply value is either a second voltage value or a third voltage value;

[0012] The isolation control signal is one of a first voltage value, a second voltage value, and a third voltage value;

[0013] The first voltage value is greater than the second voltage value, and the second voltage value is greater than the third voltage value.

[0014] In some embodiments, determining the isolation power supply value according to the preset instruction includes:

[0015] According to the preset instruction, the first power switching signal and / or the second power switching signal are obtained;

[0016] The isolation power value is determined based on the first power switching signal and / or the second power switching signal;

[0017] Determining the isolation power value based on the first power switching signal and / or the second power switching signal includes:

[0018] When the first power switching signal has a first level state and the second power switching signal has a second level state, it is determined that the isolation power supply value has a first voltage value; or

[0019] When the first power switching signal has a second level state and the second power switching signal has a first level state, it is determined that the isolation power supply value has a second voltage value;

[0020] Both the first voltage value and the second voltage value belong to the second level state.

[0021] In some embodiments, generating an isolation control signal based on the isolation power supply value and the control command signal includes:

[0022] When the control command signal has a second state and the isolation power supply value has a first voltage value, it is determined that the isolation control signal has a first voltage value; or

[0023] When the control command signal has a second state and the isolation power supply value has a second voltage value, it is determined that the isolation control signal has a second voltage value; or

[0024] If the control command signal has a first state, it is determined that the isolation control signal has a third voltage value;

[0025] The first state is either a first level state or a second level state, the second state is either a first level state or a second level state, and the first state and the second state are at different level states; the third voltage value belongs to the first level state.

[0026] In some embodiments, the amplification circuit processes the signal to be processed, including: a signal amplification stage, wherein the amplification circuit amplifies the signal to be processed and writes it into a storage unit during the signal amplification stage;

[0027] When the amplifier circuit is in one of the signal amplification stages, the isolation control signal is controlled to have a first voltage value;

[0028] The preset instruction is a read instruction or a refresh instruction, and the signal amplification stage includes a first amplification stage and a second amplification stage.

[0029] The preset instruction is a write instruction, and the signal amplification stage includes a first amplification stage, a signal writing stage, and a second amplification stage.

[0030] In some embodiments, when the preset instruction is a read instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage;

[0031] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal maintains a third voltage value; or

[0032] If the amplification circuit is in the standby stage, the second charge sharing stage, or the first amplification stage, then the isolation control signal maintains a second voltage value; or

[0033] If the amplifier circuit is in the pre-charge stage or the second amplification stage, the isolation control signal is maintained at the first voltage value.

[0034] In some embodiments, when the preset instruction is a read instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage;

[0035] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal maintains a third voltage value; or

[0036] If the amplification circuit is in the second charge-sharing stage or the first amplification stage, then the isolation control signal is maintained at a first voltage value; or

[0037] If the amplifier circuit is in the standby stage, the pre-charge stage, or the second amplification stage, the isolation control signal is maintained to have a second voltage value.

[0038] In some embodiments, when the preset instruction is a refresh instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage.

[0039] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal is maintained with a third voltage value; or

[0040] If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal is determined to have a second voltage value; or

[0041] If the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained to have a first voltage value.

[0042] In some embodiments, when the preset instruction is a write instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a charge sharing stage, a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage.

[0043] If the amplification circuit is in the noise cancellation stage, the charge sharing stage, or the first amplification stage, then the isolation control signal is maintained at a third voltage value; or

[0044] If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or

[0045] If the amplifier circuit is in the signal writing stage, the isolation control signal is maintained at a first voltage value.

[0046] In some embodiments, when the preset instruction is a read instruction, the operating state of the amplifier circuit includes a standby stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage;

[0047] If the amplifier circuit is in the standby stage or the second charge sharing stage, then the isolation control signal is maintained with a third voltage value; or

[0048] If the amplifier circuit is in signal processing or pre-charging state, the isolation control signal is maintained at the second voltage value; or

[0049] If the amplifier circuit is in the first charge sharing stage, the isolation control signal is maintained to have a first voltage value.

[0050] In some embodiments, when the preset instruction is a refresh instruction, the operating state of the amplifier circuit includes a standby stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage;

[0051] If the amplifier circuit is in the first charge sharing phase, then the isolation control signal is maintained at a third voltage value; or

[0052] If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or

[0053] If the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained to have a first voltage value.

[0054] In some embodiments, when the preset instruction is a write instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a charge sharing stage, a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage.

[0055] If the amplification circuit is in the charge sharing stage or the first amplification stage, then the isolation control signal is maintained with a third voltage value; or

[0056] If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or

[0057] If the amplifier circuit is in the signal writing stage, the isolation control signal is maintained at a first voltage value.

[0058] In some embodiments, the amplifier circuit is in the standby phase, used to maintain the voltage of each node in the amplifier circuit at a preset potential;

[0059] The amplifier circuit is in the first charge sharing stage, and the target storage unit forms a signal to be processed according to the preset instruction.

[0060] When the amplifier circuit is in the second charge sharing stage, in response to the isolation control signal, the signal to be processed is transmitted to the amplifier circuit.

[0061] The amplifier circuit is in the first amplification stage, and the amplifier circuit amplifies and processes the signal to be processed.

[0062] The amplification circuit is in the second amplification stage, and recovers the data of the target storage unit through the amplified signal to be processed;

[0063] The amplifier circuit is in the pre-charge stage. The amplifier circuit completes the preset command to the target storage unit and restores the voltage of each node in the amplifier circuit to the preset potential.

[0064] In some embodiments, when the preset instruction is a write instruction, the amplification circuit is in the write phase. The amplification circuit receives a write signal, which replaces the signal generated by the storage unit to form the signal to be processed. The amplification circuit then amplifies the signal to be processed.

[0065] In some embodiments, the amplifier circuit is in a noise cancellation phase, maintaining the isolation power supply value as a first power supply value.

[0066] In some embodiments, the amplifier circuit is in a noise cancellation phase, and the amplifier circuit performs offset cancellation operation on the transistors in the amplifier circuit in response to an isolation cancellation signal.

[0067] Secondly, embodiments of this disclosure provide a control amplification circuit, which includes a signal determination circuit, an isolation control circuit, and an amplification circuit; wherein,

[0068] The signal determination circuit is used to determine the isolation power supply value and control command signal according to the preset command after receiving the preset command;

[0069] The isolation control circuit is used to receive the isolation power value and the control command signal, and generate an isolation control signal according to the control command signal;

[0070] The amplification circuit is used to receive the isolation control signal and the signal to be processed according to the preset instruction, amplify the signal to be processed, and complete the preset instruction.

[0071] In some embodiments, the isolation power supply value and the control command signal are determined by a signal determination circuit, and the isolation control signal is determined by an isolation control circuit.

[0072] The signal determination circuit includes a first signal determination circuit, a power output circuit, and a second signal determination circuit; wherein...

[0073] The first signal determining circuit is used to output a first power switching signal and / or a second power switching signal according to the preset instruction after receiving the preset instruction;

[0074] The power output circuit is used to output an isolation power value according to the first power switching signal and / or the second power switching signal;

[0075] The second signal determining circuit is used to generate the control command signal according to the preset instruction;

[0076] The preset instructions include at least one of the following: read instructions, refresh instructions, and write instructions.

[0077] In some embodiments, the power output circuit is configured to determine that the isolated power supply value has a first voltage value when the first power switching signal has a first level state and the second power switching signal has a second level state; or

[0078] When the first power switching signal has a second level state and the second power switching signal has a first level state, it is determined that the isolation power value has a second voltage value;

[0079] Wherein, both the first voltage value and the second voltage value belong to the second level state, and the first voltage value is greater than the second voltage value.

[0080] In some embodiments, the isolation control circuit is specifically configured to determine that the isolation control signal has a first voltage value when the control command signal has a second state and the isolation power supply value has a first voltage value; or

[0081] When the control command signal has a second state and the isolation power supply value has a second voltage value, it is determined that the isolation control signal has a second voltage value; or

[0082] If the control command signal has a first state, it is determined that the isolation control signal has a third voltage value;

[0083] Wherein, the first state is either a first level state or a second level state, the second state is either a first level state or a second level state, and the first state and the second state are at different level states; the third voltage value belongs to the first level state, and the third voltage value is less than the second voltage value.

[0084] In some embodiments, the power output circuit includes a first preset power supply, a second preset power supply, a first switching transistor, and a second switching transistor; wherein,

[0085] The first terminal of the first switching transistor is connected to the first power switching signal, and the first terminal of the second switching transistor is connected to the second power switching signal;

[0086] The second end of the first switching transistor is connected to the first preset power supply, and the second end of the second switching transistor is connected to the second preset power supply;

[0087] The third terminal of the first switching transistor is connected to the third terminal of the second switching transistor, and is used to output the isolation power value;

[0088] Wherein, the first preset power supply is used to output the first voltage value, and the second preset power supply is used to output the second voltage value.

[0089] In some embodiments, the isolation control circuit includes a first inverter, a third switch, and a fourth switch; wherein,

[0090] The input terminal of the first inverter is connected to the control command signal, and the output terminal of the first inverter is connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively.

[0091] The second terminal of the third switch is connected to the isolation power supply value, and the third terminal of the fourth switch is connected to the ground signal;

[0092] The third terminal of the third switch is connected to the second terminal of the fourth switch to output the isolation control signal.

[0093] In some embodiments, the amplification circuit includes a control circuit and a cross-coupling circuit. The cross-coupling circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The control circuit includes a ninth switch and a tenth switch.

[0094] The first end of the fifth switch is connected to the third end of the ninth switch for receiving the signal to be processed. The second end of the fifth switch, the third end of the seventh switch, the first end of the eighth switch, and the second end of the tenth switch are connected.

[0095] The first end of the sixth switch is connected to the third end of the tenth switch for receiving a reference signal to be processed. The second end of the sixth switch, the third end of the eighth switch, the first end of the seventh switch, and the second end of the ninth switch are connected.

[0096] The third terminal of the fifth switch and the third terminal of the sixth switch are connected to the first reference signal, the second terminal of the seventh switch and the second terminal of the eighth switch are connected to the second reference signal, and the first terminal of the ninth switch and the first terminal of the tenth switch are connected to the isolation control signal.

[0097] In some embodiments, the amplification circuit further includes a pre-charging circuit, and the pre-charging circuit includes a thirteenth switch and a fourteenth switch; wherein,

[0098] The first terminal of the thirteenth switch and the first terminal of the fourteenth switch are connected to the precharge control signal;

[0099] The second terminal of the thirteenth switch is connected to the fourth preset power supply, and the third terminal of the thirteenth switch is connected to the second terminal of the sixth switch.

[0100] The third terminal of the fourteenth switch is connected to the second terminal of the fifth switch, and the second terminal of the fourteenth switch is connected to the second terminal of the sixth switch.

[0101] In some embodiments, the amplification circuit further includes a noise cancellation circuit, which includes a fifteenth switching transistor and a sixteenth switching transistor; wherein,

[0102] The first terminal of the fifteenth switch and the first terminal of the sixteenth switch are connected to the noise control signal;

[0103] The second end of the fifteenth switch is connected to the second end of the fifth switch, and the third end of the fifteenth switch is connected to the first end of the fifth switch.

[0104] The second terminal of the sixteenth switch is connected to the second terminal of the sixth switch, and the third terminal of the sixteenth switch is connected to the first terminal of the sixth switch.

[0105] In some embodiments, the first switch, the second switch, the third switch, the seventh switch, and the eighth switch are P-channel MOSFETs.

[0106] The fourth, fifth, sixth, ninth, tenth, thirteenth, fourteenth, fifteenth, and sixteenth switching transistors are N-channel MOSFETs.

[0107] Wherein, the first terminal of the P-type field-effect transistor is the gate terminal, the second terminal of the P-type field-effect transistor is the source terminal, and the third terminal of the P-type field-effect transistor is the drain terminal; the first terminal of the N-type field-effect transistor is the gate terminal, the second terminal of the N-type field-effect transistor is the drain terminal, and the third terminal of the N-type field-effect transistor is the source terminal.

[0108] Thirdly, embodiments of this disclosure provide a sensitive amplifier, including a control amplifier circuit as described in any one of the second aspects.

[0109] Fourthly, embodiments of this disclosure provide a semiconductor memory including a sensitive amplifier as described in any one of the third aspects.

[0110] This disclosure provides a control amplification method and circuit, a sensitive amplifier, and a semiconductor memory. The method includes: receiving a preset instruction; determining an isolation power supply value and a control instruction signal according to the preset instruction; generating an isolation control signal according to the isolation power supply value and the control instruction signal; and having an amplification circuit receive the isolation control signal and a target signal to be processed according to the preset instruction, process the target signal, and complete the preset instruction. Thus, by controlling the specific voltage value of the isolation control signal through the isolation power supply value, the signal amplification process can be optimized, at least partially improving the problems of slow signal amplification speed and high circuit noise. Attached Figure Description

[0111] Figure 1 A schematic diagram illustrating an application scenario for a sensitive amplifier;

[0112] Figure 2 A schematic diagram of the composition structure of a control amplifier circuit provided in an embodiment of this disclosure;

[0113] Figure 3 A schematic diagram of the composition structure of another control amplifier circuit provided in an embodiment of this disclosure;

[0114] Figure 4 A partial detailed structural diagram of a control amplifier circuit provided in an embodiment of this disclosure;

[0115] Figure 5 A partial detailed structural diagram of another control amplifier circuit provided in an embodiment of this disclosure;

[0116] Figure 6 This is a schematic diagram of the structure of an inverter provided in an embodiment of the present disclosure;

[0117] Figure 7 A partial detailed structural schematic diagram of another control amplifier circuit provided in an embodiment of this disclosure;

[0118] Figure 8 This is a schematic diagram illustrating an application scenario of a control amplifier circuit provided in an embodiment of the present disclosure;

[0119] Figure 9 A schematic flowchart of a control amplification method provided in an embodiment of this disclosure;

[0120] Figure 10 This is a schematic diagram illustrating another application scenario of the control amplifier circuit provided in the embodiments of this disclosure;

[0121] Figure 11 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0122] Figure 12A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0123] Figure 13 A signal timing diagram provided for an embodiment of this disclosure Figure 3 ;

[0124] Figure 14 A signal timing diagram provided for an embodiment of this disclosure Figure 4 ;

[0125] Figure 15 A schematic diagram of the composition structure of a sensitive amplifier provided in an embodiment of this disclosure;

[0126] Figure 16 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0127] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0128] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0129] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0130] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0131] P-channel MOSFET: Hole-type MOSFET;

[0132] N-channel MOSFET: Electronic MOSFET.

[0133] It is understandable that sensitive amplifiers are needed to amplify signals during various operational processes in DRAM. (See also...) Figure 1 This illustrates a schematic diagram of an application scenario for a sensitive amplifier. For example... Figure 1 As shown, this application scenario includes a first signal line 11, a second signal line 12, and a sensitive amplifier 113. Among them,

[0134] The first signal line 11 has a first switch 111 and a second capacitor 112 for receiving the signal to be processed, Vin+; the second signal line 12 has a second switch 121 and a first capacitor 122 for receiving a reference signal to be processed, Vin-. A sensitive amplifier 113 amplifies both the signal to be processed, Vin+, and the reference signal to be processed, Vin-, with a voltage difference of ΔVin between them. Here, the first switch 111 and the first capacitor 112 can be considered as one storage unit, and the second switch 121 and the second capacitor 122 can be considered as another storage unit.

[0135] Specifically, the sensitive amplifier includes a first switch 131, a second switch 132, a third switch 133, and a fourth switch 134. The first terminal of the first switch 131, the first terminal of the second switch 132, the third terminal of the third switch 133, and the second terminal of the fourth switch 134 are all connected to a reference signal to be processed, Vin-. The third terminal of the first switch 131, the second terminal of the second switch 132, the first terminal of the third switch 133, and the first terminal of the fourth switch 134 are all connected to the signal to be processed, Vin+. In this application scenario, a fifth switch 135 and a sixth switch 136 also exist. The first terminal of the fifth switch 135 is connected to a first control signal, SAP, and the second terminal of the fifth switch 135 is connected to a power supply signal, VBLH. The third terminal of the fifth switch 135, the second terminal of the first switch 131, and the second terminal of the third switch 133 are connected to form a first reference signal terminal. The first terminal of the sixth switch 136 is connected to the second control signal SAN, and the second terminal of the sixth switch 136 is connected to the ground signal GND. The second terminal of the sixth switch 136, the third terminal of the second switch 132, and the third terminal of the fourth switch 134 are connected to form the second reference signal terminal. Among them, the first switch 131, the third switch 132, and the fifth switch 135 are P-type field-effect transistors, with the first terminal of the P-type field-effect transistor being the gate pin, the second terminal of the P-type field-effect transistor being the source pin, and the third terminal of the P-type field-effect transistor being the drain pin; the second switch 132, the fourth switch 134, and the sixth switch 136 are N-type field-effect transistors, with the first terminal of the N-type field-effect transistor being the gate pin, the second terminal of the N-type field-effect transistor being the drain pin, and the third terminal of the N-type field-effect transistor being the source pin.

[0136] In addition, a pre-charging circuit may exist between the first signal line 11 and the second signal line 12, and a pre-charging circuit may also exist between the second terminal of the third switch 133 and the third terminal of the fourth switch, for pre-charging the first reference signal terminal and the second reference signal terminal.

[0137] Currently, sensitive amplifiers have slow signal amplification speeds and are prone to noise, which affects the performance of semiconductor memories.

[0138] This disclosure provides a control amplification circuit, including: a power output circuit for receiving a power switching signal and generating a preset power signal based on the power switching signal; an isolation control circuit for receiving a control command signal and the preset power signal, and generating an isolation control signal based on the control command signal; and an amplification circuit for receiving the isolation control signal and a signal to be processed, and amplifying the signal to be processed based on the isolation control signal to obtain a target amplified signal. In this way, the preset power signal can be controlled using the power switching signal. Subsequently, the specific voltage value of the preset power signal can be adjusted by changing the power switching signal, thereby adjusting the specific voltage value of the isolation control signal, optimizing the signal amplification process, and improving the problems of slow signal amplification speed and susceptibility to noise generation.

[0139] This disclosure provides a control amplification method, comprising: receiving a preset instruction; determining an isolation power supply value and a control instruction signal according to the preset instruction; generating an isolation control signal according to the isolation power supply value and the control instruction signal; and having an amplification circuit receive the isolation control signal and a target signal to be processed according to the preset instruction, process the target signal, and complete the preset instruction. Thus, by controlling the specific voltage value of the isolation control signal through the isolation power supply value, the signal amplification process can be optimized, at least partially improving the problems of slow signal amplification speed and high circuit noise.

[0140] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0141] In one embodiment of this disclosure, see Figure 2 This illustrates a schematic diagram of the composition of a control amplifier circuit 20 provided in an embodiment of the present disclosure. For example... Figure 2 As shown, the control amplifier circuit 20 may include:

[0142] The signal determination circuit 21 is used to determine the isolation power supply value and control command signal according to the preset command after receiving the preset command;

[0143] The isolation control circuit 22 is used to receive the isolation power supply value and control command signal, and generate an isolation control signal according to the control command signal;

[0144] Amplifier circuit 23 is used to receive isolation control signals and signals to be processed according to preset instructions, amplify the signals to be processed, and complete the preset instructions.

[0145] It should be noted that the control amplifier circuit 20 provided in this embodiment can be applied in various signal amplification scenarios, such as the sensitive amplifier in DRAM.

[0146] Here, the preset instruction can be a read instruction, a write instruction, or a refresh instruction. Specifically, for the control amplifier circuit 20, after receiving the preset instruction, the signal determination circuit 21 determines the isolation power supply value and the control instruction signal; the isolation control circuit 22 outputs an isolation control signal according to the control instruction signal, and the voltage value of the isolation control signal is affected by the isolation power supply value; the amplifier circuit 23 amplifies the signal to be processed according to the isolation control signal in order to complete the preset instruction.

[0147] In some embodiments, Figure 2 On the basis of, such as Figure 3 As shown, the isolation power supply value and control command signal are determined by signal determination circuit 21, and the isolation control signal is determined by isolation control circuit 22; signal determination circuit 21 includes a first signal determination circuit 211, a power output circuit 212, and a second signal determination circuit 213; wherein,

[0148] The first signal determination circuit 211 is used to output a first power switching signal and / or a second power switching signal according to the preset command after receiving the preset command.

[0149] The power output circuit 212 is used to output an isolation power value according to the first power switching signal and / or the second power switching signal;

[0150] The second signal determination circuit 213 is used to generate control command signals according to preset instructions.

[0151] Here, the first power switching signal and / or the second power switching signal are in Figure 3 In Chinese, it is represented by a "power switching signal".

[0152] In one specific embodiment, the power output circuit 212 is configured to determine that the isolation power supply value has a first voltage value when the first power switching signal has a first level state and the second power switching signal has a second level state; or

[0153] When the first power switching signal has a second level state and the second power switching signal has a first level state, it is determined that the isolation power supply value has a second voltage value;

[0154] It should be noted that both the first and second voltage values ​​belong to the second voltage level state, and the first voltage value is greater than the second voltage value. Specifically, for a P-type MOSFET, the first voltage level state enables it to conduct, and the second voltage level state enables it to turn off; for an N-type MOSFET, the first voltage level state enables it to turn off, and the second voltage level state enables it to conduct. Here, due to the different specifications of different switching transistors, the first voltage level state may have different voltage ranges for different switching transistors.

[0155] In this way, the isolation power supply value can be controlled by the power switching signal. Subsequently, the specific voltage value of the isolation power supply can be adjusted by changing the power switching signal, thereby adjusting the specific voltage value of the isolation control signal, optimizing the signal amplification process, and partially improving the problems of slow signal amplification speed and easy noise generation.

[0156] In some embodiments, the isolation control circuit 22 is specifically configured to determine that the isolation control signal has a first voltage value when the control command signal has a second state and the isolation power supply value has a first voltage value; or to determine that the isolation control signal has a second voltage value when the control command signal has a second state and the isolation power supply value has a second voltage value; or to determine that the isolation control signal has a third voltage value when the control command signal has a first state.

[0157] It should be noted that the first state is the first level state and the second state is the second level state; or, the first state is the second level state and the second state is the first level state.

[0158] In other words, for the isolation control circuit 22, if the control command signal is at a first level and the preset power supply signal has a first voltage value, then the isolation control signal has a first voltage value; if the control command signal is at a first level and the preset power supply signal has a second voltage value, then the isolation control signal has a second voltage value; if the control command signal is at a second level, then the isolation control signal has a third voltage value.

[0159] Alternatively, if the control command signal is at the second level and the preset power supply signal has a first voltage value, the isolation control signal has a first voltage value; if the control command signal is at the second level and the preset power supply signal has a second voltage value, the isolation control signal has a second voltage value; if the control command signal is at the first level, the isolation control signal has a third voltage value.

[0160] Here, the third voltage value belongs to the first level state, the first voltage value and the second voltage value both belong to the second level state, and the third voltage value is lower than the second voltage value, and the second voltage value is lower than the first voltage value.

[0161] In this way, the isolation control signal has three different voltage values, which can provide more control methods for the amplifier circuit, so as to optimize the signal amplification process and partially improve the problems of slow signal amplification speed and high circuit noise.

[0162] The following example, taking a power switching signal that includes both a first power switching signal and a second power switching signal, provides a feasible structure for a power output circuit 212.

[0163] exist Figure 3 On the basis of, such as Figure 4 As shown, the power output circuit 212 includes a first preset power supply VisoH, a second preset power supply VisoL, a first switching transistor 301, and a second switching transistor 302; wherein,

[0164] The first terminal of the first switching transistor 301 is connected to the first power switching signal, and the first terminal of the second switching transistor 302 is connected to the second power switching signal.

[0165] The second end of the first switching transistor 301 is connected to the first preset power supply VisoH, and the second end of the second switching transistor 302 is connected to the second preset power supply VisoL.

[0166] The third terminal of the first switching transistor 301 is connected to the third terminal of the second switching transistor 302 to output the isolation power supply value VisoInt.

[0167] Here, the first preset power supply VisoH is used to output the first voltage value, and the second preset power supply VisoL is used to output the second voltage value.

[0168] It should be noted that, as Figure 4 As shown, both the first switch 301 and the second switch 302 are P-type field-effect transistors. In the following description, the first terminal of the P-type field-effect transistor is the gate pin, the second terminal is the source pin, and the third terminal is the drain pin.

[0169] It should be noted that when the first power switching signal is at the first level and the second power switching signal is at the second level, the first switch 301 is turned on and the second switch 302 is turned off. Therefore, the isolation power supply value VisoInt is the same as the voltage value of the first preset power supply VisoH, that is, the isolation power supply value VisoInt is the first voltage value. When the first power switching signal is at the second level and the second power switching signal is at the first level, the first switch 301 is turned off and the second switch 302 is turned on. Therefore, the isolation power supply value VisoInt is the same as the voltage value of the second preset power supply VisoL, that is, the isolation power supply value VisoInt is the second voltage value.

[0170] The following describes a feasible structure for an isolation control circuit, assuming the first state is a first-level state and the second state is a second-level state. In some embodiments, such as... Figure 4 As shown, the isolation control circuit 22 includes a first inverter 321, a third switch 303, and a fourth switch 304; wherein,

[0171] The input terminal of the first inverter 321 is connected to the control command signal, and the output terminal of the first inverter 321 is connected to the first terminal of the third switch 303 and the first terminal of the fourth switch 304, respectively.

[0172] The second terminal of the third switch 303 is connected to the isolation power supply value VisoInt, and the third terminal of the fourth switch 304 is connected to the ground signal.

[0173] The third terminal of the third switch 303 is connected to the second terminal of the fourth switch 304 to output the isolation control signal Iso.

[0174] It should be noted that the third switch 303 is a P-type field-effect transistor (FET), and the fourth switch 304 is an N-type FET. In the following description, the first terminal of the N-type FET is the gate pin, the second terminal is the drain pin, and the third terminal is the source pin.

[0175] Thus, when the control command signal is at the first level, the third switch 303 is off and the fourth switch 304 is on, so the isolation control signal Iso has a third voltage value, which is equivalent to ground potential; when the control command signal is at the second level, the third switch 303 is on and the fourth switch 304 is off, so the voltage value of the isolation control signal Iso is the same as the voltage value VisoInt of the isolation power supply, that is, the first voltage value or the second voltage value.

[0176] In addition, for the case where the first state is the second level state and the second state is the first level state, the isolation control circuit 22 can also include only the third switch 303 and the fourth switch 304, and the output terminal of the signal control circuit 25 is connected to the first terminal of the third switch 303 and the first terminal of the fourth switch 304, while other connections remain unchanged.

[0177] At this time, when the control command signal is in the second level state, the third switch 303 is in the off state and the fourth switch 304 is in the on state, so that the isolation control signal Iso has a third voltage value, which is equivalent to the ground potential; when the control command signal is in the first level state, the third switch 303 is in the on state and the fourth switch 304 is in the off state, so that the voltage value of the isolation control signal Iso is the same as the voltage value VisoInt of the preset power supply signal, that is, the first voltage value or the second voltage value.

[0178] Thus, through the above processing, the isolation control circuit outputs an isolation control signal, and the amplifier circuit amplifies the signal to be processed according to the isolation control signal to obtain the target amplified signal.

[0179] It should be noted that, taking DRAM as an example, amplifier circuit 23 is connected to the target memory cell via a bit line and to the complementary memory cell via a complementary bit line. Initially, the potentials on the bit line and the complementary bit line are the same. After the target memory cell (the object of the preset instruction) on the bit line is turned on, the memory cell shares charge with the bit line, causing the potential on the bit line to rise or fall; the memory cell on the complementary bit line is always off, so the potential on the complementary bit line remains unchanged. Due to the rise and fall of the potential on the bit line, the voltage difference between the bit line and the complementary bit line changes, thereby turning on some devices in amplifier circuit 23 to perform signal amplification processing. At this time, the signal received by amplifier circuit 23 from the bit line can be considered as the signal to be processed, and the signal received by amplifier circuit 23 from the complementary bit line can be considered as the reference signal to be processed.

[0180] During the amplification stage, the amplifier circuit 23 sets the isolation control signal Iso to the first voltage value to accelerate the transmission speed of the signal to be processed between the target storage unit and the amplifier circuit. In the process where the internal nodes of the amplifier circuit 23 can quickly reach the low reference potential or the high reference potential, the bit line or complementary bit line will also be quickly pulled up or pulled down to improve the signal amplification speed.

[0181] Subsequently, amplifier circuit 23 completes the signal amplification process; see subsequent sections for details.

[0182] In some embodiments, Figure 3 On the basis of, such as Figure 5 and Figure 8 As shown, the amplifier circuit 23 includes a control circuit and a cross-coupling circuit. The cross-coupling circuit includes a fifth switch 305, a sixth switch 306, a seventh switch 307, and an eighth switch 308. The control circuit includes a ninth switch 309 and a tenth switch 310.

[0183] The first terminal of the fifth switch 305 is connected to the third terminal of the ninth switch 309, and both are connected to the bit line Bla to receive the signal to be processed. The second terminal of the fifth switch 305, the third terminal of the seventh switch 307, the first terminal of the eighth switch 308, and the second terminal of the tenth switch are connected. The second terminal of the fifth switch 305, the third terminal of the seventh switch 307, the first terminal of the eighth switch 308, and the second terminal of the tenth switch 310 are all connected to the complementary readout bit line saBLb.

[0184] The first terminal of the sixth switch 306 is connected to the third terminal of the tenth switch 310, and both are connected to the complementary bit line Blb for receiving the reference signal to be processed. The second terminal of the sixth switch 306, the third terminal of the eighth switch 308, the first terminal of the seventh switch, and the second terminal of the ninth switch are connected. The second terminal of the sixth switch 306, the third terminal of the eighth switch 308, the first terminal of the seventh switch 307, and the second terminal of the ninth switch 309 are all connected to the readout bit line saBLa.

[0185] The third terminal of the fifth switch 305 and the third terminal of the sixth switch 306 are connected to the first reference signal NCS. The second terminal of the seventh switch 307 and the second terminal of the eighth switch 308 are connected to the second reference signal PCS. The first terminal of the ninth switch 309 and the first terminal of the tenth switch 310 are connected to the isolation control signal Iso.

[0186] like Figure 5 As shown, the fifth switch 305, the sixth switch 306, the ninth switch 309 and the tenth switch 310 are N-type field-effect transistors, and the seventh switch 307 and the eighth switch 308 are P-type field-effect transistors.

[0187] Thus, when the isolation control signal Iso is in the second level state (with a first voltage value or a second voltage value), the ninth switch 309 and the tenth switch 310 in the control circuit 232 are turned on, and the cross-coupling circuit 231 receives the signal to be processed; when the isolation control signal Iso is in the first level state (with a third voltage value), the ninth switch 309 and the tenth switch 310 in the control circuit 232 are turned off, and the cross-coupling circuit 231 cannot transmit signals to the outside.

[0188] In some embodiments, such as Figure 5 As shown, the amplifier circuit 23 also includes a first reference circuit and a second reference circuit. The first reference circuit includes n eleventh switching transistors (e.g., ...). Figure 5 The eleventh switch transistors 311-1, 311-2, and 311-3 are included in the first reference circuit. The second reference circuit includes m twelfth switches (e.g., 11th switch transistors 311-1, 311-2, and 311-3). Figure 5The twelfth switch transistors 312-1, 312-2, and 312-3 are used in the circuit, where n and m are both positive integers.

[0189] The first terminal of the eleventh switch is connected to the first reference control signal, and the third terminal of the eleventh switch is connected to the ground signal; the second terminal of the eleventh switch is connected to the output terminal of the first reference circuit and is used to output the first reference signal NCS.

[0190] The first terminal of the twelfth switch is connected to the second reference control signal, and the second terminal of the twelfth switch is connected to the third preset power supply; the second terminal of the twelfth switch is connected to the output terminal of the second reference circuit to output the second reference signal PCS.

[0191] It should be noted that, Figure 5 The diagram shows three eleventh-stage switches, but in practical applications, there may be more or fewer eleventh-stage switches. Additionally, there are multiple first reference control signals (pdn), with one pdn corresponding to one eleventh-stage switch. The voltage levels of these multiple pdn signals can be different; that is, the voltage levels of pdn1, pdn2, and pdn3 change independently. In other words, one eleventh-stage switch is controlled by a single first reference control signal (pdn).

[0192] like Figure 5 As shown, all eleventh switching transistors can be N-type field-effect transistors. Taking the eleventh switching transistor 311-1 as an example, when the first reference control signal pdn1 is at the first level, the eleventh switching transistor 311-1 is off; when the first reference control signal pdn1 is at the second level, the eleventh switching transistor 311-1 is on.

[0193] In this way, by adjusting the potential of the first reference signal NCS through the eleventh switch in the on state, a low reference potential is provided for the cross-coupled circuit. Furthermore, each of the different eleventh switches is connected to a separate ground potential, and these ground potentials can have different voltage values ​​to provide different rates of voltage drop for the first reference signal NCS. Additionally, the rate of voltage drop for the first reference signal NCS can also be controlled by controlling the number of eleventh switches in the on state. Thus, by controlling the different voltage adjustment rates, noise generated by the signal being processed during rapid voltage drops can be reduced during signal amplification.

[0194] It should also be noted that, Figure 5The diagram shows three twelfth switches, but in practical applications, there may be more or fewer twelfth switches. Additionally, there are multiple second reference control signals (pup), with one second reference control signal (pup) corresponding to one twelfth switch. The level states of the multiple second reference control signals (pup) can be different; that is, the level states of pup1, pup2, and pup3 change independently. In other words, one twelfth switch is controlled by one second reference control signal (pup) individually.

[0195] like Figure 5 As shown, the twelfth switch can be an N-type field-effect transistor. Therefore, taking the twelfth switch 312-1 as an example, when the second reference control signal pup1 is at the first level, the twelfth switch 312-1 is turned off; when the first reference control signal pup1 is at the second level, the eleventh switch 312-1 is turned on.

[0196] Thus, the twelfth switch, in its on state, charges the second reference signal PCS to a second level (high reference potential), providing a high reference potential for the cross-coupled circuit. Different twelfth switches are each connected to a separate third preset power supply; these third preset power supplies can have different voltage values ​​to provide different voltage rise rates for the second reference signal PCS. Furthermore, the voltage rise rate can be controlled by adjusting the number of twelfth switches in the on state. By controlling the different voltage rise rates, noise generated by the second reference signal during rapid voltage rises can be reduced during signal amplification.

[0197] The first reference signal and the second reference signal are also connected to a fourth preset power supply, which can maintain the first reference signal NCS and the second reference signal PCS at the reference voltage value when the second reference control signal pup1 is in the first level state and when the first reference control signal pdn1 is in the second level state.

[0198] In some embodiments, such as Figure 5 As shown, the amplifier circuit 23 also includes a first signal establishment circuit and a second signal establishment circuit. The first signal establishment circuit includes a second inverter (e.g., Figure 5 The second inverters 322-1, 322-2, and 322-3 are included in the second signal establishment circuit, which includes m third inverters (e.g., ...). Figure 5 The third inverters 323-1, 323-2, and 323-3 are included; among them,

[0199] The input terminal of the second inverter is connected to the first control input signal (e.g., Figure 5The Vpd1, Vpd2, and Vpd3 terminals are connected, and the output of the second inverter is used to output the first reference control signal (e.g., ...). Figure 5 (pdn1, pdn2, pdn3); where, in the n second inverters, the first reference control signal of each eleventh switch is output through a second inverter;

[0200] The input terminal of the third inverter is connected to the second control input signal (e.g.) Figure 5 The Vpu1, Vpu2, and Vpu3 are connected, and the output of the third inverter is used to output the second reference control signal (e.g., Figure 5 In the m third inverters, the second reference control signal of each twelfth switch is output through a third inverter.

[0201] It should be noted that, as Figure 5 As shown, the input terminal of the second inverter is also connected to the power supply signal Vncsg. When the first control input signal is at the first level, the second inverter outputs a first reference control signal at the second level according to the power supply signal Vncsg; when the first control input signal is at the second level, the second inverter outputs a first reference control signal at the first level.

[0202] It should be understood that there are multiple first control input signals, with one second inverter used to receive one first control input signal, and the level states of these first control input signals can be different. Figure 5 Taking the first control input signal as an example, when the first control input signal Vpd1 is at the first level, the second inverter 322-1 outputs the first reference control signal pdn1 at the second level, and the eleventh switch 311-1 is in the on state; conversely, when the first control input signal Vpd1 is at the second level, the second inverter 322-1 outputs the first reference control signal pdn1 at the first level, and the eleventh switch 311-1 is in the off state.

[0203] It should also be noted that the input of the third inverter is also connected to the power supply signal Vpcsg. When the second control input signal is at the first level, the third inverter outputs a second reference control signal at the second level according to the power supply signal Vpcsg; when the second control input signal is at the second level, the third inverter outputs a second reference control signal at the first level.

[0204] Similarly, there are multiple second control input signals, with one third inverter receiving one second control input signal, and these second control input signals can have different level states. Figure 5 Taking the second control input signal as an example, when the second control input signal Vpu1 is at the first level, the third inverter 323-1 outputs the second reference control signal pup1 at the second level, and the twelfth switch 312-1 is in the on state; conversely, when the second control input signal Vpu1 is at the second level, the third inverter 323-1 outputs the second reference control signal pup1 at the first level, and the twelfth switch 312-1 is in the off state.

[0205] The second and third inverters can use the same circuit structure, for example, implemented using an N-type field-effect transistor and a P-type field-effect transistor. See also Figure 6 This diagram illustrates the structure of the inverter provided in an embodiment of this disclosure. The specific structure of the second inverter 322 is as follows: Figure 6 As shown in (a), the specific structure of the third inverter is as follows: Figure 6 As shown in (b).

[0206] In this way, by using the signal establishment circuit and the reference circuit, a first reference signal and a second reference signal can be provided to the amplifier circuit, thereby suppressing the noise generated when the voltage of the signal to be processed increases or decreases during the amplification process.

[0207] In some embodiments, such as Figure 5 As shown, the amplifier circuit 23 also includes a pre-charging circuit, which includes a thirteenth switch 313 and a fourteenth switch 314; wherein,

[0208] The first terminal of the thirteenth switch 313 and the first terminal of the fourteenth switch 314 are connected to the precharge signal Eq;

[0209] The second terminal of the thirteenth switch 313 is connected to the fourth preset power supply, and the third terminal of the thirteenth switch 313 is connected to the second terminal of the sixth switch 306.

[0210] The third terminal of the fourteenth switch 314 is connected to the second terminal of the fifth switch 305, and the second terminal of the fourteenth switch 314 is connected to the second terminal of the sixth switch 306.

[0211] Here, both the thirteenth switch 313 and the fourteenth switch 314 are N-type field-effect transistors.

[0212] In this way, the pre-charging circuit responds to the pre-charging signal Eq and performs pre-charging processing for the amplifier circuit 23, so that each circuit node of the amplifier circuit 23 is at the same voltage value after the pre-charging processing is completed.

[0213] In some embodiments, such as Figure 7 As shown, the amplifier circuit 23 also includes a noise cancellation circuit, which includes a fifteenth switching transistor 315 and a sixteenth switching transistor 316; wherein,

[0214] The first terminal of the fifteenth switch 315 and the first terminal of the sixteenth switch 316 are connected to the noise cancellation signal Nc.

[0215] The second terminal of the fifteenth switch 315 is connected to the second terminal of the fifth switch 305, and the third terminal of the fifteenth switch 315 is connected to the first terminal of the fifth switch 305.

[0216] The second terminal of the sixteenth switch 316 is connected to the second terminal of the sixth switch 306, and the third terminal of the sixteenth switch 316 is connected to the first terminal of the sixth switch 306.

[0217] Here, both the fifteenth switch 315 and the sixteenth switch 316 are N-type field-effect transistors. Therefore, when the noise cancellation signal is in the second level state, the fifteenth switch 315 and the sixteenth switch 316 are turned on, shorting the first and third terminals of the fifth switch 305 and the sixth switch 306. This controls the first reference signal NCS to be at a low reference potential and the second reference signal PCS to be at a high reference potential, thereby performing offset cancellation operation on the fifth switch 305 and the sixth switch 306. In this way, the threshold difference of the switches during signal amplification can be further eliminated, improving the accuracy of sensing the signal to be processed during amplification.

[0218] In particular, Figures 4-7 This is merely one optional circuit structure for controlling the amplifier circuit, wherein the first switch 301, the second switch 302, the third switch 303, the seventh switch 307, and the eighth switch 308 are P-type channel field-effect transistors; and the fourth switch 304, the fifth switch 305, the sixth switch 306, the ninth switch 309, the tenth switch 310, the eleventh switch 311, the twelfth switch 312, the thirteenth switch 313, the fourteenth switch 314, the fifteenth switch 315, and the sixteenth switch 316 are N-type channel field-effect transistors. Of course, the selection of the above-mentioned switches does not constitute a limitation of the embodiments of this disclosure. In practical application scenarios, the aforementioned circuit control logic can be implemented using various types of circuit devices, and specific selections can be made according to the actual application scenario.

[0219] In summary, in this embodiment, by adding a power switching circuit, a preset power signal with two voltage values ​​(a first voltage value or a second voltage value) is provided. The isolation control circuit can then output an isolation control signal with three different voltage values ​​(a first voltage value, a second voltage value, or a third voltage value) based on the preset power signal. When the amplifier circuit is not in operation, the voltage of the preset power signal can be reduced to the second voltage value to reduce leakage current in the switching transistor of the isolation control circuit, prevent transistor failure, and extend the service life of the isolation control circuit. Furthermore, by adjusting the voltage value of the isolation control signal to the first or second voltage value at different stages of amplifier circuit operation, the voltage change rate of the signal to be processed is accelerated, optimizing the signal amplification process and improving the problems of slow signal amplification speed and high circuit noise.

[0220] In another embodiment of this disclosure, see Figure 8 This illustration shows a schematic diagram of an application scenario for a control amplifier circuit provided in an embodiment of this disclosure. For example... Figure 8 As shown, in this application scenario, there are bit line Bla, complementary bit line Blb, readout bit line saBla, complementary readout bit line saBlb, and control amplifier circuit 20. A first storage unit 51 is provided on bit line Bla, and a second storage unit 52 is provided on complementary bit line Blb. Here, both the first storage unit 51 and the second storage unit 52 can each serve as the object of a preset instruction.

[0221] The control amplifier circuit 20 includes a first signal determination circuit 211, a power output circuit 212, a second signal determination circuit 213, an isolation control circuit 22, and an amplifier circuit 23. Here, the power output circuit 212 includes a first switch 301 and a second switch 302, and the isolation control circuit 22 includes a third switch 303, a fourth switch 304, and a first inverter 321. The amplifier circuit 23 may include a fifth switch 305, a sixth switch 306, a seventh switch 307, an eighth switch 308, a ninth switch 309, a tenth switch 310, and three eleventh switches (…). Figure 8 The eleventh switch transistors 311-1, 311-2, and 311-3, and the three twelfth switches ( Figure 8 The 12th switch transistor 312-1, 12th switch transistor 312-2, 12th switch transistor 312-3, 13th switch transistor 313, 14th switch transistor 314, and 15th switch transistor 315 are three second inverters. Figure 8 The second inverter 322-1, second inverter 322-2, second inverter 322-3 and three third inverters ( Figure 8The circuit consists of three inverters (323, 323, 323), and the connection relationships and types of each device are as follows: Figure 8 As shown, the working principle of its circuit can be found in the aforementioned content, and will not be repeated here.

[0222] exist Figure 8 Based on this, see Figure 10 This illustrates a schematic diagram of an application scenario for another control amplifier circuit 20 provided in an embodiment of this disclosure. For example... Figure 10 As shown, the amplifier circuit also includes a fifteenth switch 315 and a sixteenth switch 316. The second terminal of the fifteenth switch 315 is connected to the complementary readout bit line saBlb, and the third terminal of the fifteenth switch 315 is connected to the bit line Bla. The second terminal of the sixteenth switch 316 is connected to the readout bit line saBla, and the third terminal of the sixteenth switch 316 is connected to the complementary bit line Blab. In response to the noise cancellation signal Nc, by controlling the first reference signal NCS to be at a low potential and the second reference signal PCS to be at a high reference potential, offset cancellation operation is performed on the ninth switch 309 and the tenth switch 310.

[0223] Based on the above circuit structure, the control method of amplifier circuit 23 will be briefly explained.

[0224] See Figure 9 This illustrates a flowchart of a control amplification method provided in an embodiment of this disclosure. Figure 9 As shown, the control amplification method may include:

[0225] S401: Receives preset instructions and determines the isolation power supply value and control command signal according to the preset instructions.

[0226] Specifically, in some embodiments, determining the isolation power supply value according to a preset instruction may include:

[0227] According to the preset instructions, acquire the first power switching signal and / or the second power switching signal;

[0228] The isolation power supply value is determined based on the first power switching signal and / or the second power switching signal.

[0229] It should be noted that the isolation power value can be determined based on one signal or two signals, and the specific choice needs to be made according to the actual application scenario.

[0230] It should be noted that the preset instruction includes at least one of the following: read instruction, refresh instruction, and write instruction; the isolation power supply value is a second voltage value or a third voltage value; the isolation control signal is one of a first voltage value, a second voltage value, and a third voltage value; the first voltage value is greater than the second voltage value, the second voltage value is greater than the third voltage value, the first voltage value and the second voltage value are both in a second level state, and the third voltage value is in a first level state.

[0231] In some embodiments, determining the isolation power value based on the first power switching signal and / or the second power switching signal may include:

[0232] When the first power switching signal has a first level state and the second power switching signal has a second level state, it is determined that the isolation power supply value has a first voltage value; or

[0233] When the first power switching signal has a second level state and the second power switching signal has a first level state, it is determined that the isolation power supply value has a second voltage value.

[0234] In this way, after receiving the preset command, the isolation power supply value and control command signal are determined, and the value of the isolation power supply can be flexibly adjusted. Multiple control strategies are provided later to improve the problems of slow signal amplification speed and high circuit noise.

[0235] S402: Generates an isolation control signal based on the isolation power supply value and control command signal.

[0236] It should be noted that the isolation power supply value and the control command signal can determine the voltage value of the isolation control signal.

[0237] In some embodiments, generating an isolation control signal based on the isolation power supply value and the control command signal may include:

[0238] When the control command signal has a second state and the isolation power supply value has a first voltage value, it is determined that the isolation control signal has a first voltage value; or

[0239] When the control command signal has a second state and the isolation power supply value has a second voltage value, it is determined that the isolation control signal has a second voltage value; or

[0240] When the control command signal has a first state, it is determined that the isolation control signal has a third voltage value.

[0241] Here, the first state is a first level state and the second state is a second level state; or the first state is a second level state and the second state is a first level state.

[0242] In this way, the isolation control signal has three different voltage values, which can provide more control methods to optimize the signal amplification process and improve the problems of slow signal amplification speed and high circuit noise.

[0243] S403: The amplifier circuit receives the isolation control signal and the signal to be processed according to the preset instruction, processes the signal to be processed, and completes the preset instruction.

[0244] In this way, after receiving the preset command, the isolation control signal and the signal to be processed are determined. The amplifier circuit can then process the signal to be processed based on the isolation control signal to complete the preset command. Furthermore, since the isolation control signal has three different voltage values, it provides more control methods to optimize the signal amplification process and partially improve the problems of slow signal amplification speed and high circuit noise.

[0245] Specifically, in some embodiments, for Figure 8 The amplifier circuit 23 shown includes the following operating stages: standby stage, first charge sharing stage, second charge sharing stage, first amplification stage, second amplification stage, and pre-charge stage. The method may also include...

[0246] When the amplifier circuit is in standby mode, it is used to maintain the voltage of each node in the amplifier circuit at a preset potential.

[0247] The amplifier circuit is in the first charge sharing stage, and the target storage unit forms a signal to be processed according to the preset instructions;

[0248] The amplifier circuit is in the second charge sharing stage. In response to the isolation control signal, the signal to be processed is transmitted to the amplifier circuit.

[0249] The amplifier circuit is in the first amplification stage, amplifying and processing the signal to be processed.

[0250] The amplifier circuit is in the second amplification stage, and recovers the data of the target storage unit through the amplified signal to be processed;

[0251] During the pre-charge phase, the amplifier circuit completes the preset instructions to the target memory cell and restores the voltage of each node in the amplifier circuit to the preset potential.

[0252] It should be noted that, as Figure 8 As shown, during the standby phase, bit line Bla / complementary bit line Blab, read bit line saBla / complementary read bit line saBlb, and the first reference signal NCS / second reference signal PCS are maintained at a preset potential by the fourth preset power supply, so that they can work according to the received preset instructions. At this time, the isolation control signal Iso needs to be in the second level state, and the ninth switch 309 and the tenth switch 310 are in the on state.

[0253] Assume the target memory cell of the preset instruction is the first memory cell 51. Upon receiving the preset instruction, the first charge sharing stage begins, activating the first memory cell 51 to facilitate connection between it and the bit line Bla, thus enabling charge sharing between the two. At this time, the isolation control signal Iso needs to be in the first level state, and the ninth switch 309 and the tenth switch 310 are in the off state, preventing connection between the bit line Bla and the read bit line saBla, as well as between the complementary bit line Blb and the complementary read bit line saBlb, to avoid affecting charge sharing between the first memory cell 51 and the bit line Bla.

[0254] After the first charge sharing phase ends, bit line Bla and read bit line saBla need to be connected, and complementary bit line Blb and complementary read bit line saBlb need to be connected. Amplifier circuit 23 then enters the second charge sharing phase. At this time, bit line Bla and read bit line saBla share charge, and complementary bit line Blb and complementary read bit line saBlb also share charge. During this period, the isolation control signal Iso needs to be in the second level state, and the ninth switch 309 and the tenth switch 310 are in the on state to connect bit line Bla and read bit line saBla, and also connect complementary bit line Blb and complementary read bit line saBlb.

[0255] After the second charge sharing phase ends, the amplifier circuit 23 enters the first amplification phase, amplifying the potentials of the readout bit line saBla and the complementary readout bit line saBlb through the amplifier circuit 23.

[0256] After the first amplification stage ends, the amplifier circuit 23 enters the second amplification stage. It needs to use the amplified potential on the read bit line saBla to rewrite data to the first storage cell 51 via the connection between the bit line Bla and the first storage cell 51, thereby restoring the data in the first storage cell 51. It should be understood that at this time, the amplified potential on the complementary read bit line saBlb will also be transmitted to the complementary bit line Blb, but since the storage cell on the complementary bit line Blb is not turned on, it will not be written to the storage cell.

[0257] After the second amplification stage ends, the first memory cell 51 needs to be turned off, and the connection between the target memory cell and the bit line Bla needs to be disconnected. At this point, the preset instruction can be considered completed. Then, the amplification circuit enters the pre-charge stage, and then restores the bit line Bla, the complementary bit line Blb, the read bit line saBla, and the complementary read bit line saBlb to the preset potential.

[0258] In addition, during the first amplification stage, the second amplification stage, and the precharge stage, the isolation control signal is maintained at the second level. The ninth switch 309 and the tenth switch 310 are in the on state, thereby keeping the bit line Bla and the read bit line saBla on, and the complementary bit line Blb and the complementary read bit line saBlb on.

[0259] After the pre-charge phase ends, the amplifier circuit enters the standby phase again to prepare for the next operation.

[0260] In this way, through the above stages, the signal to be processed is amplified by the amplifier circuit 23 in order to complete the preset instructions.

[0261] Based on this, such as Figure 8 and Figure 10 As shown, since the isolation power supply value VisoInt output by the power output circuit 212 can have a first voltage value or a second voltage value, the isolation control signal Iso output by the isolation control circuit 22 can have a first voltage value, a second voltage value, or a third voltage value. In other words, based on the isolation control signal Iso being in the second level state, it is possible to further control whether the isolation control signal Iso is in the first voltage value or the second voltage value.

[0262] The following is for Figure 10 The application scenarios are explained in detail, and the variation of the isolation control signal in different operating stages of the amplifier circuit is described in detail.

[0263] In some embodiments, the amplification circuit processes the signal to be processed, which may include:

[0264] When the amplifier circuit is in one of the signal amplification stages, the isolation control signal is controlled to have a first voltage value;

[0265] The preset instruction is a read instruction or a refresh instruction, and the signal amplification stage includes a first amplification stage and a second amplification stage.

[0266] The preset instruction is a write instruction, and the signal amplification stage includes a first amplification stage, a signal writing stage, and a second amplification stage.

[0267] In this way, by controlling the isolation control signal to have a first voltage value during one stage of the signal amplification process, the rate of change of the signal to be processed can be accelerated. Meanwhile, by controlling the isolation control signal to have a second voltage value during other stages of the signal amplification process, power consumption can be saved and the circuit lifespan can be extended. Thus, the signal amplification process is optimized.

[0268] The following sections provide a detailed description of read, refresh, and write commands.

[0269] In one specific embodiment, the preset instruction is a read instruction. The amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes:

[0270] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the standby stage, the second charge sharing stage, or the first amplification stage, the isolation control signal is maintained with a second voltage value; or if the amplifier circuit is in the pre-charge stage or the second amplification stage, the isolation control signal is maintained with a first voltage value.

[0271] It should be noted that, see Figure 11 This illustrates a signal timing diagram of a read operation provided in an embodiment of this disclosure. Figure 11 In this context, VisoInt refers to the aforementioned preset power supply signal, which can be a first voltage value or a second voltage value; Iso refers to the aforementioned isolation control signal, which can be a first voltage value, a second voltage value, or a third voltage value; Eq refers to the aforementioned precharge signal; Nc refers to the aforementioned noise cancellation signal; SanEn refers to the aforementioned first reference control signal; SapEn refers to the aforementioned second reference control signal; WL refers to the word line enable signal. When WL is at the second level, the word line where the target memory cell is located is enabled, thus connecting the target memory cell and the bit line. When WL is at the first level, the word line where the target memory cell is located is disabled, thus de-connecting the target memory cell and the bit line; NCS / PCS refers to the first reference signal / second reference signal. The first reference signal has a fourth voltage value and a fifth voltage value, and the second reference signal has a fourth voltage value and a sixth voltage value. The fourth voltage value refers to the aforementioned preset potential, and the fourth voltage value is between the fifth voltage value and the sixth voltage value; Bla refers to the bit line; Blb refers to the complementary bit line; saBla refers to the read bit line; and saBlb refers to the complementary read bit line.

[0272] like Figure 11As shown, when the amplifier circuit is in standby mode, the preset power supply signal VisoInt maintains the second voltage value, the isolation control signal Iso maintains the second voltage value, the precharge signal Eq and the noise cancellation signal Nc are at the second level, the first reference control signal SanEn and the second reference control signal SapEn are both at the first level, the word line enable signal WL is at the first level, the first reference signal NCS and the second reference signal PCS maintain the fourth voltage value, and the bit line Bla / complementary bit line Blab and the readout bit line saBla / complementary readout bit line saBlb are all at the fourth voltage value. At this time, all circuit nodes of the amplifier circuit 23 are at the same voltage value, preparing for the execution of user operation commands.

[0273] Assuming the target memory cell is the first memory cell 51, after the user sends a read command for the target memory cell, the amplifier circuit 23 enters the noise cancellation stage from the standby stage. At this time, the isolation control signal Iso is adjusted from the second voltage value to the third voltage value, the precharge signal Eq is adjusted from the second level state to the first level state, and the first reference control signal SanEn and the second reference control signal SapEn are both adjusted from the first level state to the second level state. Therefore, the first reference signal NCS changes from the fourth voltage value to the fifth voltage value, and the second reference signal PCS changes from the fourth voltage value to the sixth voltage value, while the noise cancellation signal Nc remains at the second level state, thereby performing noise cancellation processing on the amplifier circuit 23. Afterwards, the first reference control signal SanEn and the second reference control signal SapEn switch to the first level state, and the first reference signal NCS and the second reference signal PCS continue to be powered by the precharge power supply to recover to the fourth voltage value.

[0274] After the noise cancellation phase ends, the word line enable signal WL changes to the second level, and the word line containing the target memory cell is turned on. This allows the amplifier circuit 23 to enter the first charge sharing phase, at which point the target memory cell (e.g., the first memory cell 51) is read. Figure 11 As shown, taking the data stored in the first storage cell 51 as "0" as an example, after the first charge sharing phase ends, the voltage of bit line Bla decreases, thus generating a signal to be processed, while the complementary bit line Blb forms a reference signal to be processed. Furthermore, during the first charge sharing phase, the preset power supply signal maintains a second voltage value, and the isolation control signal Iso maintains a third voltage value, so that bit line Bla is not connected to the read bit line saBla, and bit line Blb is not connected to saBlb. The precharge signal Eq, the noise cancellation signal Nc, and the first reference control signal SanEn / second reference control signal SapEn are all in the first level state.

[0275] After the first charge sharing phase ends, the amplifier circuit 23 enters the second charge sharing phase. In the second charge sharing phase, the isolation control signal Iso maintains the second voltage value, connecting bit line Bla to the read bit line saBla, and bit line Blb to saBlb. This allows the amplifier circuit 23 to receive the signal to be processed and the reference signal to be processed into the internal node, reducing the voltage of the read bit line saBla. This can be considered as charge sharing between bit line Bla / complementary bit line Blb and read bit line saBla / complementary read bit line saBlb. Furthermore, all signals except the isolation control signal Iso maintain the voltage values ​​from the previous phase.

[0276] After the second charge sharing phase ends, the amplifier circuit 23 enters the first amplification phase. The first reference control signal SanEn and the second reference control signal SapEn are adjusted from the first level state to the second level state. As a result, the first reference signal NCS changes from the fifth voltage value, and the second reference signal PCS changes from the fourth voltage value to the sixth voltage value. The voltage of the readout bit line saBla decreases, causing the ninth switch 309 to turn on. The second reference signal PCS pulls up the voltage of the complementary readout bit line saBlb, causing the sixth switch 306 to turn on. The first reference signal NCS pulls down the voltage of the readout bit line saBla. Thus, the amplifier circuit 23 can amplify the signal to be processed (the signal of bit line Bla) / the reference signal to be processed (the signal of complementary bit line Bla) according to the first reference signal NCS / the second reference signal PCS. The isolation control signal Iso still maintains the second voltage value to complete the signal amplification on the signal to be processed (the signal of bit line Bla) / the reference signal to be processed (the signal of complementary bit line Bla).

[0277] Additionally, if the data stored in the first storage cell 51 is "1", the voltage of the bit line Bla in the first amplification stage will be pulled up. Since the isolation control signal Iso is at the second voltage value, it can suppress the rise rate on the bit line Bla / complementary bit line Blb and reduce the noise on the bit line Bla / complementary bit line Blb. However, the signal on the readout bit line saBla / complementary readout bit line saBlb inside the amplifier circuit 23 can quickly reach the high reference potential / low reference potential.

[0278] After the first amplification stage, amplifier circuit 23 enters the second amplification stage. At this stage, the preset power supply signal VisoInt maintains the first voltage value, the isolation control signal Iso maintains the first voltage value, and the conduction levels of the ninth switch 309 and the tenth switch 310 are increased. This amplifies the signals on the signal to be processed (the signal on bit line Bla) / the reference signal to be processed (complementary bit line Blab). The amplified signal is then output by subsequent modules to obtain the target amplified signal, completing the read command. During this stage, a decrease or increase in the voltage of bit line Bla will rewrite the data to the target memory cell, preventing data loss due to the read command. Figure 11 As shown, before the end of the second amplification stage, the first reference control signal SanEn and the second reference control signal SapEn return to the first level state.

[0279] After the second amplification stage ends, the amplifier circuit 23 enters the precharge stage. The precharge signal Eq and the noise cancellation signal Nc are adjusted to the second level. At this time, the first reference signal NCS / second reference signal PCS will be restored to the fourth voltage value, and the bit line Bla / complementary bit line Blab and the readout bit line saBla / complementary readout bit line saBlb will be restored to the same voltage value.

[0280] After the pre-charge phase ends, the amplifier circuit 23 enters the standby phase again to prepare for the next operation.

[0281] Thus, the control amplifier circuit 20 provided in this embodiment has at least the following advantages: On the one hand, in the standby stage, the isolation control signal is a lower voltage value (second voltage value) in the second level state, which can avoid the problem of leakage current of the switching transistor, reduce the phenomenon of device failure, and improve the service life of the semiconductor memory; on the other hand, when entering the noise cancellation stage from the standby stage, the isolation control signal needs to be adjusted from the second level state to the first level state. Since the isolation control signal of this embodiment has a lower voltage value in the standby stage, the level state adjustment is faster, which can improve the speed of signal processing; on another hand, after entering the second signal sharing stage, since the isolation control signal is a lower voltage value (second voltage value) in the second level state, the noise during the voltage rise of the signal to be processed can be reduced, and the amplification margin can be improved; on yet another hand, by controlling the state of the three eleventh switching transistors, the discharge rate of the first reference signal can be adjusted, thereby reducing the noise during the potential decrease of the signal to be processed.

[0282] In another specific embodiment, when the preset instruction is a read instruction, another amplification control method can also be used:

[0283] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained with a first voltage value; or if the amplifier circuit is in the standby stage, the pre-charge stage, or the second amplification stage, the isolation control signal is maintained with a second voltage value.

[0284] It should be noted that, see Figure 12 This diagram illustrates a signal timing diagram of another read operation provided in an embodiment of this disclosure. The precharge signal Eq, noise cancellation signal Nc, second reference control signal SapEn, first reference signal NCS, second reference signal PCS, bit line Bla, complementary bit line Blb, readout bit line saBla, and complementary readout bit line saBlb are all related to the signal timing diagram of each stage of the amplification process. Figure 11 The amplification process is the same. In addition, the first reference control signal SanEn1 is used to control the on or off of the eleventh switch, and the first and second reference control signals SanEn2 are used to control the on and off of the other eleventh switches, thereby saving energy.

[0285] In this embodiment, during the second charge sharing stage or the first amplification stage, it is necessary to maintain the isolation control signal at a first voltage value. Increasing the turn-on speed of the ninth switch 309 and the tenth switch 310 improves the signal transmission speed between bit line Bla and readout bit line saBla, accelerates the amplification and rewriting process of the signal to be processed, saves signal amplification time, reduces the time the ninth switch 309 and the tenth switch 310 are in a high-voltage state, and extends their service life. Furthermore, by changing the isolation power supply value to the first voltage value earlier during the noise cancellation stage, the time required for the subsequent isolation control signal voltage to rise can be reduced.

[0286] Both of the above amplification control methods for read operations are acceptable, and the appropriate method can be selected based on the actual application scenario.

[0287] In another specific embodiment, the preset instruction is a refresh instruction. The amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes:

[0288] If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, the isolation control signal is determined to have a second voltage value; or if the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained with a first voltage value.

[0289] In some embodiments, the amplifier circuit is in a noise cancellation phase, maintaining the isolation power supply value as a first power supply value.

[0290] It should be noted that, see Figure 13 It shows a signal timing diagram of a refresh operation provided in an embodiment of the present disclosure. Figure 13 The status of each signal can be referred to Figure 11 I understand. In particular, Figure 13 The variation patterns of the precharge signal Eq, noise cancellation signal Nc, first reference control signal SanEn, second reference control signal SapEn, word line enable signal WL, first reference signal NCS, and second reference signal PCS are all consistent with... Figure 11 Similarly, the following only explains the changes in the isolation power supply value VisoInt and the isolation control signal Iso at different operating stages.

[0291] During standby mode Figure 13 and Figure 11 Similarly, the isolation power supply value VisoInt is also the second voltage value, and the isolation control signal Iso is also the second voltage value.

[0292] During the noise cancellation phase, the isolation control signal Iso also decreases from the second voltage value to the third voltage value. However, the isolation power supply value VisoInt is adjusted to the first voltage value in advance, thereby increasing the speed at which the subsequent isolation power supply signal Iso changes from the third voltage value to the first voltage value, and accelerating the signal transmission speed.

[0293] During the first charge sharing phase, the isolation power supply value Iso and the isolation power supply value VisoInt remain at the first voltage value, meaning that the control bit line Bla and the read bit line saBla are not connected, and the bit lines Blb and saBlb are not connected.

[0294] During the second charge sharing phase, the isolation power supply value VisoInt maintains the first voltage value, while the isolation power supply signal Iso directly increases from the third voltage value to the first voltage value. This is because the isolation power supply value is typically generated far from the amplifier circuit. By switching the isolation power supply value VisoInt to the first voltage value in advance, it not only matches the operation command signal but also reduces the transmission time of the first voltage value, thereby increasing the turn-on speed of the ninth switch 309 and the tenth switch 310.

[0295] During the first amplification stage, the isolation power supply value Iso and the isolation control signal Iso both maintain the first voltage value. This is because, under the influence of the first voltage value, the ninth switch 309 and the tenth switch 310 increase their conduction level. The voltage change of the read bit line saBLa is rapidly transmitted to the bit line BLa, and the voltage change of the bit line BLa is also transmitted to the first memory cell 51. This enables rapid amplification and rewriting of the signal to be processed, and shortens the time that the ninth switch 309 and the tenth switch 310 are under high voltage, thus improving their lifespan.

[0296] In the second amplification stage, the isolation power supply value VisoInt and the isolation control signal Iso are adjusted to the second voltage value. The reason is that in the first amplification stage, the voltage of the bit line BLa reaches 80-90% of the final voltage value, essentially completing the amplification of the signal to be processed. Adjusting the isolation control signal Iso to the second voltage value at this point allows the voltage of the bit line BLa to continue changing to the final voltage value, reducing the power consumption of the ninth switch 309 and the tenth switch 310, thereby shortening the signal amplification time.

[0297] During the pre-charge phase, the pre-charge signal Eq and the noise cancellation signal Nc are adjusted to the second level state to pre-charge each circuit node.

[0298] Thus, as Figure 13 As shown, for the refresh instruction, by raising the isolation power supply value to the first voltage value within the time period indicated by tRAS, the voltage rise process of the isolation control signal can be accelerated, increasing the charge transfer speed in the second charge sharing stage and the first amplification stage, and thus accelerating the signal transmission speed.

[0299] The control amplifier circuit 20 provided in this embodiment has at least the following advantages: On the one hand, in the standby stage, the isolation control signal is a lower voltage value (second voltage value) in the second level state, which can avoid the problem of leakage current of the switching transistor, reduce the phenomenon of device failure, and improve the service life of the semiconductor memory; on the other hand, when entering the noise cancellation stage from the standby stage, the isolation control signal needs to be adjusted from the second level state to the first level state. Since the isolation control signal of this embodiment has a lower voltage value in the standby stage, the level state adjustment is faster, which can improve the speed of signal processing.

[0300] In another specific embodiment, the preset instruction is a write instruction. The amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a charge sharing stage (a first charge sharing stage and a second charge sharing stage), a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage; the method further includes:

[0301] If the amplifier circuit is in the noise cancellation stage, charge sharing stage, or first amplification stage, then the isolation control signal maintains a third voltage value; or

[0302] If the amplifier circuit is in standby, second amplification, or pre-charge stage, the isolation control signal maintains a second voltage value; or

[0303] If the amplifier circuit is in the signal writing stage, the isolation control signal will maintain a first voltage value.

[0304] It should be noted that, see Figure 14 It shows a signal timing diagram of a refresh operation provided in an embodiment of the present disclosure, with stored data as "0" and written data as "1" for illustration. Figure 14 The status of each signal can be referred to Figure 11 understand.

[0305] In particular, Figure 14 The variation patterns of the precharge signal Eq, noise cancellation signal Nc, first reference control signal SanEn, second reference control signal SapEn, word line enable signal WL, first reference signal NCS, and second reference signal PCS are all consistent with... Figure 11 Similarly, the following only explains the changes in the isolation power supply value VisoInt and the isolation control signal Iso at different operating stages.

[0306] During the standby phase, noise cancellation phase, and first charge sharing phase, the isolation power supply value VisoInt and the isolation control signal Iso are... Figure 14 and Figure 11 The patterns of change are the same, so I will not elaborate on them here.

[0307] During the second charge sharing phase and the first amplification phase, the isolation control signal Iso does not increase from the third voltage value, but continues to maintain the third voltage value. The reason is that after the first memory cell 51 is turned on, it is connected to the bit line Bla, and a signal to be processed is formed on the bit line Bla. Since the signal to be processed is formed by the memory cell, and the write instruction needs to transmit a new write signal to the memory cell, in the second charge sharing phase, the write signal has not yet been transmitted to the bit line Bla. The amplification circuit can only process the signal to be processed formed by the memory cell, and there is no need to process the signal to be processed quickly. However, the complementary bit line Blb voltage, which is higher than the bit line Bla, will cause the sixth switch 306 to partially conduct. The second reference voltage PCS gradually lowers the voltage of the readout bit line saBla, causing the sixth switch 306 to partially conduct. The first reference voltage NCS gradually raises the voltage of the complementary readout bit line saBlb, thereby affecting the turn-off state of the ninth switch 309 and the tenth switch 310. The voltage of the bit line Bla will slowly decrease, and the voltage of the complementary bit line Blb will slowly increase. Maintaining the third voltage value by the isolation control signal Iso can extend the turn-off time of the amplifier circuit and reduce the power consumption of the amplifier circuit.

[0308] During the signal writing phase, the isolation control signal increases from the third voltage value to the first voltage value. At this time, the high-voltage signal being written is transmitted to the bit line BLa. Under the influence of the write signal, the voltage of bit line BLa rises rapidly, causing the fifth switch 305 to turn on quickly. The first reference signal NCS pulls down the voltage of the complementary readout bit line saBlb, promoting the turn-on of the eighth switch 308. The second reference signal PCS pulls up the voltage of the readout bit line saBla. At this time, the ninth and tenth switches 310, with their high conduction levels, further accelerate the change in the bit line BLa voltage, quickly reaching the maximum voltage value. The change in BLa voltage causes the voltage of the connected memory cells to also change rapidly, converting the stored data from "0" to "1". The increase in the isolation control signal from the third voltage value to the first voltage value improves the signal writing speed and ensures data writing quality.

[0309] In the second amplification stage, the isolation control signal is reduced from the first voltage value to the second voltage value. The reason is that since the signal writing is basically completed in the previous stage, setting the isolation control signal to the second voltage value can continue to maintain the voltage of the write signal, ensure the completion of the write command, and reduce the power consumption of the ninth switch 309 and the tenth switch 310.

[0310] During the pre-charge phase, the pre-charge signal Eq and the noise cancellation signal Nc are adjusted to the second level state to pre-charge each circuit node.

[0311] Thus, as Figure 14As shown, for write commands, when a precharge operation follows a data write operation, the isolation power supply value switches from the second voltage value to the first voltage value within the tWR time after the data write operation, thus achieving a fast write operation. At other times, the isolation power supply value remains at the second voltage value to save power.

[0312] It should also be noted that the embodiments disclosed herein protect the timing variation of the isolation control signal, and the operating stages of the amplifier circuit are only for illustrative purposes. Therefore, the operating stages of the amplifier circuit in these embodiments do not have any additional limiting significance. In fact, the operating stages of the amplifier circuit can have various names and distinctions.

[0313] In addition, for Figure 8 The amplifier circuit shown, which does not have noise cancellation functionality, may not have a noise cancellation stage. Therefore, in some embodiments, the operating states of the amplifier circuit for a read command include a standby stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage. The amplifier circuit shown receives an isolation control signal and a signal to be processed according to a preset command, which may include:

[0314] If the amplifier circuit is in the standby stage or the second charge sharing stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the signal processing state or the pre-charge stage, the isolation control signal is maintained with a second voltage value; or if the amplifier circuit is in the first charge sharing stage, the isolation control signal is maintained with a first voltage value.

[0315] In other embodiments, the operating states of the amplifier circuit in response to a refresh command include a standby phase, a first charge sharing phase, a second charge sharing phase, a first amplification phase, a second amplification phase, and a pre-charge phase; the amplifier circuit shown receives an isolation control signal and a signal to be processed according to a preset command, and may include:

[0316] If the amplifier circuit is in the first charge sharing stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, the isolation control signal is maintained with a second voltage value; or if the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained with a first voltage value.

[0317] In some other embodiments, for a write instruction, the operating states of the amplifier circuit include a standby stage, a charge sharing stage, a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage; the amplifier circuit shown receives an isolation control signal and a signal to be processed according to a preset instruction, and may include:

[0318] If the amplifier circuit is in the charge sharing stage or the first amplification stage, the isolation control signal is maintained at a third voltage value; or if the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, the isolation control signal is maintained at a second voltage value; or if the amplifier circuit is in the signal writing stage, the isolation control signal is maintained at a first voltage value.

[0319] In this way, during the process of completing the preset operation, the isolation power supply has at least three voltage values, which are switched according to the specific working stage of the amplifier circuit. This can optimize the signal amplification process and partially improve the problems of slow signal amplification speed and high circuit noise.

[0320] In particular, the above stages and signal change patterns can be understood with reference to the foregoing embodiments.

[0321] This disclosure provides a control amplification method, comprising: receiving a preset instruction; determining an isolation power supply value and a control instruction signal according to the preset instruction; generating an isolation control signal according to the isolation power supply value and the control instruction signal; and having an amplification circuit receive the isolation control signal and a target signal to be processed according to the preset instruction, process the target signal, and complete the preset instruction. Thus, by controlling the specific voltage value of the isolation control signal through the isolation power supply value, the signal amplification process can be optimized, at least partially improving the problems of slow signal amplification speed and high circuit noise.

[0322] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 15 This illustrates a schematic diagram of the composition of a sensitive amplifier 60 provided in an embodiment of this disclosure. For example... Figure 15 As shown, the sensitive amplifier 60 may include the control amplifier circuit 20 described in any of the foregoing embodiments.

[0323] Thus, since the sensitive amplifier 60 may include the control amplifier circuit 20 described in any of the foregoing embodiments, it can control the isolation power supply value using the power switching signal. Subsequently, the specific voltage value of the isolation power supply can be adjusted by changing the power switching signal, thereby improving the problems of slow signal amplification speed and high circuit noise.

[0324] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 16 This illustrates a schematic diagram of the structural composition of a semiconductor memory 70 provided in an embodiment of this disclosure. For example... Figure 16 As shown, the semiconductor memory 70 may include the sensitive amplifier 60 described in any of the foregoing embodiments.

[0325] In this embodiment of the disclosure, the semiconductor memory 70 can be a DRAM chip.

[0326] Thus, since the semiconductor memory 70 includes the aforementioned sensitive amplifier 60, it can control the isolation power supply value using the power switching signal. Subsequently, the specific voltage value of the isolation power supply can be adjusted by changing the power switching signal, thereby improving the problems of slow signal amplification speed and high circuit noise.

[0327] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0328] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0329] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0330] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0331] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0332] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0333] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for controlling amplification, characterized in that, Applied to amplifier circuits; the method includes: Receive a preset instruction and determine the isolation power value and control instruction signal according to the preset instruction; An isolation control signal is generated based on the isolation power supply value and the control command signal; The amplifier circuit receives the isolation control signal and the target signal to be processed according to the preset instruction, processes the signal to be processed, and completes the preset instruction. The preset instructions include at least one of the following: read instructions, refresh instructions, and write instructions; The isolation power supply value is a first voltage value or a second voltage value; the first voltage value is greater than the second voltage value. When the preset instruction is a read instruction, the amplification circuit processes the signal to be processed, including: a first amplification stage and a second amplification stage; the method further includes: If the amplifier circuit is in the first amplification stage, then the isolation control signal is maintained at the second voltage value; or If the amplifier circuit is in the second amplification stage, the isolation control signal is maintained at the first voltage value.

2. The controlled amplification method according to claim 1, characterized in that, The isolation control signal is one of a first voltage value, a second voltage value, and a third voltage value; The second voltage value is greater than the third voltage value.

3. The controlled amplification method according to claim 2, characterized in that, The step of determining the isolation power supply value according to the preset instruction includes: According to the preset instruction, the first power switching signal and / or the second power switching signal are obtained; The isolation power value is determined based on the first power switching signal and / or the second power switching signal; Determining the isolation power value based on the first power switching signal and / or the second power switching signal includes: When the first power switching signal has a first level state and the second power switching signal has a second level state, it is determined that the isolation power supply value has a first voltage value; or When the first power switching signal has a second level state and the second power signal has a first level state, it is determined that the isolation power value has a second voltage value; Both the first voltage value and the second voltage value belong to the second level state.

4. The controlled amplification method according to claim 2, characterized in that, The step of generating an isolation control signal based on the isolation power supply value and the control command signal includes: When the control command signal has a second state and the isolation power supply value has a first voltage value, it is determined that the isolation control signal has a first voltage value; or When the control command signal has a second state and the isolation power supply value has a second voltage value, it is determined that the isolation control signal has a second voltage value; or If the control command signal has a first state, it is determined that the isolation control signal has a third voltage value; The first state is either a first level state or a second level state, the second state is either a first level state or a second level state, and the first state and the second state are at different level states; the third voltage value belongs to the first level state.

5. The controlled amplification method according to claim 2, characterized in that, The amplification circuit processes the signal to be processed, including a signal amplification stage, in which the amplification circuit amplifies the signal to be processed and writes it into a storage unit. When the amplifier circuit is in one of the signal amplification stages, the isolation control signal is controlled to have a first voltage value; The preset instruction is a read instruction or a refresh instruction, and the signal amplification stage includes a first amplification stage and a second amplification stage. The preset instruction is a write instruction, and the signal amplification stage includes a first amplification stage, a signal writing stage, and a second amplification stage.

6. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a read instruction, the amplification circuit further includes the following steps when processing the signal to be processed: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, and a pre-charge stage; the method further includes: If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal maintains a third voltage value; or If the amplifier circuit is in the standby stage or the second charge sharing stage, then the isolation control signal is maintained with a second voltage value; or If the amplifier circuit is in the pre-charge phase, the isolation control signal is maintained at a first voltage value.

7. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a read instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes: If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal maintains a third voltage value; or If the amplification circuit is in the second charge-sharing stage or the first amplification stage, then the isolation control signal is maintained at a first voltage value; or If the amplifier circuit is in the standby stage, the pre-charge stage, or the second amplification stage, the isolation control signal is maintained to have a second voltage value.

8. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a refresh instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes: If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, then the isolation control signal is maintained with a third voltage value; or If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal is determined to have a second voltage value; or If the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained to have a first voltage value.

9. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a write instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a charge sharing stage, a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage; the method further includes: If the amplification circuit is in the noise cancellation stage, the charge sharing stage, or the first amplification stage, then the isolation control signal is maintained at a third voltage value; or If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or If the amplifier circuit is in the signal writing stage, the isolation control signal is maintained at a first voltage value.

10. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a read instruction, the operating states of the amplification circuit include a standby stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes: If the amplifier circuit is in the standby stage or the second charge sharing stage, then the isolation control signal is maintained with a third voltage value; or If the amplifier circuit is in signal processing or pre-charging state, the isolation control signal is maintained at the second voltage value; or If the amplifier circuit is in the first charge sharing stage, the isolation control signal is maintained to have a first voltage value.

11. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a refresh instruction, the operating states of the amplification circuit include a standby stage, a first charge sharing stage, a second charge sharing stage, a first amplification stage, a second amplification stage, and a pre-charge stage; the method further includes: If the amplifier circuit is in the first charge sharing phase, then the isolation control signal is maintained at a third voltage value; or If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or If the amplifier circuit is in the second charge sharing stage or the first amplification stage, the isolation control signal is maintained to have a first voltage value.

12. The controlled amplification method according to claim 2, characterized in that, When the preset instruction is a write instruction, the amplification circuit processes the signal to be processed, including: a standby stage, a charge sharing stage, a first amplification stage, a signal writing stage, a second amplification stage, and a pre-charge stage. If the amplification circuit is in the charge sharing stage or the first amplification stage, then the isolation control signal is maintained with a third voltage value; or If the amplifier circuit is in the standby stage, the second amplification stage, or the pre-charge stage, then the isolation control signal maintains a second voltage value; or If the amplifier circuit is in the signal writing stage, the isolation control signal is maintained at a first voltage value.

13. The control amplification method according to any one of claims 6-12, characterized in that, The method further includes: The amplifier circuit is in the standby stage, which is used to maintain the voltage of each node in the amplifier circuit at a preset potential. The amplifier circuit is in the first charge sharing stage, and the target storage unit forms a signal to be processed according to the preset instruction. When the amplifier circuit is in the second charge sharing stage, in response to the isolation control signal, the signal to be processed is transmitted to the amplifier circuit. The amplifier circuit is in the first amplification stage, and the amplifier circuit amplifies and processes the signal to be processed. The amplification circuit is in the second amplification stage, and recovers the data of the target storage unit through the amplified signal to be processed; The amplifier circuit is in the pre-charge stage. The amplifier circuit completes the preset command to the target storage unit and restores the voltage of each node in the amplifier circuit to the preset potential.

14. The controlled amplification method according to claim 13, characterized in that, When the preset instruction is a write instruction, the amplifier circuit is in the signal writing stage. The amplifier circuit receives a write signal, and the write signal replaces the signal generated by the storage unit to form the signal to be processed. The amplifier circuit amplifies the signal to be processed.

15. The control amplification method according to claim 7 or 8, characterized in that, The method further includes: The amplifier circuit is in the noise cancellation stage, and the isolation power supply value is maintained as the first power supply value.

16. The controlled amplification method according to any one of claims 6-9, characterized in that, The amplifier circuit is in the noise cancellation stage, and the amplifier circuit performs offset cancellation operation on the transistors in the amplifier circuit in response to the isolation cancellation signal.

17. A control amplifier circuit, applied to the control amplification method according to any one of claims 1 to 16, characterized in that, The control amplifier circuit includes a signal determination circuit, an isolation control circuit, and an amplifier circuit; wherein... The signal determination circuit is used to determine the isolation power supply value and control command signal according to the preset command after receiving the preset command; The isolation control circuit is used to receive the isolation power value and the control command signal, and generate an isolation control signal according to the control command signal; The amplification circuit is used to receive the isolation control signal and the signal to be processed according to the preset instruction, amplify the signal to be processed, and complete the preset instruction.

18. The control amplifier circuit according to claim 17, characterized in that, The isolation power supply value and control command signal are determined by a signal determination circuit, and the isolation control signal is determined by an isolation control circuit. The signal determination circuit includes a first signal determination circuit, a power output circuit, and a second signal determination circuit; wherein... The first signal determining circuit is used to output a first power switching signal and / or a second power switching signal according to the preset instruction after receiving the preset instruction; The power output circuit is used to output an isolation power value according to the first power switching signal and / or the second power switching signal; The second signal determining circuit is used to generate the control command signal according to the preset instruction; The preset instructions include at least one of the following: read instructions, refresh instructions, and write instructions.

19. The control amplifier circuit according to claim 18, characterized in that, The power output circuit is used to determine that the isolation power value has a first voltage value when the first power switching signal has a first level state and the second power switching signal has a second level state. or When the first power switching signal has a second level state and the second power signal has a first level state, it is determined that the isolation power value has a second voltage value; Wherein, both the first voltage value and the second voltage value belong to the second level state, and the first voltage value is greater than the second voltage value.

20. The control amplifier circuit according to claim 19, characterized in that, The isolation control circuit is specifically used to determine that the isolation control signal has a first voltage value when the control command signal has a second state and the isolation power supply value has a first voltage value. or When the control command signal has a second state and the isolation power supply value has a second voltage value, it is determined that the isolation control signal has a second voltage value. or If the control command signal has a first state, it is determined that the isolation control signal has a third voltage value; Wherein, the first state is either a first level state or a second level state, the second state is either a first level state or a second level state, and the first state and the second state are at different level states; The third voltage value belongs to the first level state, and the third voltage value is less than the second voltage value.

21. The control amplifier circuit according to claim 20, characterized in that, The power output circuit includes a first preset power supply, a second preset power supply, a first switching transistor, and a second switching transistor; wherein... The first terminal of the first switching transistor is connected to the first power switching signal, and the first terminal of the second switching transistor is connected to the second power switching signal; The second end of the first switching transistor is connected to the first preset power supply, and the second end of the second switching transistor is connected to the second preset power supply; The third terminal of the first switching transistor is connected to the third terminal of the second switching transistor, and is used to output the isolation power value; Wherein, the first preset power supply is used to output the first voltage value, and the second preset power supply is used to output the second voltage value; The isolation control circuit includes a first inverter, a third switch, and a fourth switch; wherein... The input terminal of the first inverter is connected to the control command signal, and the output terminal of the first inverter is connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively. The second terminal of the third switch is connected to the isolation power supply value, and the third terminal of the fourth switch is connected to the ground signal; The third terminal of the third switch is connected to the second terminal of the fourth switch to output the isolation control signal.

22. The control amplifier circuit according to claim 21, characterized in that, The amplifier circuit includes a control circuit and a cross-coupling circuit. The cross-coupling circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The control circuit includes a ninth switch and a tenth switch. The first end of the fifth switch is connected to the third end of the ninth switch for receiving the signal to be processed. The second end of the fifth switch, the third end of the seventh switch, the first end of the eighth switch, and the second end of the tenth switch are connected. The first end of the sixth switch is connected to the third end of the tenth switch for receiving a reference signal to be processed. The second end of the sixth switch, the third end of the eighth switch, the first end of the seventh switch, and the second end of the ninth switch are connected. The third terminal of the fifth switch and the third terminal of the sixth switch are connected to the first reference signal, the second terminal of the seventh switch and the second terminal of the eighth switch are connected to the second reference signal, and the first terminal of the ninth switch and the first terminal of the tenth switch are connected to the isolation control signal.

23. The control amplifier circuit according to claim 22, characterized in that, The amplifier circuit further includes a pre-charging circuit, and the pre-charging circuit includes a thirteenth switching transistor and a fourteenth switching transistor; wherein, The first terminal of the thirteenth switch and the first terminal of the fourteenth switch are connected to the precharge control signal; The second terminal of the thirteenth switch is connected to the fourth preset power supply, and the third terminal of the thirteenth switch is connected to the second terminal of the sixth switch. The third terminal of the fourteenth switch is connected to the second terminal of the fifth switch, and the second terminal of the fourteenth switch is connected to the second terminal of the sixth switch. The amplification circuit further includes a noise cancellation circuit, which comprises a fifteenth switching transistor and a sixteenth switching transistor; wherein, The first terminal of the fifteenth switch and the first terminal of the sixteenth switch are connected to the noise control signal; The second end of the fifteenth switch is connected to the second end of the fifth switch, and the third end of the fifteenth switch is connected to the first end of the fifth switch. The second terminal of the sixteenth switch is connected to the second terminal of the sixth switch, and the third terminal of the sixteenth switch is connected to the first terminal of the sixth switch.

24. The control amplifier circuit according to any one of claims 18 to 23, characterized in that, The first, second, third, seventh, and eighth switching transistors are P-channel MOSFETs. The fourth, fifth, sixth, ninth, tenth, thirteenth, fourteenth, fifteenth, and sixteenth switching transistors are N-channel MOSFETs. Wherein, the first terminal of the P-type field-effect transistor is the gate terminal, the second terminal of the P-type field-effect transistor is the source terminal, and the third terminal of the P-type field-effect transistor is the drain terminal; the first terminal of the N-type field-effect transistor is the gate terminal, the second terminal of the N-type field-effect transistor is the drain terminal, and the third terminal of the N-type field-effect transistor is the source terminal.

25. A sensitive amplifier, characterized in that, Includes the control amplifier circuit as described in any one of claims 17 to 24.

26. A semiconductor memory, characterized in that, Includes the sensitive amplifier as described in claim 25.

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