Method of fabricating a multilayer chip package structure
By using two carrier boards filled with molding compound in board-level fan-out packaging technology, a multi-layer chip packaging structure is formed, which solves the problems of excessive packaging size, low strength and high cost, and achieves miniaturized, high-strength and high-reliability packaging effect.
CN116417351BActive Publication Date: 2026-07-17CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
- Filing Date
- 2021-12-31
- Publication Date
- 2026-07-17
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Figure CN116417351B_ABST
Abstract
The application provides a preparation method of a multilayer chip packaging structure. In the preparation method, a plurality of dies are fixed on two carrier boards respectively, the two carrier boards are arranged oppositely, and plastic sealing material is filled in the region between the two carrier boards. The dies on the two carrier boards are simultaneously subjected to plastic sealing, the stacking of the dies in space can be realized, the prepared chip packaging structure product is small in size, high in strength and reliability, high in material utilization rate, and low in cost.
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