Improved rise time control circuit with wide modulation range

Abstract

An improved rise time control circuit with a wide modulation range can achieve a wider modulation range by combining a second NMOS transistor, a first NMOS transistor, an error amplifier, and a first PMOS transistor that modulates the gate voltage of the power transistor at the gate node of the power transistor.

Description

Technical Field

[0001] The present invention relates to voltage rise time control technology, particularly an improved rise time control circuit with a wide modulation range. Background Art

[0002] Figure 3 It is a schematic diagram of the original rise time control circuit. Figure 4 It is Figure 3 a waveform schematic diagram of relevant nodes in Figures 3 to 4 As shown in the reference Figure 4 , the original rise time control circuit includes a power transistor MnPWR. The drain of MnPWR is connected to the power supply voltage terminal IN, the source of MnPWR is the voltage output voltage node OUT, and the gate node gate of MnPWR is respectively connected to a charge pump and the drain of a second NMOS transistor Mn1. The gate of Mn1 is connected to the power supply voltage terminal IN, the drain of Mn1 is connected to the source of a first PMOS transistor Mp0, the drain of Mp0 is grounded, and the gate of Mp0 is connected to the power supply voltage terminal IN through a first PMOS transistor gate node Vramp via a first path through a second current source Ibias and to ground through a first capacitor C0 via a second path. From the connection relationship of Mn1 and Mp0, it can be known that IN - Vramp = Vgsn1 + |Vgsp0|. When Vramp is low such that both Mp0 and Mn1 can be turned on, the gate voltage gate of MnPWR is modulated by Mp0, and VgnPWR = Vramp + Vgsp0. The gate voltage waveform is as Figure 4 shown. When Vramp rises to IN - Vramp = Vgsn1 + |Vgsp0| < Vthn1 + |Vthp0|, that is, when Vramp ≥ IN - Vthn1 - |Vthp0| = IN - 1.4V, then Mn1 and Mp0 are turned off, the path from the gate of MnPWR to ground is cut off, and the modulation effect of Mp0 on the gate voltage of MnPWR disappears, resulting in a segmented phenomenon with inconsistent rising slopes of the gate voltage of MnPWR as shown in SUMMARY OF THE INVENTION

[0003] In view of the defects or deficiencies in the prior art, the present invention provides an improved rise time control circuit with a wide modulation range.

[0004] The technical solution of the present invention is as follows:

[0005] An improved wide-range rise time control circuit is characterized by comprising a power transistor gate node, wherein the power transistor gate node is first connected to a charge pump and second connected to the source of a first PMOS transistor. The first PMOS transistor gate node is first connected to a power supply voltage terminal via a second current source and second connected to ground via a first capacitor. The drains of the first PMOS transistor and a second NMOS transistor are interconnected. The gate of the second NMOS transistor is connected to the power supply voltage terminal. The source of the second NMOS transistor is connected to the drain of the first NMOS transistor via a first node. The source of the first NMOS transistor is grounded. The gate of the first NMOS transistor is connected to the output terminal of an error amplifier. The negative input terminal of the error amplifier is connected to the gate node of the first PMOS transistor. The positive input terminal of the error amplifier is first connected to the power supply voltage terminal via a first resistor and second connected to ground via a first current source.

[0006] A first diode is connected across the gate and source of the second NMOS transistor.

[0007] The positive terminal of the first diode is connected to the first node, and the negative terminal of the first diode is connected to the power supply voltage terminal.

[0008] The maximum voltage of the first node = power supply voltage + forward bias voltage drop of the first diode.

[0009] Let the current of the first current source be I0 and the resistance of the first resistor be R0, then I0*R0≤50mV.

[0010] Let the power supply voltage be IN and the gate voltage of the first PMOS transistor be Vramp, then IN-I0*R0 >> IN-1.4V.

[0011] The power transistor is an NMOS power transistor, with its drain connected to the power supply voltage terminal and its source connected to the output voltage node.

[0012] The technical effects of the present invention are as follows: The present invention provides an improved rise time control circuit with a wide modulation range. By combining a second NMOS transistor, a first NMOS transistor, an error amplifier, and a first PMOS transistor that modulates the gate voltage of the power transistor at the gate node of the power transistor, it is possible to achieve a wider modulation range. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the structural principle of an improved wide modulation range rise time control circuit that implements the present invention.

[0014] Figure 2 yes Figure 1 A waveform diagram of the relevant nodes. Figure 2It includes the gate node of the power transistor (MnPWR), the gate node Vramp of the first PMOS transistor (Mp0), and the source output voltage node OUT of the power transistor (MnPWR). Figure 2 Compared to the gate in Figure 4 In the gate, the third of the five segments is longer, and the fourth segment is shorter. Figure 2 Compared to OUT Figure 4 In the OUT section, the second of the four paragraphs is longer, and the third paragraph is shorter. Figure 2 In the value, IN-I0*R0 >> IN-1.4V.

[0015] Figure 3 This is a schematic diagram of the original rise time control circuit.

[0016] Figure 4 yes Figure 3 A waveform diagram of the relevant nodes. Figure 4 It includes the gate node of the power transistor (MnPWR), the gate node Vramp of the first PMOS transistor (Mp0), and the source output voltage node OUT of the power transistor (MnPWR). Figure 4 Compared to the gate in Figure 2 In the gate, the third of the five segments is shorter, and the fourth segment is longer. Figure 4 Compared to OUT Figure 2 In the OUT section, the second of the four segments is shorter, and the third segment is longer. Figure 4 In the expression IN-1.4V << IN-I0*R0.

[0017] The reference numerals in the attached diagram are listed below: IN - power supply voltage terminal or power supply voltage (or represented by VIN); MnPWR - NMOS power transistor; gate - gate node of power transistor; OUT - output voltage node or output voltage of power transistor; Mp0 - first PMOS transistor; Mn0~Mn1 - first NMOS transistor to second NMOS transistor; Vramp - gate node of first PMOS transistor; A - first node; D0 - first diode; C0 - first capacitor; R0 - first resistor; Ibias - second current source; I0 - first current source; EA - error amplifier or comparator. Detailed Implementation

[0018] The following is in conjunction with the attached diagram ( Figures 1-2 The present invention will be described below.

[0019] Figure 1 This is a schematic diagram illustrating the structural principle of an improved wide modulation range rise time control circuit that implements the present invention. Figure 2 yes Figure 1 A waveform diagram of the relevant nodes. (Reference) Figures 1 to 2As shown, an improved wide modulation range rise time control circuit includes a power transistor gate node. The power transistor gate node is first connected to a charge pump and second connected to the source of a first PMOS transistor Mp0. The first PMOS transistor gate node Vramp is first connected to the power supply voltage terminal IN through a second current source Ibias and second connected to ground through a first capacitor C0. The first PMOS transistor Mp0 is interconnected with the drain of a second NMOS transistor Mn1. The gate of the second NMOS transistor Mn1 is connected to the power supply voltage terminal IN. The source of the second NMOS transistor Mn1 is connected to the drain of the first NMOS transistor Mn0 through a first node A. The source of the first NMOS transistor Mn0 is grounded. The gate of the first NMOS transistor Mn0 is connected to the output terminal of an error amplifier EA. The negative input terminal (-) of the error amplifier EA is connected to the first PMOS transistor gate node Vramp. The positive input terminal (+) of the error amplifier EA is first connected to the power supply voltage terminal IN through a first resistor R0 and second connected to ground through a first current source I0. A first diode D0 is connected across the gate and source of the second NMOS transistor Mn1.

[0020] The anode of the first diode D0 is connected to the first node A, and the cathode of the first diode D0 is connected to the power supply voltage terminal IN. The maximum voltage at the first node A equals the power supply voltage plus the forward bias voltage drop of the first diode. Assuming the first current source current is I0 and the first resistor is R0, then I0*R0 ≤ 50mV. Assuming the power supply voltage is IN and the gate voltage of the first PMOS transistor is Vramp, then IN - I0*R0 >> IN - 1.4V. The power transistor is an NMOS power transistor MnPWR, with its drain connected to the power supply voltage terminal IN and its source connected to the output voltage node OUT.

[0021] The circuit of the present invention is as follows Figure 1As shown, when the gate voltage Vramp of Mp0 < IN - I0 * R0, the comparator outputs a high level, causing Mn0 to conduct. This creates a current path between the gate of MnPWR and ground, flowing through Mp0, Mn1, and Mn0. The gate voltage of MnPWR is VgnPWR = Vramp + Vgsp0. When Vramp > IN - I0 * R0, the comparator outputs a low level, causing Mn0 to turn off. This cuts off the gate-to-ground path of MnPWR, allowing the gate voltage of MnPWR to rise to a higher potential under the drive of the charge pump, thus reducing the on-resistance of MnPWR. After Mn0 turns off, if there is no diode D0, the voltage at point A is pulled up to the gate potential of MnPWR. Generally, the gate voltage of MnPWR will rise to a potential of 2 * VIN under the drive of the charge pump. Therefore, the voltage difference between point A and ground, i.e., the drain-source voltage difference of Mn0, is 2 * VIN. When IN is connected to a power supply of 3V or higher, this will cause the drain-source of Mn0 to break down. Therefore, this scheme introduces diode D0 connected across the gate and source of Mn1. Under the protection of D0, the maximum value of the voltage VA at point A = IN + the forward bias voltage drop of diode D0, thus achieving the protection of the drain of Mn0 when Mn0 is cut off and the gate voltage of MnPWR rises to a high voltage. Generally, the design will ensure that the product of I0 and R0 does not exceed 50mV, so that the range of MnPWR gate voltage modulation by Mp0 is as wide as possible. The waveforms of the gate and source voltages of MnPWR after the improvement are as follows: Figure 2 As shown, Figure 2 Compared to the gate in Figure 4 In the gate, the third of the five segments is longer, and the fourth segment is shorter. Figure 2 Compared to OUT Figure 4 In the OUT section, the second of the four paragraphs is longer, and the third paragraph is shorter. Figure 2 In the value, IN-I0*R0 >> IN-1.4V.

[0022] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. An improved rise time control circuit with a wide modulation range, characterized in that, The device includes a power transistor gate node. The first path of the power transistor gate node is connected to a charge pump, and the second path is connected to the source of a first PMOS transistor. The first path of the first PMOS transistor gate node is connected to a power supply voltage terminal via a second current source, and the second path is grounded via a first capacitor. The drains of the first PMOS transistor and a second NMOS transistor are interconnected. The gate of the second NMOS transistor is connected to the power supply voltage terminal, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor via a first node. The source of the first NMOS transistor is grounded. The gate of the first NMOS transistor is connected to the output terminal of an error amplifier. The negative input terminal of the error amplifier is connected to the gate node of the first PMOS transistor. The positive input terminal of the error amplifier is connected to the power supply voltage terminal via a first resistor, and the second path is grounded via a first current source.

2. The improved wide modulation range rise time control circuit according to claim 1, characterized in that, A first diode is connected across the gate and source of the second NMOS transistor.

3. The improved wide modulation range rise time control circuit according to claim 1, characterized in that, The positive terminal of the first diode is connected to the first node, and the negative terminal of the first diode is connected to the power supply voltage terminal.

4. The improved wide modulation range rise time control circuit according to claim 3, characterized in that, The maximum voltage of the first node = power supply voltage + forward bias voltage drop of the first diode.

5. The improved wide modulation range rise time control circuit according to claim 1, characterized in that, Let the current of the first current source be I0 and the resistance of the first resistor be R0, then I0*R0≤50mV.

6. The improved wide modulation range rise time control circuit according to claim 5, characterized in that, Let the power supply voltage be IN and the gate voltage of the first PMOS transistor be Vramp, then IN-I0*R0 >> IN-1.4V.

7. The improved wide modulation range rise time control circuit according to claim 1, characterized in that, The power transistor is an NMOS power transistor, with its drain connected to the power supply voltage terminal and its source connected to the output node.

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