An impulse fuze modulation method and system

Abstract

The present invention provides an impulse fuze modulation method and system, belonging to the field of radio fuze technology. The method uses direct digital frequency synthesis technology to achieve pulse position modulation. The phase control word of the direct digital frequency synthesis technology can flexibly adjust the pulse position. At the same time, the phase control word is a true random signal sequence. The system includes: a random number generator, a crystal oscillator, an FPGA chip, an amplification and filtering circuit, and a signal judgment module. This solves the problem that the pseudo-random code modulation method used in existing impulse fuzes has the risk of being intercepted and the risk of adjacent fuzes winding around each other. It can fundamentally limit digital radio frequency storage technology, making forwarding deception interference completely ineffective.

Description

Technical Field

[0001] The present invention relates to the technical field of radio fuzes, and in particular to an impulse fuze modulation method and system. Background Art

[0002] Radio fuzes face an increasingly complex electromagnetic environment, primarily due to the complex electromagnetic space created by high-density, high-intensity, and multi-spectrum electromagnetic waves released intentionally or unintentionally by electronic information systems such as radar, communications, and satellites in battlefield environments. Furthermore, radio fuzes face the challenge of fuze jammers. Fuze jammers, now in their fourth generation, utilize digital radio frequency memory (DRFM) technology and possess the ability to intercept, store, and forward fuze signals. They can simultaneously jam multiple systems and targets, with improved jamming frequency bands, instantaneous bandwidth, and response times. They are capable of transmitting various electronic jamming signals, including targeted, swept, and deceptive jamming.

[0003] Impulse fuzes have become a hot topic in radio fuze research due to their excellent anti-interference and anti-stealth capabilities, high ranging accuracy, compact size, and low power consumption. To improve the sensitivity of impulse fuzes, a high repetition rate (PRF) design is generally used to increase the number of pulse accumulations and thus enhance processing gain. This high repetition rate design can cause range ambiguity. Impulse fuzes resolve range ambiguity by varying the pulse repetition frequency (PRF), a technique known as pulse position modulation (PPM). PPM signals generally use pseudorandom codes. Although PPM periods can be very long, the possibility of interception still exists. Furthermore, when using PPM modulation, there is a risk of interfering signals between adjacent fuzes. Summary of the Invention

[0004] The technical problem solved by the present invention is that the pseudo-random code modulation method adopted by the existing impulse fuze has the risk of being intercepted and adjacent fuzes winding around each other.

[0005] To solve the above problems, the technical solutions of the present invention are as follows:

[0006] An impulse fuze modulation method comprises the following steps:

[0007] S1, obtain the direct digital frequency synthesis operating frequency and pulse position modulation depth according to the impulse fuze pulse repetition frequency PRF;

[0008] S2, the clock signal output by the crystal oscillator is multiplied by the phase-locked loop to obtain the working clock signal of the direct digital frequency synthesis working frequency, and the working clock signal is transmitted to the phase accumulator, the phase-to-amplitude converter, and the digital-to-analog converter;

[0009] S3, obtaining a frequency control word according to the pulse repetition frequency and the direct digital frequency synthesis operating frequency;

[0010] S4, driven by the working clock signal, the phase accumulator continuously accumulates the frequency control word to obtain the instantaneous phase;

[0011] S5, a random number generator generates a random pulse sequence, uses the random pulse sequence as a phase control word, and outputs the phase control word to a phase accumulator;

[0012] S6, the phase accumulator adds the phase control word to the instantaneous phase to obtain a composite phase;

[0013] S7, the synthesized phase is converted into an output amplitude by a phase-to-amplitude converter, and the output amplitude is output to a digital-to-analog converter to obtain an analog output signal;

[0014] S8, the analog output signal is filtered out by a low-pass filter to remove the image and nonlinear noise, thereby obtaining a direct digital frequency synthesis output signal, and the direct digital frequency synthesis output signal is passed through a pulse shaping circuit to obtain a pulse signal with position modulation;

[0015] S9. The position-modulated pulse signal is divided into two paths. One path of the position-modulated pulse signal is passed through the first narrow pulse generator to obtain an impulse signal, which is then radiated outward through the first ultra-wideband antenna. The other path of the position-modulated pulse signal is delayed by the delay circuit and then passed through the second narrow pulse generator to obtain a sampling pulse signal.

[0016] S10, the impulse signal sent by the first ultra-wideband antenna is scattered by the target to obtain a scattered signal, the second ultra-wideband antenna receives the scattered signal, and the scattered signal and the sampling pulse signal are correlated and received by an equivalent sampling circuit to obtain a detection signal;

[0017] S11, the detection signal is output to the signal judgment module after the amplification and filtering circuit, and the signal judgment module outputs the proximity start signal after determining that the detection signal meets the target echo characteristics.

[0018] In step S1 of the above method, the direct digital frequency synthesis operating frequency F DDS The value range is (8~12)*PRF, and the pulse position modulation depth range is (1 / 4~1 / 8) / PRF.

[0019] In step S9 of the above method, the delay of the delay circuit is used to set the explosion height.

[0020] In modern battlefield environments, radio fuzes face challenges from both complex electromagnetic environments and radio fuze jammers. Fuze jammers, now in their fourth generation, are based on digital radio frequency memory (DRFM) technology and are capable of intercepting fuze signals and storing and forwarding them. They can simultaneously jam multiple systems and targets, with improved jamming frequency bands, instantaneous bandwidth, and response times. They are capable of transmitting various electronic jamming signals, including targeted, swept, and deceptive types. Impulse fuzes using random pulse position modulation (RPPM) fundamentally limit the use of DRFM technology due to their short pulse repetition period and true random pulse position modulation, making their signals non-relayable.

[0021] The above method realizes direct digital synthesis (DDS) through field programmable gate array (FPGA) and digital-to-analog converter (DAC).

[0022] This method uses direct digital frequency synthesis (DDS) technology to implement pulse position modulation. The DDS phase control word allows for flexible adjustment of the pulse position. The phase control word is a truly random signal sequence, making the pulse position unreproducible and unpredictable. This fundamentally limits digital radio frequency memory (DRFM) technology, rendering repeater-based deceptive jamming completely ineffective.

[0023] Furthermore, the random number generator generates a random pulse sequence including the following:

[0024] The noise amplifier circuit generates circuit noise, which is converted into a digital signal by the ADC acquisition circuit, and the digital signal is converted into a random pulse sequence by the parallel-to-serial conversion circuit.

[0025] Furthermore, the number of random digits of the circuit noise generated by the noise amplifier circuit is M, the pulse repetition frequency of the circuit noise generated by the noise amplifier circuit is PRF, the number of sampling bits of the ADC acquisition circuit is SB, the sampling frequency of the ADC acquisition circuit is FS, and the pulse repetition frequency PRF satisfies the condition: SB*FS≥M*PRF.

[0026] Furthermore, the relationship between the number of random digits of the circuit noise generated by the noise amplifier circuit and the pulse position modulation depth is expressed as follows:

[0027]

[0028] In the above formula, Depth rand is the pulse position modulation depth, M is the number of random bits of circuit noise generated by the noise amplifier circuit, Bits_Phase_in is the input bit of the phase-to-amplitude converter, F DDS is the operating frequency of the phase-to-amplitude converter, that is, the operating frequency of the direct digital frequency synthesis.

[0029] Furthermore, the signal decision module determines the detection signal including the following: after the detection signal is processed by the digital bandpass filter submodule, the template matching algorithm performs a correlation operation on the processed detection signal and the template signal stored locally in the FPGA chip to obtain the correlation coefficient ρ. When the correlation coefficient ρ is less than 0.8, the signal decision module determines that the detection signal meets the target echo characteristics, and the proximity start command output submodule outputs the proximity start command. The calculation formula of the correlation coefficient ρ is:

[0030]

[0031] In the above formula, ρ is the correlation coefficient, s i is the processed detection signal, m i is the template signal.

[0032] The present invention also provides an impulse fuze modulation system, which is applied to the above-mentioned impulse fuze modulation method, comprising:

[0033] Random number generator, which is used to generate phase control words.

[0034] Crystal oscillator, a crystal oscillator is used to provide a clock signal,

[0035] FPGA chip, FPGA chip is used to synthesize the phase control word and the frequency control word to obtain the output amplitude. The FPGA chip is electrically connected to the random number generator and the crystal oscillator.

[0036] Electrically connected in sequence: a digital-to-analog converter for converting the output amplitude into an analog output signal, a low-pass filter for filtering out the noise caused by the image and nonlinearity in the analog output signal to obtain a direct digital frequency synthesis output signal, a pulse shaping circuit for converting the direct digital frequency synthesis output signal into a pulse signal with position modulation, a first narrow pulse generator for converting the pulse signal with position modulation into an impulse signal, a first ultra-wideband antenna for transmitting the impulse signal, and the digital-to-analog converter is electrically connected to the FPGA chip.

[0037] Sequentially electrically connected are: a delay circuit, a second narrow pulse generator, an equivalent sampling circuit, and a second ultra-wideband antenna. The delay circuit is electrically connected to the pulse shaping circuit. The delay circuit is used to delay the position-modulated pulse signal. The second narrow pulse generator is used to sample the delayed position-modulated pulse signal. The second ultra-wideband antenna is used to receive the scattered signal after being scattered by the target. The equivalent sampling circuit is used to correlate the scattered signal with the sampled pulse signal.

[0038] The amplifying and filtering circuit is electrically connected to the equivalent sampling circuit.

[0039] The signal decision module is mounted on the FPGA chip and is electrically connected to the amplification and filtering circuit.

[0040] In the above system, the noise amplifier circuit adjusts the amplification factor according to the noise level, with the aim of amplifying the noise level to the full scale of the ADC. The ADC has differential nonlinearity during sampling, and the presence of sampling errors also makes the low-bit sampling values ​​random.

[0041] Preferably, the FPGA chip further includes:

[0042] A phase accumulator is electrically connected to the random number generator.

[0043] The phase-to-amplitude converter is electrically connected to the phase accumulator and the digital-to-analog converter.

[0044] The phase-locked loop is electrically connected to the phase accumulator, the phase-to-amplitude converter, the digital-to-analog converter, and the crystal oscillator.

[0045] Preferably, the random number generator includes: a noise amplifying circuit for generating and amplifying circuit noise, an ADC acquisition circuit for acquiring and performing digital-to-analog conversion on the circuit noise, and a parallel-to-serial conversion circuit electrically connected in sequence.

[0046] Preferably, the signal determination module includes: a digital bandpass filter submodule, a template matching algorithm, and a proximity start instruction output submodule electrically connected in sequence.

[0047] Further preferably, the low-pass filter is a fifth-order LC filter, the first narrow pulse generator and the second narrow pulse generator are both composed of step recovery diodes and peripheral inductors and capacitors electrically connected in sequence, the delay circuit is composed of several logic chips electrically connected in sequence, the equivalent sampling circuit is composed of mixing diodes and peripheral integral and differential resistance-capacitance circuits electrically connected in sequence, and the amplification and filtering circuit is a stage-by-stage active filtering amplifier circuit composed of three-stage operational amplifiers.

[0048] The fifth-order LC filter can use low-temperature co-fired ceramic (LTCC) technology to save volume.

[0049] The operational amplifier in the above-mentioned amplification and filtering circuit is powered by a single power supply, and the positive input port of the operational amplifier is connected to the reference power supply Vref, which is generally obtained by dividing the power supply voltage and following the operational amplifier.

[0050] The beneficial effects of the present invention are:

[0051] (1) The present invention provides an impulse fuze modulation method that implements direct digital frequency synthesis (DDS) through a field programmable gate array (FPGA) and a digital-to-analog converter (DAC). It has the advantages of high frequency resolution, continuous phase change, short frequency switching time, and is implemented in a fully digital manner.

[0052] (2) The present invention flexibly adjusts the pulse repetition period by introducing a phase control word. The phase control word is a true random signal sequence, and the pulse position is non-replicable and unpredictable. It can fundamentally limit the DRFM technology and make the forwarding deception interference completely ineffective. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a flow chart of an impulse fuze modulation method according to Example 1;

[0054] Figure 2 is an architecture diagram of a direct digital frequency synthesis system according to Example 2;

[0055] Figure 3 This is the amplification and filtering circuit diagram of Example 2;

[0056] Figure 4 1 is a circuit diagram of a first narrow pulse generator and a second narrow pulse generator in Example 2;

[0057] Figure 5 This is a block diagram of the random noise sequence implementation in Example 1;

[0058] Figure 6 is a circuit diagram of the delay circuit in Example 2;

[0059] Figure 7 1 is a circuit diagram of the peripheral integral-differential resistance-capacitance circuit in Example 2;

[0060] Among them, 1-random number generator, 2-FPGA chip, 21-phase accumulator, 22-phase-to-amplitude converter, 23-phase-locked loop, 24-signal judgment module, 3-crystal oscillator, 4-digital-to-analog converter, 5-low-pass filter, 6-pulse shaping circuit, 7-first narrow pulse generator, 8-first ultra-wideband antenna, 9-delay circuit, 10-second narrow pulse generator, 11-equivalent sampling circuit, 12-amplification and filtering circuit, 13-second ultra-wideband antenna. DETAILED DESCRIPTION

[0061] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0062] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a," "an," "the," and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, and unless the context clearly indicates otherwise, "a plurality" generally includes at least two.

[0063] It should be understood that although the terms "first," "second," "third," etc. may be used to describe "...," these "..." should not be limited to these terms. These terms are merely used to distinguish "...." For example, "first..." could also be referred to as "second...", and similarly, "second..." could also be referred to as "first..." without departing from the scope of the present invention.

[0064] Example 1

[0065] This embodiment is an impulse fuze modulation method. Figure 1 As shown, the following steps are included:

[0066] S1, according to the impulse fuze pulse repetition frequency PRF, the direct digital frequency synthesis operating frequency and pulse position modulation depth are obtained. DDS The value range is (8~12)*PRF, and the pulse position modulation depth range is (1 / 4~1 / 8) / PRF.

[0067] The clock signal output by S2 and the crystal oscillator 3 is multiplied by the phase-locked loop 23 to obtain a working clock signal of the direct digital frequency synthesis working frequency, and the working clock signal is transmitted to the phase accumulator 21, the phase-to-amplitude converter 22, and the digital-to-analog converter 4.

[0068] S3. Obtain a frequency control word according to the pulse repetition frequency and the direct digital frequency synthesis operating frequency.

[0069] S4. Driven by the working clock signal, the phase accumulator 21 continuously accumulates the frequency control word to obtain the instantaneous phase.

[0070] S5. The random number generator 1 generates a random pulse sequence, uses the random pulse sequence as a phase control word, and outputs the phase control word to the phase accumulator 21. The random number generator 1 generates the random pulse sequence including the following:

[0071] like Figure 5 As shown, the noise amplifier circuit generates circuit noise, which is converted into a digital signal by the ADC acquisition circuit. The digital signal is converted into a random pulse sequence by the parallel-serial conversion circuit. The number of random digits of the circuit noise generated by the noise amplifier circuit is M, and the pulse repetition frequency of the circuit noise generated by the noise amplifier circuit is PRF.

[0072] The sampling bit number of the ADC acquisition circuit is SB, the sampling frequency of the ADC acquisition circuit is FS, and the pulse repetition frequency PRF meets the condition: SB*FS≥M*PRF,

[0073] The relationship between the number of random digits of circuit noise generated by the noise amplifier circuit and the pulse position modulation depth is expressed as follows:

[0074]

[0075] In the above formula, Depth rand is the pulse position modulation depth, M is the number of random bits of circuit noise generated by the noise amplifier circuit, Bits_Phase_in is the number of input bits of the phase-to-amplitude converter 22, and F DDS is the operating frequency of the phase-to-amplitude converter 22.

[0076] In step S5, the key to generating the random pulse sequence lies in properly managing the relationship between the noise bandwidth of the noise amplifier circuit, the number of random digits M (related to the pulse position modulation depth), and the pulse repetition frequency (PRF). This can be achieved through a cascaded voltage negative feedback circuit. On the one hand, the op amp's gain-bandwidth product (GBP) should be large enough to ensure that the noise at the ADC acquisition front end exhibits white noise characteristics, meaning that the noise bandwidth is greater than the ADC sampling frequency.

[0077] S6. The phase accumulator 21 adds the phase control word to the instantaneous phase to obtain a composite phase.

[0078] S7. The synthesized phase is converted into an output amplitude by the phase-to-amplitude converter 22, and the output amplitude is output to the digital-to-analog converter 4 to obtain an analog output signal.

[0079] S8. The analog output signal is filtered out by a low-pass filter 5 to remove the noise caused by the image and nonlinearity, and a direct digital frequency synthesis output signal is obtained. The direct digital frequency synthesis output signal is passed through a pulse shaping circuit 6 to obtain a pulse signal with position modulation.

[0080] S9. The pulse signal with position modulation is divided into two paths. One path of the pulse signal with position modulation obtains an impulse signal through the first narrow pulse generator 7 and then radiates outward through the first ultra-wideband antenna 8. The other path of the pulse signal with position modulation is delayed by the delay circuit 9 and then obtains a sampling pulse signal through the second narrow pulse generator 10.

[0081] S10, the impulse signal sent by the first ultra-wideband antenna 8 is scattered by the target to obtain a scattered signal, the second ultra-wideband antenna 13 receives the scattered signal, and the scattered signal and the sampling pulse signal are correlated and received by the equivalent sampling circuit 11 to obtain a detection signal.

[0082] S11, the detection signal is output to the signal decision module 24 after the amplification and filtering circuit 12. After the signal decision module 24 determines that the detection signal meets the target echo characteristics, it outputs a proximity trigger signal. The signal decision module 24 determines that the detection signal includes the following contents:

[0083] After the detection signal is processed by the digital bandpass filter submodule, the template matching algorithm performs a correlation operation on the processed detection signal and the template signal stored locally in the FPGA chip 2 to obtain the correlation coefficient ρ. When the correlation coefficient ρ is less than 0.8, the signal judgment module 24 determines that the detection signal meets the target echo characteristics, and the proximity start command output submodule outputs the proximity start command. The calculation formula of the correlation coefficient ρ is:

[0084]

[0085] In the above formula, ρ is the correlation coefficient, s i is the processed detection signal, m i is the template signal.

[0086] Example 2

[0087] This embodiment provides an impulse fuze modulation system, which is applied to an impulse fuze modulation method in embodiment 1 based on, for example, Figure 2 As shown, including:

[0088] Random number generator 1, used to generate a phase control word, comprises a noise amplifier circuit for generating and amplifying circuit noise, an ADC acquisition circuit for acquiring and performing digital-to-analog conversion on the circuit noise, and a parallel-to-serial conversion circuit, all electrically connected in sequence. The noise amplifier circuit adjusts its amplification factor based on the noise level to amplify the noise level to the ADC's full scale. The ADC sampling exhibits differential nonlinearity, and sampling errors also contribute to randomness in low-bit sample values.

[0089] The crystal oscillator 3 is used to provide a clock signal.

[0090] FPGA chip 2, FPGA chip 2 is used to synthesize the phase control word and the frequency control word to obtain the output amplitude. FPGA chip 2 is electrically connected to random number generator 1 and crystal oscillator 3. FPGA chip 2 includes:

[0091] Phase accumulator 21, phase accumulator 21 is electrically connected to random number generator 1,

[0092] The phase-to-amplitude converter 22 is electrically connected to the phase accumulator 21 and the digital-to-analog converter 4.

[0093] The phase-locked loop 23 is electrically connected to the phase accumulator 21 , the phase-to-amplitude converter 22 , the digital-to-analog converter 4 , and the crystal oscillator 3 .

[0094] Electrically connected in sequence are: a digital-to-analog converter 4 for converting the output amplitude into an analog output signal, a low-pass filter 5 for filtering out noise caused by mirror images and nonlinearity in the analog output signal to obtain a direct digital frequency synthesis output signal, a pulse shaping circuit 6 for converting the direct digital frequency synthesis output signal into a pulse signal with position modulation, a first narrow pulse generator 7 for converting the pulse signal with position modulation into an impulse signal, and a first ultra-wideband antenna 8 for sending the impulse signal. The digital-to-analog converter 4 is electrically connected to the FPGA chip 2.

[0095] Electrically connected in sequence are: a delay circuit 9, a second narrow pulse generator 10, an equivalent sampling circuit 11, and a second ultra-wideband antenna 13. The delay circuit 9 is electrically connected to the pulse shaping circuit 6. The delay circuit 9 is used to delay the pulse signal with position modulation. The second narrow pulse generator 10 is used to sample the delayed pulse signal with position modulation. The second ultra-wideband antenna 13 is used to receive the delay circuit 9 of the scattered signal after being scattered by the target. The equivalent sampling circuit 11 is used to correlate the scattered signal with the sampled pulse signal.

[0096] Among them, such as Figure 4 As shown, the first narrow pulse generator 7 and the second narrow pulse generator 10 are composed of a step recovery diode and peripheral inductors and capacitors that are electrically connected in sequence, as shown in FIG. Figure 6 As shown, the delay circuit 9 is composed of several logic chips electrically connected in sequence, where the logic chip is a buffer or NOT gate, and the equivalent sampling circuit 11 is composed of a mixer diode and a peripheral integral differential resistance-capacitance circuit electrically connected in sequence, where the peripheral integral differential resistance-capacitance circuit is as shown in FIG. Figure 7 shown.

[0097] The amplifying and filtering circuit 12 is electrically connected to the equivalent sampling circuit 11, such as Figure 3 As shown, the amplifying and filtering circuit 12 is a step-by-step active filtering amplifying circuit composed of three stages of operational amplifiers.

[0098] The signal decision module 24 is mounted on the FPGA chip 2 and is electrically connected to the amplification and filtering circuit 12. The signal decision module 24 includes: a digital bandpass filter submodule, a template matching algorithm, and a proximity start command output submodule, which are electrically connected in sequence. The calculation logic of the template matching algorithm is: the processed detection signal is correlated with the template signal stored locally in the FPGA chip 2 to obtain a correlation coefficient ρ. The calculation formula of the correlation coefficient ρ is:

[0099]

[0100] In the above formula, ρ is the correlation coefficient, s i is the processed detection signal, m i is the template signal.

Claims

1. A method for modulating an impulse fuze, characterized in that: The following steps are involved: S1, according to the impulse fuze pulse repetition frequency PRF, the direct digital frequency synthesis operating frequency and pulse position modulation depth are obtained. DDS The value range is (8 to 12)*PRF, and the pulse position modulation depth range is (1 / 4 to 1 / 8) / PRF; The clock signal outputted by S2 and the crystal oscillator (3) is frequency-multiplied by the phase-locked loop (23) to obtain a working clock signal of a direct digital frequency synthesis working frequency, and the working clock signal is transmitted to the phase accumulator (21), the phase-to-amplitude converter (22), and the digital-to-analog converter (4); S3, obtaining a frequency control word according to the pulse repetition frequency and the direct digital frequency synthesis operating frequency; S4, the phase accumulator (21) is driven by the working clock signal to continuously accumulate the frequency control word to obtain the instantaneous phase; S5, a random number generator (1) generates a random pulse sequence, uses the random pulse sequence as a phase control word, and outputs the phase control word to a phase accumulator (21); the random number generator (1) generates a random pulse sequence including the following: a noise amplifier circuit generates circuit noise, the circuit noise is converted into a digital signal by an ADC acquisition circuit, and the digital signal is converted into a random pulse sequence by a parallel-serial conversion circuit; the number of random digits of the circuit noise generated by the noise amplifier circuit is M, the pulse repetition frequency of the circuit noise generated by the noise amplifier circuit is PRF, the number of sampling bits of the ADC acquisition circuit is SB, the sampling frequency of the ADC acquisition circuit is FS, and the pulse repetition frequency PRF satisfies the condition: SB*FS≥M*PRF; The relationship between the number of random digits of circuit noise generated by the noise amplifier circuit and the pulse position modulation depth is expressed as follows: In the above formula, Depth rand is the pulse position modulation depth, M is the number of random bits of circuit noise generated by the noise amplifier circuit, Bits_Phase_in is the number of input bits of the phase-to-amplitude converter (22), and F DDS is the operating frequency of the phase-to-amplitude converter (22); S6, the phase accumulator (21) adds the phase control word to the instantaneous phase to obtain a composite phase; S7, the synthesized phase is passed through a phase-to-amplitude converter (22) to obtain an output amplitude, and the output amplitude is output to a digital-to-analog converter (4) to obtain an analog output signal; S8, the analog output signal is filtered out by a low-pass filter (5) to remove the noise caused by the image and nonlinearity, thereby obtaining a direct digital frequency synthesis output signal, and the direct digital frequency synthesis output signal is passed through a pulse shaping circuit (6) to obtain a pulse signal with position modulation; S9, the pulse signal with position modulation is divided into two paths, one path of the pulse signal with position modulation is passed through the first narrow pulse generator (7) to obtain an impulse signal, and then radiated outward through the first ultra-wideband antenna (8), and the other path of the pulse signal with position modulation is delayed by the delay circuit (9) and then passed through the second narrow pulse generator (10) to obtain a sampling pulse signal; S10, the impulse signal sent by the first ultra-wideband antenna (8) is scattered by the target to obtain a scattered signal, the second ultra-wideband antenna (13) receives the scattered signal, and the scattered signal and the sampling pulse signal are correlated and received by the equivalent sampling circuit (11) to obtain a detection signal; S11, the detection signal is output to the signal judgment module (24) after passing through the amplification and filtering circuit (12), and the signal judgment module (24) outputs a proximity trigger signal after judging that the detection signal meets the target echo characteristics.

2. The impulse fuze modulation method according to claim 1, wherein: The signal decision module (24) determines the detection signal including the following contents: After the detection signal is processed by the digital bandpass filter submodule, the template matching algorithm performs a correlation operation on the processed detection signal and the template signal stored locally in the FPGA chip (2) to obtain a correlation coefficient ρ. When the correlation coefficient ρ is less than 0.8, the signal judgment module (24) judges that the detection signal meets the target echo characteristics, and the proximity start instruction output submodule outputs the proximity start instruction. The calculation formula of the correlation coefficient ρ is: In the above formula, ρ is the correlation coefficient, s i is the processed detection signal, m i is the template signal.

3. An impulse fuze modulation system, characterized in that: An impulse fuze modulation method according to any one of claims 1 to 2, comprising: A random number generator (1) is used to generate a phase control word, and the random number generator (1) comprises: a noise amplifying circuit for generating circuit noise and amplifying the circuit noise, an ADC acquisition circuit for acquiring the circuit noise and performing digital-to-analog conversion on the circuit noise, and a parallel-to-serial conversion circuit, which are electrically connected in sequence; a crystal oscillator (3), the crystal oscillator (3) being used to provide a clock signal, An FPGA chip (2) is used for synthesizing a phase control word and a frequency control word to obtain an output amplitude, and the FPGA chip (2) is electrically connected to the random number generator (1) and the crystal oscillator (3). The following are electrically connected in sequence: a digital-to-analog converter (4) for converting the output amplitude into an analog output signal, a low-pass filter (5) for filtering out the noise caused by the image and nonlinearity in the analog output signal to obtain a direct digital frequency synthesis output signal, a pulse shaping circuit (6) for converting the direct digital frequency synthesis output signal into a pulse signal with position modulation, a first narrow pulse generator (7) for converting the pulse signal with position modulation into an impulse signal, and a first ultra-wideband antenna (8) for transmitting the impulse signal. The digital-to-analog converter (4) is electrically connected to the FPGA chip (2). The delay circuit (9), the second narrow pulse generator (10), the equivalent sampling circuit (11), and the second ultra-wideband antenna (13) are electrically connected in sequence. The delay circuit (9) is electrically connected to the pulse shaping circuit (6). The delay circuit (9) is used to delay the pulse signal with position modulation. The second narrow pulse generator (10) is used to sample the pulse signal with position modulation after delay. The second ultra-wideband antenna (13) is used to receive the delay circuit (9) of the scattered signal after being scattered by the target. The equivalent sampling circuit (11) is used to correlate the scattered signal with the sampled pulse signal. an amplifying and filtering circuit (12), wherein the amplifying and filtering circuit (12) is electrically connected to the equivalent sampling circuit (11), A signal decision module (24) is mounted on the FPGA chip (2) and is electrically connected to the amplification and filtering circuit (12).

4. An impulse fuze modulation system as claimed in claim 3, characterized in that: The FPGA chip (2) further comprises: A phase accumulator (21), the phase accumulator (21) being electrically connected to the random number generator (1), A phase-to-amplitude converter (22), the phase-to-amplitude converter (22) being electrically connected to the phase accumulator (21) and the digital-to-analog converter (4), A phase-locked loop (23), the phase-locked loop (23) is electrically connected to the phase accumulator (21), the phase-amplitude converter (22), the digital-to-analog converter (4), and the crystal oscillator (3).

5. An impulse fuze modulation system as claimed in claim 3, characterized in that: The signal judgment module (24) includes: a digital bandpass filter submodule, a template matching algorithm, and a proximity start instruction output submodule.

6. An impulse fuze modulation system as claimed in claim 3, characterized in that: The low-pass filter (5) is a fifth-order LC filter, the first narrow pulse generator (7) and the second narrow pulse generator (10) are both composed of step recovery diodes and peripheral inductors and capacitors that are electrically connected in sequence, the delay circuit (9) is composed of several logic chips that are electrically connected in sequence, the equivalent sampling circuit (11) is composed of mixing diodes and peripheral integral and differential resistance-capacitance circuits that are electrically connected in sequence, and the amplification and filtering circuit (12) is a step-by-step active filtering amplification circuit composed of three-stage operational amplifiers.

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