Transient enhancement controller and method for controlling transient enhancement circuit of voltage regulator

Abstract

The present invention provides a transient enhancement controller and a method for controlling a transient enhancement circuit of a voltage regulator, which can improve load transient response. The present invention provides a transient enhancement controller for controlling the transient enhancement circuit of a voltage regulator, which may include: a feedback circuit arranged to obtain a first feedback signal and a second feedback signal sensed from an output capacitor of the voltage regulator, wherein the first feedback signal is obtained from a voltage signal at a first plate of the output capacitor, and the second feedback signal is obtained from a voltage signal at a second plate of the output capacitor; and a processing circuit arranged to generate a detection result based on the first feedback signal and the second feedback signal and output the detection result for use in controlling the transient enhancement circuit of the voltage regulator.

Description

Technical Field

[0001] The present invention relates to voltage regulator design, and more particularly, to an apparatus and method for controlling a transient boost circuit of a voltage regulator by using a feedback signal obtained by differential sensing applied to an output capacitor. Background Art

[0002] In electronic devices, voltage regulators are used to provide stable power to electronic loads. Voltage regulators are typically designed to maintain output voltage within a specified range. However, when a load transient occurs, the output voltage of the regulator can vary significantly. The ability of a regulator to maintain a stable output voltage in response to sudden changes in load current is known as load transient response. Today, requirements for load transient response are extremely stringent, making it one of the most important parameters for voltage regulators. Therefore, innovative transient-hardening designs that can improve a regulator's load transient response are needed. Summary of the Invention

[0003] The present invention provides a transient enhancement controller and a method for controlling a transient enhancement circuit of a voltage stabilizer, which can improve load transient response.

[0004] In one embodiment, the present invention provides a transient enhancement controller for controlling a transient enhancement circuit of a voltage regulator, which may include: a feedback circuit arranged to obtain a first feedback signal and a second feedback signal sensed from an output capacitor of the voltage regulator, wherein the first feedback signal is obtained from a voltage signal at a first plate of the output capacitor, and the second feedback signal is obtained from a voltage signal at a second plate of the output capacitor; and a processing circuit arranged to generate a detection result based on the first feedback signal and the second feedback signal and output the detection result for controlling the transient enhancement circuit of the voltage regulator.

[0005] In another embodiment, the present invention provides a method for controlling a transient enhancement circuit of a voltage regulator, comprising: obtaining a first feedback signal and a second feedback signal sensed from an output capacitor of the voltage regulator, wherein the first feedback signal is obtained from a voltage signal at a first plate of the output capacitor, and the second feedback signal is obtained from a voltage signal at a second plate of the output capacitor; and generating a detection result based on the first feedback signal and the second feedback signal, and outputting the detection result for controlling the transient enhancement circuit of the voltage regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of a first voltage regulator according to an embodiment of the present invention.

[0007] Figure 2FIG. 1 is a first circuit design diagram of a processing circuit in a transient enhancement controller according to an embodiment of the present invention.

[0008] Figure 3 FIG. 2 is a second circuit diagram of a processing circuit design in a transient enhancement controller according to an embodiment of the present invention.

[0009] Figure 4 FIG. 4 is a schematic diagram of a second voltage regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0010] Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality. Throughout the specification and claims, the terms "including" and "comprising" are open-ended and should be interpreted as meaning "including, but not limited to." "Substantially" or "approximately" means that within an acceptable range of error, a person skilled in the art can solve the technical problem and achieve the desired technical effect. Furthermore, the term "coupled" or "coupled" encompasses any direct or indirect electrical connection. Therefore, if a first device is described as being coupled to a second device, this means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device via other devices or connections. The following describes preferred embodiments of the present invention and is intended to illustrate the spirit of the invention rather than to limit its scope, which shall be determined by the appended claims.

[0011] The following description is intended to be the preferred embodiment of the present invention. These descriptions are intended to illustrate the general principles of the present invention and should not be used to limit the present invention. The scope of protection of the present invention should be determined based on the claims of the present invention.

[0012] Figure 1is a schematic diagram of a first voltage regulator according to an embodiment of the present invention. The voltage regulator 100 may be a single-phase switching regulator, which is capable of adjusting the output voltage signal Vo transmitted to the load 101 according to the input voltage signal VIN. For example, the voltage regulator 100 may be a switching buck converter, the input voltage signal VIN may be a DC voltage signal provided by a battery device, the load 101 may be a central processing unit (CPU), and the output voltage signal Vo may be a DC voltage signal provided to the CPU. It should be noted that the load current Io provided to the load 101 may vary depending on the different load conditions of the load 101. Figure 1 As shown, the voltage regulator 100 may include a controller circuit 102, a power stage circuit 104, an inductor L, an output capacitor Co, an error amplifier circuit 106, and a transient boost controller 108. The controller circuit 102 may include a comparator circuit (labeled as "CMP") 112 and a logic and gate driver block 114. The controller circuit 102 is part of the output voltage feedback loop. In this embodiment, the control voltage signal Vc fed into the comparator circuit 112 is output from the error amplifier circuit 106, which represents the difference between the regulated voltage of the voltage regulator 100 and the reference voltage signal V DAC In this embodiment, the error amplifier circuit 106 receives feedback signals FB1 and FB2. The feedback signal FB1 is derived from the voltage signal Vo of the first plate 120 of the output capacitor Co, and the feedback signal FB2 is derived from the voltage signal Gnd_fb of the second plate 122 of the output capacitor Co. Therefore, the error amplifier circuit 106 receives the reference voltage signal V DAC The difference between the voltage across the output capacitor Co (eg, FB1 - FB2 = Vo - Gnd_fb) generates the control voltage signal Vc. However, this is for illustration purposes only and is not intended to limit the present invention.

[0013] The logic and gate driver block 114 includes circuits required to perform PWM control of the power stage circuit 104 and / or perform additional functions. For example, the logic and gate driver block 114 may also support overvoltage protection, overcurrent protection, etc. The logic and gate driver block 114 may adjust the output voltage signal Vo delivered to the load 101 by controlling the PWM pulses applied to the power stage circuit 104. For example, the power stage circuit 104 may include a high-side switch and a low-side switch controlled by the PWM pulses generated by the logic and gate driver block 114. Generally speaking, when the reference voltage signal V DACAfter being set, the logic and gate driver block 114 controls the power stage circuit 104 in response to the control voltage signal Vc, so that the voltage level of the output voltage signal Vo is close to the reference voltage signal V DAC voltage level.

[0014] In this embodiment, the voltage regulator 100 supports a transient enhancement function for improving load transient response. For example, the logic and gate driver block 114 may include a transient enhancement circuit (labeled "TB CKT") 115. The transient enhancement controller 108 is configured to generate and output a detection result TB / OVP for controlling (e.g., enabling / disabling) the transient enhancement circuit 115 of the voltage regulator 100. If the output voltage signal Vo experiences a sudden load increase, the transient enhancement controller 108 may set the detection result TB to trigger the transient enhancement circuit 115, causing the output voltage signal Vo to increase and restore the output voltage signal Vo to a regulated state. If the output voltage signal Vo experiences a sudden load decrease, the transient enhancement controller 108 may set the detection result OVP to trigger the transient enhancement circuit 115, causing the output voltage signal Vo to decrease and restore the output voltage signal Vo to a regulated state. Since the present invention focuses on the transient enhancement controller design (eg, transient enhancement enable / disable mechanism), further description of the transient enhancement circuit 115 for restoring the output voltage signal Vo to a regulated state when a sudden load change occurs is omitted for brevity.

[0015] like Figure 1 As shown, the proposed transient enhancement controller 108 includes a feedback circuit 116 and a processing circuit 118. The feedback circuit 116 can be implemented by two feedback paths coupled to a first plate 120 and a second plate 122 of the output capacitor Co, respectively. Specifically, the feedback circuit 116 applies differential sensing of the output capacitor Co. Like the error amplifier circuit 106, the feedback circuit 116 obtains a feedback signal FB1 (e.g., FB1=Vo) and a feedback signal FB2 (e.g., FB2=Gnd_fb) sensed from the output capacitor Co of the regulator 100.

[0016] The processing circuit 118 is configured to generate a detection result TB / OVP based on the feedback signals FB1 and FB2, and output the detection result TB / OVP to control the transient enhancement circuit 115 of the voltage regulator 100. For example, the processing circuit 118 may jointly consider the feedback signals FB1 and FB2 to generate and output the detection result TB / OVP. When the transient enhancement controller 108 detects a sudden increase in load (i.e., a sudden decrease in the output voltage signal Vo), the detection result TB is asserted. When the transient enhancement controller 108 detects a sudden decrease in load (i.e., a sudden increase in the output voltage signal Vo), the detection result OVP is asserted.

[0017] In some embodiments of the present invention, the processing circuit 118 is further configured to generate a time derivative dVo of the feedback signal FB1 (FB1=Vo) and a time derivative dGnd_fb of the feedback signal FB2 (FB2=Gnd_fb). The detection result TB / OVP is generated at least in part based on the time derivative dVo of the feedback signal FB1 and the time derivative dGnd_fb of the feedback signal FB2.

[0018] In some embodiments of the present invention, the processing circuit 118 is further arranged to receive a reference voltage signal V DAC and at least one offset voltage signal V ref_TB 、V ref_OVP For example, the processing circuit 118 may receive a single offset voltage signal VOS, where VOS=V ref_VB =V ref_oVP For another example, the processing circuit 118 may receive two offset voltage signals V ref_TB and V ref_OVP , where V ref_VB ≠V ref_OVP In addition, the detection result TB / OVP is based on the reference voltage signal V DAC , at least one offset voltage signal V ref_TB 、V ref_OVP , a feedback signal FB1 (FB1=Vo), a feedback signal FB2 (FB2=Gnd_fb), a time derivative dVo of the feedback signal FB1 (FB1=Vo), and a time derivative dGnd_fb of the feedback signal FB2 (FB2=Gnd_fb) are generated.

[0019] Figure 2 This is a first circuit design diagram of a processing circuit in a transient enhancement controller according to an embodiment of the present invention. For example, Figure 1 The processing circuit 118 shown in FIG. Figure 2 The processing circuit 200 is implemented as shown. The processing circuit 200 includes a differential amplifier circuit 202 and a plurality of comparator circuits (labeled "CMP") 204 and 206. The differential amplifier circuit 202 is implemented by an operational amplifier (labeled "OP-AMP") 203. The operational amplifier circuit performs a differential mathematical operation, that is, generates a voltage output proportional to the rate of change of the input voltage over time. In this embodiment, the differential amplifier circuit 202 is configured to generate a voltage output proportional to the rate of change of the input voltage over time based on at least the feedback signal FB1 (FB1 = Vo), the feedback signal FB2 (FB2 = Gnd_fb), and the reference voltage signal V DAC Generates an amplifier output signal S3, wherein the amplifier output signal S3 depends at least on the reference voltage signal VDAC , the time derivative dVo of the feedback signal FB1 (FB1=Vo), and the time derivative dGnd_fb of the feedback signal FB2 (FB2=Gnd_fb). Specifically, the differential amplifier circuit 202 includes an inverting input node (-), a non-inverting input node (+), and an output node, wherein the inverting input node (-) of the operational amplifier 203 is arranged to receive the amplifier input signal S1 obtained from the feedback signal FB1 (FB1=Vo), and the non-inverting input node (+) of the operational amplifier 203 is arranged to receive the amplifier input signal S1 obtained from the feedback signal FB1 (FB1=Vo), and the reference voltage signal V DAC The output node of the operational amplifier 203 is configured to output the amplifier output signal S3 by obtaining the amplifier input signal S2 and the reference ground signal GND_ref. The reference ground signal GND_ref may be the common ground terminal of the voltage regulator 100. Ideally, the reference ground signal GND_ref is equal to 0V. Due to the inherent characteristics of the differential amplifier circuit 202, the amplifier output signal S3 is equal to (V DAC -GND_ref)-(dV o -dGnd_fb).

[0020] The comparator circuit 204 is arranged to generate a voltage signal according to the feedback signal FB1 (FB1=Vo), the feedback signal FB2 (FB2=Gnd_fb), the offset voltage signal V ref_TB , amplifier output signal S3 (S3 = (V DAC -GND_ref)-(dV o -dGnd_fb)) generates the detection result TB. The offset voltage signal V ref_TB The offset voltage threshold for triggering the level transition of the detection result TB is defined. Specifically, the comparator circuit 204 includes an inverting input node (-), a non-inverting input node (+), and an output node, wherein the inverting input node (-) is arranged to receive (V o -Gnd_fb)+V ref_TB , the non-inverting input node (+) is arranged to receive the amplifier output signal S3 (S3 = (V DAC -GND_ref)-(dV o -dGnd_fb)), the output node is arranged to output the detection result TB. When the difference between the feedback signals FB1 and FB2 (V o -Gnd_fb) drops below (V DAC -GND_ref)-(dV o -dGnd_fb)-V ref_TBWhen the load suddenly increases (i.e., the output voltage signal Vo suddenly drops), the comparator circuit 204 sets the detection result TB to a logic high level to indicate that the load suddenly increases (i.e., the output voltage signal Vo suddenly drops). Therefore, in response to the logic high level of the detection result TB (i.e., TB=1), the transient enhancement circuit 115 is enabled to increase the output voltage signal Vo and restore the output voltage signal Vo to a stable state. When the difference between the feedback signals FB1 and FB2 (V o -Gnd_fb) is no longer lower than (V DAC -GND_ref)-(dV o -dGnd_fb)-V ref_TB When TB=0, the comparator circuit 204 sets the detection result TB to a logic low level. Therefore, in response to the detection result TB being a logic low level (ie, TB=0), the transient enhancement circuit 115 is disabled and does not cause the output voltage signal Vo to rise.

[0021] The comparator circuit 206 is arranged to generate a voltage signal based on the feedback signal FB1 (FB1=Vo), the feedback signal FB2 (FB2=Gnd_fb), the offset voltage signal V ref_OVP , amplifier output signal S3 (S3 = (V DAC -GND_ref)-(dV o -dGnd_fb), generates the detection result OVP. Offset voltage signal V ref_OVP Defines the offset voltage threshold that triggers the level transition of the detection result OVP and can be equal to or different from the offset voltage signal V ref_TB , which depends on actual design considerations. Specifically, the comparator circuit 206 includes an inverting input node (-), a non-inverting input node (+), and an output node, wherein the non-inverting input node (+) is arranged to receive (V o -Gnd_fb)-V ref_OVP , the inverting input node (-) is arranged to receive the amplifier output signal S3 (S3 = (V DAC -GND_ref)-(dV o -dGnd_fb)), the output node is arranged to output the detection result OVP. When the difference between the feedback signals FB1 and FB2 (V o -Gnd_fb) rises above (V DAC -GND_ref)-(dV o -dGnd_fb)+V ref_oVP When the load suddenly decreases, the comparator circuit 206 sets the detection result OVP to a logic high level to indicate that the load suddenly decreases (i.e., the output voltage signal Vo suddenly increases). Therefore, in response to the logic high level of the detection result OVP (i.e., OVP=1), the transient enhancement circuit 115 is enabled to reduce the output voltage signal Vo and restore the output voltage signal Vo to a stable state. When the difference between the feedback signals FB1 and FB2 (Vo -Gnd_fb) is no longer higher than (V DAC -GND_ref)-(dV o -dGnd_fb)+V ref_OVP When , the comparator circuit 206 sets the detection result OVP to a logic low level. Therefore, in response to the detection result OVP being a logic low level (ie, OVP=0), the transient enhancement circuit 115 is disabled and does not cause the output voltage signal Vo to drop.

[0022] Since the feedback circuit 116 provides two feedback signals FB1 and FB2 through differential sensing of the output capacitor Co, the voltages Vo and Gnd_fb of the opposite plates 120 and 122 of the output capacitor Co are both fed back and input to the differential amplifier 202. Figure 1 As shown, due to the parasitic effects of the ground path (for example, the parasitic series resistor R parasitic and parasitic series inductor L parasitic ), the voltage Gnd_fb at the plate 122 of the output capacitor Co may be affected by ground noise, and the ground noise may be coupled to the voltage Vo through the output capacitor Co. Considering the situation where only the output voltage signal Vo is sensed and fed back to the differential amplifier circuit to detect a sudden load change (i.e., a sudden change in the output voltage signal Vo), the transient enhancement circuit 115 may be erroneously triggered by the time derivative of the output voltage signal Vo interfered with by the ground noise. To solve this problem, the present invention proposes to jointly consider the feedback voltage Vo and Gnd_fb differentially sensed through the output capacitor Co. Figure 2 As shown, the amplifier output signal S3 generated from the differential amplifier circuit 202 benefits from the noise cancellation caused by the differential signal sensing of Vo and Gnd_fb received by the inverting node (-) and the non-inverting node (+) of the operational amplifier 203. Specifically, the (dV o The (-dGnd_fb) term is not affected by ground noise. The differential amplifier circuit 202 is able to detect the rate of change of the regulated voltage with respect to time. When the load suddenly increases (i.e., the output voltage signal Vo suddenly decreases) with a high rate of change (for example, when the output voltage signal Vo suddenly decreases at a fast rate), the (dV o -dGnd_fb) is a larger value, so that the detection result TB is the difference between the feedback signals FB1 and FB2 (V o -Gnd_fb) actually drops below (V DAC -GND_ref)-V ref_TBBefore, there is a level transition from a logic low level (i.e., 0) to a logic high level (i.e., 1). In this way, the transient enhancement circuit 115 can be triggered earlier to increase the output voltage signal Vo and restore the output voltage signal Vo to a stable state, thereby improving the load transient response of the regulator 100. Similarly, when the load suddenly decreases (i.e., the output voltage signal Vo suddenly increases) with a high rate of change (for example, when the output voltage signal Vo suddenly increases at a fast rate), the (dV o -dGnd_fb) has a larger value, so that the detection result OVP is greater than the difference (V o -Gnd_fb) actually rises above (V DAC -GND_ref)+V ref_OVP Previously, there was a level transition from a logic low level (i.e., 0) to a logic high level (i.e., 1). As a result, the transient enhancement circuit 115 can be triggered earlier to cause the output voltage signal Vo to drop and restore the output voltage signal Vo to a stable state, thereby improving the load transient response of the regulator 100.

[0023] The operating range of the main loop of the voltage regulator 100 is in the low frequency band, and the operating range of the differential amplifier circuit is in the high frequency band. In order to improve the transient response performance in the mid-frequency band, the comparator circuits 204 and 206 further use a DC reference (V DAC -GND_ref)-V ref_TB and (V DAC -GND_ref)+V ref_OVP To detect sudden load changes (i.e., sudden changes in the output voltage signal Vo). Therefore, when the sudden load change (i.e., sudden change in the output voltage signal Vo) has a high rate of change (i.e., the load changes quickly, for example, when the output voltage signal Vo suddenly increases / decreases quickly, the sudden load change has a high rate of change), the detection result TB / OVP can be generated by the differential amplifier circuit 202 with a large (dV o -dGnd_fb). When the load changes suddenly (i.e., the output voltage signal Vo changes suddenly) with a medium or low rate of change (i.e., the speed of the load change is medium or slow, for example, when the output voltage signal Vo increases / decreases suddenly at a medium or slow rate, the load change suddenly has a medium or low rate of change), the detection result TB / OVP can be obtained by using the DC reference voltage. The voltage comparison (i.e. With (V o -Gnd_fb) to be effective).

[0024] The setting of the detection result TB can be expressed by the following formula.

[0025] TB=[(V o -Gnd_fb)+V ref_TB ]-[(V DAC -GND_ref)-(dV o -dGnd_fb)]

[0026] =(V o -V DAC )+(GND_ref-Gnd_fb)+(dV o -dGnd_fb)+(V ref_TB -GND_ref) (1)

[0027] The setting of the detection result OVP can be expressed by the following formula.

[0028] OVP=[(V o -Gnd_fb)-V ref_OVP ]-[(V DAC -GND_ref)-(dV o -dGnd_fb)]

[0029] =(V o -V DAC )+(GND_ref-Gnd_fb)+(dV o -dGnd_fb)+(GND ref -V ref_OVP ) (2)

[0030] Based on the above formulas (1) and (2), a transient enhancement controller can be easily implemented by using a parallel processing hardware architecture. Figure 3 This is a second circuit design diagram of a processing circuit in a transient enhancement controller according to an embodiment of the present invention. For example, Figure 1 The processing circuit 118 shown in FIG. 1 may be composed of Figure 3 The processing circuit 300 shown is implemented as shown in FIG. The processing circuit 300 includes a plurality of transconductance amplifier circuits (labeled as “GM”) 302 , 304 , 306 , 308 , 312 , 314 , 316 , 318 and a plurality of current comparator circuits 310 , 320 .

[0031] The transconductance amplifier circuits 302, 304, 306, 308 are arranged to generate a plurality of amplifier output signals (current-mode signals) S11, S12, S13, S14 according to voltage-mode amplifier input signals including a reference voltage signal V DAC , offset voltage signal V ref_TB, feedback signal FB1 (FB1=Vo), feedback signal FB2 (FB2=Gnd_fb), time derivative dVo of feedback signal FB1 (FB1=Vo), time derivative dGnd_fb of feedback signal FB2 (FB2=Gnd_fb). Specifically, transconductance amplifier circuit 302 includes a non-inverting input node (+) for receiving feedback signal FB1 (FB1=Vo) and a reference voltage signal V DAC The transconductance amplifier circuit 304 includes a non-inverting input node (+) for receiving the reference ground signal GND_ref and an inverting input node (-) for receiving the feedback signal Gnd_fb. The transconductance amplifier circuit 306 includes a non-inverting input node (+) for receiving the time derivative dVo of the feedback signal FB1 (FB1=Vo) and an inverting input node (-) for receiving the time derivative dGnd_fb of the feedback signal FB2 (FB2=Gnd_fb). The transconductance amplifier circuit 308 includes a non-inverting input node for receiving the offset voltage signal V ref_TB The current comparator circuit 310 has a positive input node (+) for receiving the reference ground signal GND_ref and an inverting input node (-) for receiving the reference ground signal GND_ref. The current comparator circuit 310 is arranged to receive the amplifier output signals S11, S12, S13, S14 and output a detection result (voltage mode signal) TB based on the amplifier output signals S11, S12, S13, S14.

[0032] The transconductance amplifier circuits 312, 314, 316, 318 are arranged to generate a plurality of amplifier output signals (current mode signals) S21, S22, S23, S24 according to voltage mode amplifier input signals including a reference voltage signal V DAC , offset voltage signal V ref_OVP , feedback signal FB1 (FB1=Vo), feedback signal FB2 (FB2=Gnd_fb), time derivative dVo of feedback signal FB1 (FB1=Vo), time derivative dGnd_fb of feedback signal FB2 (FB2=Gnd_fb). Specifically, transconductance amplifier circuit 312 includes a non-inverting input node (+) for receiving feedback signal FB1 (FB1=Vo) and a reference voltage signal V DACThe transconductance amplifier circuit 314 includes a non-inverting input node (+) for receiving the reference ground signal GND_ref and an inverting input node (-) for receiving the feedback signal Gnd_fb. The transconductance amplifier circuit 316 includes a non-inverting input node (+) for receiving the time derivative dVo of the feedback signal FB1 (FB1=Vo) and an inverting input node (-) for receiving the time derivative dGnd_fb of the feedback signal FB2 (FB2=Gnd_fb). The transconductance amplifier circuit 318 includes a non-inverting input node (+) for receiving the reference ground signal GND_ref and an inverting input node (-) for receiving the offset voltage signal V ref_TB The current comparator circuit 320 is arranged to receive the amplifier output signals S21, S22, S23, S24 and output a detection result (voltage mode signal) OVP according to the amplifier output signals S21, S22, S23, S24.

[0033] The transient enhancement technique can also be used by a regulator that is a multi-phase switching regulator (e.g., a multi-phase buck converter), wherein the detection result TB / OVP generated from the proposed transient enhancement controller can be further used to control (e.g., enable / disable) at least one slave phase. Figure 4 FIG4 is a schematic diagram of a second voltage regulator according to an embodiment of the present invention. For the sake of brevity and simplicity, it is assumed that voltage regulator 400 may be a two-phase buck converter including a master phase 410 and a slave phase 412. However, this is for illustrative purposes only and is not intended to limit the present invention. In an alternative design, the proposed transient enhancement controller may be used with a multi-phase switching regulator having a master phase and more than one slave phase.

[0034] The voltage regulator 400 can adjust the output voltage signal Vo transmitted to the load 101 according to the input voltage signal VIN. For example, the input voltage signal VIN can be a DC voltage signal provided by a battery device, the load 101 can be a CPU, and the output voltage signal Vo can be a DC voltage signal provided to the CPU. It should be noted that the load current Io provided to the load 101 can vary depending on the load conditions of the load 101. Figure 4As shown, the voltage regulator 400 may include a controller circuit 402, a master phase 410 (which includes the power stage circuit 104 and the inductor L1), a slave phase 412 (which includes the power stage circuit 406 and the inductor L2), an output capacitor Co, an error amplifier circuit 106, and a transient enhancement controller 108. The controller circuit 402 may include a comparator circuit (labeled "CMP") 112, a clock generator circuit (labeled "CLK GEN") 404, a logic and gate driver block 114 for the master phase 410, and a logic and gate driver block 408 for the slave phase 412. The clock generator circuit 404 generates a pulse-width modulation (PWM) control signal PWM1 and outputs it to the logic and gate driver block 114, and generates another PWM control signal PWM2 and outputs it to the logic and gate driver block 408.

[0035] The logic and gate driver block 114 is configured to handle PWM control of the power stage circuit 104 belonging to the master phase 410. Therefore, the logic and gate driver block 114 can regulate the output voltage signal Vo delivered to the load 101 by controlling the PWM pulses applied to the power stage circuit 104. The logic and gate driver block 408 is configured to handle PWM control of the power stage circuit 406 belonging to the slave phase 412. Therefore, the logic and gate driver block 408 can regulate the output voltage signal Vo delivered to the load 101 by controlling the PWM pulses applied to the power stage circuit 406. In this embodiment, the transient enhancement controller 108 further outputs the detection result TB / OVP to the logic and gate driver block 408.

[0036] As described above, when the processing circuit 118 / 200 / 300 sets the detection result TB to a logic high level (i.e., TB=1), the transient enhancement circuit 115 can be enabled to increase the output voltage signal Vo and restore the output voltage signal Vo to a stable state; when the processing circuit 118 / 200 / 300 sets the detection result OVP to a logic high level (i.e., OVP=1), the transient enhancement circuit 115 can be enabled to decrease the output voltage signal Vo and restore the output voltage signal Vo to a stable state. Figure 4In the illustrated regulator 400, when the processing circuit 118 / 200 / 300 sets the detection result TB to a logic high level (i.e., TB=1), the logic and gate driver block 408 can enable the slave phase 412 to increase the load current Io provided to the load 101; and when the processing circuit 118 / 200 / 300 sets the detection result OVP to a logic high level (i.e., OVP=1), the logic and gate driver block 408 can disable the slave phase 412 to reduce the load current Io provided to the load 101. In other words, the transient enhancement controller 108 generates and outputs the detection result TB / OVP to control (e.g., enable / disable) the transient enhancement circuit 115 of the regulator 400, and further outputs the detection result TB / OVP for controlling (e.g., enabling / disabling) the slave phase 412 of the regulator 400.

[0037] Although the present invention is disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A transient enhancement controller for controlling a transient enhancement circuit of a voltage regulator, characterized in that: include: a feedback circuit arranged to obtain a first feedback signal and a second feedback signal sensed from an output capacitor of the voltage regulator, wherein the first feedback signal is obtained from a voltage signal at a first plate of the output capacitor and the second feedback signal is obtained from a voltage signal at a second plate of the output capacitor; and a processing circuit, arranged to generate a detection result according to the first feedback signal and the second feedback signal and output the detection result for controlling the transient enhancement circuit of the regulator; The processing circuit is further arranged to generate a time derivative of the first feedback signal and a time derivative of the second feedback signal, and the detection result is generated at least in part based on the time derivative of the first feedback signal and the time derivative of the second feedback signal.

2. The transient enhancement controller according to claim 1, wherein: The processing circuit is also arranged to receive a reference voltage signal and at least one offset voltage signal, and the detection result is generated based on at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal.

3. The transient enhancement controller according to claim 2, wherein: The processing circuit includes: a differential amplifier circuit arranged to generate an amplifier output signal as a function of at least the first feedback signal, the second feedback signal and the reference voltage signal, wherein the amplifier output signal depends on at least the reference voltage signal, the time derivative of the first feedback signal and the time derivative of the second feedback signal; and The comparator circuit is arranged to generate the detection result according to the first feedback signal, the second feedback signal, the at least one offset voltage signal and the amplifier output signal.

4. The transient enhancement controller according to claim 3, wherein: The differential amplifier circuit includes an inverting input node, a non-inverting input node, and an output node, wherein the inverting input node is arranged to receive a first amplifier input signal obtained from the first feedback signal, the non-inverting input node is arranged to receive a second amplifier input signal obtained from the second feedback signal, the reference voltage signal, and a reference ground signal, and the output node is arranged to output the amplifier output signal.

5. The transient enhancement controller according to claim 3, wherein: The comparator circuit includes an inverting input node, a non-inverting input node, and an output node. The inverting input node is arranged to receive a voltage difference signal plus an offset voltage signal, wherein the voltage difference signal is equal to the first feedback signal minus the second feedback signal and the offset voltage signal is one of the at least one offset voltage signal. The non-inverting input node is arranged to receive the amplifier output signal, and the output node is arranged to output the detection result.

6. The transient enhancement controller according to claim 3, wherein: The comparator circuit includes an inverting input node, a non-inverting input node, and an output node, wherein the non-inverting input node receives a voltage difference signal minus an offset voltage signal, wherein the voltage difference signal is equal to the first feedback signal minus the second feedback signal and the offset voltage signal is one of the at least one offset voltage signal, the inverting input node is arranged to receive the amplifier output signal, and the output node is arranged to output the detection result.

7. The transient enhancement controller according to claim 2, wherein: The processing circuit includes: a plurality of transconductance amplifier circuits arranged to generate a plurality of amplifier output signals based on at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal; and The current comparator circuit receives the multiple amplifier output signals output by the multiple transconductance amplifier circuits respectively, and outputs the detection result according to the multiple amplifier output signals.

8. The transient enhancement controller according to claim 7, wherein: The plurality of transconductance amplifier circuits include: a first transconductance amplifier circuit comprising a non-inverting input node arranged to receive the first feedback signal and an inverting input node arranged to receive the reference voltage signal; a second transconductance amplifier circuit comprising a non-inverting input node arranged to receive a reference ground signal and an inverting input node arranged to receive the second feedback signal; a third transconductance amplifier circuit comprising a non-inverting input node arranged to receive the time derivative of the first feedback signal and an inverting input node arranged to receive the time derivative of the second feedback signal; and A fourth transconductance amplifier circuit includes a non-inverting input node arranged to receive one of the at least one offset voltage signal and an inverting input node arranged to receive the reference ground signal.

9. The transient enhancement controller according to claim 7, wherein: The plurality of transconductance amplifier circuits include: a first transconductance amplifier circuit comprising a non-inverting input node arranged to receive the first feedback signal and an inverting input node arranged to receive the reference voltage signal; a second transconductance amplifier circuit comprising a non-inverting input node arranged to receive a reference ground signal and an inverting input node arranged to receive the second feedback signal; a third transconductance amplifier circuit comprising a non-inverting input node arranged to receive the time derivative of the first feedback signal and an inverting input node arranged to receive the time derivative of the second feedback signal; and A fourth transconductance amplifier circuit includes a non-inverting input node arranged to receive the reference ground signal and an inverting input node arranged to receive one of the at least one offset voltage signal.

10. The transient enhancement controller according to claim 1, wherein: The voltage regulator is a multi-phase switching regulator comprising a master phase and at least one slave phase, and the processing circuit is further arranged to output the detection result to control the at least one slave phase of the multi-phase switching regulator.

11. A method for controlling a transient enhancement circuit of a voltage regulator, characterized in that: include: Obtaining a first feedback signal and a second feedback signal sensed from an output capacitor of the voltage regulator, wherein the first feedback signal is obtained from a voltage signal at a first plate of the output capacitor, and the second feedback signal is obtained from a voltage signal at a second plate of the output capacitor; and generating a detection result according to the first feedback signal and the second feedback signal, and outputting the detection result for controlling the transient enhancement circuit of the voltage regulator; The step of generating a detection result according to the first feedback signal and the second feedback signal includes: generating a time derivative of the first feedback signal and a time derivative of the second feedback signal; and The detection result is generated based at least in part on the time derivative of the first feedback signal and the time derivative of the second feedback signal.

12. The method according to claim 11, wherein Generating the detection result based at least in part on the time derivative of the first feedback signal and the time derivative of the second feedback signal includes: receiving a reference voltage signal and at least one offset voltage signal; and The detection result is generated according to at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal.

13. The method according to claim 12, wherein: Generating the detection result based on at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal includes: a differential amplifier circuit generating an amplifier output signal according to at least the first feedback signal, the second feedback signal, and the reference voltage signal, wherein the amplifier output signal depends on at least the reference voltage signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal; and The comparator circuit generates the detection result according to the first feedback signal, the second feedback signal, the at least one offset voltage signal and the amplifier output signal.

14. The method according to claim 12, wherein Generating the detection result based on at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal includes: A plurality of transconductance amplifier circuits generate a plurality of amplifier output signals based on at least the reference voltage signal, the at least one offset voltage signal, the first feedback signal, the second feedback signal, the time derivative of the first feedback signal, and the time derivative of the second feedback signal; and a current comparator circuit generates the detection result based on the plurality of amplifier output signals respectively output by the plurality of transconductance amplifier circuits.

15. The method according to claim 11, wherein The voltage regulator is a multi-phase switching regulator including a master phase and at least one slave phase, and the method further comprises: The detection result is output to control the at least one slave phase of the multi-phase switching regulator.

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