Method and system for mining processor side-channel attacks based on performance monitoring unit

Abstract

This invention discloses a method and system for mining processor side-channel attacks based on a performance monitoring unit. The performance monitoring unit records processor behavior at a fine-grained level, uncovering more processor details. It is found that the performance monitoring unit can not only record the impact of normally submitted instructions on the processor using events, but also, for some events, the impact of transient instructions on the processor's microarchitecture behavior, thus expanding the applicability of the performance monitoring unit. Furthermore, methods for mining cache side-channel attacks and transient side-channel attacks are proposed. These two methods treat the processor as a black box, automatically completing the processes of generating test cases, scenario testing, and data analysis, achieving the effect of automatically mining processor side-channel attacks.

Description

Technical Field

[0001] This invention relates to the field of processor security, and more particularly to a method and system for detecting processor side-channel attacks based on a performance monitoring unit. Background Technology

[0002] A Performance Monitoring Unit (PMU) is a hardware module integrated into modern processors to record the behavior of the processor architecture and microarchitecture during program execution. This includes, for example, the number of instructions allocated to a specific port, the number of cache hits / misses at different levels of the memory hierarchy, and the number of mispredicted branches. The measurement results are stored in several special performance monitoring counters (PMCs).

[0003] The performance monitoring unit (VM) was originally designed to provide software developers with a tool to analyze code execution efficiency, thereby helping them optimize applications. However, because the VM can reveal processor behavior during instruction execution in a fine-grained manner, researchers have also explored using it for other purposes, including reverse engineering black-box processors and speculating on encryption algorithm keys. The processor has a certain number of programmable event selection registers and performance counters; these two types of registers are equal in number and have one-to-one address correspondences.

[0004] Side-channel attacks (SCA) primarily aim to acquire side signals generated by a system during operation, such as sound, electromagnetic radiation, and power consumption, and then use these signals to leak confidential internal data. Traditional side-channel attacks require physical contact with the target device and the use of specialized tools to collect these side signals. These traditional attacks suffer from significant drawbacks, including high cost and low efficiency, as signal acquisition necessitates physical contact with the target device, and signal analysis and noise processing consume considerable time.

[0005] To overcome the shortcomings of traditional side-channel attacks, research on software side-channel attacks has become increasingly in-depth, and it has become one of the mainstream side-channel attack techniques. The basic idea of ​​software side-channel attacks is to construct the attack in software. Hardware security vulnerabilities leak confidential data into microarchitectural components, and finally utilize the form of architectural state (such as caching time information in the side-channel attack) to construct the corresponding side-channel attack.

[0006] To improve performance, processors employ mechanisms such as branch prediction, out-of-order execution, and microarchitecture data sampling, but these also introduce new security vulnerabilities. In cases of branch prediction errors or premature execution of unauthorized instructions, the processor's exception handling mechanism does not immediately process the exception; instead, it waits a time window before processing it. Due to this delayed exception handling mechanism, attackers can exploit transient instructions to leak private data temporarily accessed within the transient window to the microarchitecture layer, altering the microarchitecture's state. Subsequently, based on information about the microarchitecture layer's state, attackers can use side-channel attacks to deduce the leaked private data and then leak it to the architecture layer, which they can directly access, thus completing the entire transient execution attack. Therefore, side-channel attacks are a crucial component of transient execution attacks, and researching side-channel attacks is valuable for understanding transient execution attacks. Summary of the Invention

[0007] The purpose of this invention is to design a method and system for mining processor side-channel attacks based on the ability of a performance monitoring unit to record the behavior of the processor microarchitecture. The processor is treated as a black box, and risky events supporting cache side-channel attacks and transient side-channel attacks supported by different processor models are automatically mined. Finally, the mined risky events are used to construct side-channel attacks.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a method for detecting processor side-channel attacks based on a performance monitoring unit, for detecting cache side-channel attacks, comprising the following steps:

[0010] S1. Iterate through the monitoring events supported by the current processor, construct test cases in event format, and pass the test cases to the cache test module; where event is the monitoring event supported by the processor under test.

[0011] S2. Construct scenarios that trigger cache hit and cache miss behaviors using the cache testing module, configure the test cases to record processor behavior in the performance monitoring unit, and use the performance monitoring unit to record the execution process of the cache hit and cache miss scenarios. Then, pass the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module.

[0012] S3. Use the data analysis module to analyze whether there are differences in the test data for cache hit and cache miss scenarios. If there are differences, it means that the monitoring events in the test cases can record and distinguish between cache hit and cache miss behaviors, and there is a risk of constructing a cache side-channel attack to achieve leakage. Otherwise, the monitoring events do not pose a risk of constructing a cache side-channel attack to achieve leakage.

[0013] Furthermore, in step S3, the data analysis module is used to analyze whether there are differences in the test data of cache hit and cache miss scenarios. Specifically, the data analysis module is responsible for analyzing the performance monitoring unit count values ​​of 1000 cache hits and cache misses under the cache scenario test, selecting reasonable thresholds for cache hits and cache misses, and finally determining whether the thresholds for cache hits and cache misses are equal. If the thresholds for cache hits and cache misses are not equal, there is a risk of constructing a cache side-channel attack; otherwise, there is no risk of constructing a cache side-channel attack.

[0014] Furthermore, in step S3, the data analysis module sets the median of the count values ​​for 1000 cache hits and cache misses as the threshold for the two scenarios, respectively.

[0015] Secondly, the present invention also provides a method for detecting processor side-channel attacks based on a performance monitoring unit, for detecting transient side-channel attacks, comprising the following steps:

[0016] S1. Use the test case generation module to traverse the monitoring events and instruction sets supported by the current processor, construct test cases in the format of event, instruction1 and instruction2, and pass the test cases to the transient test module; where event is the monitoring event supported by the processor under test, and instruction1 and instruction2 are the instructions executed transiently, which can trigger different microarchitectural behaviors.

[0017] S2. Construct code snippets that associate private data with microarchitecture behavior during transient execution using the transient test module. Use the performance monitoring unit to record the microarchitecture behavior when the comparison results of the self-controlled variables and private data are the same and different. Then, pass the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module.

[0018] S3. Use the data analysis module to analyze whether there are differences in the test data when the comparison results of the self-controlled variables and private data are the same and different; if there are differences, the monitoring event can record and distinguish the behavior of the microarchitecture during transient execution, and the monitoring event has the risk of constructing a transient side-channel attack to achieve leakage; otherwise, the monitoring event does not have the risk of constructing a transient side-channel attack to achieve information leakage.

[0019] Furthermore, in step S2, the processor microarchitecture behaviors triggered by instruction1 and instruction2 are different, and the event has the ability to monitor one of the behaviors, or the two behaviors have different increments in the event's count value.

[0020] Furthermore, the transient test module iterates through all possible values ​​of the private data, compares the results of the self-controlled variables and the private data to determine whether to execute instruction1 or instruction2 during transient execution, and uses the performance monitoring unit to record the behavior of the microarchitecture during transient execution.

[0021] Furthermore, in step S3, the data analysis module searches for a comparison variable whose count value appears only once in the performance monitoring unit count values ​​recorded during the comparison process, and infers that the private data is equal to the comparison variable; if the inference is successful, there is a risk of constructing a transient side-channel attack; otherwise, there is no risk of constructing a cache side-channel attack.

[0022] Thirdly, the present invention provides a processor side-channel attack detection system based on a performance monitoring unit for detecting cache side-channel attacks, comprising the following modules to implement the aforementioned processor side-channel attack detection method based on a performance monitoring unit:

[0023] The test case generation module is responsible for iterating through the monitoring events supported by the current processor, constructing test cases in event format, and passing the test cases to the cache test module; where event is the monitoring event supported by the processor under test.

[0024] The cache testing module is responsible for constructing scenarios that trigger cache hit and cache miss behaviors, configuring the test cases to record processor behavior in the performance monitoring unit, using the performance monitoring unit to record the execution process of cache hit and cache miss scenarios, and passing the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module.

[0025] The data analysis module is responsible for analyzing whether there are differences in the test data for cache hit and cache miss scenarios. If there are differences, it can record and distinguish between cache hit and cache miss behaviors, and monitor the events to identify the risk of constructing a cache side-channel attack to achieve leakage. Otherwise, the monitoring events do not identify the risk of constructing a cache side-channel attack to achieve leakage.

[0026] Fourthly, the present invention provides a processor side-channel attack detection system based on a performance monitoring unit for detecting transient side-channel attacks, comprising the following modules to implement the aforementioned processor side-channel attack detection method based on a performance monitoring unit:

[0027] The test case generation module is responsible for traversing the monitoring events and instruction sets supported by the current processor, constructing test cases in the format of event, instruction1, and instruction2, and passing the test cases to the cache test module. Among them, event is the monitoring event supported by the processor under test, and instruction1 and instruction2 are instructions that are executed transiently and can trigger different microarchitectural behaviors.

[0028] The transient testing module is responsible for constructing code snippets that associate private data with the microarchitecture behavior during transient execution. It determines whether to execute instruction1 or instruction2 during transient execution based on the comparison results between the self-controlled variable and the private data. It uses the performance monitoring unit to record the microarchitecture behavior when the comparison results between the self-controlled variable and the private data are the same and different, respectively, and passes the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module.

[0029] The data analysis module analyzes whether there are differences in the test data when the comparison results of the self-controlled variables and private data are the same and different. If there are differences, the monitoring event can record and distinguish the behavior of the microarchitecture during transient execution, and the monitoring event has the risk of constructing a transient side-channel attack to achieve leakage. Otherwise, the monitoring event does not have the risk of constructing a transient side-channel attack to achieve information leakage.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] This invention proposes a method and system for mining processor side-channel attacks based on a performance monitoring unit. The performance monitoring unit records processor behavior at a fine-grained level, uncovering more processor details. It discovers that the performance monitoring unit can not only record the impact of normally submitted instructions on the processor using events, but also, in some cases, the impact of transient instructions on the processor's microarchitecture behavior, thus expanding the applicability of the performance monitoring unit. Furthermore, it proposes methods for mining cache side-channel attacks and transient side-channel attacks. These two methods treat the processor as a black box, automatically completing the processes of generating test cases, scenario testing, and data analysis, achieving the effect of automatically mining processor side-channel attacks. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0033] Figure 1An overview diagram of the processor-side channel automatic mining system based on a performance monitoring unit provided by the present invention.

[0034] Figure 2 An overview diagram of the method for mining cache side-channel attacks provided by the present invention.

[0035] Figure 3 The diagram shows the core code snippet for constructing a cache missing information provided by this invention.

[0036] Figure 4 The diagram shows the core code snippet for constructing cache hits provided by this invention.

[0037] Figure 5 An overview diagram of the method for mining transient side-channel attacks provided by this invention.

[0038] Figure 6 This is a diagram of the core code snippet illustrating the association of private data and the microarchitectural behavior during transient execution provided by this invention. Detailed Implementation

[0039] To better understand this technical solution, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described examples are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of the present invention.

[0040] This invention proposes a method for detecting processor side-channel attacks based on a performance monitoring unit, such as... Figure 1 As shown. This method is divided into a three-layer structure from the perspective of a computer system, and designs methods for detecting cache side-channel attacks and methods for detecting transient side-channel attacks. Among them:

[0041] The three-layer structure includes a hardware layer, an operating system layer, and a user layer, such as... Figure 1 As shown.

[0042] (1) Based on monitoring events configured at the operating system level, the hardware layer automatically monitors the processor microarchitecture behavior. The hardware layer's performance monitoring unit monitors the processor microarchitecture behavior under cache test and transient test scenarios and quantifies the microarchitecture behavior into count values, such as the number of cache hits / misses. Simultaneously, it provides user-privileged programs with the rdpmc instruction to read the count values ​​at any time. However, rdpmc can only be used by user-mode programs if the relevant registers are enabled in kernel mode; this task is completed by the operating system layer.

[0043] (2) The operating system layer is responsible for configuring the events selected by the user layer and enabling the rdpmc instruction. Specifically, the operating system needs to configure the PMU at the hardware layer so that the events selected by the user layer can be correctly monitored and recorded, and the rdpmc instruction needs to achieve the effect of user-mode programs reading the count value of the performance monitoring unit. The driver at the operating system layer writes the event encoding and mask into the event selection register; at the same time, the driver responsible for enabling the CR4.PCE (Performance Monitoring Counter Enable) bit enables user-mode programs to directly read the current PMU count value using the rdpmc instruction, thus avoiding microarchitectural pollution caused by reading the count value.

[0044] (3) The user layer is designed with methods for detecting cache side-channel attacks and transient side-channel attacks. It is responsible for providing selected monitoring events to the operating system layer and utilizing the performance monitoring unit's records of the processor's microarchitectural behavior in cache and transient test scenarios. Ultimately, it analyzes whether the behavior poses a risk of constructing cache side-channel attacks and transient side-channel attacks. The user layer consists of three modules: a test case generation module, a scenario testing module, and a data analysis module. Although the methods for detecting cache side-channel attacks and transient side-channel attacks achieve similar effects to the test case generation module, scenario testing module, and data analysis module, their implementation design methods differ.

[0045] The performance monitoring unit is processor hardware used to monitor the behavior of the processor architecture layer and microarchitecture layer and quantify the behavior into count values ​​stored in special registers. The processor side-channel attack detection method is divided into hardware layer, operating system layer and user layer, including methods for detecting cache side-channel attacks and transient side-channel attacks. The performance monitoring unit records the microarchitecture behavior during cache and transient execution during instruction execution, respectively. Then, based on the count values ​​of the performance monitoring unit during instruction execution, it automatically analyzes whether there is a risk of constructing a side-channel attack.

[0046] Example 1

[0047] This invention proposes a method for mining cache side-channel attacks based on performance monitoring units, such as... Figure 2As shown. The test case module iterates through all monitoring events supported by the current processor and generates test cases in (event) format. The cache test module constructs cache hit and miss behaviors, then records the cache miss and hit behaviors caused by data loading instructions, and assigns the count values ​​to the data analysis module. The data analysis module is responsible for analyzing the count values ​​of 1000 cache hits and cache misses under the cache scenario test, selecting reasonable thresholds for cache hits and cache misses, and finally determining whether the cache hit threshold and the cache miss threshold are equal. If the cache hit threshold and the cache miss threshold are not equal, there is a risk of constructing a cache side-channel attack; otherwise, there is no risk of constructing a cache side-channel attack. To ensure the uniqueness and representativeness of the cache hit and cache miss thresholds, the data analysis module sets the median of the 1000 cache hit and cache miss count values ​​as the threshold for both scenarios. While using the mode as the threshold for both behaviors can ensure the representativeness of the threshold, multiple count values ​​may appear with the same number of occurrences, which cannot guarantee the uniqueness of the threshold. While using the mean as the threshold for both scenarios ensures the uniqueness of the threshold, it can be affected by noise, whether very large or very small, which may compromise its representativeness. Therefore, the data analysis module chooses the median as the threshold for both scenarios, which can ignore the influence of noise while still guaranteeing the uniqueness of the threshold.

[0048] The code snippet that constructs the cache missing behavior, such as Figure 3 As shown. The cacheMiss array in line 1 stores the count value triggered by 1000 cache misses under the current event; line 2 configures the monitoring event; line 5 uses the clflush instruction to flush the data at the address under test from the entire multi-level cache structure; line 6 accesses data from memory, triggering the cache miss behavior. Lines 5, 8, and 9 record the increment of the count value of the current monitoring event triggered by the cache miss behavior.

[0049] The code snippet that constructs the cache hit behavior, such as Figure 4 As shown. The cacheHit array in line 1 stores the count value triggered by 1000 cache hits under the current event; line 2 configures the monitoring event; the memory access operation in line 5 loads the data at the address under test into the data cache; line 6 accesses data from the cache, triggering the cache hit behavior. Lines 5, 8, and 9 record the increment of the count value of the current monitoring event triggered by the cache hit behavior.

[0050] Example 2

[0051] This invention also provides a method for detecting transient side-channel attacks based on a performance monitoring unit, such as... Figure 5As shown. The test case generation module generates test cases by traversing the event set and instruction set in the format (event, instruction1, instruction2). In an ideal test case, instruction1 and instruction2 trigger different processor microarchitecture behaviors, and the event has the ability to monitor one of the behaviors, or the two behaviors have different increments in the event's count value. The transient testing module traverses all possible values ​​of the private data, and the comparison result between the self-controlled variable and the private data determines whether to execute instruction1 or instruction2 during transient execution, and uses the PMU to record the microarchitecture behavior during transient execution. The data analysis module searches for the comparison variable with the unique occurrence of the PMU count value in the PMU count value recorded during the traversal process, and infers that the private data is equal to the comparison variable. If the inference is successful, there is a risk of constructing a transient side-channel attack; otherwise, there is no risk of constructing a cache side-channel attack.

[0052] The core code snippets that relate the private data and the microarchitectural behavior during transient execution, such as Figure 6 As shown. A crucial step in the scenario testing module is triggering transient execution. To prevent program crashes, exception handling is essential. Transactional Synchronization Extensions (TSX) is a good method for handling exceptions; it's simple to implement and the exception handling process has minimal microarchitectural pollution. However, only some Intel processors support TSX. For processors that don't support TSX, the transient testing module implements exception handling functions to prevent the program from being killed, a process that may pollute the microarchitecture. In short, regardless of the method used to handle exceptions, the approach to establishing a connection between private data and the microarchitectural behavior during transient execution is the same. In line 2, the private data triggers an exception; lines 3 through 10 are all transient instructions. Line 3 compares the control variable with the private data. If they are equal, lines 7 through 10 are executed; otherwise, lines 5, 6, 9, and 10 are executed. The instructions in line 5 (instruction1) and line 8 (instruction2) are provided in the test case. These two instructions are different and trigger different behaviors in the microarchitecture. The code snippet implements a mechanism that determines different code execution paths based on the comparison results of self-controlled variables and private data, with different paths triggering different behaviors in the microarchitecture.

[0053] This invention proposes a method and system for mining processor side-channel attacks based on a performance monitoring unit. The performance monitoring unit records processor behavior at a fine-grained level, uncovering more processor details. It discovers that the performance monitoring unit can not only record the impact of normally submitted instructions on the processor using events, but also, in some cases, the impact of transient instructions on the processor's microarchitecture behavior, thus expanding the applicability of the performance monitoring unit. Furthermore, it proposes methods for mining cache side-channel attacks and transient side-channel attacks. These two methods treat the processor as a black box, automatically completing the processes of generating test cases, scenario testing, and data analysis, achieving the effect of automatically mining processor side-channel attacks.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method of mining based on performance monitoring unit side-channel attacks of a processor, characterized in that, To exploit cache side-channel attacks, the following steps are included: S1. Iterate through the monitoring events supported by the current processor, construct test cases in event format, and pass the test cases to the cache test module; where event is the monitoring event supported by the processor under test. S2. Construct scenarios that trigger cache hit and cache miss behaviors using the cache test module, configure the test cases to record processor behavior in the performance monitoring unit, and use the performance monitoring unit to record the execution process of the cache hit and cache miss scenarios. Then, pass the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module. S3. Use the data analysis module to analyze whether there are differences in the test data for cache hit and cache miss scenarios. If there are differences, it means that the monitoring events in the test cases can record and distinguish between cache hit and cache miss behaviors, and there is a risk of constructing a cache side-channel attack to achieve leakage. Otherwise, the monitoring events do not pose a risk of constructing a cache side-channel attack to achieve leakage.

2. The method of claim 1, wherein, In step S3, the data analysis module is used to analyze whether there are differences in the test data of cache hit and cache miss scenarios. Specifically, the data analysis module is responsible for analyzing the performance monitoring unit count values ​​of 1000 cache hits and cache misses under the cache scenario test, selecting reasonable thresholds for cache hits and cache misses, and finally determining whether the thresholds for cache hits and cache misses are equal. If the thresholds for cache hits and cache misses are not equal, there is a risk of constructing a cache side-channel attack. Otherwise, there is no risk of constructing a cache side-channel attack.

3. The method of claim 2, wherein the performance monitoring unit based processor side channel attack mining method is characterized by, In step S3, the data analysis module sets the median of the counts of 1000 cache hits and cache misses as the threshold for the two scenarios.

4. A method for detecting processor side-channel attacks based on a performance monitoring unit, characterized in that, To detect transient side-channel attacks, the following steps are included: S1. Use the test case generation module to traverse the monitoring events and instruction sets supported by the current processor, construct test cases in the format of event, instruction1 and instruction2, and pass the test cases to the transient test module; where event is the monitoring event supported by the processor under test, and instruction1 and instruction2 are the instructions executed transiently, which can trigger different microarchitectural behaviors. S2. Construct code snippets that associate private data with microarchitecture behavior during transient execution using the transient test module. Use the performance monitoring unit to record the microarchitecture behavior when the comparison results of the self-controlled variables and private data are the same and different. Then, pass the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module. S3. Use the data analysis module to analyze whether there are differences in the test data when the comparison results of the self-controlled variables and private data are the same and different; if there are differences, the monitoring event can record and distinguish the behavior of the microarchitecture during transient execution, and the monitoring event has the risk of constructing a transient side-channel attack to achieve leakage; otherwise, the monitoring event does not have the risk of constructing a transient side-channel attack to achieve information leakage.

5. The method for detecting processor side-channel attacks based on a performance monitoring unit according to claim 4, characterized in that, In step S2, the processor microarchitecture behaviors triggered by instruction1 and instruction2 are different, and the event has the ability to monitor one of the behaviors, or the two behaviors have different increments in the event's count value.

6. The method for detecting processor side-channel attacks based on a performance monitoring unit according to claim 5, characterized in that, The transient testing module iterates through all possible values ​​of the private data, compares the results of the self-controlled variables and the private data to determine whether to execute instruction1 or instruction2 during transient execution, and uses the performance monitoring unit to record the behavior of the microarchitecture during transient execution.

7. The method for detecting processor side-channel attacks based on a performance monitoring unit according to claim 4, characterized in that, In step S3, the data analysis module searches for a comparison variable whose count value appears only once in the performance monitoring unit count values ​​recorded during the comparison process, and infers that the private data is equal to the comparison variable. If the prediction is successful, there is a risk of constructing a transient side-channel attack. Otherwise, there is no risk of constructing a cache side-channel attack.

8. A processor side-channel attack detection system based on a performance monitoring unit, characterized in that, The method for detecting cache side-channel attacks includes the following modules to implement the processor side-channel attack detection method based on a performance monitoring unit as described in any one of claims 1-3: The test case generation module is responsible for iterating through the monitoring events supported by the current processor, constructing test cases in event format, and passing the test cases to the cache test module; where event is the monitoring event supported by the processor under test. The cache testing module is responsible for constructing scenarios that trigger cache hit and cache miss behaviors, configuring the test cases to record processor behavior in the performance monitoring unit, using the performance monitoring unit to record the execution process of cache hit and cache miss scenarios, and passing the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module. The data analysis module is responsible for analyzing whether there are differences in the test data for cache hit and cache miss scenarios. If there are differences, it can record and distinguish between cache hit and cache miss behaviors, and monitor the events to identify the risk of constructing a cache side-channel attack to achieve leakage. Otherwise, the monitoring events do not identify the risk of constructing a cache side-channel attack to achieve leakage.

9. A processor side-channel attack detection system based on a performance monitoring unit, characterized in that, For detecting transient side-channel attacks, the method includes the following modules to implement the processor side-channel attack detection method based on a performance monitoring unit as described in any one of claims 4-7: The test case generation module is responsible for traversing the monitoring events and instruction sets supported by the current processor, constructing test cases in the format of event, instruction1, and instruction2, and passing the test cases to the cache test module. Among them, event is the monitoring event supported by the processor under test, and instruction1 and instruction2 are instructions that are executed transiently and can trigger different microarchitectural behaviors. The transient testing module is responsible for constructing code snippets that associate private data with the microarchitecture behavior during transient execution. It determines whether to execute instruction1 or instruction2 during transient execution based on the comparison results between the self-controlled variable and the private data. It uses the performance monitoring unit to record the microarchitecture behavior when the comparison results between the self-controlled variable and the private data are the same and different, respectively, and passes the count values ​​of the two scenarios recorded by the performance monitoring unit as test data to the data analysis module. The data analysis module analyzes whether there are differences in the test data when the comparison results of the self-controlled variables and private data are the same and different. If there are differences, the monitoring event can record and distinguish the behavior of the microarchitecture during transient execution, and the monitoring event has the risk of constructing a transient side-channel attack to achieve leakage. Otherwise, the monitoring event does not have the risk of constructing a transient side-channel attack to achieve information leakage.

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